Image sensor and analog-to-digital converter

Abstract

To provide an image sensor that converts a pixel signal into a digital code highly accurately in a short time.SOLUTION: An image sensor 100 includes: a pixel 110 for outputting a pixel signal PIXEL; a lamp voltage generation circuit 120 for generating a lamp voltage RAMP which changes according to a first inclination in a first interval and generating a lamp voltage RAMP which changes according to a second inclination with a larger absolute value than that of the first inclination in a second interval after the first interval; an operation amplification unit 130 for comparing the pixel signal PIXEL with the lamp voltages RAMP between the first interval and the second interval; and a counter circuit 140 for generating a digital code DOUT corresponding to the pixel signal PIXEL in response to output of the operation amplification unit 130.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This patent document relates to image sensors and analog-to-digital converters. [Background technology]

[0002] CMOS image sensors (CIS) have a trade-off between speed and power. Therefore, currently, CMOS image sensors mainly use a column-parallel structure that has the optimal trade-off between speed and power. Because of this, there is a difficulty in integrating an analog-to-digital converter (ADC) into a narrow pixel width, so a simple single-slope analog-to-digital converter (ADC) is mainly used.

[0003] As image sensors continue to develop, there is an increasing demand for higher accuracy (resolution) in analog-to-digital conversion. In the past, converting pixel voltages into 10-bit digital codes was sufficient, but nowadays, converting pixel voltages into 12-bit or 14-bit digital codes is required. However, the problem arises that the higher the accuracy (resolution) of the analog-to-digital conversion, the longer the time required for the analog-to-digital conversion. For example, converting a voltage into a 12-bit digital code may take four times as long as converting it into a 10-bit digital code. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention can provide an image sensor that converts pixel signals into digital codes with high accuracy in a short time. [Means for solving the problem]

[0005] An image sensor according to an embodiment of the present invention may include a pixel that outputs a pixel signal; a ramp voltage generation circuit that generates a ramp voltage that changes with a first slope during a first interval and that generates the ramp voltage that changes with a second slope having an absolute value greater than the first slope during a second interval after the first interval; an operational amplifier that compares the pixel signal with the ramp voltage between the first interval and the second interval; and a counter circuit that generates a digital code corresponding to the pixel signal in response to an output of the operational amplifier.

[0006] A method of operating an image sensor according to an embodiment of the present invention may include the steps of generating a pixel signal, generating a ramp voltage that changes with a first slope during a first interval, counting clocks during the first interval to generate a digital code, the level of the ramp voltage failing to reach a voltage level of the pixel signal during the first interval and ending the first interval, initializing the digital code, generating a ramp voltage that changes with a second slope having an absolute value greater than the first slope during a second interval, counting the clocks during the second interval to generate the digital code, the level of the ramp voltage reaching the voltage level of the pixel signal, and stopping counting the clocks in response to the reaching and providing the digital code corresponding to the pixel signal.

[0007] An analog-to-digital converter according to one embodiment of the present invention may include a ramp voltage generation circuit that generates a ramp voltage that changes with a first slope during a first interval and generates the ramp voltage that changes with a second slope having an absolute value greater than the first slope during a second interval after the first interval; an operational amplifier that compares a voltage to be converted with the ramp voltage between the first interval and the second interval; and a counter circuit that generates a digital code corresponding to the voltage to be converted in response to an output of the operational amplifier. [Effects of the Invention]

[0008] According to embodiments of the present invention, an image sensor can generate high quality digital images in a short time. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing the configuration of an image sensor 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram of one embodiment of a pixel 110 of FIG. 1. [Figure 3] 2 illustrates one embodiment of the operation of the image sensor 100 of FIG. 1. [Figure 4] 2 illustrates one embodiment of the operation of the image sensor 100 of FIG. 1. [Figure 5] FIG. 10 is a diagram showing yet another example of the ramping operation of the ramp voltage RAMP in the signal readout section SR. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the most preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical concept of the present invention. In describing the present invention, known structures unrelated to the gist of the present invention may be omitted. When assigning reference numerals to components in each drawing, it should be noted that the same components are assigned the same numerals as much as possible, even if they are shown in different drawings.

[0011] FIG. 1 is a diagram showing the configuration of an image sensor 100 according to an embodiment of the present invention.

[0012] As shown in FIG. 1, the image sensor 100 may include a pixel 110, a ramp voltage generating circuit 120, an operational amplifier 130, a counter circuit 140, a controller 150, switches 131 and 132, and capacitors 133 and 134.

[0013] The pixel 110 can output a pixel signal PIXEL using the sensed light. A plurality of pixels 110 can be provided in an array configuration including a plurality of rows and columns, but only one pixel 110 is shown here for ease of explanation.

[0014] The ramp voltage generating circuit 120 generates a ramp voltage RAMP. The slope of the ramp voltage RAMP generated by the ramp voltage generating circuit 120 may vary depending on the operating period, as will be described in detail with reference to FIG.

[0015] The operational amplifier 130 may receive a pixel signal PIXEL and a ramp voltage RAMP via capacitors 133 and 134. The operational amplifier 130 may compare the levels of the pixel signal PIXEL input to the input terminal INN via capacitor 133 with the ramp voltage RAMP input to the input terminal INP via capacitor 134 and output the result to the output terminal OUTP. The input terminal INN may be a negative (-) input terminal, the input terminal INP may be a positive (+) input terminal, the output terminal OUTP may be a positive (+) output terminal, and the output terminal OUTN may be a negative (-) output terminal. The switches 131 and 132 may be used for an auto-zeroing operation of the operational amplifier 130. The switches 131 and 132 may be turned on during the auto-zeroing operation. The switch 131 may electrically connect the input terminal INN to the output terminal OUTP, and the switch 132 may electrically connect the input terminal INP to the output terminal OUTN. The switches 131 and 132 can be turned on / off in response to a signal SW.

[0016] The counter circuit 140 counts the clock CNT_CLK in response to the signal at the output terminal OUTP of the operational amplifier 130, and as a result, can generate the digital code DOUT.

[0017] The controller 150 can control the ramp voltage generating circuit 120, the switches 131 and 132, and the counter circuit 140 so that appropriate operations are performed during the reset read interval, the first interval, and the second interval. The control operation of the controller 150 will be described in detail with reference to FIG. 3. "CONTROL" in the drawing may indicate control by the controller 150.

[0018] 1, the remaining components excluding the pixel 110 are components for converting the analog voltage PIXEL output from the pixel 110 into a digital code DOUT. Therefore, the present invention can be applied not only to image sensors but also to general analog-to-digital converters for converting an analog voltage into a digital code.

[0019] FIG. 2 is a block diagram of one embodiment of pixel 110 of FIG.

[0020] As shown in FIG. 2, the pixel 110 may include a photodetector 201 , a transfer transistor 203 , a reset transistor 205 , a capacitor 207 , a drive transistor 209 , a select transistor 211 , and a current source 213 .

[0021] The photodetector 201 may perform a photoelectric conversion function. The photodetector 201 may be connected between a ground voltage terminal and a transfer transistor 203. The photodetector 201 may receive light from an external source and generate a photocharge based on the received light. The photodetector 201 may be implemented using at least one of a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor 203 may transfer the photocharge of the photodetector 201 to a floating diffusion node FD in response to a transfer signal TX. The floating diffusion node FD is a diffusion region connected to the transfer transistor 203 and a reset transistor 205, and is a node where a charge corresponding to a video signal or a charge corresponding to an initialization voltage is accumulated. A capacitor 207 for storing the charge may be connected to the floating diffusion node FD.

[0022] The reset transistor 205 may transmit a power supply voltage to the floating diffusion node FD in response to a reset control signal RX, i.e., the reset transistor 205 may reset the photocharges stored in the floating diffusion node FD in response to the reset control signal RX.

[0023] The driving transistor 209 may have a gate connected to the floating diffusion node FD, and a drain and a source connected between a power supply voltage terminal and the selection transistor 211. The driving transistor 209 may serve to amplify the voltage of the floating diffusion node FD.

[0024] The selection transistor 211 can electrically connect the source terminal of the driving transistor 209 to the output line PIXEL in response to a selection signal SX.

[0025] The current source 213 can sink a constant current from the output line PIXEL to the ground terminal, and can be shared by multiple pixels.

[0026] The pixel signal is output from the output line PIXEL, and the voltage level of the output line PIXEL can be determined by the amount of current sourced to the output line PIXEL by the driving transistor 209 and the amount of current sinked from the output line PIXEL by the current source 213. Consequently, the voltage level of the output line PIXEL can be higher as the voltage level of the floating diffusion node FD is higher.

[0027] Figures 3 and 4 are diagrams illustrating an embodiment of the operation of image sensor 100 in Figure 1. Figure 3 illustrates the operation when the voltage level of the pixel signal generated in pixel 100 is low, and Figure 4 illustrates the operation when the voltage level of the pixel signal generated in pixel 100 is high.

[0028] 3 may indicate an auto-zeroing period. During this period, the controller 150 activates the signal SW, turning on the switches 131 and 132, and the auto-zeroing operation of the operational amplifier 130 may be performed.

[0029] 3 may indicate a reset readout period. In this period, a reset signal is output from the pixel 100, and the ramp voltage generating circuit 120, the operational amplifier 130, and the counter circuit 140 may convert the reset signal into a digital code DOUT.

[0030] In the reset readout period RR, the reset control signal RX is activated in the pixel 100 to reset the floating diffusion node FD, and the selection signal SX is activated to output a reset signal to the output line PIXEL of the pixel 100. It can be seen that the voltage level of the output line PIXEL changes in the reset readout period RR, and from this point on, the reset signal of the pixel 100 can be output to the output line PIXEL.

[0031] During the reset readout period RR, a ramping operation in which the ramp voltage RAMP rises and falls may occur. From the time when the ramp voltage RAMP begins to fall until the time when the ramp voltage RAMP meets the voltage of the output line PIXEL, i.e., until the time when the output OUTP of the operational amplifier 130 transitions, the counter circuit 140 may count the number of activations of the clock CNT_CLK to generate a digital code DOUT. Here, the digital code DOUT may be a code obtained by converting the reset signal of the pixel 100 into a digital form. During the reset readout period RR, the ramp voltage RAMP may fall with a first slope having a small absolute value. Therefore, the resolution of the digital code DOUT generated by the counter circuit 140 during the reset readout period RR may be high. For example, the digital code DOUT generated during the reset readout period RR may have a 12-bit resolution.

[0032] 3 indicates a signal readout section, in which a pixel signal is output from the pixel 100 and converted into a digital code DOUT by the ramp voltage generating circuit 120, the operational amplifier 130, and the counter circuit 140.

[0033] During the signal readout period SR, the transfer signal TX is activated in the pixel 100, transferring the photocharges of the photodetector 201 to the floating diffusion node FD, and the selection signal SX is activated, outputting a pixel signal of the pixel 100, i.e., a signal corresponding to the light sensed by the pixel 100, to the output line PIXEL of the pixel 100. It can be seen that the voltage level of the output line PIXEL changes during the signal readout period SR, and from this point on, the pixel signal of the pixel 100 can be output to the output line PIXEL.

[0034] Within the signal readout section SR, a ramping operation in which the ramp voltage RAMP rises and falls may be performed in two sections 310 and 320. The first section 310 may be a section for digitally converting pixel signals to high resolution, and the second section 320 may be a section for digitally converting pixel signals to low resolution if digital conversion of the pixel signals in the first section 310 fails.

[0035] During the period 310, a ramping operation in which the ramp voltage RAMP rises and falls may occur. From the time the ramp voltage RAMP begins to fall until the time the ramp voltage RAMP meets the voltage (pixel signal) of the output line PIXEL, the counter circuit 140 counts the number of activations of the clock CNT_CLK to generate the digital code DOUT. However, during the period 310, the ramp voltage RAMP may not fall to the voltage level of the output line PIXEL, and the two voltage levels may not meet. That is, digital conversion of the pixel signal during the period 310 may fail. During the period 310, the ramp voltage RAMP may fall with a first slope, which is the same slope as the reset read period RR. Therefore, this period 310 may be a period in which an attempt is made to generate a digital code DOUT with high resolution.

[0036] Since conversion of the voltage of the output line PIXEL into the digital code DOUT failed in section 310, the operation of converting the voltage of the output line PIXEL into the digital code DOUT can be attempted again in section 320. Under the control of the controller 150, the counter circuit 140 can initialize the digital code DOUT and generate a new digital code in section 320. Also, under the control of the controller 150, the ramp voltage generating circuit 120 can generate a ramp voltage RAMP with a slope different from that in section 310. The controller 150 can determine whether the conversion of the digital code DOUT in section 310 was successful or failed by monitoring the output OUTP of the operational amplifier.

[0037] A ramping operation in which the ramp voltage RAMP rises and falls may occur in the section 320. The ramp voltage RAMP may fall at a second slope having a larger absolute value than the ramp voltage in the section 310. For example, the second slope may be 2^N (N = an integer greater than or equal to 1) times the first slope. Here, the second slope is illustrated as being four times the first slope. From the time the ramp voltage RAMP starts to fall in the section 320 until the time the ramp voltage RAMP meets the voltage of the output line PIXEL (pixel signal), i.e., until the output OUTP of the operational amplifier 130 transitions, the counter circuit 140 counts the number of activations of the clock CNT_CLK and generates the digital code DOUT. In the section 320, the ramp voltage RAMP falls at a second slope having a larger absolute value, so that the ramp voltage RAMP meets the voltage of the output line PIXEL. In section 320, the ramp voltage RAMP drops sharply at a slope that is 2^N times that of sections RR and 310, so the resolution of the digital code DOUT generated in section 320 may be 1 / (2^N) times that of the digital code DOUT generated in sections RR and 310. Here, the second slope is illustrated as being four times the first slope, so the resolution of the digital code DOUT generated in section 320 may be 1 / 4 times that of the digital code DOUT generated in section RR. In other words, if the digital code DOUT generated in section RR is a 12-bit code, the digital code DOUT generated in section 320 may be a 10-bit code.

[0038] The exact image sensed by pixel 100 can be obtained by subtracting the reset signal from the pixel signal. The pixel signal is generated as a digital code DOUT with a 10-bit resolution in section 320, and the reset signal is generated as a digital code DOUT with a 12-bit resolution in section RR. Therefore, the final image can be obtained by subtracting the digital code generated in section 320 × 4 from the digital code generated in section RR, and this image can be a 12-bit code.

[0039] 4 may indicate an auto-zeroing period. During this period AZ, the controller 150 activates the signal SW, turning on the switches 131 and 132, and the auto-zeroing operation of the operational amplifier 130 may be performed.

[0040] 4 may indicate a reset readout period. In this period, a reset signal is output from the pixel 100, and the ramp voltage generating circuit 120, the operational amplifier 130, and the counter circuit 140 may convert the reset signal into a digital code DOUT.

[0041] In the reset readout period RR, the reset control signal RX is activated in the pixel 100, resetting the floating diffusion node FD, and the selection signal SX is activated, so that a reset signal can be output to the output line PIXEL of the pixel 100. It can be seen that the voltage level of the output line PIXEL changes in the reset readout period RR, and from this point on, the reset signal of the pixel 100 can be output to the output line PIXEL.

[0042] During the reset readout period RR, a ramping operation in which the ramp voltage RAMP rises and falls may occur. From the time when the ramp voltage RAMP begins to fall until the time when the ramp voltage RAMP meets the voltage of the output line PIXEL, i.e., until the time when the output OUTP of the operational amplifier 130 transitions, the counter circuit 140 may count the number of activations of the clock CNT_CLK to generate a digital code DOUT. Here, the digital code DOUT may be a code obtained by converting the reset signal of the pixel 100 into a digital form. During the reset readout period RR, the ramp voltage RAMP may fall with a first slope having a small absolute value. Therefore, the resolution of the digital code DOUT generated by the counter circuit 140 during the reset readout period RR may be high. For example, the digital code DOUT generated during the reset readout period RR may have a 12-bit resolution.

[0043] 4 indicates a signal readout section, in which a pixel signal is output from the pixel 100 and converted into a digital code DOUT by the ramp voltage generating circuit 120, the operational amplifier 130, and the counter circuit 140.

[0044] During the signal readout period SR, the transfer signal TX is activated in the pixel 100, transferring the photocharge of the photodetector 201 to the floating diffusion node FD, and the selection signal SX is activated, outputting the pixel signal of the pixel 100, i.e., a signal corresponding to the light sensed by the pixel 100, to the output line PIXEL of the pixel 100. It can be seen that the voltage level of the output line PIXEL changes during the signal readout period SR, and from this point on, the pixel signal of the pixel 100 can be output to the output line PIXEL.

[0045] Within the signal readout section SR, a ramping operation in which the ramp voltage RAMP rises and falls may be performed in two sections 410 and 420. The first section 410 may be a section for digitally converting pixel signals to high resolution, and the second section 420 may be a section for digitally converting pixel signals to low resolution if digital conversion of the pixel signals in the first section 410 fails.

[0046] During the period 410, a ramping operation in which the ramp voltage RAMP rises and falls may occur. From the time when the ramp voltage RAMP begins to fall until the time when the ramp voltage RAMP meets the voltage (pixel signal) of the output line PIXEL, i.e., until the time when the output OUTP of the operational amplifier 130 transitions, the counter circuit 140 counts the number of activations of the clock CNT_CLK to generate the digital code DOUT. Because the voltage level of the output line PIXEL is relatively high in FIG. 4, there may be a time during the period 410 when the ramp voltage RAMP and the voltage level of the output line PIXEL become the same. The digital code DOUT generated during the period 410 may be a code obtained by digitally converting the pixel signal of the pixel 100. Because the ramp voltage falls with a first slope during the period 410, the digital code DOUT generated during this period 410 may have high resolution, for example, 12 bits.

[0047] In section 420, the ramp voltage RAMP may rise and then fall again at a second slope. Because the pixel signal of the output line PIXEL has already been successfully converted into the digital code DOUT in section 410, generation of the digital code DOUT may not be attempted again in section 420. That is, if the conversion of the digital code DOUT is successful in section 410, the controller 150 may control the counter circuit 140 not to perform a counting operation without initializing the digital code DOUT of the counter circuit 140.

[0048] The exact image sensed by pixel 100 can be obtained by subtracting the reset signal from the pixel signal. The pixel signal is generated as a 12-bit digital code DOUT in section 410, and the reset signal is generated as a 12-bit digital code DOUT in section RR. Therefore, the final image can be obtained by subtracting the digital code generated in section 410 from the digital code generated in section RR, and this image can be a 12-bit code.

[0049] As shown in Figures 3 and 4, a reset signal having a high voltage level can be analog-to-digital converted to high resolution in section RR. When the voltage level of the pixel signal is high (e.g., Figure 4), it can be analog-to-digital converted to high resolution in section 410, and when the voltage level is low (e.g., Figure 3), it can be analog-to-digital converted to low resolution in section 320. A high voltage level of the pixel signal means that the amount of light sensed by the pixel 100 is small. In this case, the pixel signal needs to be analog-to-digital converted to high resolution because even subtle differences in the amount of sensed light must be distinguishable. In contrast, a low voltage level of the pixel signal means that the amount of light sensed by the pixel 100 is large. In this case, the need to distinguish subtle differences in the amount of light may be less than when the amount of sensed light is small. Therefore, when the amount of light sensed by the pixel 100 is large, analog-to-digital conversion of the pixel signal to low resolution may not have a significant impact on image quality.

[0050] When the voltage level of a pixel signal is high, it does not take much time to perform analog-to-digital conversion of the pixel signal to a high resolution, but when the voltage level of the pixel signal is low, it takes a very long time to perform analog-to-digital conversion of the pixel signal to a high resolution. Therefore, the image sensor 100 can perform analog-to-digital conversion of the pixel signal to a high resolution when the voltage level of the pixel signal is high, and can perform analog-to-digital conversion of the pixel signal to a low resolution when the voltage level of the pixel signal is low. That is, when the voltage level of the pixel signal is high and high-resolution analog-to-digital conversion is required, the high-resolution analog-to-digital conversion operation can be performed quickly, and when the voltage level of the pixel signal is low and high-resolution analog-to-digital conversion is not required, the low-resolution analog-to-digital conversion operation can be performed.

[0051] 5 is a diagram showing another example of the ramping operation of the ramp voltage RAMP in the signal readout section SR. While FIGS. 3 and 4 show that the signal readout section SR is divided into two sections, namely, the high-resolution conversion section 310, 410 and the low-resolution conversion section 320, 420, in FIG. 5, it will be explained that the signal readout section SR is divided into three sections, namely, the high-resolution conversion section 510, the medium-resolution conversion section 520, and the low-resolution conversion section 530.

[0052] 5, a ramping operation in which the ramp voltage RAMP rises and then falls at a low slope may occur in the high-resolution conversion section 510. When the voltage level of the pixel signal output to the output line PIXEL of the pixel 100 is between 511 and 512, the ramp voltage RAMP may become equal to the voltage level of the pixel signal in the section 510, so that the pixel signal may be digitally converted to a high resolution (e.g., 12 bits) to generate the digital code DOUT.

[0053] A ramping operation in which the ramp voltage RAMP rises and then falls at a medium slope may also occur in the medium resolution conversion section 520. When the voltage level of the pixel signal output to the output line PIXEL of the pixel 100 is between levels 512 and 521, the ramp voltage RAMP may become equal to the voltage level of the pixel signal in section 520, so that the pixel signal may be digitally converted to a medium resolution (e.g., 11 bits) to generate the digital code DOUT.

[0054] A ramping operation in which the ramp voltage RAMP rises and then falls at a steep slope may also occur in the low-resolution conversion section 530. When the voltage level of the pixel signal output to the output line PIXEL of the pixel 100 is between 521 and 531, the ramp voltage RAMP may become equal to the voltage level of the pixel signal in section 530, so that the pixel signal may be digitally converted to a low resolution (e.g., 10 bits) to generate the digital code DOUT.

[0055] Although FIG. 5 illustrates an example in which pixel voltages are converted into digital codes DOUT using three levels of resolution, it is obvious that pixel voltages can be converted into digital codes DOUT using more levels of resolution.

[0056] Although the technical concept of the present invention has been specifically described by the above-mentioned preferred embodiments, it should be noted that the above-mentioned embodiments are for the purpose of explanation and not for the purpose of limitation. In addition, those skilled in the art of the present invention will understand that various embodiments are possible within the scope of the technical concept of the present invention. [Explanation of symbols]

[0057] 100 image sensors 110 pixels 120 Lamp voltage generation circuit 130 Operational Amplifier 140 Counter Circuit 150 Controller 131, 132 Switches 133, 134 Capacitor

Claims

1. a pixel that outputs a pixel signal; a ramp voltage generating circuit that generates a ramp voltage that changes with a first slope during a first interval, and that generates the ramp voltage that changes with a second slope having an absolute value greater than the first slope during a second interval after the first interval; an operational amplifier that compares the pixel signal and the ramp voltage between the first interval and the second interval; a counter circuit responsive to an output of the operational amplifier to generate a digital code corresponding to the pixel signal; Equipped with If the output of the operational amplifier transitions during the first period, the counter circuit does not perform a counting operation during the second period.

2. The counter circuit generating the digital code by counting clocks until the output of the operational amplifier transitions during the first interval; 2. The image sensor according to claim 1, wherein if the output of the operational amplifier does not transition during the first period, the clock is counted until the output of the operational amplifier transitions during the second period, thereby generating the digital code.

3. 3. The image sensor according to claim 2, wherein the absolute value of the second gradient is 2^N times the absolute value of the first gradient (N is an integer equal to or greater than 1).

4. the ramp voltage generating circuit generates the ramp voltage that changes with a third slope having an absolute value greater than the second slope during a third interval that follows the second interval; 3. The image sensor according to claim 2, wherein if the output of the operational amplifier does not transition during the second period, the counter circuit counts the clock to generate the digital code until the output of the operational amplifier transitions during the third period.

5. The pixel outputs a reset signal during a reset readout period; the ramp voltage generating circuit generates the ramp voltage that changes with the first slope during the reset readout period; 3. The image sensor of claim 2, wherein the operational amplifier compares the reset signal with the ramp voltage during the reset readout period.

6. The counter circuit 6. The image sensor according to claim 5, wherein the clock is counted until the output of the operational amplifier transitions during the reset readout period, and a digital code corresponding to the reset signal is generated.

7. generating a pixel signal; generating a ramp voltage that varies with a first slope during a first interval; a step of counting a clock during the first interval to generate a digital code; a step of the level of the ramp voltage not reaching the voltage level of the pixel signal during the first interval and the first interval ending; the digital code is initialized; generating a ramp voltage that varies with a second slope having an absolute value greater than the first slope during a second interval; counting the clock during the second interval to generate the digital code; the level of the ramp voltage reaching the voltage level of the pixel signal; responsive to said arrival, ceasing counting of said clock and providing said digital code corresponding to said pixel signal; Including, a counting operation of the clock not being performed during the second interval if the level of the ramp voltage reaches the voltage level of the pixel signal during the first interval;

8. Prior to the step of generating the pixel signal, generating a reset signal; generating a ramp voltage that changes with the first slope during a reset readout period; counting the clock during the reset read section to count the digital code; the level of the ramp voltage reaching the voltage level of the reset signal; responsive to said arrival, ceasing counting of said clock and providing said digital code corresponding to said reset signal; The method of operating an image sensor of claim 7 further comprising:

9. 8. The method of claim 7, wherein the absolute value of the second gradient is 2^N times the absolute value of the first gradient (N is an integer equal to or greater than 1).

10. a ramp voltage generating circuit that generates a ramp voltage that changes with a first slope during a first interval, and that generates the ramp voltage that changes with a second slope having an absolute value greater than the first slope during a second interval after the first interval; an operational amplifier that compares a voltage to be converted with the ramp voltage between the first section and the second section; a counter circuit that generates a digital code corresponding to the voltage to be converted in response to an output of the operational amplifier; Equipped with The analog-to-digital converter, wherein if the output of the operational amplifier transitions during the first interval, the counter circuit does not perform a counting operation during the second interval.

11. The counter circuit generating the digital code by counting clocks until the output of the operational amplifier transitions during the first interval; 11. The analog-to-digital converter according to claim 10, wherein if the output of the operational amplifier does not transition during the first interval, the clock is counted until the output of the operational amplifier transitions during the second interval, thereby generating the digital code.

12. 12. The analog-to-digital converter according to claim 11, wherein the absolute value of the second slope is 2^N times the absolute value of the first slope (N is an integer equal to or greater than 1).

13. the ramp voltage generating circuit generates the ramp voltage that changes with a third slope having an absolute value greater than the second slope during a third interval that follows the second interval; 13. The analog-to-digital converter according to claim 12, wherein if the output of the operational amplifier does not transition during the second interval, the counter circuit counts the clock to generate the digital code until the output of the operational amplifier transitions during the third interval.

Images