Lookup table-based analog-to-digital converter

Abstract

The analog-to-digital converter system (10) includes a digital-to-analog converter (32) for generating a calibration voltage based on a digital input code, and an analog-to-digital converter (18) connected to the digital-to-analog converter (32) for receiving the calibration voltage from the digital-to-analog converter (32), receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating a digital output code based on the sampled voltage. The analog-to-digital converter system (10) may have a look-up table (20) connected to the analog-to-digital converter (18) for storing a first digital output code in association with the digital input code. A method for calibrating the analog-to-digital converter system (10) is also described.

Description

Technical Field

[0001] An analog-to-digital (A / D) converter (ADC) can be used to generate a digital code representing an analog signal. An analog-to-digital converter for digitizing signals in a radio frequency sampling receiver may need to operate at high speed. Analog-to-digital converters are described in U.S. Patent Application Publication Nos. 2012 / 0212358 (Shi et al.), 2015 / 0244386 (El-Chammas), 2019 / 0007071 (Nagarajan et al.), and 2019 / 0280703 (Naru et al.).

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0002] Some analog-to-digital converters have one or more voltage-to-delay (V2D) components and operate at least partially in the delay domain. Delay-based analog-to-digital converters are described in U.S. Patent Application No. 16 / 217,643 (Soundararajan et al., filed December 12, 2018) (U.S. Publication No. 2020 / 0195268 (June 18, 2020)), 16 / 410,698 (Dusad et al., filed May 13, 2019) (U.S. Patent No. 10,673,456 (June 2, 2020)), and 16 / 517,796 (Pentakota et al., filed July 22, 2019) (U.S. Patent No. 10,673,453 (June 20, 2020)). U.S. Patent applications 16 / 217,643, 16 / 410,698, and 16 / 517,796 are incorporated herein by reference in their entirety. Furthermore, the disclosures of five U.S. Patent applications identified in Table 1 below are incorporated herein by reference in their entirety. Delay-based analog-to-digital converters can operate at high speeds with reduced area and power requirements, if desired. [Patent Document 5] U.S. Patent Application No. 16 / 217,643 [Patent Document 6] U.S. Patent Application No. 16 / 410,698 [Patent Document 7] U.S. Patent Application No. 16 / 517,796 [Table 1] [Overview of the project]

[0003] This description relates to an analog-to-digital converter system, and more particularly to an analog-to-digital converter system having a digital-to-analog converter for generating a calibration voltage based on a digital input code, and an analog-to-digital converter connected to the digital-to-analog converter for receiving a calibration voltage from the digital-to-analog converter, receiving a sampled voltage, generating a digital output code based on the calibration voltage, and generating a digital output code based on the sampled voltage.

[0004] This description also relates to a lookup table-based analog-to-digital converter system, and more particularly to a lookup table-based analog-to-digital converter system having: a digital-to-analog converter for generating a calibration voltage based on a digital input code; an analog-to-digital converter connected to the digital-to-analog converter for receiving the calibration voltage, receiving a sampled voltage, generating a first digital output code based on the calibration voltage, and generating a second digital output code based on the sampled voltage; and a lookup table connected to the analog-to-digital converter for storing the first digital output code in relation to a digital input code.

[0005] This description also relates to a method for calibrating an analog-to-digital converter system. This method includes causing a digital-to-analog converter to generate a calibration voltage based on a digital input code, causing an analog-to-digital converter to receive the calibration voltage from the digital-to-analog converter, generate a first digital output code based on the calibration voltage, generate a second digital output code based on a sampled voltage, and storing the first digital output code in a lookup table in relation to the digital input code. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram of a delay-based analog-to-digital converter system.

[0007] [Figure 2] Figure 1 shows the popularity and usage of the lookup table for the analog-to-digital converter system.

[0008] [Figure 3]Figure 1 is a block diagram of the analog-to-digital converter system, showing two analog-to-digital converters and two lookup tables arranged in parallel.

[0009] [Figure 4] Figure 1 is a block diagram of the analog-to-digital converter system, showing three analog-to-digital converters arranged in parallel.

[0010] [Figure 5] Figure 1 is a block diagram of the backend of the analog-to-digital converter.

[0011] [Figure 6] Figure 5 is a block diagram of a coupler for connecting the multi-bit stage shown to the first of the single-bit stages.

[0012] [Figure 7] Figure 5 shows graphs of the backend, representing the AND gate delay and comparator delay generated by the AND gate and the delay comparator, respectively. The AND gate delay and comparator delay are functions of the input signal delay.

[0013] [Figure 8] This graph shows the output signal delay as a function of the input signal delay in Figure 7.

[0014] [Figure 9] Figure 5 is a schematic diagram of an example of a comparator circuit that has been merged with the sign-out circuit and delay-out circuit for the backend. [Modes for carrying out the invention]

[0015] Figure 1 shows an analog-to-digital converter system 10 constructed according to this description. System 10 receives a sampled voltage V on the input line 16. INThe system includes at least first and second multiplexers 12 and 14, which may be analog multiplexers for receiving the output voltage V1 from the first multiplexer 12 on line 17, and a lookup table (LUT) 20. As will be described in more detail later, the lookup table 20 may be constructed from a digital memory circuit and may constitute one or more parts of a memory / digital processor system 300 (Figure 4). The lookup table 20 is populated in calibration mode. The populated table 20 is then used as an information resource in analog-to-digital conversion (or mission) mode.

[0016] The analog-to-digital converter system 10 also has a third multiplexer 22 (Figure 1), which may be a digital multiplexer for receiving a digital code from the analog-to-digital converter 18 on line 24 and applying that digital code to the lookup table 20. As will be described in more detail thereafter, the third multiplexer 22 operates in calibration mode and analog-to-digital conversion (or mission) mode on read and write paths 26 and 28, respectively. The first and second multiplexers 12 and 14 and the third multiplexer 22 are operated by the calibration controller 30. The digital-to-analog (D / A) converter (DAC) 32 is also operated by the calibration controller 30. The digital-to-analog converter 32 operates under a calibration voltage V DAC The calibration voltage V is applied to the first and second multiplexers 12 and 14 on line 34. DAC This is generated by the digital-to-analog converter 32 (Figure 1) based on the digital input code 100 (Figure 2) applied to the digital-to-analog converter 32 (Figure 1) by the calibration controller 30 on line 36.

[0017] The first multiplexer 12, the analog-to-digital converter 18, and the third multiplexer 22 can be operated together in a calibration mode and an analog-to-digital conversion mode. In the calibration mode, the calibration controller 30 issues a series of 2 ∧ N (2 N ) digital codes 100 (Figure 2) to the digital-to-analog converter 32 to apply a corresponding series of 2 ∧ N different voltages V DAC = Vr / (2 ∧ N) on line 34. Here, Vr is the input range from the lowest value to the highest value of the sampled voltage V IN that is expected to be sampled and input on line 16, and N bits is the resolution of the first analog-to-digital converter 18. Thus, for example, if V IN is expected to be within the range of 0V to 5V, Vr is a value near 5V.

[0018] In the calibration mode, as shown as an example (N = 9) in Figure 2, the calibration controller 30 (Figure 1) issues a series of 2 ∧ 9 = 512 input codes 100 (Figure 2) on line 36 to cause the digital-to-analog converter 32 (Figure 1) to generate a corresponding calibration voltage V DAC . The calibration voltage V DAC is transmitted by the first multiplexer 12 on line 17 as the output voltage V1 to the first analog-to-digital converter 18. The first analog-to-digital converter 18 converts the calibration voltage V DAC (V1) into a corresponding output code 102 (Figure 2) of N + n bits. To populate the look-up table, the output code 102 is recorded in the look-up table 20 via the third multiplexer 22 (Figure 1) and the write path 26.

[0019] In the example shown in Figure 2, N+n > N (i.e., n > 0) is used to accommodate the nonlinearity of the first analog-to-digital converter 18. In the illustrated example, the total number of possible output codes 102 that can be output by the analog-to-digital converter 18 (N+n) must be greater than the actual number of input codes 100 stored in the lookup table 20 (N). This is because, in operation, the relationship between the output codes generated by the analog-to-digital converter 18 and the corresponding input codes transmitted on line 36 is not expected to be linear. In the illustrated example, N=9, 2 9 = 512, and the input codes 100 stored in the lookup table 20 range from 0 to 511, with the least significant bit (LSB) of each input code 100 representing 1 millivolt (mv) on line 17, while N+n=11, 2 11 = 2048, and the total number of different codes 102 that can be output by the analog-to-digital converter 18 is in the range of 0 to 2047.

[0020] In the lookup table 20, in calibration mode, the two analog-to-digital converter 18 actually generate 2 ∧ The N output code 102 is transmitted to the digital-to-analog converter 32 by the calibration controller 30. ∧N is correlated with the input code 100. The empirically developed transfer function 104 (Figure 2) from the input code 100 to the recorded output code 102 is nonlinear but monotonic and unique for each input code 100. In the illustrated example, the transfer function 104 is empirically established by observing the output of the analog-to-digital converter 18 in response to different input codes 100 being input to the digital-to-analog converter 32 in calibration mode. Furthermore, the illustrated method for popularizing the lookup table 20 is memoryless in the sense that mapping a value of a particular input code (e.g., 5) to a value of an output code (e.g., 14) is independent of the value of the previous input code (e.g., 4). If desired, each capture of an output code may include capturing multiple codes from the analog-to-digital converter 18, averaging those codes, and removing noise before mapping.

[0021] In the analog-to-digital conversion (or mission) mode, which is illustrated as an example in Figure 2, the first multiplexer 12 (Figure 1) receives the sampled voltage V IN The first multiplexer 12 receives the sampled voltage V under the control of the calibration controller 30. IN (V1) is output to the analog-digital controller 18, and the analog-digital controller 18 outputs the corresponding code to the third multiplexer 22. The calibration controller 30 causes the third multiplexer 22 to apply the code to the lookup table 20 via the read path 28.

[0022] Unknown sampled voltage V IN (V1) For each, the N+n bit output of the analog-to-digital converter 18 is retrieved in the lookup table 20, and its calibrated value (in the N bit input code) is output on line 50. Based on Figure 2, the unknown voltage V INWhen (V1) causes the analog-to-digital converter 18 to output a code for 37 units (for example), the lookup table 20 is used to output a code for 10 units on the output line 50. In the illustrated example, in mission mode, the lookup table 20 is used to select the stored input code whose corresponding output code is closest to the code output by the analog-to-digital converter 18. However, if the code output by the analog-to-digital converter 18 is equidistant from two stored output codes, the lookup table 20 is used to select the stored input code whose stored output code is the smaller of the two stored output codes. Thus, in the example shown in Figure 2, 37 is equidistant from 34 and 40, and 34 is smaller than 40, so the selected stored input code is 34.

[0023] A specific example shown is when the calibration controller 30 issues an input code 100 to 10 units in calibration mode, and the digital-to-analog converter 32 receives the voltage V of the 10 units. DAC This refers to a situation where (V1) is applied, and the voltage is converted by the analog-to-digital converter 18 into an output code 102 for 34 units, and the output code 100 (34 units) is correlated with the input code 102 for 10 units and recorded in the lookup table 20. In other words, when the system 10 is calibrated, a correlation is observed between the input code for 10 units and the output code for 34 units, and the observed output code (34 units) is associated with the input code (10 units) and stored in the lookup table 20. The transfer function 104 is based on calibration, and the correlations stored in the lookup table 20 are created by experiment (i.e., observation). However, this description is not limited to the illustrated example.

[0024] In the illustrated configuration, the digital-to-analog converter 32 has a calibration voltage V that covers the input range Vr of the analog-to-digital converter 18. DACIt is used to generate the linear output V of the digital-to-analog converter 32 in calibration mode. DAC This is input to the analog-to-digital converter 18. For each of such input codes 100, Vr / (2 ∧ At N) stepped intervals, N+n bit output codes 102 are output by the analog-to-digital converter 18. The lookup table 20 may include memory elements of the digital circuit. In the illustrated example, the output codes 102 on lines 24 and 28 in calibration mode are stored in the memory elements of the lookup table 20.

[0025] Therefore, during the calibration mode, the nonlinear input-output characteristics of the analog-to-digital converter 18 (circuit block) are acquired using the known input code 100. The calibration process, in which the lookup table 20 is populated, may be a relatively time-consuming process performed periodically but at long intervals. Subsequently, during the analog-to-digital conversion mode, an unknown sampled voltage V is acquired. IN In response, system 10 outputs output code 102 to the sampled voltage V IN The data is then digitally mapped to the output. The nonlinear processing performed by the analog-to-digital converter 18 can be performed at high speed, during which the output code of the nonlinear block is passed through the inversion of the block's transfer function 104 (Figure 2) acquired in calibration mode to obtain a linear output (e.g., the code output on line 50). In the illustrated configuration, the calibration process and the analog-to-digital conversion process can be advantageously performed without using complex arithmetic functions or hardware that requires considerable space and power.

[0026] If desired, the analog-to-digital converter 18 may be constructed as illustrated, for example, as described in relation to Figures 5 to 9. The analog-to-digital converter 18 may have a delay circuit and a delay comparator operating in parallel to generate 2 bits of digital information. The remaining delays from the multi-bit stages may be coupled by a coupler and applied to a series of single-bit stages. If desired, the first, second, and third to i-th single-bit stages may be constructed and operated in succession, providing each bit of the digital information to the lookup table 20. It is possible to design time-based units of the type used in the systems described thereafter and to operate time-based units at high speed, but they are inherently nonlinear. In the example of delay-based signal processing described thereafter in relation to Figures 5 to 9, the remaining signals passed in each stage are monotonic but nonlinear.

[0027] Referring here to Figures 3 and 4, the analog-to-digital converter system 10 may have two, three, four, or more channels. Figure 3 shows two channels. Figure 4 shows three channels. As shown in Figure 3, the second channel has a second analog-to-digital converter 110, a second lookup table 112, and a coupling circuit 114. The second analog-to-digital converter 110 is essentially the same as the first analog-to-digital converter 18 in the sense that both are made up of essentially the same components arranged in almost the same configuration. Nevertheless, due to differences in manufacturing, the two analog-to-digital converters 18 and 110 may have different transfer functions 104, and as a result, it may be desirable to calibrate these two devices 18 and 110 individually. A fourth multiplexer, similar to the third multiplexer 22 shown in Figure 1, is placed between the second analog-to-digital converter 110 and the second lookup table 112. The third and fourth multiplexers 22 can be constructed and operated in essentially the same way and are not shown in Figure 3 for clarity.

[0028] Figure 3 shows that the first channel is operating in calibration mode and the second channel is operating in analog-to-digital conversion mode. Thus, the first multiplexer 12 receives the calibration voltage V (via the MUX12 output, V1). DAC It is shown that the first analog-to-digital converter 18 receives the first lookup table 20, while the second multiplexer 14 receives the sampled voltage V (via the MUX14 output, V2). INv The diagram illustrates how the signal is sent to a second analog-to-digital converter 110 to generate an output code, which is then subjected to an inversion of the transfer function recorded in a second lookup table 112 for the second analog-to-digital converter 110 to generate a calibrated code, which is then output to line 50 via a coupler circuit 114.

[0029] If desired, the analog-to-digital converter system 10 may operate the second channel in calibration mode while the first channel operates in analog-to-digital conversion mode. In this case, the second multiplexer 14 applies a calibration voltage V DAC (V2) is sent to the second analog-to-digital converter 110 to populate the second lookup table 112, while the first multiplexer 12 receives the sampled voltage V IN (V1) is transmitted to the first analog-to-digital converter 18 to generate an output code, which is then subjected to the inversion of the transfer function recorded in the first lookup table 20 to generate a calibrated code, which is then output onto line 50 via the coupler circuit 114. In the illustrated configuration, the coupler circuit 114 is operated selectively under the control of the calibration controller 30.

[0030] Referring to Figure 4, the third channel may be provided with a third analog-to-digital converter 200 and a fifth multiplexer 202, the fifth multiplexer 202 being a digital multiplexer. In each of the three channels, buffers 204, 206, and 208 are positioned between the respective multiplexers 12, 14, and 202 and the respective analog-to-digital converters 18, 110, and 200. For clarity, buffers 204, 206, and 208 are not shown in Figures 1 and 3. Similarly, a suitable digital multiplexer may be positioned between the three analog-to-digital converters 18, 110, and 200 and the memory / digital processor system 300. The lookup tables 20 and 112 for the first and second channels, as well as the similar lookup table for the third channel, are part of the memory / digital processor system 300. Each of the three lookup tables operates as described above in relation to the first channel's lookup table 20.

[0031] As shown in Figure 4, the second sampled voltage V IN2 (2) is applied to the second and third channel multiplexers 14 and 202, and the first sampled voltage V IN (1) is applied to the first and second channel multiplexers 12 and 14, and the calibration voltage V DAC (D) is applied to all three multiplexers 12, 14, and 202. If desired, the analog-to-digital converter system 10 may be configured to receive and process the third and fourth sampled voltages (0) and (3) applied to the first and fourth multiplexers 12 and 202, respectively. All three channels and the digital-to-analog converter 32 operate under the control of a calibration controller 30, which is not shown in Figure 4 for clarity.

[0032] Therefore, if desired, one of the channels of the analog-to-digital converter system 10 may be calibrated while one or more of the other channels are used for analog-to-digital conversion. The multi-channel configuration has the advantage of being relatively easy to expand. In the illustrated configuration, all channels may be calibrated using only a single digital-to-analog converter 32, and the number of channels per system may be increased without a proportional increase in the high-linearity block, thus saving power and area. Furthermore, there is no need to match the requirements between different channels. In the illustrated configuration, each analog-to-digital converter 18, 100, and 200 may be calibrated independently, thereby reducing or eliminating the requirements for background estimation and calibration algorithms.

[0033] In another embodiment described herein, if the nonlinear analog-to-digital converter cannot exit mission mode, an auxiliary analog-to-digital converter of the same type may be used in a round-robin manner. That is, while the first analog-to-digital converter is in calibration phase, the other analog-to-digital converter operates in mission mode, and vice versa. In this embodiment described herein, the input and the output of the digital-to-analog converter are multiplexed into the first analog-to-digital converter and the auxiliary analog-to-digital converter.

[0034] Where desired, some or all of the elements of the devices and systems described herein may be integrated within an integrated circuit (IC) or formed on or on a single semiconductor die (not shown in the figures) according to various semiconductor and / or other processes. Conductive wires may be metallic structures formed in an insulating layer on the semiconductor die, doped regions (which may be silicided) formed on the semiconductor die, or doped semiconductor structures (which may be silicided) formed on the semiconductor die. Transistors used to implement some example circuit structures may be bipolar junction transistors (BJTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and may be n-type or p-type. Integrated devices and elements may also include resistors, capacitors, logic gates, and other suitable electronic devices not shown for clarity.

[0035] The analog-to-digital system 10 may have a good signal-to-noise ratio (SNR), operate at high speed, and function with lower-level technology nodes. According to one aspect of this description, advantages are achieved by providing a linear analog-to-digital converter system having highly nonlinear delay-based components (e.g., the type shown in Figure 5), but with relaxed area and power requirements, high-speed operation, and good scalability using technology nodes. In summary, this description may be used to provide a highly linear, high-speed analog-to-digital converter system 10 using inherently nonlinear analog blocks operably connected to digital circuits.

[0036] In terms of scalability, the performance of digital integrated circuits has improved significantly with CMOS scaling, but this has not been applicable to analog integrated circuits. As described herein, CMOS scaling can be used to improve performance in analog integrated circuits by employing time-domain (or delay-domain) signal processing. Therefore, analog-to-digital converter systems using time-to-digital converters (TDCs) are advantageous. Although time-to-digital converters can be inherently nonlinear, they can be designed to be memoryless and monotonic, and since they do not require significant feedback loops, they can be very fast and have very good bit error rate (BER) performance. These advantageous characteristics can be achieved, if desired, by constructing a backend for the analog-to-digital converter 18 using memoryless devices, as illustrated in Figures 5 to 9. As shown above, according to one aspect of this description, mapping a value of a particular input code (e.g., 5) to a value of an output code (e.g., 14) is independent of the previous value of the input code (e.g., 4). Furthermore, the backend of the analog-to-digital converter 18 can be constructed such that, during calibration, the corresponding output code (on line 24) also increases each time the input code (on line 36) increases, but it does not necessarily have to be linear.

[0037] This description offers many advantages. One such advantage is the ability to decouple coupled constraints. In particular, an effectively high-speed, linear analog-to-digital converter system can be constructed by combining at least three components: (1) a linear, low-speed digital-to-analog converter 32, (2) one or more nonlinear digital-to-analog converters 18, 110, and 200 formed from high-speed analog blocks, and (3) a memory / digital processing system 300 having one or more high-speed digital lookup tables 20 and 112.

[0038] Using the architecture described herein, high linearity requirements can be passed to the digital-to-analog converter 32 instead of the analog-to-digital converters 18, 110, and 200. This is advantageous because it is relatively easy to design and implement slow-operating analog circuits with linearity and accuracy. In accordance with this description, one or more analog-to-digital converters 18, 110, and 200 may be designed to operate at high speed by compromising linearity. However, the analog-to-digital converters 18, 110, and 200 can be coupled with lookup tables 20 and 112 to operate like linear analog-to-digital converters. Similarly, memories 20 and 122 may be implemented within the digital circuitry and configured for high speed.

[0039] Interfaces of external analog signals to high-speed digital processing cores generally require analog-to-digital converters. As data transmission speeds increase, analog-to-digital converters may be needed to operate at very high speeds with a good signal-to-noise ratio. Without the advantages described herein, such constraints can result in significant power losses and large area requirements for the supporting integrated circuits. These problems can be particularly pronounced at GHz rates due to the non-ideal nature of analog, which can limit performance. This description opens up a wide range of architectures by providing a lookup table-based analog-to-digital converter approach, using one or more analog-to-digital converters that are inherently nonlinear but can be calibrated to provide the superior performance of highly linear analog-to-digital converters.

[0040] The analog-to-digital converter 18 shown in Figure 1 may have a front end and a back end. The front end may perform a voltage-delay function. The back end may perform a delay-digital function. According to one aspect of this description, the front end of the analog-to-digital converter 18 may include one or more voltage-delay devices for converting an analog signal on line 17 into delayed signals A0 and B0 on ​​lines 488 and 490 (Figure 5), such that the delayed signals A0 and B0 represent a voltage V1 on line 17. A voltage-delay device in the front end that can be used to generate delayed signals A0 and B0 based on an input voltage V1 may be constructed and operated as described, for example, in U.S. Patent No. 10,673,456 (based on U.S. Patent Application No. 16 / 410,698). A voltage-delay device may include, for example, the conversion and folding circuit described in U.S. Patent No. 10,673,456, which includes a voltage-delay converter block including a preamplifier for converting a voltage signal to a delayed signal, and a folding block including a logic gate coupled to the preamplifier for selecting which of the delayed signals arrive earlier and which arrive later.

[0041] An example of a voltage-delay device that may be used in the front end of an analog-to-digital converter 18 to generate delayed signals A0 and B0 based on an input voltage V1 is shown in U.S. Patent Application No. 17 / 131,981, filed December 23, 2020. A voltage-delay device constructed in accordance with U.S. Patent Application No. 17 / 131,981 may, for example, have first and second comparators connected to first and second lines carrying complementary voltages representing the input voltage V1, and when the complementary voltage reaches an appropriate threshold voltage, generate first and second output signals during the active phase such that the delay between the output signals represents the input voltage V1. However, this description is not limited to the devices and processes described in detail herein. Other suitable devices may implement suitable voltage-delay functions in the front end of an analog-to-digital converter 18. As stated above, U.S. Patent No. 10,673,456 and U.S. Patent Application No. 17 / 131,981 are incorporated herein by reference in their entirety. [Patent Document 8] U.S. Patent Application No. 17 / 131,981

[0042] An example of the backend of an analog-to-digital converter is shown in Figures 5 to 9. The backend may have, for example, a multibit stage 798 and first to i-th single-bit stages 7102 and 7104 connected in series with the multibit stage 798. If desired, the backend may have three, four, or more such single-bit stages (i=3, 4, or more). The single-bit stages 7102 and 7104 shown in Figure 5 are an example of consecutive nonlinear stages. The backend receives delayed signals A0 and B0 from the frontend voltage-delay circuit. The timing of the delayed signals A0 and B0 has a delay that represents the voltage V1 on line 17. The backend works with the calibration engine / controller 740 to generate the corresponding multibit digital code that is output on line 24 (Figure 1). Thus, the digital code on line 24 predictably corresponds to a value very close to the voltage V1 on line 17.

[0043] The multi-bit stage 798 (Figure 5) may have delay circuits and delay comparators operating in parallel to generate M bits of digital information on lines 330, 332, 334, and 336. In the illustrated example, M = 2. However, M can be greater than 2. This description is not limited to the illustrated example. The remaining delay from the multi-bit stage 798 may be coupled by a coupler 304 and applied to a first single-bit stage 7102. If desired, the first to i-th single-bit stages 7102 and 7104 may be constructed and operated as consecutive stages to provide each bit of the digital information to the calibration engine / controller 740.

[0044] The first stage 798 may have, for example, four delay comparators 306, 308, 310, and 312, connected to the coupler 304. However, this description is not limited to the details of the example shown. This description may be implemented using a first stage which may have fewer or more delay comparators than four, if desired. In the configuration shown in the figure, the first stage 798 generates two bits of digital information for the calibration engine / controller 740. In the illustrated embodiment, each of the consecutive stages 7102 and 7104 generates a single bit of digital information for the calibration engine / controller 740.

[0045] In the illustrated example, the rising edge of signal B0 on ​​line 490 precedes the rising edge of signal A0 on line 488. The first signal A0 is applied to the threshold input 494 of delay comparators 306, 308, 310, and 312. In the illustrated configuration, for example, delay comparators 306, 308, 310, and 312 are essentially identical to one another. The second signal B0 is applied to four different delay circuits 314, 316, 318, and 320, which in turn apply to four corresponding signals B on their respective lines 322, 324, 326, and 328. 04 B 03 B 02 , and B 01 Generates.

[0046] Corresponding signal B 04 B 03 B 02 , and B 01 The timing of is delayed by a different known amount equal to or less than the maximum gain of the front end relative to the timing of signal B0 on ​​line 490. 04 B 03 B 02 , and B 01 This is applied to the first input 492 of each delay comparator 306, 308, 310, and 312. The first delay comparator 306 determines which signal (B 04The first delay comparator 306 issues a code signal on line 330 indicating which signal (B) (or A0) arrives first. Similarly, the second delay comparator 308 issues a code signal on line 330 indicating which signal (B) 03 Alternatively, A0) issues a code signal on line 332 indicating which signal is the first to reach the second delay comparator 308. Similarly, the third and fourth delay comparators 310 and 312 issue code signals on lines 334 and 336 indicating which signal is the first to reach the third and fourth delay comparators 310 and 312.

[0047] Because the delay circuits 314, 316, 318, and 320 are different from each other, the delayed signal B 04 B 03 B 02 , and B 01 The timing of the rising edges of the signals differs from one another. Each of the delay comparators 306, 308, 310, and 312 issues a coded signal to the respective digital lines 330, 332, 334, and 336 to the calibration engine / controller 740. The coded signals on lines 330, 332, 334, and 336 are functionally related to the difference between the rising edges of input signals A0 and B0, and therefore functionally related to the voltage V1 on line 17.

[0048] Since the amounts of delay provided by the four delay comparators 306, 308, 310, and 312 are different from each other, the code signals 330, 332, 334, and 336 provide four binary data points for determining two bits of the output. For example, B0 precedes A0, and B 01 If B0 precedes A0, the calibration engine / controller 740 determines that the delay between the timings of signals A0 and B0 is greater than the delay provided by the four delay circuits 320. Similarly, if B0 precedes A0, and A0 precedes B 02 B 03 , and B 04 If this precedes the first one, the calibration engine / controller 740 determines that the delay between the timings of signals A0 and B0 is less than the delays provided by the third, second, and first delay circuits 318, 316, and 314, respectively.

[0049] If desired, the structure and operation of delay comparators 306, 308, 310, and 312 may be the same as those of delay comparator 482 described later. In operation, delay comparators 306, 308, 310, and 312 generate their respective delay signals IN4, IN3, IN2, and IN1 on their respective output lines 338, 340, 342, and 344. The delay signals IN4, IN3, IN2, and IN1 are applied to coupler 304 by the output lines 338, 340, 342, and 344. In the illustrated configuration, the delay circuits 314, 316, 318, and 320 are different from each other, resulting in a difference in the amount of delay, while delay comparators 306, 308, 310, and 312 are essentially the same. Therefore, the timing of the rising edges of the delay signals IN4, IN3, IN2, and IN1 are different from each other.

[0050] In the example shown in Figure 6, the coupler 304 has two fifth delay circuits 350 and 352, two AND gates 354 and 356, and a sixth delay circuit 358. In the illustrated configuration, the fifth delay circuits 350 and 352 are essentially the same as each other. However, this description is not limited to the details of the structure illustrated and described herein. The third and fourth delay signals IN2 and IN1 are applied to the fifth delay circuits 350 and 352 on conductive wires 342 and 344, and the first and second delay signals IN4 and IN3 are applied to the AND gates 354 and 356 on conductive wires 338 and 340. The output signals from the fifth delay circuits 350 and 352 are also applied to the AND gates 354 and 356 on conductive wires 362 and 364, respectively. The output signal from one AND gate 356 is applied to the sixth delay circuit 358 on the conductive wire 360, and the other AND gate 354 generates signal A1 on the conductive wire 488A1. The sixth delay circuit 358 generates signal B1 on the conductive wire 490B1.

[0051] In operation, the timing of the rising edges of the signals output from the fifth and sixth delay circuits 350, 352, and 358 onto the conductive lines 362, 364, and 490 is delayed relative to the timing of the rising edges of the signals input to the delay circuits 350, 352, and 358, respectively. The timing of the rising edges of the signals output from the AND gates 354 and 356 on lines 488A1 and 360 corresponds to the later arrival timings of the signals input to the AND gates 354 and 356, respectively. The relative timing of the rising edges of signals A1 and B1 on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the voltage V1 on line 17 (Figure 1). In other words, the delay circuits 350, 352, and 358, and the logic gates 354 and 356 establish a transfer function between the delays of the incoming signals IN4, IN3, IN2, and IN1 and the delays of the first and second signals A1 and B1.

[0052] In the illustrated configuration, the transfer function is as follows: [A] If the timing of the signal on line 338 precedes the timing of the signal on line 362 (the timing of the signal on line 362 corresponds to the timing of the signal on line 342 delayed by the fifth delay circuit 350), then the timing of the signal on line 488A1 corresponds to the timing of the signal on line 362. However, if the timing of the signal on line 362 precedes the timing of the signal on line 338, then the timing of the signal on line 488A1 corresponds to the timing of the signal on line 338. [B] If the timing of the signal on line 340 precedes the timing of the signal on line 364 (the timing of the signal on line 364 corresponds to the timing of the signal on line 344 delayed by the fifth delay circuit 352), then the timing of the signal on line 360 ​​corresponds to the timing of the signal on line 364. However, if the timing of the signal on line 364 precedes the timing of the signal on line 340, then the timing of the signal on line 360 ​​corresponds to the timing of the signal on line 340. [C] The timing of the signal on line 490B1 corresponds to the timing of the signal on line 360, which has been delayed by the sixth delay circuit 358.

[0053] The amount by which delay elements 350, 352, and 358 delay the signals transmitted through them can be selected to maximize or improve the gain of the first and second signals A1 and B1 as much as possible. The coupler 304 operates in a delay mode where the gain is related to the delay (rather than the voltage). If the gain of the first and second signals A1 and B1 is too low, i.e., if the first and second signals A1 and B1 are too close to each other, the information represented by the relative timing of these signals may become difficult to resolve.

[0054] One aspect of this description is that the timing of signals on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the timing of signals on lines 338, 340, 342, and 344. If a certain set of signal timings on lines 338, 340, 342, and 344 constitutes a first set of signal timings on lines 488A1 and 490B1, then whenever the same set of signal timings occurs on lines 338, 340, 342, and 344, it can be expected that the same first set of signal timings will occur on lines 488A1 and 490B1. Similarly, if another set of signal timings on lines 338, 340, 342, and 344 constitutes a second set of signal timings on lines 488A1 and 490B1, then whenever another set of signal timings occurs on lines 338, 340, 342, and 344, it can be expected that the same second set of signal timings will occur on lines 488A1 and 490B1. Furthermore, since the signal timings on lines 338, 340, 342, and 344 are functionally (e.g., predictably) related to voltage V1, the signal timings on lines 488A1 and 490B1 are also functionally related to voltage V1.

[0055] Referring again to Figure 5, the signals A1 and B1 generated by the coupler 304 are applied to the second stage 7102 on output lines 488A1 and 490B1. The second stage (which is the remaining stage of the first) 7102 is coupled to the first stage 798 (via the coupler 304), and the i-th stage 7104 (which is the remaining stage of the second in the illustrated example) is coupled to the second stage 7102.

[0056] In the illustrated example, stages 7102 and 7104 from the second to the ith stage each include an AND gate (e.g., AND gate 476 for stage 7102 and AND gate 478 for stage 7104) and a delayed comparator (e.g., delayed comparator 482 for stage 7102 and delayed comparator 484 for stage 7104). However, the illustrated AND gates are merely examples of logic gates that may be employed in accordance with this description. If desired, this description may be implemented with or without AND gates and / or with or without gates other than AND gates.

[0057] Furthermore, in the illustrated configuration, AND gates 476 and 478 may be essentially identical to each other, and delay comparators 482 and 484 may be essentially identical to each other. Conductive output lines 488A1 and 490B1 from coupler 304 are coupled to the inputs of the first AND gate 476 and delay comparator 482. Specifically, conductive line 488A1 is coupled to the first input 492 of delay comparator 482, and conductive line 490B1 is coupled to the threshold input 494 of delay comparator 482.

[0058] The output line 488A2 from the AND gate 476 is electrically coupled to one of the inputs of the AND gate 478 and to input 492 of the delay comparator 484. The conductive line 490B2 from the first delay comparator 482 is electrically coupled to the other input of the AND gate 478 and to the threshold input 494 of the delay comparator 484. The patterns generated by the second and third stages 7102 and 7104 can be continued for any desired number of additional stages. Each successive stage has AND gates and delay comparators that are essentially identical to those of the second and third stages 7102 and 7104, and are similarly electrically coupled to the AND gates and delay comparators of the preceding stage.

[0059] In operation, signal A N and B N (N=1, 2, 3... for stages 7102 and 7104... respectively) are applied to AND gates 476 and 478, respectively, and the corresponding signal A is applied to AND gates 476 and 478. N+1 This generates the following signal A for each of AND gates 476 and 478. N+1 The timing of the rising edge is, signal A N and B N Track the timing of the rising edge of the one that arrives later. In particular, for AND gates 476 and 478, signal A N+1 The timing of the rising edge is, signal A N and B N At the timing of the rising edge of the one that arrives first, signal A N and B N The rising edge of the one that arrives later is signal A N and B N It is equal to the sum of the amounts of time related to how much the first one to arrive lags from the rising edge. As shown in Figure 7, the AND-gate delay 7100 introduced by each AND gate is linearly related to the absolute value of the input signal delay T_IN, where the input signal delay T_IN is the signal A input to each AND gate. N and B NThis is the difference in timing between the two. In the illustrated configuration, the relationship between the AND gate delay 7100 and the input signal delay T_IN is A N or B N It is linear regardless of whether it happens first or second.

[0060] Signal A N and B N These are also applied to the inputs 492 and 494 of the delay comparators 482 and 484, respectively, to the delay comparators 482 and 484, respectively, to the corresponding signal B N+1 This generates the signal B for each of the delay comparators 482 and 484. N+1 The timing of the rising edge is, signal A N and B N The timing of the rising edge of the one that arrived first is tracked. In particular, for one of the delay comparators 482 and 484, signal B N+1 The timing of the rising edge is (1) signal A N and B N (2) The timing of the rising edge of the first one to arrive is equal to the sum of the comparator delay 7102 (Figure 7), which is logarithmically inversely proportional to the absolute value of the input signal delay T_IN (in other words, the comparator delay increases when the input values ​​are similar, and decreases when the difference between the two inputs to the comparator increases).

[0061] Subtracting the AND gate delay 7100 from the comparator delay 7102 yields the output signal delay T_OUT (Figure 8) for any given single-bit stages 7102 and 7104. If the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, then the output signal delay T_OUT is a positive value (this is the signal B generated by the respective delay comparators 482 and 484). N+1 The rising edge of the signal A is generated by the respective AND gates 476 and 478. N+1 (This means it precedes the rising edge of the signal B). On the other hand, if the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is a negative value (this means that the signal B N+1The rising edge of which is delayed with respect to the rising edge of the corresponding signal A N+1 (which means that it is delayed relative to the rising edge of the corresponding signal A). The positive or negative characteristic of the output signal delay T_OUT is reported to the calibration engine / controller 740 on the signal line of the subsequent delay comparator.

[0062] In operation, the first delay comparator 482 issues a first sign signal (“1” or “0”) on a digital line 408 (an example of a digital output) to the calibration engine / controller 740. The first sign signal (an example of a digital signal according to this description) is based on which of the rising edges of signals A1 and B1 is received first by the first delay comparator 482. As a result, the first sign signal reflects the order of the rising edges of signals A1 and B1 applied to the first input 492 and the threshold input 494 of the delay comparator 482. The AND gate 476 and the delay comparator 482 generate signals A2 and B2 applied to the AND gate 478 and the delay comparator 484 of the third stage 104. The delay comparator 484 outputs a second sign signal (“1” or “0”) on a second digital line 412 to the calibration engine / controller 40. The second sign signal is based on which of the rising edges of signals A2 and B2 is received first by the second delay comparator 484. As a result, the second sign signal reflects the order of the rising edges of signals A2 and B2 applied to the inputs 492 and 494 of the second delay comparator 484.

[0063] The delay between signals A1 and B1 can be predicted as a function of the input voltage V1, and vice versa. Also, the signals A N+1 and B N+1 The delay between is the signal A received from the previous stage N and B NThe code signal output by the cascaded stage delay comparator can be predicted as a function of voltage V1, and vice versa, so the code consisting of the code signals can be reliably compared to a predefined correlation to determine an approximation of the input voltage V1. In operation, the timing of the signals on lines 488A1 and 490B1 is functionally (e.g., predictably) related to the timing of the signals on lines 488 and 490, as described above. The timing of the signals on lines 488A2 and 490B2 is functionally (e.g., predictably) related to the timing of the signals on lines 488A1 and 490B1. The timing of the signals on lines 488A3 and 490B3 is functionally (e.g., predictably) related to the timing of the signals on lines 488A2 and 490B2, and so on.

[0064] Furthermore, if a certain set of signal timings on lines 488 and 490 becomes the first set of signal timings on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc., then when the same set of signal timings occurs on lines 488 and 490, it can be expected that the same first set of signal timings will always occur on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc. Similarly, if another distinct set of signal timings on lines 488 and 490 constitutes a second set of signal timings on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc., then whenever another set of signal timings occurs on lines 488 and 490, it can be expected that the same second set of signal timings will occur on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc. Also, since the signal timings on lines 488 and 490 are functionally (e.g., predictably) related to the input voltage V1, the signal timings on lines 488A1, 490B1, 488A2, 490B2, 488A3, 490B3, etc., which determine the code signals of the output code, are also functionally related to the input voltage V1.

[0065] Referring here to Figure 9, the delay comparator 482 has a comparator circuit 2083, which has first, second, third, fourth, fifth, sixth, seventh, and eighth transistors 2400, 2402, 2404, 2406, 2408, 2410, 2412, and 2414. In the illustrated example, the timing of the delay comparator 482 is controlled by signals from a clock (CLK) applied to the gates of the first and fourth transistors 2400 and 2406 on conductive line 2122. The first and second signals A1 and B1 on lines 488A1 and 490B1 are applied to the gates of the sixth and fifth transistors 2410 and 2408, respectively. The drains of the first, second, and fifth transistors 2400, 2402, and 2408 are electrically connected to each other and are also electrically connected to the third and eighth transistors 2404 and 2414 via the first conductive wire 2416. The drains of the third, fourth, and sixth transistors 2404, 2406, and 2410 are similarly electrically connected to each other and are also electrically connected to the second and seventh transistors 2402 and 2412 via the second conductive wire 2418.

[0066] The first and second conductive wires 2416 and 2418 of the comparator circuit 2083 are electrically connected to the sign-out circuit 2420 via the third and fourth conductive wires 2422 and 2424, respectively. As shown in Figure 9, the sign-out circuit 2420 is merged with the comparator circuit 2083. The sign-out circuit 2420 has first, second, third, and fourth transistors 2426, 2428, 2430, and 2432. The third conductive wire 2422 is electrically connected to the gate and source of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively, while the fourth conductive wire 2424 is electrically connected to the source and gate of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively.

[0067] In operation, when the delay comparator 482 is activated by the clock signal on line 2122, a sign signal is generated in the sign-out circuit 2420 on line 408. The sign signal is transferred on line 408 to the calibration engine / processor 40, which represents the order in which output signals A1 and B1 reach the first and threshold inputs 492 and 494 of the delay comparator 482. The operation of the sign-out circuit 2420 is controlled by an inverted clock signal CLKZ applied to the gates of the third and fourth transistors 2430 and 2432 of the sign-out circuit 2420. The inverted clock signal CLKZ is an inverted version of the clock signal applied to the gates of the first and fourth transistors 2400 and 2406 of the comparator circuit 2083 on line 2122.

[0068] The third and fourth conductive wires 2422 and 2444 are also electrically connected to the delay-out circuit 2450. As shown in Figure 9, the delay-out circuit 2450 is merged with the comparator circuit 2083. The delay-out circuit 2450 has first, second, and third transistors 2442, 2444, and 2446. The third conductive wire 2422 is electrically connected to the gates and sources of the first and second transistors 2442 and 2444 of the delay-out circuit 2450, respectively, while the fourth conductive wire 2424 is electrically connected to the sources and gates of the first and second transistors 2442 and 2444 of the delay-out circuit 2450, respectively.

[0069] In operation, the delayed signal B2 is generated on line 490B2, which is electrically connected to the drains of both the first and second transistors 2442 and 2444 of the delay-out circuit 2450. The timing of the rising edge of the delayed signal B2 on line 490B2 is the comparator delay 7102 (Figure 7), relative to the timing of whichever of the rising edges of signals A1 and B2 on inputs 492 and 494 arrives first. The operation of the delay-out circuit 2450 (Figure 9) is controlled by the same inverting clock signal CLKZ applied to the third and fourth transistors 2430 and 2432 of the sign-out circuit 2420. The inverting clock signal CLKZ is applied to the gate of the third transistor 2446 of the delay-out circuit 2450. The drain of the third transistor 2446 of the delay-out circuit 2450 is electrically connected to the drains of the first and second transistors 2442 and 2444 of the delay-out circuit 2450.

[0070] The above description is an example. This description includes changes, modifications, and variations to the subject matter described herein that fall within the scope of this application, including the attached claims. If desired, for example, one or more clockless delay comparators may be used in the backend of the analog-to-digital converter 18.

[0071] As used herein, the term “including” means including but not limited to; the term “based on” means based at least in part; and where the specification or claims refer to “a certain,” “first,” or “another” element or equivalent, it includes one or more such elements, but does not require or exclude two or more such elements.

[0072] The following are examples of new claims that are desired to be made and protected:

Claims

1. It is an analog-to-digital converter system, A calibration circuit element having an N-bit digital code input and a calibration voltage output based on the digital code input, A first analog-to-digital converter (ADC) having an input operable to be connected to the calibration voltage output or the sampled voltage, wherein the first analog-to-digital converter is operable to output a first digital output code of N+n bits (N+n>N, n>0) based on the calibration voltage output, and to output a second digital output code based on the sampled voltage and the first digital output code, Analog-to-digital converter systems, including [specific component / feature].

2. The analog-to-digital converter system according to claim 1, The calibration circuit element includes a digital-to-analog converter, The analog-to-digital converter system further includes a first multiplexer connected to the digital-to-analog converter and the first analog-to-digital converter, the first multiplexer selectively transmitting the calibration voltage output and the sampled voltage to the first analog-to-digital converter.

3. The analog-to-digital converter system according to claim 2, An analog-to-digital converter system further comprising a calibration controller connected to the digital-to-analog converter and the first multiplexer, the calibration controller transmitting the digital code input to the digital-to-analog converter, and while the digital code input is transmitted to the digital-to-analog converter, causing the first multiplexer to transmit the calibration voltage output to the first analog-to-digital converter.

4. The analog-to-digital converter system according to claim 3, An analog-digital converter system further comprising a second analog-digital converter connected to the digital-analog converter, the second analog-digital converter receiving the calibration voltage output and the sampled voltage from the digital-analog converter, and generating a digital output code based on the calibration voltage output and the sampled voltage.

5. The analog-to-digital converter system according to claim 4, An analog-to-digital converter system further comprising a second multiplexer connected to the aforementioned digital-to-analog converter and the second analog-to-digital converter, the second multiplexer selectively transmitting the calibration voltage output to the second analog-to-digital converter.

6. The analog-to-digital converter system according to claim 1, An analog-to-digital converter system further comprising a lookup table for storing the first digital output code in relation to the digital code input.

7. The analog-to-digital converter system according to claim 1, An analog-to-digital converter system comprising a first analog-to-digital converter including a circuit that converts a voltage into a delayed signal and generates first and second digital output codes based on the delayed signal.

8. A lookup table-based analog-to-digital converter system, A digital-to-analog converter having an N-bit digital code input and a calibration voltage output based on the digital code input, A first analog-to-digital converter coupled to a calibration voltage output and a sampled voltage input, the first analog-to-digital converter being operable to output a first digital output code of N+n bits (N+n>N, n>0) based on the calibration voltage output, and to output a second digital output code based on the sampled voltage input and the first digital output code, A lookup table connected to the first analog-to-digital converter, the lookup table storing the first digital output code in relation to the digital code input, A lookup table-based analog-to-digital converter system, including [specific component / feature].

9. A lookup table-based analog-to-digital converter system according to claim 8, A lookup table-based analog-digital converter system further comprising a first multiplexer connected to the digital-to-analog converter and the first analog-to-digital converter, the first multiplexer selectively transmitting one of the calibration voltage output and the sampled voltage input to the first analog-to-digital converter.

10. A lookup table-based analog-to-digital converter system according to claim 9, A lookup table-based analog-digital converter system, further comprising a calibration controller connected to the digital-to-analog converter and the first multiplexer, the calibration controller transmitting the digital code input to the digital-to-analog converter, and while the digital code input is transmitted to the digital-to-analog converter, causing the first multiplexer to transmit the calibration voltage output to the first analog-to-digital converter.

11. A lookup table-based analog-to-digital converter system according to claim 10, A lookup table-based analog-digital converter system further comprising a second analog-digital converter connected to the digital-analog converter, the second analog-digital converter receiving the calibration voltage output and the sampled voltage input from the digital-analog converter, and generating a digital output code based on the calibration voltage output and the sampled voltage input.

12. A lookup table-based analog-to-digital converter system according to claim 11, A lookup table-based analog-digital converter system further comprising a second multiplexer connected to the aforementioned digital-to-analog converter and the second analog-to-digital converter, the second multiplexer selectively transmitting the calibration voltage output to the second analog-to-digital converter.

13. A lookup table-based analog-to-digital converter system according to claim 8, A lookup table-based analog-to-digital converter system, wherein the first analog-to-digital converter includes a circuit that converts a voltage into a delayed signal and generates the first and second digital output codes based on the delayed signal.

14. A method for calibrating an analog-to-digital converter system, The digital-to-analog converter generates a calibration voltage based on an N-bit digital input code, A first analog-to-digital converter generates a first digital output code of N+n bits (N+n>N, n>0) based on the calibration voltage, A second digital output code is generated based on the voltage sampled by the first analog-to-digital converter and the first digital output code, The first digital output code is stored in a lookup table in relation to the digital input code, Methods that include...

15. A calibration method according to claim 14, A calibration method further comprising using a first multiplexer to selectively transmit one of the calibration voltage and the sampled voltage to the first analog-to-digital converter.

16. The calibration method according to claim 15, Transmitting the aforementioned digital input code to the aforementioned digital-to-analog converter, The digital input code is transmitted to the digital-to-analog converter, while the calibration voltage is transmitted to the first analog-to-digital converter. A calibration method further including the following.

17. A calibration method according to claim 16, A calibration method further comprising causing a second analog-to-digital converter to receive the calibration voltage from the digital-to-analog converter and to generate a digital output code based on the calibration voltage and the sampled voltage.

18. A calibration method according to claim 14, Calibration method wherein the first analog-to-digital converter includes a circuit for converting a voltage into a delayed signal, and the first and second digital output codes are generated based on the delayed signal.

Images