Electro-optical devices and electronic equipment

Abstract

To provide an electro-optical device in which the output voltage of a temperature detection circuit is not easily affected by the parasitic capacitance between a temperature detection element and wiring, and an electronic apparatus.SOLUTION: In an electro-optical device 100, on the outside of a display area 10a, a temperature detection element 11 is provided in which a plurality of diodes D are electrically connected in series by relay parts P1, P2. On the outside of the display area 10a, common potential wiring 8a provided with an opening 8a0 is provided, and the temperature detection element 11 is located inside the opening 8a0 in plan view. With this, a parasitic capacitance with a large capacitance is not present between the relay parts P1,P2 and the common potential wiring 8a. On the inside of the opening 8a0 in plan view, an island-like light-shielding layer 8e on the same layer as the common potential wiring 8a is provided separate from the common potential wiring 8a.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device provided with a temperature detection element, and an electronic device. [Background technology]

[0002] In electro-optical devices such as liquid crystal devices, a technology has been proposed in which a temperature detection element is provided outside the display area and the driving conditions of the electro-optical device are corrected based on the detection results of the temperature detection element. In this case, if a signal wiring that supplies an AC signal is provided near the temperature detection element, the temperature detection element may be affected by potential changes in the signal wiring, which may reduce the temperature detection accuracy. Therefore, a technology has been proposed in which a constant potential wiring that applies a constant potential is provided as a shielding layer between the temperature detection element and the signal wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-73810 Summary of the Invention [Problem to be solved by the invention]

[0004] However, even when constant-potential wiring is used as a shielding layer, noise may occur in the constant potential applied to the constant-potential wiring used as a shielding layer when the electro-optical device is driven. As a result, if the noise affects the temperature detection element via the parasitic capacitance between the constant-potential wiring and the temperature detection element, the temperature detection accuracy of the temperature detection element may decrease. Therefore, when wiring overlaps the temperature detection element in a planar view, there is a problem in that the temperature detection element is easily affected by the parasitic capacitance between the temperature detection element and the wiring. [Means for solving the problem]

[0005] In order to solve the above problem, one aspect of the electro-optical device according to the present invention is characterized in that it comprises wiring having an opening outside the display area, and a temperature detection element that is provided outside the display area and inside the opening in a planar view.

[0006] Another aspect of the electro-optical device of the present invention comprises a temperature detection element provided outside a display area and wiring having a portion that overlaps the temperature detection element in a planar view, wherein the temperature detection element has a first diode, a second diode, and an electrode that electrically connects the first diode and the second diode in series, the first diode and the second diode being arranged along a first direction, and the electrode has a portion whose width in a direction along a second direction that intersects with the first direction is narrower than the width in the direction along the second direction of the semiconductor layer that constitutes the first diode and the semiconductor layer that constitutes the second diode.

[0007] Yet another aspect of the electro-optical device according to the present invention comprises a temperature detection element provided outside the display area, wiring having a portion overlapping the temperature detection element in a planar view, and a complementary transistor having an N-channel transistor and a P-channel transistor outside the display area, wherein the temperature detection element has a first diode, a second diode, and an electrode that electrically connects the first diode and the second diode in series, and the distance between the semiconductor layer constituting the first diode and the semiconductor layer constituting the second diode is equal to or less than the distance between the semiconductor layer constituting the N-channel transistor and the semiconductor layer constituting the P-channel transistor.

[0008] Yet another aspect of the electro-optical device of the present invention comprises a plurality of data lines provided in a display area, a common potential wiring having a portion overlapping each of the plurality of data lines in a planar view, a temperature detection element outside the display area overlapping with the wiring in a planar view, a selection circuit electrically connected to each of the plurality of data lines, and a control circuit that controls the selection circuit for each horizontal scanning period during a precharge period, wherein the plurality of horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to some of the plurality of data lines, and a second horizontal scanning period in which the precharge signal is supplied to another portion of the plurality of data lines different from the first portion.

[0009] Yet another aspect of the electro-optical device of the present invention comprises a plurality of data lines provided in a display area, a common potential wiring having a portion overlapping each of the plurality of data lines in a planar view, a temperature detection element outside the display area overlapping with the wiring in a planar view, a selection circuit electrically connected to each of the plurality of data lines, and a control circuit that controls the selection circuit for each horizontal scanning period during a precharge period, wherein the plurality of horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to all of the plurality of data lines, and a second horizontal scanning period in which a precharge signal is not supplied to all of the plurality of data lines.

[0010] The electro-optical device according to the present invention is used in electronic equipment. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of an electro-optical device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is an explanatory diagram schematically showing a cross section of the electro-optical device shown in FIG. [Figure 3] FIG. 3 is a circuit block diagram showing the electrical configuration of the first substrate shown in FIG. 2. [Figure 4] FIG. 4 is an explanatory diagram of a data line driving circuit and the like shown in FIG. [Figure 5] 2 is a timing chart for displaying an image in the electro-optical device shown in FIG. [Figure 6] FIG. 4 is an explanatory diagram of the temperature detection circuit shown in FIG. 3. [Figure 7] FIG. 7 is an explanatory diagram schematically showing a cross section of the temperature detection element and the like shown in FIG. 6. [Figure 8] FIG. 2 is an explanatory diagram of a comparative example to the first embodiment of the present invention. [Figure 9] FIG. 10 is a diagram showing the relationship between precharge and the output voltage of the temperature detection circuit. [Figure 10] 4 is a graph showing the effect of a parasitic capacitance of the temperature detection element shown in FIG. 3 on the output voltage of the temperature detection circuit. [Figure 11] FIG. 4 is an explanatory diagram of an electro-optical device according to a second embodiment of the present invention. [Figure 12] 12 is an explanatory diagram schematically showing a cross section of the temperature detection element and the like shown in FIG. 11. [Figure 13] FIG. 10 is an explanatory diagram of an electro-optical device according to a modified example of the second embodiment of the present invention. [Figure 14] FIG. 10 is an explanatory diagram of an electro-optical device according to a third embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view of the temperature detection element shown in FIG. [Figure 16] FIG. 10 is an explanatory diagram of an electro-optical device according to a first modification of the third embodiment of the present invention. [Figure 17] FIG. 10 is an explanatory diagram of an electro-optical device according to a second modification of the third embodiment of the present invention. [Figure 18] FIG. 10 is an explanatory diagram of precharging in odd-numbered frames of an electro-optical device according to a fourth embodiment of the present invention. [Figure 19] FIG. 10 is an explanatory diagram of precharging in an even-numbered frame of an electro-optical device according to a fourth embodiment of the present invention. [Figure 20] FIG. 10 is an explanatory diagram of precharging of an electro-optical device according to a fifth embodiment of the present invention. [Figure 21] 1 is a block diagram showing an example of the configuration of a projection display device to which the present invention is applied. [Figure 22] FIG. 22 is an explanatory diagram of the light path shift element shown in FIG. 21. DETAILED DESCRIPTION OF THE INVENTION

[0012] An embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, each layer and each component is shown at a different scale so that they can be easily recognized. When describing the arrangement of layers formed on the first substrate, the upper layer side or surface side refers to the side opposite the side where the substrate main body of the first substrate is located (the side where the counter substrate and liquid crystal layer are located), and the lower layer side refers to the side where the substrate main body of the first substrate is located. When describing the arrangement of layers formed on the second substrate, the upper layer side or surface side refers to the side opposite the side where the substrate main body of the counter substrate is located (the side where the first substrate and liquid crystal layer are located), and the lower layer side refers to the side where the substrate main body of the second substrate is located. In the present invention, the term "planar view" refers to a view from the normal direction to the first substrate 10 or the second substrate 20.

[0013] 1. Embodiment 1 1-1. Specific configuration of the electro-optical device 100 FIG. 1 is a plan view showing an example of the configuration of an electro-optical device 100 according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram schematically illustrating a cross section of the electro-optical device 100 shown in FIG. 1. The electro-optical device 100 shown in FIGS. 1 and 2 is a liquid crystal device and includes an electro-optical panel 100p made of a liquid crystal panel. In the electro-optical device 100, the first substrate 10 and the second substrate 20 are bonded together with a predetermined gap therebetween by a sealant 107, which is provided in a frame shape along the outer edge of the second substrate 20. The sealant 107 is an adhesive made of a photocurable resin, a thermosetting resin, or the like, and contains a gap material 107a such as glass fiber or glass beads to maintain a predetermined distance between the two substrates. In the electro-optical device 100, an electro-optical layer 50 made of a liquid crystal layer is provided between the first substrate 10 and the second substrate 20 within the region surrounded by the sealant 107. The sealant 107 has a discontinuous portion 107c formed therein to serve as a liquid crystal injection port, and this discontinuous portion 107c is sealed with a sealing material 108 after the liquid crystal material is injected. Note that if the liquid crystal material is injected using a dropping method, the discontinuous portion 107c is not formed. The first substrate 10 and the second substrate 20 are both rectangular, and a display area 10a is provided as a rectangular area approximately in the center of the electro-optical device 100. Corresponding to this shape, the sealant 107 is also provided in a substantially rectangular shape, and a rectangular frame-shaped peripheral area 10c is formed outside the display area 10a.

[0014] In the display region 10a, two sides extending in the X direction are defined as a first side 10a1 and a second side 10a2, and two sides extending in the Y direction are defined as a third side 10a3 and a fourth side 10a4. In the peripheral region 10c of the first substrate 10, a data line driving circuit 101 is provided between an end of the first substrate 10 and the first side 10a1 of the display region 10a, and an inspection circuit 105 is provided between the end of the first substrate 10 and the second side 10a2 of the display region 10a. Furthermore, a scanning line driving circuit 104 is provided between the end of the first substrate 10 and the third side 10a3 of the display region 10a and between the end of the first substrate 10 and the fourth side 10a4 of the display region 10a. Mounting terminals 102 to which a wiring substrate 70 is electrically connected are arranged on the end of the first substrate 10 on the data line driving circuit 101 side. A driving IC 75 including a control circuit 76 that outputs image signals VID1, VID2, ... VID2n and selection signals SEL1, SEL2, ... SEL8, etc., which will be described later with reference to FIG. 5, is mounted on the wiring board 70. The wiring board 70 is electrically connected to a higher-level circuit 60 via a connector 61. The higher-level circuit 60 is provided with an image control circuit 65. The higher-level circuit 60 also is provided with a temperature detection driving circuit 66 that drives a temperature detection circuit 1, which will be described later. The higher-level circuit 60 is provided in a higher-level device for the electro-optical device 100 in an electronic device, which will be described later.

[0015] The first substrate 10 has a translucent substrate body 10w such as a quartz substrate or a glass substrate, and a display region 10a on one surface 10s of the first substrate 10 has a matrix of pixel transistors and pixel electrodes 9a electrically connected to each of the pixel transistors. A first alignment film 16 is formed on the upper layer side of the pixel electrodes 9a. A rectangular frame region 10b on the one surface 10s of the first substrate 10 extends between the display region 10a and the sealing material 107, and dummy pixel electrodes 9b formed simultaneously with the pixel electrodes 9a are provided in portions extending along each side of the display region 10a.

[0016] The second substrate 20 has a light-transmitting substrate body 20w, such as a quartz substrate or a glass substrate, and a common electrode 21 is formed on one surface 20s of the second substrate 20. The common electrode 21 is formed on substantially the entire surface of the one surface 20s of the second substrate 20. On the one surface 20s of the second substrate 20, a light-shielding parting 29 is formed below the common electrode 21 in the frame-shaped region 10b, and a second alignment film 26 is laminated on the surface of the common electrode 21. The display region 10a is defined by the inner edge of the parting 29. A light-transmitting planarizing film 22 is formed between the parting 29 and the common electrode 21. The light-shielding layer constituting the parting 29 may be formed as a black matrix portion overlapping the inter-pixel region 10f sandwiched between adjacent pixel electrodes 9a. The parting 29 is formed at a position overlapping the dummy pixel electrodes 9b in plan view. The parting 29 is made of a light-shielding metal film or black resin.

[0017] The first alignment film 16 and the second alignment film 26 are made of, for example, SiO X (x≦2), TiO2, M It is an inorganic alignment film made of obliquely evaporated films of SiO, Al2O3, etc., and has pillar-shaped structures called columns. The electro-optical device 100 is made up of a columnar structure layer formed at an angle with respect to the first substrate 10 and the second substrate 20. Therefore, the first alignment film 16 and the second alignment film 26 align the nematic liquid crystal molecules with negative dielectric anisotropy used in the electro-optical layer 50 at an oblique angle with respect to the first substrate 10 and the second substrate 20, thereby providing a pretilt to the liquid crystal molecules. In this way, the electro-optical device 100 is configured as a normally black VA (Vertical Alignment) mode liquid crystal device.

[0018] On the first substrate 10, outside the sealing material 107, electrode portions 14t for inter-substrate conduction are formed at positions overlapping four corner portions 24t of the second substrate 20. The electrode portions 14t for inter-substrate conduction are electrically connected to wiring 6g, and the wiring 6g is electrically connected to a terminal 102g of the terminal 102 for supplying a common potential LCCOM. An inter-substrate conductive material 109 containing conductive particles is disposed between the electrode portions 14t for inter-substrate conduction and the corner portions 24t, and the common electrode 21 of the second substrate 20 is electrically connected to the first substrate 10 via the electrode portions 14t for inter-substrate conduction and the inter-substrate conductive material 109. Therefore, a common potential LCCOM is applied to the common electrode 21 from the first substrate 10 side.

[0019] The multiple terminals 102 include terminals 102d, 102h, 102f, 102t, 102s, 102g, 102c, and 102a. The terminal 102d is a terminal for supplying a start pulse SP to the scanning line driving circuit 104. The terminal 102h is a terminal for supplying a clock signal CLY to the scanning line driving circuit 104. The terminal 102f is a terminal for supplying an output control signal ENBY to the scanning line driving circuit 104. The terminal 102t is a terminal for supplying a high-level constant potential VDDY to the scanning line driving circuit 104. The terminal 102s is a terminal for supplying a low-level constant potential VSSY to the scanning line driving circuit 104. The terminal 102g is a terminal for supplying a common potential LCCOM. The cathode terminal 102c and the anode terminal 102a are terminals electrically connected to a cathode wiring Lc and an anode wiring La of the temperature detection circuit 1, which will be described later with reference to FIG. 3, respectively.

[0020] The electro-optical device 100 of this embodiment is a transmissive liquid crystal device. Therefore, the pixel electrodes 9a and the common electrode 21 are formed of a translucent conductive layer such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. In such a transmissive liquid crystal device, for example, light from a light source incident from the second substrate 20 side is modulated while being emitted from the first substrate 10, thereby displaying an image. Note that if the pixel electrodes 9a are made of a reflective metal such as aluminum, the electro-optical device 100 can be made into a reflective liquid crystal device.

[0021] 1-2. Electrical configuration of the electro-optical device 100 FIG. 3 is a circuit block diagram showing the electrical configuration of the first substrate 10 shown in FIG. 2. In FIG. 3, the first substrate 10 has a display area 10a in which multiple pixels 100a are arranged in a matrix in a substantially central region. On the inside of the display area 10a of the first substrate 10, multiple scanning lines 3a extending in the X direction from a scanning line driving circuit 104 and multiple data lines 6a extending in the Y direction from a data line driving circuit 101 are provided, and pixels 100a are formed corresponding to intersections of the scanning lines 3a and the data lines 6a. The multiple data lines 6a are electrically connected to an inspection circuit 105 arranged on the second side 10a2 of the display area 10a. Each of the multiple pixels 100a includes a pixel transistor 30 composed of an N-channel transistor and a pixel electrode 9a electrically connected to the pixel transistor 30. A data line 6a is electrically connected to the source region of the pixel transistor 30, a scanning line 3a is electrically connected to the gate of the pixel transistor 30, and a pixel electrode 9a is electrically connected to the drain region of the pixel transistor 30. An image signal VID is supplied to the data line 6a by a data line driving circuit 101, and a scanning signal G is supplied to the scanning line 3a.

[0022] As will be described later, the data line driving circuit 101 is also used as part of a precharge circuit 106 that applies a precharge signal to the data lines 6a during a precharge period set at the beginning of each horizontal scanning period. Although not shown, the inspection circuit 105 is a transistor array. One source-drain region of each transistor in the inspection circuit 105 is electrically connected to the data line 6a, the other source-drain region is electrically connected to an inspection line (not shown), and the gate is electrically connected to a control signal line (not shown) within the inspection circuit 105.

[0023] In each pixel 100a, the pixel electrode 9a faces the common electrode 21 of the second substrate 20 described with reference to FIG. 2 via the electro-optical layer 50, thereby constituting a liquid crystal capacitance 50a. To prevent fluctuations in the image signal VID held in the liquid crystal capacitance 50a, a storage capacitance 55 is added to each pixel 100a in parallel with the liquid crystal capacitance 50a. In this embodiment, to form the storage capacitance 55, a common potential wiring 8a extending across the multiple pixels 100a is formed on the first substrate 10 as a capacitance line, and a common potential LCCOM is supplied to the common potential wiring 8a. The common potential wiring 8a is arranged to overlap at least one of the scanning lines 3a and the data lines 6a in a planar view. FIG. 3 illustrates an example in which the common potential wiring 8a overlaps both the scanning lines 3a and the data lines 6a in a planar view. The common potential wiring 8a may be configured to overlap the data line 6a of the scanning lines 3a and the data lines 6a in a planar view. In either case, the common potential wiring 8a has a portion that overlaps with the data line 6a. In the first substrate 10, a temperature detection circuit 1 is arranged outside the display area 10a. In FIG. 3, the scanning line driving circuit 104 arranged on the left side of the display area 10a drives the odd-numbered scanning lines 3a, and the scanning line driving circuit 104 arranged on the right side of the display area 10a drives the even-numbered scanning lines 3a. However, the same scanning lines 3a may also be driven by scanning line driving circuits 104 arranged on both the left and right sides.

[0024] 1-3. Configuration example of data line driving circuit 101 etc. FIG. 4 is an explanatory diagram of the data line driving circuit 101 and other components shown in FIG. 3. FIG. 5 is a timing chart for displaying an image in the electro-optical device 100 shown in FIG. 1. As shown in FIG. 4, the data line driving circuit 101 is disposed on the first substrate 10 on the first side 10a1 of the display area 10a. The data line driving circuit 101 includes a demultiplexer, which includes a selection circuit 101a as a sample-and-hold circuit. The data lines 6a extend from the selection circuit 101a in the Y direction, i.e., toward the second side 10a2 of the display area 10a. The selection circuit 101a includes transistors 30e that control the electrical connection between the data lines 6a and the image signal wiring 6j. In this embodiment, the demultiplexer includes, for example, eight transistors 30e. The transistors 30e are N-channel transistors. Therefore, for the FHD standard, 1920 / 8=240, so 240 demultiplexers are provided. The data line driving circuit 101 supplies an image signal VID to each data line 6a from the driving IC 75 shown in Fig. 3 via the terminal 102 and the image signal wiring 6j. At this time, the transistor 30e of the selection circuit 101a supplies the image signal VID to each data line 6a in a time-division manner based on selection signals SEL1, SEL2, ... SEL8 supplied from the control circuit 76 of the driving IC 75 via the control signal line 6i.

[0025] 5, when an image is displayed in the electro-optical device 100, the scanning line driving circuit 104 sequentially and exclusively sets the scanning signals G1, G2, G3, ... Gm to the selection level for each horizontal scanning period H during an Nth frame period defined by the vertical synchronization signal Vsync. During the horizontal scanning period H, the selection signals SEL1, SEL2, ... SEL8 sequentially and exclusively set to the selection level, and the driving IC 75 supplies the image signals VID1, VID2, ... VIDn in synchronization with the selection signals SEL1, SEL2, ... SEL8.

[0026] For example, during a horizontal scanning period H when the scanning signal G1 is at the selection level, when the selection signal SEL1 is at the selection level, voltages corresponding to the image signals VID1, VID2,..., VIDn are written to the pixel 100a corresponding to the intersection of the first scanning line 3a and the first data line 6a in the X direction in each of the multiple demultiplexers. Next, when the selection signal SEL2 is at the selection level, voltages corresponding to the image signals VID1, VID2,..., VIDn are written to the pixel 100a corresponding to the intersection of the first scanning line 3a and the second data line 6a in the first direction in each of the multiple demultiplexers. Similarly, when the selection signals SEL3 to SEL8 are at the selection level, voltages corresponding to the image signals VID1 to VIDn are written to the corresponding pixels 100a.

[0027] Furthermore, in driving the electro-optical device 100, a preliminary write is performed before writing an image signal voltage to the data lines 6a to improve display quality. This is generally called precharging. Therefore, at the beginning of the horizontal scanning period H, a precharge period tp is provided in which the selection signals SEL1, SEL2, ..., SEL8 simultaneously reach the selection level. During the precharge period tp, the selection signals SEL1, SEL2, ..., SEL8 all reach the selection level, thereby supplying the precharge signal PRC to all of the data lines 6a. Therefore, the control circuit 76 controls the selection circuit 101a during the precharge period tp, and the control circuit 76 and the selection circuit 101a constitute a precharge circuit.

[0028] This operation is performed in each horizontal period H. A similar operation is also performed in the (N+1)th frame after the (N)th frame. At this time, the image signal polarity for each pixel 100a may be reversed. The image signal polarity is the polarity of the image signal voltage with respect to the common potential LCCOM. For example, if the image signal voltage is positive with respect to the common potential LCCOM, the image signal polarity is positive, and if the image signal voltage is negative with respect to the common potential LCCOM, the image signal polarity is negative. For example, if positive polarity writing is performed in the (N)th frame, negative polarity writing is performed in the following (N+1)th frame. On the other hand, if negative polarity writing is performed in the (N)th frame, positive polarity writing is performed in the following (N+1)th frame. By performing this polarity reversal, deterioration of the electro-optical layer 50 can be prevented.

[0029] In this embodiment, the precharge assists in writing the image signal voltage or reduces crosstalk, which occurs when a white window is displayed on a halftone background and the top or bottom of the white window appears to have a different grayscale from the surrounding area. The precharge signal PRC is often set near the lowest voltage in the voltage range of the image signal VID. For example, in a normally black mode electro-optical device 100, the common potential LCCOM is set to a fixed potential of 7V, the image signal voltage for negative polarity display is set to 2V (white) to 7V (black), and the image signal voltage for positive polarity display is set to 7V (black) to 12V (white), and the precharge signal is set to approximately 2V to 4V. In practice, the common potential LCCOM is adjusted taking into account the push-down voltage between the transistor 30e of the selection circuit 101a and the pixel transistor 30, but this can be ignored for the purposes of explaining the embodiment.

[0030] Precharging is generally performed at the beginning of the horizontal scanning period H. Therefore, the potential of the data lines 6a simultaneously transitions to around 2V, causing relatively large noise in the potential of the common potential line 8a due to parasitic capacitance. More specifically, as shown by LCCOM in Figure 5, spike noise occurs in the common potential line 8a in synchronization with precharging, moving toward a lower potential than the common potential LCCOM. Noise also occurs when writing image signals to each pixel, but it is relatively small due to the time-division operation. In recent years, the number of data lines 6a in the display area 10a has increased due to the trend toward higher resolution, making this spike noise difficult to suppress.

[0031] 1-4. Temperature detection circuit 1 configuration Fig. 6 is an explanatory diagram of the temperature detection circuit 1 shown in Fig. 3. Fig. 6 shows the circuit configuration when the temperature detection circuit 1 detects the temperature.

[0032] 3, a temperature detection circuit 1 that detects the temperature of the electro-optical panel 100p is provided outside the display region 10a of the first substrate 10. The temperature detection circuit 1 includes a temperature detection element 11 and an electrostatic protection circuit 12 that protects the temperature detection element 11 from surge currents. On the first substrate 10, the temperature detection element 11 is disposed near the display region 10a, and the electrostatic protection circuit 12 is provided between the temperature detection element 11 and an end of the first substrate 10 where the terminals 102 are arranged.

[0033] As shown in FIG. 6, the temperature detection element 11 includes, for example, a plurality of diodes D electrically connected in series. For ease of explanation, FIG. 6 illustrates an example in which three diodes D (D1 to D3) are electrically connected in series, but five or six diodes D may be electrically connected in series. With such a temperature detection element 11, when a constant current is passed through the temperature detection element 11, the temperature sensitivity of the forward voltage can be set to approximately −10 mV / °C. An anode wiring La extending from the anode terminal 102a is electrically connected to the anode 11a of the temperature detection element 11. A cathode wiring Lc extending from the cathode terminal 102c is electrically connected to the cathode 11c of the temperature detection element 11. A ground potential GND is supplied to the cathode wiring Lc.

[0034] Therefore, when the electro-optical device 100 is mounted in an electronic device, if a minute forward drive current IF of about 100 nA to several μA is supplied from the temperature detection drive circuit 66 of the upper circuit 60 via the wiring board 70 to the temperature detection circuit 11 via the anode terminal 102a and the cathode terminal 102c, most of the drive current IF flows through the temperature detection element 11. Here, the forward voltage of the temperature detection element 11 can be considered to have a good linear relationship with temperature. Therefore, if the temperature detection drive circuit 66 detects the output voltage VF between the anode terminal 102a and the cathode terminal 102c when a constant drive current IF of about 100 nA to several μA is supplied to the temperature detection element 11, the temperature of the display region 10a of the electro-optical panel 100p can be detected. More specifically, when the electro-optical device 100 is used as a light bulb or the like in a projection display device (described later), the output voltage VF varies linearly with temperature within the specified temperature range. Therefore, if calibrated in advance, the temperature of the electro-optical panel 100p can be detected. Since the temperature detection element 11 is disposed near the display area 10a, the temperature detection element 11 can accurately detect the temperature of the display area 10a. Therefore, by correcting the image signal based on the temperature detection by the temperature detection circuit 1, the electro-optical device 100 can be driven under appropriate conditions corresponding to the temperature of the display area 10a, thereby displaying high-quality images. The temperature detection drive circuit 66 includes a constant current circuit 661 and a stabilizing capacitor 662. The stabilizing capacitor 662 is disposed between the constant current circuit 661 and ground potential GND to stabilize the measured value of the output voltage VF. The capacitance of the stabilizing capacitor 662 is, for example, 0.1 μF.

[0035] In this embodiment, the electrostatic protection circuit 12 includes a transistor Tr connected between an anode wiring La and a cathode wiring Lc, and the transistor Tr is electrically connected in parallel to the temperature detection element 11. One source-drain region 31i of the transistor Tr is electrically connected to the cathode wiring Lc between the cathode terminal 102c and the cathode 11c of the temperature detection element 11, and the other source-drain region 31j of the transistor Tr is electrically connected to the anode wiring La between the anode terminal 102a and the anode 11a of the temperature detection element 11. In this embodiment, the transistor Tr is an N-channel transistor, similar to the pixel transistor 30.

[0036] In the electrostatic protection circuit 12, a first capacitance element C1 and a second capacitance element C2 are electrically connected in series between an anode wiring La and a cathode wiring Lc. More specifically, one electrode of the second capacitance element C2 is electrically connected to the anode wiring La, one electrode of the first capacitance element C1 is electrically connected to the cathode wiring Lc, and the other electrode of the first capacitance element C1 is electrically connected to the other electrode of the second capacitance element C2. One electrode of the first capacitance element C1 is electrically connected to the cathode wiring Lc between the cathode terminal 102c and one source-drain region 31i of the transistor Tr, and one electrode of the second capacitance element C2 is electrically connected to the anode wiring La between the anode terminal 102a and the other source-drain region 31j of the transistor Tr. The capacitance of the first capacitance element C1 and the second capacitance element C2 is, for example, 5 pF.

[0037] The anode line La has a first resistor R1 between the anode terminal 102a and the connection point between the anode line La and the second capacitor C2, and the cathode line Lc has a second resistor R2 between the cathode terminal 102c and the connection point between the cathode line Lc and the first capacitor C1. A connection node Cn between the first capacitor C1 and the second capacitor C2 is electrically connected to the gate electrode 33t of the transistor Tr. The first resistor R1 and the second resistor R2 have a resistance of, for example, 10 kΩ.

[0038] The electrostatic protection circuit 12 includes a resistor R3 electrically connected in parallel to the first capacitor C1. More specifically, the gate wiring Lg extending from the gate electrode 33t of the transistor Tr is electrically connected to the connection node Cn between the first capacitor C1 and the second capacitor C2, and is further electrically connected to the cathode wiring Lc via the resistor R3. The resistor R3 has a resistance of, for example, 500 kΩ. The transistor Tr functions as a discharge path. Because the gate electrode 33t of the transistor Tr is electrically connected to the cathode wiring Lc via the resistor R3, the gate electrode 33t and the cathode wiring Lc are at the same potential in a static state. In other words, the gate-source voltage of the transistor Tr is 0 V. Therefore, the transistor Tr is off, and ideally, no current flows between the source and drain. Therefore, when the temperature detection element 11 detects temperature, the drive current IF supplied to the anode wiring La flows through the temperature detection element 11 but not through the transistor Tr.

[0039] As described above, the electrostatic protection circuit 12 includes a transistor Tr electrically connected in parallel to the temperature detection element 11, a first capacitance element C1 electrically connected to the transistor Tr, and a resistance element R3 electrically connected in parallel to the first capacitance element C1. The electrostatic protection circuit 12 also includes a second capacitance element C2 electrically connected in series with the first capacitance element C1. Therefore, when a surge current caused by static electricity flows in from the anode terminal 102a during a manufacturing process or the like, the electrostatic protection circuit 12 protects the temperature detection element 11 from static electricity.

[0040] More specifically, in the electrostatic protection circuit 12, in a static state, the gate-source voltage of the transistor Tr is 0V, and the transistor Tr is off. When a surge current due to static electricity flows into the anode terminal 102a, the first resistor R1 suppresses voltage fluctuations, while the potential of the gate electrode 33t of the transistor Tr, which corresponds to the potential of the connection node Cn between the first capacitor C1 and the second capacitor C2, rises. This turns the transistor Tr on, and the surge current flows to the cathode terminal 102c via the transistor Tr and the cathode wiring Lc. The first resistor R1 reduces the surge current flowing from the anode terminal 102a, and the second resistor R2 reduces the surge current flowing from the cathode terminal 102c. The duration during which the transistor Tr is on is determined by the first capacitor C1, the second capacitor C2, the resistor R3, and the gate capacitance of the transistor Tr. After discharging, the gate-source voltage of transistor Tr returns to 0 V due to resistor R3. Therefore, the surge current flowing through temperature detection element 11 is suppressed by electrostatic protection circuit 12, and temperature detection element 11 can be protected.

[0041] 1-5. Configuration example of temperature detection element 11, etc. 7 is an explanatory diagram schematically illustrating a cross section of the temperature detection element 11 and the like shown in FIG. 6. As shown in FIG. 7, in the first substrate 10, a light-transmitting insulating layer 41 made of a silicon oxide film or the like is formed on the substrate main body 10w, and a pixel transistor 30 including a semiconductor layer 31a is formed on the surface side of the insulating layer 41. A light-shielding layer (not shown) may be formed between the substrate main body 10w and the insulating layer 41 so as to overlap the semiconductor layer 31a and the like in a planar view. Note that, for ease of identification in the drawing, the gate insulating layer 32 is drawn only on the pixel transistor 30.

[0042] The pixel transistor 30 includes a semiconductor layer 31a and a gate electrode 33g formed of a portion of the scanning line 3a intersecting the semiconductor layer 31a. A light-transmitting gate insulating layer 32 formed of a silicon oxide film or the like is disposed between the semiconductor layer 31a and the gate electrode 33g. The gate electrode 33g is, for example, a stacked film of tungsten silicide and conductive polysilicon. The semiconductor layer 31a is formed of a polysilicon film. The pixel transistor 30 has a lightly doped drain (LDD) structure. More specifically, in the pixel transistor 30, the source region 31s includes a high-concentration region 31s1 separated from the channel region 31g and a low-concentration region 31s2 sandwiched between the channel region 31g and the high-concentration region 31s1. The drain region 31d includes a high-concentration region 31d1 separated from the channel region 31g and a low-concentration region 31d2 sandwiched between the channel region 31g and the high-concentration region 31d1. The gate insulating layer 32 is made of, for example, a silicon oxide film. Note that a light-shielding layer formed between the substrate body 10w and the insulating layer 41 may be used as the scanning line 3a, and the gate electrode 33g may be electrically connected to the light-shielding layer via a contact hole (not shown) that penetrates the gate insulating layer 32 and the insulating layer 41.

[0043] On the upper side of the gate electrode 33g, light-transmitting insulating layers 42, 43, and 44 made of silicon oxide film or the like are stacked in this order, and conductive layers are formed between the insulating layers 41, 42, and 43 to form the storage capacitor 55 described with reference to Figure 3.

[0044] A data line 6a and a relay electrode 6b are formed between the insulating layer 42 and the insulating layer 43. The data line 6a is electrically connected to the source region 31s of the pixel transistor 30 via a contact hole 42s that penetrates the gate insulating layer 32 and the insulating layer 42. The relay electrode 6b is electrically connected to the drain region 31d of the pixel transistor 30 via a contact hole 42d that penetrates the gate insulating layer 32 and the insulating layer 42. The data line 6a and the relay electrode 6b are made of a conductive layer that is simultaneously formed in the same layer, and is, for example, a low-resistance wiring that is mainly made of aluminum.

[0045] A common potential wiring 8a and a relay electrode 8d are formed between the insulating layer 43 and the insulating layer 44. The common potential wiring 8a and the relay electrode 8d are made of conductive layers that are simultaneously formed in the same layer. The relay electrode 8d is electrically connected to the relay electrode 6b via a contact hole 43d that penetrates the insulating layer 43. Although not shown, the common potential wiring 8a is electrically connected to one electrode of a storage capacitor 55, and the other electrode of the storage capacitor 55 is electrically connected to the relay electrodes 6b and 8d. The common potential wiring 8a is also electrically connected to the wiring 6g in FIG. 1.

[0046] A pixel electrode 9a is formed on the insulating layer 44. The pixel electrode 9a is electrically connected to the relay electrode 8d via a contact hole 44d that penetrates the insulating layer 44. Therefore, the pixel electrode 9a is electrically connected to the other electrode of the storage capacitor 55, and is further electrically connected to the drain region 31d of the pixel transistor 30.

[0047] Although not shown in the figure, the first substrate 10 also includes transistors for driving circuits that constitute inverter circuits, etc. in the scanning line driving circuit 104, and transistors for driving circuits that constitute the selection circuit 101a of the data line driving circuit 101, using the manufacturing process for pixel transistors 30, etc.

[0048] The diode D of the temperature detection element 11 is formed on the first substrate 10 using the same manufacturing process as the pixel transistor 30 and the transistors for the drive circuit. More specifically, the first substrate 10 has a plurality of semiconductor layers 31h separated from each other in an island shape on the upper layer of the insulating layer 41, and each of the plurality of semiconductor layers 31h has an N-type region and a P-type region. In this embodiment, the N-type region includes a high-concentration N-type region N+ and a low-concentration N-type region N−, and the P-type region includes a high-concentration P-type region P+ and a low-concentration P-type region P−, with the low-concentration N-type region P− forming a PN junction. Note that the diode D can also be formed by a high-concentration P-type region P+, a low-concentration N-type region N−, and a high-concentration N-type region N+. In either case, whether or not the diode D is a diode D can be determined by measuring its electrical characteristics.

[0049] Electrodes 6e1 and 6e2 are formed on the upper layer of the insulating layer 42, and the multiple electrodes 6e1, 6e2 are electrically connected to a high-concentration P-type region P+ of the semiconductor layer 31h and a high-concentration N-type region N+ of the adjacent semiconductor layer 31h via contact holes 42p, 42n that penetrate the insulating layer 42. The relay portion P1 electrically connects the PN junction of the first diode D1 and the PN junction of the second diode D2, and includes the N-type region of the first diode D1, the electrode 6e1, and the P-type region of the second diode D2. The relay portion P2 electrically connects the PN junction of the second diode D2 and the PN junction of the third diode D3, and includes the N-type region of the second diode D2, the electrode 6e2, and the P-type region of the third diode D3. Therefore, the electrode 6e1 is included in the relay portion P1 that electrically connects the first diode D1 and the second diode D2, and the electrode 6e2 is included in the relay portion P2 that electrically connects the second diode D2 and the third diode D3. Here, the electrode 6e1 corresponds to the portion that electrically connects the semiconductor layer 31h of the first diode D1 and the semiconductor layer 31h of the second diode D2, and the electrode 6e2 corresponds to the portion that electrically connects the semiconductor layer 31h of the second diode D2 and the semiconductor layer 31h of the third diode D3.

[0050] In addition, an anode wiring La is electrically connected to the high-concentration P-type region P+ of the semiconductor layer 31h located at one end via a contact hole 42p, and a cathode wiring Lc is electrically connected to the high-concentration N-type region N+ of the semiconductor layer 31h located at the other end via a contact hole 42n.

[0051] Semiconductor layer 31h is formed simultaneously in the same layer as semiconductor layer 31a, and therefore has the same thickness as semiconductor layer 31a. The N-type and P-type regions are formed using the manufacturing process for the driving transistors that make up scanning line driving circuit 104 and the like shown in Figure 3, and the pixel transistors 30. Electrodes 6e1 and 6e2 are formed simultaneously in the same layer as data line 6a, for example.

[0052] Although not shown, the transistor Tr, the first resistor R1, the second resistor R2, and the resistor R3 of the electrostatic protection circuit 12 are formed using the respective conductive layers shown in FIG. 7 . For example, the first resistor R1, the second resistor R2, and the resistor R3 are made of a conductive polysilicon film or the like. For example, they are provided in the same layer as the gate electrode 33g and the semiconductor layer 31a. The first resistor R1, the second resistor R2, and the resistor R3 are not limited to this, and may be made of a metal material such as tungsten silicide or aluminum. The transistor Tr is formed simultaneously with the pixel transistor 30 in the same layer. The first capacitor C1 and the second capacitor C2 are formed simultaneously with the storage capacitor 55 in the same layer.

[0053] As shown in FIGS. 4 and 7 , the common potential wiring 8a is a wiring that extends from the terminal 102g through the region where the temperature detection element 11 is formed, toward the display region 10a and the scanning line driving circuit 104. Here, the common potential wiring 8a has an opening 8a0 provided outside the display region 10a, and the temperature detection element 11 is formed inside the opening 8a0 in a planar view. In this embodiment, a light-shielding layer 8e that overlaps the temperature detection element 11 in a planar view is formed inside the opening 8a0 in a planar view. The light-shielding layer 8e is a light-shielding conductive layer that is formed in the same layer as the common potential wiring 8a at the same time. Furthermore, the light-shielding layer 8e is a film that is formed in the same layer as the common potential wiring 8a at the same time, but is provided separately from the common potential wiring 8a.

[0054] The parting line 29 of the second substrate 20 is formed in an area that overlaps with the temperature detection element 11 in a planar view, and the parting line 29 is further formed in an area that overlaps with the data line driving circuit 101 and the scanning line driving circuit 104 in a planar view.

[0055] In the first substrate 10 configured in this manner, the data line 6a and electrodes 6e1, 6e2, etc. formed between the insulating layer 42 and the insulating layer 43 correspond to the first conductive layer, the common potential wiring 8a and the light-shielding layer 8e, etc. formed between the insulating layer 43 and the insulating layer 44 correspond to the second conductive layer, and the pixel electrode 9a and the dummy pixel electrode 9b formed on the upper layer of the insulating layer 44 correspond to the third conductive layer.

[0056] 1-6. Effects of the First Embodiment FIG. 8 is an explanatory diagram of a comparative example of the first embodiment of the present invention. FIG. 9 is a diagram illustrating an example of the relationship between precharge and the output voltage VF of the temperature detection circuit 1. FIG. 10 is a graph illustrating the effect of the parasitic capacitance Cb of the temperature detection element 11 shown in FIG. 6 on the output voltage VF. Specifically, FIG. 10 illustrates the relationship between the electrostatic capacitance of the parasitic capacitance Cb between the temperature detection element 11 and the common potential wiring 8a and the output voltage VF of the temperature detection circuit 1. In FIG. 10, the parasitic capacitance Cb is a capacitance parasitic between the relay portion P1 including the electrode 6e1 of the diode D of the temperature detection element 11 and the common potential wiring 8a, and a capacitance parasitic between the relay portion P2 including the electrode 6e2 and the common potential wiring 8a. Note that one pole of the diode D electrically connected to the electrode 6e1 is the same node as the electrode 6e1. Similarly, one pole of the diode D electrically connected to the electrode 6e2 is the same node as the electrode 6e2.

[0057] 8, the common potential wiring 8a does not have an opening 8a0, and the temperature detection element 11 overlaps the common potential wiring 8a in a plan view. Therefore, in the comparative example, a parasitic capacitance Cb (see FIG. 6) having a large capacitance exists between the relay portions P1 and P2 of the diode D and the common potential wiring 8a. The parasitic capacitance Cb is significantly affected by the electrodes 6e1 and 6e2 arranged in a layer above the semiconductor layer 31h.

[0058] 7, in the electro-optical device 100 according to the first embodiment of the present invention, an opening 8a0 is formed in the common potential wiring 8a at a position that overlaps with the temperature detection element 11 in a planar view. Therefore, the temperature detection element 11 does not overlap with the common potential wiring 8a in a planar view. Therefore, in the electro-optical device 100 according to the first embodiment of the present invention, no parasitic capacitance having a large capacitance exists between the electrodes 6e1 and 6e2 of the diode D and the common potential wiring 8a, and therefore no parasitic capacitance Cb having a large capacitance exists between the relay portions P1 and P2 and the common potential wiring 8a. Therefore, as will be described below, when spike noise occurs in the potential of the common potential wiring 8a due to precharging, in the comparative example, the change in the potential of the common potential wiring 8a affects the output voltage VF of the temperature detection element 11 via the parasitic capacitance Cb, whereas in the first embodiment, this effect is less likely to occur.

[0059] For example, when the drive current of the temperature detection circuit 1 including the temperature detection element 11 consisting of six diodes D was set to 100 nA, the following problem occurred. As shown in FIG. 9, when precharging of the electro-optical device 100 was stopped from time t0 to t1, the output voltage VF of the temperature detection circuit 1 approximately matched the forward voltage expected of the six diodes D. Next, when precharging was performed from time t1 to t2, the output voltage VF of the temperature detection circuit 1 decreased by ΔVF1 and saturated. When precharging was stopped after time t2, the output voltage VF of the temperature detection circuit 1 returned to the output voltage VF at times t0 to t1. Furthermore, this ΔVF1 was reduced when the conductive layer disposed above the temperature detection element 11 on the first substrate 10 and to which the common potential LCCOM was applied was electrically floating.

[0060] Therefore, assuming parasitic capacitance Ca (see FIG. 6) and parasitic capacitance Cb (see FIG. 6), diode D was modeled based on measurement data, and a circuit simulator was used to calculate the effect that a change in potential of common potential wiring 8a has on output voltage VF of temperature detection circuit 1 via parasitic capacitances Ca and Cb. Note that to shorten the calculation time, stabilizing capacitance 662 shown in FIG. 6 was set to 100 pF. Although the response time of the output voltage VF differs from that of the actual electro-optical device 100, it is sufficient to verify the behavior of the output voltage VF. The output voltage VF drops and saturates after the start of pre-charge, but a small voltage fluctuation synchronized with the pre-charge remains. Therefore, the output voltage VF was set to the average voltage over 0.01 seconds, which is sufficiently longer than one horizontal period. The calculations were performed at room temperature.

[0061] The potential of the common potential wiring 8a is basically a fixed potential, for example, 7V, as the common potential LCCOM, but the following noise is periodically superimposed as the wiring 8a is precharged. Here, one horizontal scanning period of 3 μsec is close to one horizontal period when, for example, a WUXGA electro-optical panel is driven at 240 frames per second. The noise voltage has a negative polarity because spike noise that moves toward a lower potential than the common potential LCCOM occurs on the common potential wiring 8a. 1 horizontal scanning period = 3 μsec Noise voltage = -1.5V Noise voltage fall time = 100nsec Noise voltage rise time = 300nsec

[0062] As a result of calculations, the parasitic capacitance Ca (see FIG. 6) was assumed to be 0.5 pF, but the effect on the output voltage VF of the temperature detection element 11 was small.

[0063] On the other hand, the calculation results shown in Figure 10 were obtained for the relationship between the capacitance of the parasitic capacitance Cb and the output voltage VF. In Figure 10, the calculation results for the output voltage VF of the temperature detection circuit 1 when the drive current IF is set to 100 nA, 200 nA, 400 nA, and 800 nA are shown by solid lines L100, L200, L400, and L800, respectively.

[0064] For example, calculations have shown that if a parasitic capacitance Cb of 0.03 pF exists between the relay portions P1, P2, ... of the diode D and the common potential wiring 8a, the fluctuation ΔVF1 in the output voltage VF of the temperature detection element 11 may exceed 100 mV. If the output voltage VF fluctuates by 100 mV and the temperature detection element 11 has a sensitivity of approximately -10 mV / °C, the temperature measurement error will reach 10°C, making it difficult to control the temperature of the electro-optical device 100.

[0065] 10, it can be seen that reducing the parasitic capacitance Cb or increasing the drive current IF is an effective way to solve the above problem. Therefore, if the parasitic capacitance Cb between the relay portions P1, P2, ... of the diodes D electrically connected in series and the common potential wiring 8a is reduced, as in this embodiment, it is possible to suppress fluctuations in the output voltage VF, such as ΔVF2 in FIG. 9. In other words, even if the potential of the common potential wiring 8a changes due to precharging, the fluctuations in the output voltage VF of the temperature detection circuit 1 are small, thereby improving the accuracy of temperature detection by the temperature detection element 11.

[0066] Increasing the drive current IF makes it less likely that potential changes in the common potential wiring 8a will affect the output voltage VF of the temperature detection circuit 1. However, increasing the drive current IF also increases the influence of series resistance, increasing the fluctuation ΔVF in the forward voltage of the temperature detection element 11 relative to the fluctuation ΔIF in the drive current at the operating point, thereby reducing the reliability of the detected temperature. Therefore, it is not desirable to simply increase the drive current of the diode D, as this makes the temperature detection circuit 1 difficult to use.

[0067] Furthermore, increasing the drive current IF increases the output voltage VF, which is the operating point, and may make it impossible to maintain the compliance voltage (operating point voltage upper limit) of the constant current circuit. For example, in a discharge-type constant current circuit using a transistor, an operational amplifier, a shunt regulator, etc., the upper limit of the operating point voltage for constant current operation when using a 5V power supply is approximately 3.7V. As shown in FIG. 10, for example, if the drive current IF is 400nA, the operating point voltage at room temperature is approximately 3.8V, making it impossible to use a constant current circuit driven by a 5V power supply. In this case, the number of series diodes must be reduced to lower the operating point voltage, i.e., the output voltage VF, resulting in a decrease in the temperature sensitivity of the temperature detection circuit 1. Furthermore, maintaining the number of series diodes requires the addition of a new drive voltage source for the external circuit, resulting in increased costs. From this perspective, the configuration of the first embodiment reduces the parasitic capacitance Cb, making it less likely that changes in the potential of the common potential line 8a will affect the output voltage VF of the temperature detection circuit 1, even without increasing the drive current IF. Therefore, the temperature detection circuit 1 using the temperature detection element 11 with high sensitivity can be driven by the temperature detection drive circuit 66 which can be configured at low cost.

[0068] In this embodiment, the island-shaped light-shielding layer 8e is provided in the opening 8a0, so even when the opening 8a0 is provided, incident light is prevented from becoming stray light and projecting the pattern of the diode D. Furthermore, the provision of the island-shaped light-shielding layer 8e makes it easier to transmit the temperature of the electro-optic layer 50 to the temperature detection element 11.

[0069] 2. Embodiment 2 Fig. 11 is an explanatory diagram of an electro-optical device 100 according to a second embodiment of the present invention. Fig. 11 shows a planar configuration in the vicinity of a temperature detection element 11 of the electro-optical device 100 according to the second embodiment of the present invention. Fig. 12 is an explanatory diagram that schematically shows a cross section of the temperature detection element 11 and the like shown in Fig. 11. Note that the basic configuration of this embodiment is the same as that of the first embodiment, and therefore common parts are assigned the same reference numerals and their description will be omitted.

[0070] As shown in FIGS. 11 and 12 , in this embodiment, a conductive layer 9b0 constituting dummy pixel electrodes 9b is disposed on the surface of the insulating layer 44 around the periphery of the display region 10a of the first substrate 10. The conductive layer 9b0 has, for example, a plurality of rectangular patterns similar to the pixel electrodes 9a, which are connected to each other at the centers of the four sides of the rectangle. The conductive layer 9b0 also overlaps the temperature detection element 11 in a planar view. The conductive layer 9b0 is electrically connected to the common potential wiring 8a through a contact hole 44e that penetrates the insulating layer 44. Therefore, a common potential LCCOM is applied to the conductive layer 9b0. This configuration allows the voltage applied to the electro-optical layer 50 around the periphery of the display region 10a to be maintained at 0 V, thereby suppressing deterioration of the electro-optical layer 50.

[0071] Here, as in the first embodiment, the common potential wiring 8a has an opening 8a0 in a region overlapping the temperature detection element 11 in a planar view. A light-shielding layer 8e is provided inside the opening 8a0, overlapping the temperature detection element 11 in a planar view. The light-shielding layer 8e is electrically floating. The conductive layer 9b0 is electrically connected to the common potential wiring 8a and overlaps the temperature detection element 11 in a planar view. Therefore, parasitic capacitance exists between the conductive layer 9b0 and the junctions P1 and P2 of the temperature detection element 11. However, as is clear from the comparative example of FIG. 8 , the distance between the junctions P1 and P2 of the temperature detection element 11 and the conductive layer 9b0 to which the common potential LCCOM is applied is increased by the thickness of the insulating layer 44. As a result, the parasitic capacitance formed between the junctions P1 and P2 of the temperature detection element 11 and the conductive layer 9b0 can be reduced. Therefore, even if spike noise occurs in the common potential wiring 8a during precharging, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed. Therefore, the temperature detection accuracy in the electro-optical device 100 is high, and the temperature control can be performed appropriately in the electro-optical device 100.

[0072] 2-1. Modification of the second embodiment Fig. 13 is an explanatory diagram of an electro-optical device 100 according to a modified example of embodiment 2 of the present invention. Fig. 13 shows a schematic cross section of a temperature detection element 11 and other components of an electro-optical device 100 according to a modified example of embodiment 2 of the present invention. Note that the basic configuration of this embodiment is similar to embodiments 1 and 2, so common parts are assigned the same reference numerals and their description will be omitted.

[0073] 13, in this embodiment, a conductive layer 9b0 constituting dummy pixel electrodes 9b is disposed on the surface of the insulating layer 44 around the periphery of the display region 10a of the first substrate 10, as in the second embodiment. The conductive layer 9b0 has, for example, a plurality of rectangular patterns similar to the pixel electrodes 9a, which are connected to each other at the centers of the four sides constituting the rectangle.

[0074] Here, between the electro-optical layer 50 and the common potential wiring 8a, insulating layers 44 and 45 are provided between the common potential wiring 8a and the conductive layer 9b0, and the relay electrode 7a is provided between the insulating layers 44 and 45. Therefore, the pixel electrode 9a is electrically connected to the relay electrode 7a via a contact hole 45d that penetrates the insulating layer 45, and the relay electrode 7a is electrically connected to the relay electrode 8d via a contact hole 44d that penetrates the insulating layer 44.

[0075] Furthermore, a conductive layer 7e0 constituting the wiring 7e is provided between the insulating layer 44 and the insulating layer 45. Therefore, the conductive layer 9b0 is electrically connected to the conductive layer 7e0 through a contact hole 45e penetrating the insulating layer 45, and the conductive layer 7e0 is electrically connected to the common potential wiring 8a through a contact hole 44e penetrating the insulating layer 44. Therefore, a common potential LCCOM is supplied to the dummy pixel electrode 9b and the wiring 7e. This configuration allows the voltage applied to the electro-optical layer 50 around the display region 10a to be maintained at 0 V, thereby suppressing deterioration of the electro-optical layer 50. Furthermore, the wiring 7e electrically connects the common potential wiring 8a, which is electrically connected to the capacitance line in the display region 10a, to the terminal 102g with low resistance, thereby stabilizing the potential.

[0076] Here, as in the first embodiment, the common potential wiring 8a has an opening 8a0 in a region overlapping the temperature detection element 11 in a planar view. A light-shielding layer 8e is provided inside the opening 8a0, overlapping the temperature detection element 11 in a planar view, and the light-shielding layer 8e is in an electrically floating state. The conductive layer 7e0 is electrically connected to the common potential wiring 8a and overlaps the temperature detection element 11 in a planar view. Therefore, parasitic capacitance exists between the conductive layer 7e0 and the relay portions P1 and P2 of the temperature detection element 11. However, as is clear from the comparative example in FIG. 8 , the distance between the relay portions P1 and P2 of the temperature detection element 11 and the conductive layer 7e0 to which the common potential LCCOM is applied is increased by the thickness of the insulating layer 44. As a result, it is possible to reduce the parasitic capacitance formed between the relay portions P1, P2 of the diode D of the temperature detection element 11 and the conductive layer 7e0. Therefore, even if spike noise occurs in the common potential wiring 8a when precharging is performed, it is possible to suppress fluctuations in the output voltage VF of the temperature detection circuit 1. Therefore, the electro-optical device 100 has high temperature detection accuracy, and therefore the electro-optical device 100 can perform appropriate temperature control, thereby achieving the same effects as those of the second embodiment.

[0077] 3. Embodiment 3 FIG. 14 is an explanatory diagram of an electro-optical device 100 according to a third embodiment of the present invention. FIG. 14 shows a planar configuration near a temperature detection element 11 of the electro-optical device 100 according to the third embodiment of the present invention. FIG. 15 is a cross-sectional view of the temperature detection element 11 shown in FIG. 14. Note that the basic configuration of this embodiment is similar to that of the first and second embodiments, and therefore common parts are assigned the same reference numerals and their description will be omitted. Note that in FIGS. 14 and 15, to make the configuration easier to understand, the number of diodes D electrically connected in series in the temperature detection element 11 is set to three.

[0078] As shown in FIGS. 14 and 15 , in the temperature detection element 11, the direction in which the diodes D are arranged is defined as a first direction E, and the direction perpendicular to the first direction E is defined as a second direction F. The semiconductor layers 31h constituting the diodes D are arranged in the first direction E, and adjacent diodes D are electrically connected by an electrode 6e1 of the relay portion P1 and an electrode 6e2 of the relay portion P2. In this embodiment, the first direction E is the Y direction, and the second direction F is the X direction. Note that one electrode of the diode D electrically connected to the electrode 6e1 is at the same node as the electrode 6e1. Similarly, the other electrode of the diode D electrically connected to the electrode 6e2 is at the same node as the electrode 6e2.

[0079] Here, when the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, is defined as W1, and the electrode width in the direction along the second direction F for the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2 is defined as W2, the electrode width W2 has a portion narrower than the pattern width W1, as shown below. W1>W2

[0080] For example, when the pattern width W1 is 100 μm, the electrode width W2 is set to 5 μm. Since the current value flowing through the temperature detection element 11 is small, there is no problem even if the electrode width W2 is reduced. The same configuration is also used between the second diode D2 and the third diode D3. Therefore, the area of ​​the electrodes 6e1 and 6e2 in plan view is reduced, thereby reducing the parallel-plate parasitic capacitance formed between the relay portions P1 and P2, each including the electrodes 6e1 and 6e2, and the common potential wiring 8a. Therefore, even if spike noise occurs in the common potential wiring 8a during precharging, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0081] The opening 8a0 of the common potential wiring 8a may be formed so as to expose all of the diodes D, as indicated by the dotted line L1 in FIG. 14, or so as to selectively expose the relay portions P1 and P2, as indicated by the dashed-dotted line L2. In the latter case, the anode wiring La electrically connected to the first diode D1 and the cathode wiring Lc electrically connected to the third diode D3 overlap with the common potential wiring 8a in a planar view. Verification using the circuit model described above reveals that the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential wiring 8a has a significant effect on fluctuations in the output voltage VF of the temperature detection circuit 1. Therefore, even if the anode wiring La or the cathode wiring Lc overlaps with the common potential wiring 8a, the effect is small.

[0082] Furthermore, verification using the circuit model described above has revealed the importance of reducing the parasitic capacitance between the relay units P1 and P2 and the noise source, and therefore, in this embodiment, the cathode wiring Lc, which is at ground potential GND, is extended in the first direction E along the arrangement direction of the diodes D. In other words, the cathode wiring Lc may be used as a shield for wiring (not shown) for the relay units P1 and P2. In this case, if the cathode wiring Lc is arranged in a system separate from the ground potential GND wiring of the electro-optical panel 100p, the cathode wiring Lc becomes a constant potential wiring with low noise, and therefore has a high shielding effect.

[0083] Furthermore, for the relay units P1 and P2, the constant potential wiring 6s that supplies a low-level constant potential VSSY may be used as a shield for wiring (not shown) and may be extended in the first direction E along the arrangement direction of the diodes D. Alternatively, the wiring that supplies a high-level constant potential VDDY may be used as a shield.

[0084] 15, it is preferable to shorten the lengths L6e1 and 6e2 of the electrodes 6e1 and 6e2 by shortening the spacing S0, which is the spacing between the semiconductor layers 31h in the first direction E, within the limits permitted by the design rules. Reducing the lengths L6e1 and L6e2 of the electrodes 6e1 and 6e2 shortens the lengths LP1 and LP2 of the relay portions P1 and P2. This reduces the area of ​​the electrode 6e1 on the relay portion P1 and the area of ​​the electrode 6e2 on the relay portion P2, thereby reducing the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential wiring 8a. Therefore, even if spike noise occurs on the common potential wiring 8a during precharging, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0085] 3-1. Modification 1 of Embodiment 3 FIG. 16 is an explanatory diagram of an electro-optical device 100 according to a first modification of the third embodiment of the present invention. 16 shows a planar configuration near the temperature detection element 11 of an electro-optical device 100 according to a first modification of the third embodiment of the present invention. Since the basic configuration of this embodiment is similar to that of the third embodiment, the same reference numerals are used for common parts and their description will be omitted. In order to make the configuration easier to understand, in FIG. 16, the number of diodes electrically connected in series in the temperature detection element 11 is three, and part of the common potential wiring 8a is not shown.

[0086] 16, when the direction in which the diodes D are arranged is defined as a first direction E and the direction perpendicular to the first direction E is defined as a second direction F, the semiconductor layers 31h constituting the diodes D are arranged in the first direction E, and adjacent diodes D are electrically connected by an electrode 6e1 of the relay portion P1 and an electrode 6e2 of the relay portion P2. In this embodiment, the first direction E is the Y direction, and the second direction F is the X direction.

[0087] Here, when the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, is defined as W1, and the electrode width in the direction along the second direction F for the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2 is defined as W2, as in embodiment 3, the electrode width W2 has a portion narrower than the pattern width W1. W1>W2

[0088] For example, when the pattern width W1 is 100 μm, the electrode width W2 is set to 5 μm. Because the current flowing through the temperature detection element 11 is small, there is no problem with reducing the electrode width W2. Therefore, the area of ​​the electrode 6e1 of the relay portion P1 and the area of ​​the electrode 6e2 of the relay portion P2 are reduced, thereby reducing the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential wiring 8a. Therefore, even if spike noise occurs in the common potential wiring 8a during precharging, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0089] Furthermore, the spacing S0 between the semiconductor layers 31h in the first direction E is shortened to the extent permitted by the rules. More specifically, the selection circuit 101a of the data line driving circuit 101 includes complementary transistors, an N-channel transistor 30n1 and a P-channel transistor 30p1. Similarly to the selection circuit 101a, the inverter circuit 104a of the scanning line driving circuit 104 also includes an N-channel transistor 30n2 and a P-channel transistor 30p2. To shorten the circuit length, the spacing S1 between the semiconductor layer constituting the N-channel transistor 30n1 and the semiconductor layer constituting the P-channel transistor 30p1, and the spacing S2 between the semiconductor layer constituting the N-channel transistor 30n2 and the semiconductor layer constituting the P-channel transistor 30p2 are both narrowed. Similar measures can be taken in the testing circuit 105. This configuration allows the peripheral circuit area outside the display area 10a of the electro-optical panel 100p to be reduced, thereby enabling the electro-optical panel 100p to be miniaturized. As a result, the electro-optical panel 100p can be manufactured inexpensively. In this embodiment, as described below, the spacing S0 in the diode D is set to be equal to or less than the spacing S1 between the N-channel transistor 30n1 and the P-channel transistor 30p1 and the spacing S2 between the N-channel transistor 30n2 and the P-channel transistor 30p2. S0 ≤ S1, S2

[0090] The design rule for the electro-optical panel 100p can be considered to be the minimum value (not shown) of the spacing between the semiconductor layers of adjacent transistors of different conductivity types, such as spacing S1, S2, etc. Therefore, if that value is S3, the relationship with spacing S0 is as follows: S0≦S3

[0091] The spacing S3 is mainly determined by the impurity implantation mask pattern rule, because, for example, when forming a P-type region, the mask pattern must be designed to sufficiently cover the N-type region and sufficiently separate it from the P-type region.

[0092] Therefore, for the temperature detection element 11, the semiconductor layer 31h is arranged in the first direction E at a spacing S0 permitted by the design rules of the electro-optical panel 100p. As a result, the lengths L6e1 and L6e2 of the electrodes 6e1 and 6e2 shown in FIG. 15 can be shortened. Therefore, the area of ​​the electrode 6e1 on the relay portion P1 and the area of ​​the electrode 6e2 on the relay portion P2 are reduced, thereby reducing the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential wiring 8a. Therefore, even if spike noise occurs on the common potential wiring 8a during precharging, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0093] The opening 8a0 of the common potential wiring 8a may be arranged so that all of the diodes D do not overlap with the common potential wiring 8a, as shown by the dotted line L1, or may be arranged so that the common potential wiring 8a does not overlap mainly with the relay sections P1 and P2, as shown by the dashed-dotted line L2.

[0094] In this embodiment, the cathode wiring Lc extends in the first direction E between the temperature detection element 11 and the signal wiring 6d for supplying a start pulse SP, the signal wiring 6h for supplying a clock signal CLY, and the signal wiring 6f for supplying an output control signal ENBY, which extend in the first direction E. The cathode wiring Lc also extends in the first direction E along the temperature detection element 11 on the opposite side of the temperature detection element 11 from the signal wirings 6d, 6h, and 6f in the second direction F. Therefore, the cathode wiring Lc can be used as a shield against AC signal wiring for the relay sections P1 and P2. In this case, it is effective to separate the cathode wiring Lc from the ground potential GND wiring of the electro-optical panel 100p, since the cathode wiring Lc becomes a constant-potential wiring with low noise. It is preferable to extend the cathode wiring Lc in the first direction E on both sides of the temperature detection element 11. With this configuration, the capacitive coupling between the data line driving circuit 101 and the relay portions P1 and P2 can be suppressed, and the influence of the data line driving circuit 101 on the output voltage VF of the temperature detection circuit 1 can be reduced.

[0095] 3-2. Modification 2 of Embodiment 3 FIG. 17 is an explanatory diagram of an electro-optical device 100 according to a second modification of the third embodiment of the present invention. 17 shows a planar configuration near the temperature detection element 11 of an electro-optical device 100 according to Modification 2 of Embodiment 3 of the present invention. Note that the basic configuration of this embodiment is similar to that of Embodiment 3, and therefore common parts are assigned the same reference numerals and their description will be omitted. Note that in FIG. 17, to make the configuration easier to understand, the number of diodes D electrically connected in series in the temperature detection element 11 is set to three.

[0096] 17 , the direction in which the diodes D are arranged is defined as a first direction E, and the direction perpendicular to the first direction E is defined as a second direction F. The semiconductor layer 31h constituting the diodes D is arranged in the first direction E, and adjacent diodes D are electrically connected by an electrode 6e1 of the relay portion P1 and an electrode 6e2 of the relay portion P2. In this embodiment, the first direction E is the X direction, and the second direction F is the Y direction. Here, when the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, is defined as W1, and the electrode width in the direction along the second direction F of the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2 is defined as W2, the electrode width W2 has a portion narrower than the pattern width W1, as in the third embodiment. W1>W2

[0097] Therefore, the area of ​​the electrode 6e1 included in the relay portion P1 and the area of ​​the electrode 6e2 included in the relay portion P2 are reduced, and the parasitic capacitance Cb between the relay portions P1, P2 and the common potential wiring 8a can be reduced. Therefore, even if spike noise occurs in the common potential wiring 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0098] An opening 8a0 is formed in the common potential wiring 8a, overlapping with the temperature detection element 11 in a plan view. In this embodiment, the opening 8a0 reaches the end of the common potential wiring 8a and is open at the end of the common potential wiring 8a. In this manner, the opening 8a0 may be a notch provided in a side of the common potential wiring 8a. This configuration arises when it is desired to arrange the common potential wiring 8a as a low-resistance wiring. Furthermore, a part of the diode D constituting the temperature detection element 11 may be arranged outside an imaginary line 8a1 that can be drawn in the direction of extension of the side of the common potential wiring 8a in the opening 8a0. In this embodiment, the imaginary line 8a1 can be drawn, for example, as shown by the dashed line in FIG. 17.

[0099] In this embodiment, signal wirings 6d, 6h, and 6f are arranged in close proximity to the temperature detection element 11. A signal having a voltage amplitude greater than the voltage fluctuation of the common potential wiring 8a due to precharging is applied to the signal wirings 6d, 6h, and 6f. The voltage amplitude of the signal is, for example, 15.5 V. In this embodiment, the signal wirings 6d, 6h, and 6f extend along a second direction F that is perpendicular to the first direction E in which the diodes D are arranged. Therefore, the signal wirings 6d, 6h, and 6f do not extend along the relay portions P1 and P2 of the diodes D. In other words, the relay portions P1 and P2 of the diodes D do not face the signal wirings 6d, 6h, and 6f in a plan view. Therefore, the parasitic capacitance between the signal wirings 6d, 6h, 6f and the relaying portions P1 and P2 can be reduced, thereby suppressing fluctuations in the output voltage VF of the temperature detection circuit 1 due to the signal wirings 6d, 6h, 6f. Furthermore, since it is not necessary to arrange the shielded wire along the relay portions P1 and P2, the temperature detection element 11 can be more easily arranged.

[0100] In this embodiment, on the cathode side 11c of the temperature detection element 11, the cathode wiring Lc extends in the second direction F between the temperature detection element 11 and the signal wiring 6d, 6h, and 6f extending along the second direction F. Therefore, for the relay portions P1 and P2, the cathode wiring Lc can be used as a shield for the signal wiring 6d, 6h, and 6f.

[0101] 4. Embodiment 4 Fig. 18 is an explanatory diagram of precharging in odd-numbered frames of the electro-optical device 100 according to the fourth embodiment of the present invention. Fig. 19 is an explanatory diagram of precharging in even-numbered frames of the electro-optical device 100 according to the fourth embodiment of the present invention. Note that the basic configuration of this embodiment is the same as that of the first embodiment, so common parts are assigned the same reference numerals and their description will be omitted.

[0102] In this embodiment, the multiple horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to some of the multiple data lines 6a, and a second horizontal scanning period in which a precharge signal is supplied to other data lines 6a that are different from the first horizontal scanning period.

[0103] More specifically, the selection circuit 101a is composed of N-channel transistors as shown in Fig. 4. As shown in Fig. 18, in the first horizontal scanning period Ha1 of an odd-numbered frame, during the precharge period tp, the control circuit 76 shown in Fig. 3 sets the odd-numbered selection signals SEL1, SEL3, SEL5, and SEL7 to the selection level, while setting the even-numbered selection signals SEL2, SEL4, SEL6, and SEL8 to the non-selection level. Therefore, the odd-numbered data lines 6a are precharged, and the even-numbered data lines 6a are not precharged.

[0104] 3 sets the odd-numbered selection signals SEL1, SEL3, SEL5, and SEL7 to the non-selection level, while setting the even-numbered selection signals SEL2, SEL4, SEL6, and SEL8 to the selection level during the precharge period tp in the second horizontal scanning period Ha2 of the subsequent odd-numbered frame. Therefore, the even-numbered data lines 6a are precharged, but the odd-numbered data lines 6a are not precharged.

[0105] 19, during the precharge period tp of the first horizontal scanning period Hb1 of an even frame, the control circuit 76 shown in FIG. 3 deselects the odd-numbered selection signals SEL1, SEL3, SEL5, and SEL7, while selecting the even-numbered selection signals SEL2, SEL4, SEL6, and SEL8. Therefore, the even-numbered data lines 6a are precharged, but the odd-numbered data lines 6a are not precharged. During the second horizontal scanning period Hb2 of the following even frame, the control circuit 76 shown in FIG. 3 deselects the odd-numbered selection signals SEL1, SEL3, SEL5, and SEL7, while selecting the even-numbered selection signals SEL2, SEL4, SEL6, and SEL8. Therefore, the odd-numbered data lines 6a are precharged, but the even-numbered data lines 6a are not precharged.

[0106] Therefore, the number of data lines 6a precharged in one horizontal scanning period can be reduced, thereby reducing the peak voltage of noise occurring in the common potential LCCOM in the common potential wiring 8a. Qualitatively considering the verification using a circuit model, it can be said that reducing the peak voltage of noise occurring in the common potential LCCOM is preferable for suppressing fluctuations in the output voltage VF of the temperature detection circuit 1. That is, if all data lines 6a were precharged in one horizontal scanning period, the peak voltage of noise shown by the dashed lines in FIGS. 18 and 19 would be superimposed on the common potential LCCOM. However, in this embodiment, the number of data lines 6a precharged in one horizontal scanning period is reduced, so the peak voltage of noise is suppressed to the level shown by the solid lines in FIGS. 18 and 19. Therefore, even when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

[0107] 5. Embodiment 5 20 is an explanatory diagram of precharging of an electro-optical device 100 according to a fifth embodiment of the present invention. Since the basic configuration of this embodiment is the same as that of the first embodiment, the common parts are given the same reference numerals and their description will be omitted.

[0108] In this embodiment, the multiple horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to all of the multiple data lines 6a, and a second horizontal scanning period in which a precharge signal is not supplied to all of the multiple data lines 6a.

[0109] More specifically, as shown in FIG. 20, during the first horizontal scanning period Ha1 of an odd-numbered frame, all data lines 6a are precharged, and during the subsequent second horizontal scanning period Ha2, none of the data lines 6a are precharged. Also, although not shown, during the first horizontal scanning period (corresponding to the first horizontal scanning period Ha1) of an even-numbered frame, none of the data lines 6a are precharged, and during the subsequent second horizontal scanning period (corresponding to the second horizontal scanning period Ha2), all of the data lines 6a are precharged. Therefore, the frequency of noise occurring in the common potential LCCOM on the common potential wiring 8a can be reduced. Qualitatively, based on verification using a circuit model, reducing the frequency of noise occurring in the common potential LCCOM is advantageous for suppressing fluctuations in the output voltage VF of the temperature detection circuit 1. That is, during the first horizontal scanning period when all data lines 6a are precharged, large noise is superimposed, but during the second horizontal scanning period when none of the data lines 6a are precharged, no noise is superimposed. The dashed line represents the fluctuation of the common potential LCCOM when all data lines 6a are precharged. If the frequency of noise occurring in the common potential LCCOM decreases, the fluctuation of the output voltage VF of the temperature detection circuit 1 is suppressed. Therefore, even when precharging is performed, the fluctuation of the output voltage VF from the temperature detection circuit 1 can be suppressed.

[0110] 6. Modifications of Embodiments 3, 4, and 5 In the above-described third, fourth, and fifth embodiments, the parasitic capacitance Cb between the temperature detection element 11 and the common potential wiring 8a is reduced by providing the opening 8a0 in the common potential wiring 8a in the electro-optical device 100, and the fluctuation in the output voltage VF of the temperature detection circuit 1 is suppressed by configuring the precharge method. However, the third, fourth, and fifth embodiments may also be applied to an electro-optical device 100 in which the common potential wiring 8a does not have the opening 8a0. That is, by applying the third, fourth, and fifth embodiments to an electro-optical device 100 in which the common potential wiring 8a overlaps the temperature detection element 11 in a planar view, the influence of noise on the temperature detection element 11 may be suppressed, and fluctuations in the output voltage VF of the temperature detection circuit 1 may be suppressed.

[0111] 7. Another embodiment of the electro-optical device Although the common potential wiring 8a is exemplified as the wiring in the first, second, third, fourth, and fifth embodiments, the present invention can also be applied to other wiring. For example, since large noise may be superimposed on the ground potential GND wiring when precharging is performed, the configurations of the first, second, third, fourth, and fifth embodiments may be applied to reduce the parasitic capacitance between the temperature detection element 11 and the ground potential GND wiring. The present invention may also be applied to wiring to which an AC signal is supplied. Furthermore, precharging may be performed by replacing the inspection circuit 105 with a precharge circuit.

[0112] Furthermore, the electro-optical device 100 of the present invention is not limited to a liquid crystal device, and the present invention may be applied to electro-optical devices 100 other than liquid crystal devices, such as organic electroluminescence devices.

[0113] 8.Examples of electronic device configurations Fig. 21 is a block diagram showing an example of the configuration of a projection type display device 1000 to which the present invention is applied. Fig. 22 is an explanatory diagram of the light path shift element 110 shown in Fig. 21. Note that polarizing plates and the like are omitted from Fig. 21. The projection type display device 1000 shown in Fig. 21 is an example of an electronic device to which the present invention is applied, and includes an illumination device 190, a separation optical system 170, three electro-optical devices 100R, 100G, and 100B, and a projection optical system 160. Each of the electro-optical devices 100R, 100G, and 100B is formed by the electro-optical device 100 described with reference to Figs. 1 to 20.

[0114] The illumination device 190 is a white light source, and for example, a laser light source or a halogen lamp is used. The separation optical system 170 includes three mirrors 171, 172, and 175 and dichroic mirrors 173 and 174. The separation optical system 170 separates the white light emitted from the illumination device 190 into three primary colors: red (R), green (G), and blue (B). Specifically, the dichroic mirror 174 transmits light in the red (R) wavelength range and reflects light in the green (G) and blue (B) wavelength ranges. The dichroic mirror 173 transmits light in the blue (B) wavelength range and reflects light in the green (G) wavelength range. The light corresponding to red (R), green (G), and blue (B) is guided to the electro-optical devices 100R, 100G, and 100B, respectively.

[0115] The light beams modulated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 161 from three directions. The dichroic prism 161 constitutes a synthesis optical system that synthesizes red (R), green (G), and blue (B) images. Therefore, the projection lens system 162 enlarges and projects the synthesized image emitted from the light path shift element 110 onto a projection target such as a screen 180, thereby displaying a color image on the projection target such as the screen 180.

[0116] In this case, the control unit 150 can correct the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection results of the temperature detection circuit 1. This allows high-quality projection images to be displayed even when the ambient temperature fluctuates. Furthermore, if a light path shift element 110 (shown by a dashed line) is provided in the projection optical system 160 on the side from which light is emitted from the dichroic prism 161, thereby shifting the position at which the projected pixel is viewed every predetermined period, it becomes necessary to drive the liquid crystal layer at high speed. Even in this case, the electro-optical layer 50, which is made of a liquid crystal layer, can be driven at high speed by correcting the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection results of the temperature detection circuit 1 or by adjusting the temperature of the electro-optical panel 100p of the electro-optical devices 100R, 100G, and 100B.

[0117] As shown in Fig. 21, the light path shift element 110 is an optical element that shifts light emitted from the dichroic prism 161 in a predetermined direction. Fig. 22 illustrates an example in which the position of a projection pixel Pi, at which light emitted from each pixel 100a of the electro-optical panel 100p is visible, is shifted by the light path shift element 110 by a distance equivalent to 0.5 pixel pitches (=P / 2) to one side X1 in the X direction and a distance equivalent to 0.5 pixel pitches (=P / 2) to one side Y1 in the Y direction. The light path shift element 110 includes a light-transmitting plate, and an actuator, under the command of the control unit 150, swings the light-transmitting plate around an axis extending in the first direction X and / or around an axis extending in the second direction Y, thereby shifting the light path of the light emitted from each pixel 100a of the electro-optical panel 100p to light path LA and light path LB.

[0118] 9. Other embodiments of electronic devices The projection display device may be configured to use an LED light source or the like that emits light of each color as the light source unit, and supply each color light emitted from the LED light source to a separate liquid crystal device.

[0119] Electronic devices equipped with the electro-optical device 100 to which the present invention is applied are not limited to the projection display device 1000 of the above embodiment. For example, the present invention may be used in electronic devices such as a projection-type HUD (head-up display), a direct-view HMD (head-mounted display), a personal computer, a digital still camera, and a liquid crystal television. [Explanation of symbols]

[0120] 1...temperature detection circuit, 3a...scanning line, 6a...data line, 6d, 6f, 6h...signal wiring, 6e1, 6e2...electrode, 6g, 7e...wiring, 7e0, 9b0...conductive layer, 8a...common potential wiring, 8a0...opening, 8a1...virtual line, 8e...light-shielding layer, 9a...pixel electrode, 9b...dummy pixel electrode, 10...first substrate, 10a...display area, 11...temperature detection element, 11a...anode, 11c...cathode, 12...electrostatic protection circuit, 20...second substrate, 21... Common electrode, 29...partition, 30...pixel transistor, 30n1, 30n2...N-channel transistor, 30p1, 30p2...P-channel transistor, 31a, 31h...semiconductor layer, 50...electro-optical layer, 60...upper circuit, 65...image control circuit, 66...temperature detection drive circuit, 70...wiring board, 75...driver IC, 76...control circuit, 100, 100B, 100G, 100R...electro-optical device, 100a...pixel, 100p ...electro-optical panel, 101...data line driving circuit, 101a...selection circuit, 102a...anode terminal, 102c...cathode terminal, 104...scanning line driving circuit, 104a...inverter circuit, 106...precharge circuit, 110...light path shift element, 160...projection optical system, 161...dichroic prism, 162...projection lens system, 180...screen, 190...illumination device, 1000...projection type display device, D...diode, C1...first Capacitance element, C2...second capacitance element, D1...first diode, D2...second diode, D3...third diode, E...first direction, F...second direction, P1, P2...junction section, R1...first resistance element, R2...second resistance element, R3...resistance element, W1...pattern width, W2...electrode width, Ca, Cb...parasitic capacitance, Ha1, Hb1...first horizontal scanning period, Ha2, Hb2...second horizontal scanning period, La...anode wiring, Lc...cathode wiring, Cn...connection node

Claims

1. a plurality of data lines provided in the display area; a wiring having a portion that overlaps each of the plurality of data lines in a plan view outside the display area and to which a common potential is applied; a temperature detection element overlapping the wiring in a plan view; a selection circuit for selecting any one of the plurality of data lines; a control circuit that controls the selection circuit for each horizontal scanning period during a precharge period; Equipped with An electro-optical device characterized in that the multiple horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to some of the multiple data lines, and a second horizontal scanning period in which the precharge signal is supplied to other some of the multiple data lines that are different from the some of the data lines.

2. a plurality of data lines provided in the display area; a wiring having a portion that overlaps each of the plurality of data lines in a plan view outside the display area and to which a common potential is applied; a temperature detection element overlapping the wiring in a plan view; a selection circuit for selecting any one of the plurality of data lines; a control circuit that controls the selection circuit for each horizontal scanning period during a precharge period; Equipped with An electro-optical device characterized in that the multiple horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to all of the multiple data lines, and a second horizontal scanning period in which a precharge signal is not supplied to all of the multiple data lines.

3. 3. The electro-optical device according to claim 1, The electro-optical device is characterized in that the temperature detection element is provided at a position overlapping with an opening of the wiring.

4. An electronic device comprising the electro-optical device according to claim 1 .

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