transistor

Abstract

To provide a display device in which images can be rewritten for only an optional region, or a display device capable of partial driving in which a circuit structure including wires is simplified.SOLUTION: Shift of a selection signal in a shift register included in a scan line driving circuit and supply of the selection signal to a scan line are independently controlled. Thus, images can be rewritten only for an optional region. This operation is achieved by providing a wire that supplies a clock signal or a signal representing a fixed potential. Therefore, the display device including such wires is a display device capable of partial driving, in which a circuit structure including the wires is simplified.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] A display device has been developed that can reduce power consumption by partially rewriting images. In such a display device, some scanning lines are used to rewrite the image partially. The scanning line driver circuit has a scanning line driver circuit that can drive only a part of the scanning line (also called partial driving).

[0003] In Patent Document 1, a scanning line driving circuit (gate driving section) that can realize partial driving is Specifically, the scanning line driving circuit (gate driving unit) disclosed in Patent Document 1 The group is divided into several groups. Each group has a different starting point. The operation is controlled by a scan start signal. The scanning line driving circuit (gate driving section) inputs a start pulse (scanning start signal) to each group. By controlling this, partial drive is achieved. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-004176 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the display device disclosed in Patent Document 1, it is difficult to determine which area an image is to be rewritten. The only option is to select whether to perform the calculation for each group to be divided in advance. You cannot select image redraw for every scanline (e.g., every scanline). In the display device disclosed in Patent Document 1, the number of signals required to drive the scanning line driving circuit is The number of scanning line driving circuits increases according to the number of groups into which the scanning line driving circuits are divided. The number of wirings increases according to the number of groups. When the pixel part is formed on the same substrate as the external circuit part, the substrate on which the pixel part is formed and the external circuit part are separated depending on the number of groups. This will increase the number of connections to roads.

[0006] In view of the above-mentioned problems, one aspect of the present invention is to provide a method for rewriting an image only in an arbitrary area. Another object of one embodiment of the present invention is to provide a display device that can be partially driven. One of the objects of the present invention is to simplify the circuit configuration including wiring in a display device that can display an image. One embodiment of the present invention aims to achieve at least one of the above objects. [Means for solving the problem]

[0007] The above-mentioned problem is solved by the fact that the scanning line driving circuit selectively outputs a selection signal to each of the plurality of scanning lines. For example, the scanning line driving circuit may be configured to supply a plurality of pulse output circuits. When the pulse output circuit has a shift register configured as The selection signal is shifted to the pulse output circuit at the subsequent stage using the By selectively using a fixed potential and a fixed potential to supply signals to the scanning lines, a plurality of scanning It is possible to selectively apply a selection signal to the scan lines. If the signal is a clock signal, it is a select signal, and if it is a fixed potential, it is a non-select signal. By designing the scanning lines so that the selection signals are supplied to the scanning lines, it is possible to control the selection signals. .

[0008] Specifically, one aspect of the present invention is a method for manufacturing a pixel array including: a plurality of pixels arranged in m rows and n columns; a first scanning line electrically connected to n pixels arranged in the first row of the the mth scanning line electrically connected to n pixels arranged in the mth row among the pixels; a first pulse output circuit electrically connected to the first scanning line through a pulse output circuit electrically connected to the mth scanning line; and an mth pulse output circuit electrically connected to the kth pulse output circuit (k is , a natural number greater than or equal to 2 and less than m) is a wiring in which one of the source and drain supplies a clock signal. and the other of the source and drain is electrically connected to the k+1 pulse output circuit. a first transistor electrically connected to the source and drain of which one is connected to the clock signal or is electrically connected to a wiring that supplies a fixed potential, and the other of the source and drain is a second transistor electrically connected to the scanning line and a second transistor electrically connected to the (k-1)th pulse output circuit; In response to an input signal, the potential of the gate of the first transistor and the potential of the gate of the second transistor are and a control circuit for controlling the potential of the gate of the transistor.

[0009] In this specification, etc., when something is explicitly stated as singular, it is referred to as singular. However, it is not limited to this, and multiple numbers are also possible. In particular, if something is explicitly stated as plural, it is preferable that it be plural. However, it is not limited to this and may be singular.

[0010] In this specification, terms such as first, second, and third refer to various elements, members, regions, layers, It is used to describe an area separately from others. Therefore, first, second, third, etc. The terms do not limit the number of elements, members, regions, layers, areas, etc. , "first" can be replaced with "second" or "third", etc. [Effects of the Invention]

[0011] In a display device according to one embodiment of the present invention, a selection signal in a shift register included in a scan line driver circuit is It is possible to independently control the shift of the signal and the supply of the selection signal to the scanning line. Therefore, it is possible to selectively supply a selection signal to each of the plurality of scanning lines. That is, the display device of one embodiment of the present invention rewrites an image only in an arbitrary region. It is possible to do so.

[0012] In addition, in the display device of one embodiment of the present invention, the above operation is performed by a clock signal or a fixed potential. This can be realized by providing wiring for supplying signals. The display device of one embodiment is a display device capable of partial driving, and has a circuit structure including wiring. This allows for a simplified configuration. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1A is a diagram showing an example of a display device, and FIG. 1B is a circuit diagram showing an example of a pixel. [Figure 2] 1A is a diagram showing a configuration example of a scanning line driver circuit, FIG. 1B is a timing chart showing an operation example of the scanning line driver circuit, and FIG. 1C is a diagram showing a configuration example of a pulse output circuit. [Figure 3] 1A is a circuit diagram showing an example of a pulse output circuit, and FIGS. 1B and 1C are timing charts showing an example of the operation of the pulse output circuit. [Figure 4] FIG. 2 is a diagram showing an example of the configuration of a controller. [Figure 5]FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 6] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 7] Circuit diagram of an element for evaluating transistor characteristics. [Figure 8] 10 is a timing chart of an element for evaluating transistor characteristics. [Figure 9] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 10] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 11] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 12] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 13] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 14] 1A and 1B are circuit diagrams showing an example of a pulse output circuit. [Figure 15] 1A to 1C are cross-sectional views showing an example of a transistor. [Figure 16] 1A to 1F are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0015] (Example of a display device) A display device according to one embodiment of the present invention will be described below with reference to FIGS.

[0016] FIG. 1A is a diagram showing a configuration example of a display device. The display device shown in FIG. 1A has a pixel a scanning line driving circuit 11, a signal line driving circuit 12, and a controller 13, each of which m lines (m The scanning lines 14 are arranged parallel or approximately parallel to each other, and the signal line driver n (n is a natural number equal to or greater than 2) signal lines 15 whose potentials are controlled by an operation circuit 12; Furthermore, the pixel section 10 has a plurality of pixels 16 arranged in a matrix (m rows and n columns). Each scanning line 14 corresponds to one of the plurality of pixels 16 arranged in a matrix. Each signal line 15 is electrically connected to a plurality of pixels 16 arranged in a row. Among the plurality of pixels 16 arranged in a row, the plurality of pixels 16 arranged in any one column are supplied with electricity. The scanning line driving circuit 11 is electrically connected to the controller 13. Start signal for scanning line (GSP), clock signal for scanning line driving circuit (GCK), Signals such as the circuit clock signal (PGCK), high power supply potential (Vdd), and low power supply potential A driving power supply such as (Vss) is input to the signal line driving circuit 12. The signal line driver circuit start signal (SP) and the signal line driver circuit clock signal (S CK), data signal (DATA), and other signals, as well as high power supply potential (Vdd), low power supply potential ( A driving power supply such as Vss is input.

[0017] FIG. 1B is a diagram showing an example of a circuit diagram of the pixel 16 included in the display device shown in FIG. 1A. The pixel 16 shown in FIG. 1(B) has a gate electrically connected to the scanning line 14, and a source and A transistor 17 having one electrode and one drain electrically connected to a signal line 15, The other electrode is electrically connected to the other of the source and drain of the transistor 17. A capacitor element 18 electrically connected to a wiring (also called a capacitor line) that supplies a potential, and one electrode (also referred to as a pixel electrode) is connected to the other of the source and drain of the transistor 17 and the capacitor 18 The other electrode (also called the counter electrode) supplies a counter potential. The transistor 17 has a liquid crystal element 19 electrically connected to a wiring. The capacitor potential and the opposing potential can be set to the same potential. It is possible.

[0018] (Configuration example of the scanning line driving circuit 11) FIG. 2A shows a configuration example of the scanning line driver circuit 11 included in the display device shown in FIG. The scanning line driving circuit 11 shown in FIG. 2(A) is a first scanning line driving circuit clock signal. The wiring for supplying the clock signal (GCK1) for the fourth scanning line driver circuit to the wiring for supplying the clock signal (GCK4) for the fourth scanning line driver circuit and a wiring for supplying a partial clock signal (PGCK1) for the first scanning line driving circuit. a wiring for supplying a partial clock signal (PGCK4) for the first to fourth scanning line driver circuits; First pulse output circuits 20_1 to 20_3 are electrically connected to the scanning lines 14 arranged in the row. an m-th pulse output circuit 20_m electrically connected to the scanning line 14 arranged in the m-th row; It has.

[0019] FIG. 2(B) is a diagram showing an example of a specific waveform of the above signal. The clock signal (GCK1) for the scanning line driving circuit periodically goes high (Fig. 2(B) ) is the same potential as the high power supply potential (Vdd) and the low level potential (in Figure 2(B), The duty ratio is 1 / 2, and the first The second scanning line driving circuit clock signal (GCK2) is the same as the first scanning line driving circuit clock signal. The third scanning line driving circuit is a signal whose phase is shifted by 1 / 4 cycle from the first scanning line driving signal (GCK1). The clock signal (GCK3) for the first scanning line driving circuit is generated from the clock signal (GCK1) for the first scanning line driving circuit. It is a signal with a half-cycle phase shift (i.e., the first scanning line driving circuit clock signal ( The fourth scanning line driving circuit clock signal (GCK4) is an inverted signal of the fourth scanning line driving circuit clock signal (GCK1). ) is a signal whose phase is shifted by 3 / 4 cycle from the clock signal (GCK1) for the first scanning line driving circuit. (i.e., the inverted signal of the clock signal (GCK2) for the second scanning line driving circuit) The partial clock signal (PGCK1) for the first scanning line driving circuit is The clock signal (GCK1) and the fixed potential (in Figure 2(B)), The signal selectively indicates either one of the partial clock signals for the first scanning line driving circuit. The control circuit determines which signal (GCK1 or fixed potential) the clock signal (PGCK1) indicates. Similarly, the second scanning line driving circuit partial clock signal (PG CK2) is either a clock signal for the second scanning line driving circuit (GCK2) or a fixed potential The third scanning line driving circuit partial clock signal (PGCK3) is a signal that selectively indicates , the third scanning line driving circuit clock signal (GCK3) and the fixed potential are selectively The fourth scanning line driving circuit partial clock signal (PGCK4) is a signal indicating the fourth scanning line driving circuit partial clock signal (PGCK4). This signal selectively indicates either the scan line driver clock signal (GCK4) or a fixed potential. be.

[0020] In the above-described display device, the first pulse output circuit 20_1 to the m-th pulse output circuit The circuit 20_m can be a circuit having the same configuration. The electrical connection relationship between the terminals of the path varies depending on the pulse output circuit. The relationship will be explained with reference to FIGS. 2(A) and 2(C).

[0021] Each of the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m has a terminal The terminals 21 to 28 are input terminals. Terminal 26 and terminal 28 are output terminals.

[0022] First, the terminal 21 will be described. The terminal 21 of the first pulse output circuit 20_1 is connected to the scanning line It is electrically connected to the wiring that supplies the start signal (GSP) for the drive circuit and outputs the second pulse. The terminals 21 of the input circuit 20_2 to the m-th pulse output circuit 20_m are the same as those of the pulse output circuit in the previous stage. It is electrically connected to terminal 28.

[0023] Next, terminal 22 will be described. The 4a+1 pulse output circuit (a=0, 1, 2...) The terminal 22 of (m-4) / 4) supplies a clock signal (GCK1) for the first scanning line driving circuit. The terminal 22 of the 4a+2 pulse output circuit is electrically connected to the wiring that supplies the second scanning pulse. It is electrically connected to the wiring that supplies the clock signal (GCK2) for the line driver circuit, and The terminal 22 of the pulse output circuit supplies a clock signal (GCK3) for the third scanning line driving circuit. The terminal 22 of the 4a+4 pulse output circuit is electrically connected to the wiring that supplies the fourth scanning pulse. It is electrically connected to a wiring that supplies a clock signal (GCK4) for the line driver circuit.

[0024] Next, terminal 23 will be described. Terminal 23 of the 4a+1th pulse output circuit is It is electrically connected to the wiring that supplies the clock signal (GCK2) for the scanning line driving circuit, and the 4th The terminal 23 of the +2 pulse output circuit is connected to the clock signal (GCK3) for the third scanning line driving circuit. The terminal 23 of the 4a+3 pulse output circuit is electrically connected to the wiring that supplies the 4 It is electrically connected to the wiring that supplies the clock signal (GCK4) for the scanning line driving circuit, and the 4th The terminal 23 of the +4 pulse output circuit is connected to the first scanning line driving circuit clock signal (GCK1). The power supply is electrically connected to a wiring that supplies the power.

[0025] Next, terminal 24 will be described. Terminal 24 of the 4a+1th pulse output circuit is It is electrically connected to the wiring that supplies the clock signal (GCK3) for the scanning line driving circuit, and the 4th The terminal 24 of the +2 pulse output circuit is connected to the fourth scanning line driving circuit clock signal (GCK4). The terminal 24 of the 4a+3 pulse output circuit is electrically connected to the wiring that supplies the first It is electrically connected to the wiring that supplies the clock signal (GCK1) for the scanning line driving circuit, and the 4th The terminal 24 of the +4 pulse output circuit is connected to the clock signal (GCK2) for the second scanning line driving circuit. The power supply is electrically connected to a wiring that supplies the power.

[0026] Next, the terminal 25 will be described. The terminal 25 of the 4a+1th pulse output circuit is It is electrically connected to a wiring that supplies a partial clock signal (PGCK1) for the scanning line driving circuit, The terminal 25 of the 4a+2 pulse output circuit outputs the partial clock signal ( PGCK2), and terminal 2 of the 4a+3 pulse output circuit 5 is electrically connected to the wiring that supplies the partial clock signal (PGCK3) for the third scanning line driving circuit. The terminal 25 of the 4a+4 pulse output circuit is connected to the fourth scanning line driving circuit partial clock. It is electrically connected to the wiring that supplies the lock signal (PGCK4).

[0027] Next, the terminal 26 will be described. The xth pulse output circuit (x is a natural number between 1 and m) The (x)th terminal 26 is electrically connected to the scanning line 14 arranged in the xth row.

[0028] Next, the terminal 27 will be described. The terminal 27 of the (b+2)th pulse output circuit is electrically connected to the terminal 28 of the (b+2)th pulse output circuit, and the terminal 27 of the (b+2)th pulse output circuit is electrically connected to the terminal 28 of the (m)th pulse output circuit. The terminal 27 of the pulse output circuit of -1 is a stop signal for the first scanning line driving circuit (GSTP1 ), and the terminal 27 of the mth pulse output circuit is electrically connected to the wiring that supplies the second scanning It is electrically connected to the wiring that supplies the stop signal (GSTP2) for the line driver circuit. The stop signal for the first scanning line driving circuit (GSTP1) is, for example, the (m+1)th pulse output circuit. If the (m+1)th pulse output circuit is provided, the signal output from the terminal 28 of the (m+1)th pulse output circuit will Similarly, the stop signal for the second scanning line driving circuit (GSTP2) is a signal corresponding to the temporary stop signal. If the (m+2)th pulse output circuit is provided in the (m+2)th pulse output circuit, the terminal These signals correspond to the signals output from 28. providing an (m+1)th pulse output circuit and an (m+2)th pulse output circuit as Mie circuits; Alternatively, the controller 13 may directly output the signal to the scanning line driving circuit 11. can be supplied.

[0029] The connection relationship of the terminals 28 of each pulse output circuit has already been explained. The following will be cited.

[0030] (Example of pulse output circuit configuration) FIG. 3A is a diagram showing an example of the configuration of the pulse output circuit shown in FIGS. 2A and 2C. The pulse output circuit shown in FIG. 3(A) includes transistors 31 to 41.

[0031] The transistor 31 has a structure in which one of the source and drain supplies a high power supply potential (Vdd). The gate is electrically connected to the terminal 21. To be continued.

[0032] The transistor 32 has a structure in which one of the source and drain supplies a low power supply potential (Vss). The other of the source and drain is electrically connected to a line (hereinafter also referred to as a low power supply potential line). It is electrically connected to the other of the source and drain of the transistor 31 .

[0033] The transistor 33 has one of its source and drain electrically connected to the terminal 22. The other of the source and drain is electrically connected to terminal 28.

[0034] The transistor 34 has one of a source and a drain electrically connected to a low power supply line. The other of the source and drain is electrically connected to terminal 28, and the gate is It is electrically connected to the gate.

[0035] The transistor 35 has one of a source and a drain electrically connected to a low power supply line. The other of the source and drain is connected to the gate of transistor 32 and the gate of transistor 34. The gate is electrically connected to terminal 21.

[0036] The transistor 36 has one of its source and drain electrically connected to a high power supply potential line. The other of the source and drain is connected to the gate of transistor 32, the gate of transistor 34, and the other of the source and drain of transistor 35, and the gate is connected to terminal 2. 7. One of the source and drain of the transistor 36 is electrically connected to the low voltage A power supply that is higher than the power supply potential (Vss) and lower than the high power supply potential (Vdd) It may also be electrically connected to a wiring that supplies a potential (Vcc).

[0037] The transistor 37 has one of a source and a drain electrically connected to a high power supply potential line. The gate is electrically connected to the terminal 24. The source and drain of the transistor 37 One of the terminals may be electrically connected to a wiring that supplies a power supply potential (Vcc). Cut.

[0038] The transistor 38 has one of its source and drain connected to the gate of the transistor 32. The gate of transistor 34, the other of the source and drain of transistor 35, and The other of the source and drain of the transistor 36 is electrically connected to the other of the source and drain of the transistor 36. The transistor 37 has its gate electrically connected to the other of its source and drain, and its gate is connected to the terminal 23. electrically connected.

[0039] The transistor 39 has one of its source and drain connected to the source and drain of the transistor 31. the other of the input and the other of the source and drain of the transistor 32, The other of the source and drain is electrically connected to the gate of transistor 33, and the gate is connected to a high voltage It is electrically connected to a power supply line.

[0040] The transistor 40 has one of its source and drain electrically connected to the terminal 25. The other of the drain and the drain is electrically connected to the terminal 26, and the gate is the gate of the transistor 33. The input terminal of the transistor 39 is electrically connected to the other of the source and drain of the transistor 39 .

[0041] The transistor 41 has one of a source and a drain electrically connected to a low power supply potential line. The other of the source and drain is electrically connected to terminal 26, and the gate is the gate of transistor 34, the other of the source and drain of transistor 35, The other of the source and drain of transistor 36 and the other of the source and drain of transistor 38 The input is electrically connected to one of the inputs.

[0042] In the following, the gate of the transistor 33, the source and drain of the transistor 39, The node to which the other drain and the gate of the transistor 40 are electrically connected is referred to as node A. The gate of transistor 32, the gate of transistor 34, and the source of transistor 35 and the other of the source and drain of transistor 36, and the other of the source and drain of transistor 38 The node to which one of the source and drain of the transistor 41 and the gate of the transistor 41 are electrically connected In this section, the node will be described as a Node B.

[0043] (Example of pulse output circuit operation) An example of the operation of the pulse output circuit described above will be explained with reference to FIGS. 3(B) and 3(C). FIG. 3B shows the first scanning line driving circuit, which is input to the terminal 25 of the pulse output circuit. Partial clock signal for the fourth scanning line driving circuit (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGC K4) is the clock signal for the first scanning line driving circuit (GCK1) to the fourth scanning line driving circuit (GCK2). Pulse output circuit when either of the clock signals (GCK4) for the line driver circuit is used The potentials of the signals input to each terminal of the MOSFETs 1 and 2, as well as the potentials of the nodes A and B, are shown in FIG. 3(C) is a part for the first scanning line driving circuit, which is input to the terminal 25 of the pulse output circuit. Clock signal (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGCK4) When any one of the voltages is at a fixed potential (low power supply potential Vss), The potentials of the signals input to the terminals and the potentials of the nodes A and B are shown. 3B and 3C, the first pulse output circuit 20_1 under each condition. The signals input to each terminal and the signals output from the terminal 26 of the first pulse output circuit 20_1 The signal (Gout1) and the signal (SRout1) output from terminal 28 are written in parentheses. In addition, the output signal (Gout2) of the terminal 26 of the second pulse output circuit 20_2 and and the output signal (SRout2) of the terminal 28 of the third pulse output circuit 20_3. 6 output signal (Gout3) and the output signal of terminal 28 (SRout3 = first pulse output The input signal of the terminal 27 of the circuit 20_1 is also shown. , represents the output signal of the pulse output circuit to the scanning line, and SRout represents the output signal of the pulse output circuit 10 represents the output signal to the subsequent pulse output circuit.

[0044] First, referring to FIG. 3(B), the first scanning pulse is input to the terminal 25 of the pulse output circuit. Partial clock signal for scanning line driver circuit (PGCK1) ~ Partial clock for fourth scanning line driver circuit signal (PGCK4) is the clock signal (GCK1) for the first scanning line driving circuit. - The fourth scanning line driving circuit clock signal (GCK4) will be explained. Reveal.

[0045] During a period t1, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. This turns on the transistors 31 and 35. As a result, the potential of the node A becomes high. The potential of the high level (Vdd to the transistor 31 or 39) The voltage at node B drops to the low power supply voltage (Vss). In response to this, the transistors 33 and 40 are turned on, and the transistor 32 , 34, and 41 are turned off. As a result, during the period t1, The signal output from terminal 28 becomes the signal input to terminal 22, and is output from terminal 26. The signal outputted from the pulse generator 21 is inputted to the terminal 25. The signals input to the terminals 22 and 25 of the output circuit are both at the low power supply potential (Vss). Therefore, during the period t1, the pulse output circuit in question outputs a pulse to terminal 2 of the subsequent pulse output circuit. 1 and outputs a low power supply potential (Vss) to the scanning lines electrically connected to the terminals 26. , which does not directly affect the output signal of the pulse output circuit in the period t1, Since the power supply potential (Vss) is input, the transistor 38 is turned off, and a high voltage is applied to the terminal 24. Since the power supply potential (Vdd) is input, the transistor 37 is turned on, and a low Since the power supply potential (Vss) is input, the transistor 36 is turned off.

[0046] During the period t2, the high power supply potential (Vdd) is applied to the terminals 22 and 25 of the pulse output circuit. The potential of the node A (potential of the source of the transistor 39) is input during the period t1. Therefore, the transistor 39 is turned off. At this time, when a high power supply potential (Vdd) is input to the terminals 22 and 25, The capacitive coupling between the source and gate of transistor 33 and the source and gate of transistor 40 Therefore, the potential of the node A (the potential of the gate of the transistor 33 and the potential of the gate of the transistor 40) The value of the value of the reference voltage (value of the reference voltage) further rises (bootstrap operation). By doing so, a high voltage can be generated without reducing the potential output from the terminals 28 and 26. Therefore, during the period t2, the pulse output circuit The path is connected to the scanning line electrically connected to the terminal 21 and the terminal 26 of the pulse output circuit at the subsequent stage. The power supply potential (Vdd) is output. Note that the output signal of the pulse output circuit in the period t2 is However, since the low power supply potential (Vss) is input to the terminal 24, the transistor 37 is in the OFF state.

[0047] During a period t3, a low power supply potential (Vss) is input to the terminal 21 of the pulse output circuit. This turns off the transistors 31 and 35. At this time, the node A is in a floating state. Therefore, the transistor 33 and the transistor 40 are maintained in the on state. As a result, during the period t3, the signal output from the terminal 28 of the pulse output circuit is The signal input to terminal 22 is the signal output from terminal 26, and the signal output from terminal 25 is the signal input to terminal 26. During the period t3, the terminals 22 and 25 of the pulse output circuit are Therefore, during the period t3, the high power supply potential (Vdd) is input to both of the pulses. The output circuit is a scanning circuit electrically connected to the terminal 21 and the terminal 26 of the pulse output circuit in the subsequent stage. The high power supply potential (Vdd) is output to the line. Although it is not directly involved in the output signal, the high power supply potential (Vdd) is input to terminal 23, The resistor 38 is turned on.

[0048] During the period t4, the high power supply potential (Vdd) is applied to the terminals 24 and 27 of the pulse output circuit. This turns on the transistors 36 and 37. The potential of B is high level (high power supply potential (Vdd) to transistor 36, The potential of the transistor 37 or 38 is lowered by the threshold voltage of the transistor 38. As a result, the transistors 32, 34, and 41 are turned on. By turning on the transistor 39, the source (one of the source and drain) of the transistor 39 is turned on. The potential becomes the low power supply potential (Vss), which turns on the transistor 39. Therefore, the potential of node A drops to the low power supply potential (Vss). As a result, during the period t4, the pulse output circuit The signal output from the terminal 28 and the signal output from the terminal 26 are connected to a low power supply potential (Vss ) during the period t4. A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0049] After the period t5, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. Node A maintains the low power supply potential (Vss) and node B maintains the high level potential until Therefore, during this period, the pulse output circuit maintains the pulse output A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0050] Next, referring to FIG. 3(C), the first Partial clock signal for scanning line driving circuit (PGCK1) to partial clock signal for fourth scanning line driving circuit (PGCK2) When either of the clock signals (PGCK4) is at a fixed potential (low power supply potential Vss), I will explain.

[0051] During a period t1, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. As described above, during the period t1, the signal output from the terminal 28 of the pulse output circuit is the signal input to terminal 22, and the signal output from terminal 26 is the signal input to terminal 25. During the period t1, the terminals 22 and 23 of the pulse output circuit are connected to each other. The signals input to 25 are both at the low power supply potential (Vss). The pulse output circuit is electrically connected to the terminals 21 and 26 of the subsequent pulse output circuit. A low power supply potential (Vss) is output to the connected scan line.

[0052] During a period t2, a high power supply potential (Vdd) is input to the terminal 22 of the pulse output circuit. As described above, by performing the bootstrap operation, the voltage output from the terminal 28 However, the high power supply potential (Vdd) can be achieved without lowering the potential. Contrary to what has been explained, the signal input to terminal 25 does not change from the low power supply potential (Vss). Therefore, the signal output from the terminal 26 of the pulse output circuit remains at the low power supply potential (Vss). There are even some.

[0053] During a period t3, a low power supply potential (Vss) is input to the terminal 21 of the pulse output circuit. As described above, during the period t3, the signal output from the terminal 28 of the pulse output circuit is the signal input to terminal 22, and the signal output from terminal 26 is the signal input to terminal 25. During the period t3, a high voltage is applied to the terminal 22 of the pulse output circuit. A power supply potential (Vdd) is input to the terminal 21, and a low power supply potential (Vss) is input to the terminal 25. Therefore, during the period t3, the pulse output circuit applies a high voltage to the terminal 21 of the subsequent pulse output circuit. A power supply potential (Vdd) is output to the scan line electrically connected to the terminal 26, and a low power supply potential (Vss ) is output.

[0054] During the period t4, the high power supply potential (Vdd) is applied to the terminals 24 and 27 of the pulse output circuit. As described above, during the period t4, the pulse is output from the terminal 28 of the pulse output circuit. The signal input to the terminal 26 and the signal output from the terminal 26 are at the low power supply potential (Vss). Therefore, during the period t4, the pulse output circuit in question connects the terminal 21 of the subsequent pulse output circuit and A low power supply potential (Vss) is output to the scan line electrically connected to the terminal 26 .

[0055] After the period t5, a high power supply potential (Vdd) is input to the terminal 21 of the pulse output circuit. Node A maintains the low power supply potential (Vss) and node B maintains the high level potential until Therefore, during this period, the pulse output circuit maintains the pulse output A low power supply potential (Vss) is output to the scanning lines electrically connected to the terminals 21 and 26. do.

[0056] (Regarding the pulse output circuit and the scanning line driving circuit having the pulse output circuit) In the above-described pulse output circuit, the period t2 and the period At t3, it is determined whether or not to output a selection signal (high power supply potential (Vdd)) to the scan line. Specifically, the pulse output circuit is configured such that the signal input to the terminal 25 is a first scanning line driving circuit. If it is a clock signal for the circuit, the selection signal is output and the fixed potential (low power supply potential (Vss)) In this case, the pulse output circuit outputs a non-selection signal. It also has the function of shifting the selection signal to the subsequent pulse output circuit regardless of the operation. In other words, a shift register can be configured by using a plurality of such pulse output circuits. do.

[0057] In the display device disclosed in this specification, the scanning line driving circuit has the shift register. Therefore, the display device can control the supply of the selection signal for each scanning line. That is, the display device disclosed in this specification rewrites an image only in an arbitrary area. This is a display device that can do this.

[0058] In addition, the display device disclosed in this specification performs the above operation by controlling a clock for a first scanning line driving circuit. Wiring that supplies a signal indicating a clock signal (GCK1) or a fixed potential (low power supply potential (Vss)) -Fourth scanning line driving circuit clock signal (GCK4) or fixed potential (low power supply potential (Vss This can be achieved by providing wiring that supplies a signal indicating Therefore, the display device disclosed in this specification is a display device that can be partially driven, but does not require wiring. This is a display device that can simplify the circuit configuration including the display device.

[0059] The controller 1 determines whether to supply a clock signal or a fixed potential to the wiring. The specific configuration of the controller 13 and the wiring are as follows: An example of a method for selecting a signal to be output will be described below.

[0060] (Configuration example of controller 13) FIG. 4 shows a controller with three modes: normal mode, partial drive mode, and standby mode. 1 is a diagram showing an example of the configuration of the roller 13. Note that the normal mode is the first scanning line driving mode described above. Partial clock signal for the circuit (PGCK1) to partial clock signal for the fourth scanning line driving circuit (P Regardless of the period, the first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK4) This is the mode in which the signal is the same as the clock signal (GCK4) for the scanning line driving circuit. The partial driving mode is the above-mentioned partial clock signals (PGCK1) to (PGCK2) for the first scanning line driving circuit. The fourth scanning line driving circuit partial clock signal (PGCK4) is The same signal as the clock signal (GCK1) to the clock signal (GCK4) for the fourth scanning line driving circuit The standby mode is a mode in which the scanning line driving circuit 11 and the signal This is a mode in which a clock signal or the like is not supplied to the signal line driver circuit 12. The controller 13 includes a signal generating circuit 131, a memory circuit 132, a comparison circuit 133, and a selection circuit. circuit 134 and a display control circuit 135.

[0061] The signal generating circuit 131 operates the scanning line driving circuit 11 and the signal line driving circuit 12 to generate a pixel Specifically, the pixel section 10 is a circuit for generating a signal for forming an image. Image signals (Data) input to multiple pixels arranged in a trix, scanning line drive A signal (for example, a start signal (SP ), clock signal (CK), and high power supply potential (Vdd) and low power supply potential (Vdd). It is a circuit that generates and outputs a power supply potential (Vss) etc. In 3, a signal generating circuit 131 outputs an image signal (Data) to a memory circuit 132. and outputs the signal to the display control circuit 135 to control the operation of the scanning line drive circuit 11 or the signal line drive circuit 12. The signal generating circuit 131 outputs a signal to the memory circuit 132 to control the If the image signal (Data) is an analog signal, it is converted via an A / D converter, etc. The image signal (Data) can then be converted into a digital signal.

[0062] The memory circuit 132 stores image signals for forming a first image to a second image in the pixel portion 10. a plurality of memories 13 for storing image signals for forming n images (n being a natural number); 6. The memory 136 is a DRAM (Dynamic Random Access Memory). ess Memory), SRAM (Static Random Access Me The memory 136 may be configured using a memory element such as a memory. The number of memories 136 is not limited as long as they are configured to store an image signal for each image formed in the memory 136. In addition, the image signals stored in the plurality of memories 136 are compared. The signal is selectively read out by a path 133 and a selection circuit 134.

[0063] The comparison circuit 133 compares the kth image (k is an integer greater than or equal to 1 and less than n) stored in the memory circuit 132 with the kth image (k is an integer greater than or equal to 1 and less than n). Selectively select an image signal for forming an image (k+1) and an image signal for forming an image (k+2). The kth image signal is read out, compared, and the difference is detected. The image and the (k+1)th image are images that are successively displayed in the pixel section 10. The difference is detected by comparing the image signals at 133. It is determined whether the mode of 3 is a normal mode, a partial drive mode, or a standby mode. do.

[0064] The selection circuit 134 selects an image signal to the pixel unit 10 based on the difference detected by the comparison circuit 133. Specifically, the selection circuit 134 is a circuit that selects the output of the comparison circuit 133. If the drive mode is determined to be the partial drive mode, one frame of image signal is output. When the camera is in standby mode, the image signal is selectively output, and when the camera is in standby mode, the image signal is not output. It is a simple circuit.

[0065] The display control circuit 135 receives a start signal (SP), a clock signal (CK), a high power supply potential ( The scanning line driver circuit 11 and the signal line driver circuit 12 are connected to the control signals such as the power supply potential (Vdd) and the low power supply potential (Vss). This is a circuit that controls the supply to the operation circuit 12.

[0066] Specifically, when the comparison circuit 133 determines that the normal mode is selected, the selection circuit 134 The image signal (Data) supplied from the The drive circuit 11 and the signal line drive circuit 12 are supplied with control signals (start signal (SP), supplying a clock signal (CK), a high power supply potential (Vdd), and a low power supply potential (Vss) At this time, the first partial clock for the scanning line driving circuit supplied to the scanning line driving circuit 11 is The partial clock signal (PGCK1) to the partial clock signal (PGCK4) for the fourth scanning line driving circuit are The first scanning line driving circuit clock signal (GCK1) to the fourth scanning line driving clock signal (G CK4) will be the same signal.

[0067] Also, when the comparison circuit 133 determines that the partial drive mode is selected, the selection circuit 134 The image signal (Data) supplied from the image sensor 11 is selectively output to the signal line driving circuit 12, A control signal (start signal (SP)) is sent to the scanning line driving circuit 11 and the signal line driving circuit 12. , clock signal (CK), high power supply potential (Vdd), and low power supply potential (Vss). At this time, the first scanning line driving circuit portion supplied to the scanning line driving circuit 11 is Clock signal (PGCK1) to partial clock signal for the fourth scanning line driving circuit (PGCK4) The first scanning line driving circuit clock is generated in response to the image signal (Data) selectively output. The same signal as the clock signal (GCK1) to the clock signal (GCK4) for the fourth scanning line driving circuit or becomes a signal that selectively indicates a fixed potential.

[0068] If the comparison circuit 133 determines that the standby mode is selected, the selection circuit 134 selects the image. When the image signal (Data) is not supplied, the scanning line driving circuit 11 and the signal line driving circuit 1 2, control signals (start pulse signal (SP), clock signal (CK), high power supply voltage In other words, the comparator circuit 13 does not supply the power supply voltages (Vdd, Vss, etc.). When the standby mode is determined by the scanning line driving circuit 11 and the signal line driving circuit 12 completely stop the operation of

[0069] However, if the period determined to be in standby mode is short, the high power supply potential (Vdd) and low power supply potential (Vdd) are It is also possible to configure the device so that the power supply potential (Vss) is continuously supplied. And the low power supply potential (Vss) is supplied to the wiring when the potential of the wiring is higher than the high power supply potential (Vdd) or The potential of the power supply is fixed to a low potential (Vss). The line will change to a high power supply potential (Vdd) or a low power supply potential (Vss). Since changes in Vdd and Vss are accompanied by power consumption, Turning off and re-supplying power may result in increased power consumption. In such a case, a configuration in which a high power supply potential (Vdd) and a low power supply potential (Vss) are continuously supplied is used. In the above description, "not supplying" a signal means that the A potential different from a predetermined potential is supplied to a wiring that supplies a signal, or a potential is applied to the wiring. This refers to a state in which electrically connected nodes are floating.

[0070] In addition, if the standby mode is prolonged or if the driving range is within a specific range in the partial drive mode, If the scan lines are in a non-selected state for a long period of time, the liquid crystal element 19 is directly This may cause the device to burn out. Therefore, regardless of the mode, the polarity of the voltage applied to the liquid crystal element for each predetermined frame or each predetermined period is It is preferable to reverse the gender.

[0071] In the controller 13, the scanning line driving circuit 11 and the signal line driving circuit 12 are By controlling the operation of 2, it is possible to reduce the power consumption of the display device.

[0072] (An example of the transistor 17 provided in the pixel 16) The transistor 17 provided in the pixel 16 of the display device described above is in an off state for a long period of time. Therefore, the transistor 17 has excellent off characteristics (off A transistor with a low leakage current is preferred. An example of a transistor will be described with reference to FIG. 5. Specifically, a transistor including an oxide semiconductor layer will be described. The transistor is described below. By optimizing the gate insulating film, it is possible to reduce the off-state current to an extremely low level (as will be described in detail below). Therefore, there is a possibility that an image signal may not be input to a specific pixel for a long period of time. This is a transistor suitable for use as the transistor 17 in the pixel 16 of the display device. The above-mentioned pulse output circuit can also be configured using this transistor. That is, the transistors can be applied as the transistors 31 to 41. In this case, the number of manufacturing processes can be reduced, thereby reducing costs and improving yields.

[0073] The transistor 211 shown in FIG. 5 has a gate electrode provided on a substrate 220 having an insulating surface. a gate insulating layer 222 provided on the gate layer 221; an oxide semiconductor layer 223 provided thereon; and a source layer provided thereon. 5, the transistor 21 has a gate electrode 224a and a drain electrode 224b. an insulating layer 225 covering the oxide semiconductor layer 221 and in contact with the oxide semiconductor layer 223; A protective insulating layer 226 is shown.

[0074] As described above, the transistor 211 illustrated in FIG. 5 includes the oxide semiconductor layer 223 as a semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 223 is a quaternary metal oxide. In-Sn-Ga-Zn-O system, which is a ternary metal oxide, In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O system, Sn-Al-Zn-O system, binary metal oxide In-Zn-O system, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-M The materials used are In-O, Sn-O, Zn-O, and other single-element metal oxides. The oxide semiconductor may contain SiO2. The In-Ga-Zn-O oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio. Elements other than In, Ga, and Zn may also be included. stomach.

[0075] The oxide semiconductor layer 223 has the chemical formula InMO3(ZnO) m (m>0) A thin film containing M selected from Ga, Al, Mn, and Co can be used. It represents one or more metal elements. For example, M may be Ga, Ga and Al, Ga and Mn, Alternatively, Ga and Co can be selected.

[0076] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, the target to be used The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (InO In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn= 15:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0077] The oxide semiconductor described above is designed to suppress fluctuations in electrical characteristics by removing hydrogen and moisture, which are factors that cause fluctuations. By intentionally eliminating impurities such as hydroxyl groups or hydrides (also called hydrogen compounds), It is an oxide semiconductor that has been purified and made electrically i-type (intrinsic).

[0078] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers (close to zero) originating from hydrogen or oxygen vacancies in the semiconductor layer. The carrier density is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 is less than That is, the carrier density due to hydrogen or oxygen vacancies in the oxide semiconductor layer is reduced to almost zero. Since there are very few carriers derived from hydrogen, oxygen vacancies, and the like in the oxide semiconductor layer, The leakage current (off-state current) when the transistor is in the off state can be reduced. In addition, the low impurity levels resulting from hydrogen and oxygen vacancies make it possible to withstand light irradiation, temperature changes, and It is possible to reduce fluctuations and deterioration of electrical characteristics due to the application of a bias. The smaller the value, the more preferable. The current value per 1 μm of channel width (w) is preferably 100 zeptoamperes (zeptoamperes) or less. Preferably, it is 10 zA or less, and more preferably, it is 1 zA or less. There is no hot carrier degradation, so the electrical characteristics of the transistor are not affected by these factors. .

[0079] In this way, the hydrogen contained in the oxide semiconductor layer is thoroughly removed to achieve high purity. A transistor using an oxide semiconductor for a channel formation region has an extremely small off-state current. That is, when the transistor is off, the oxide semiconductor layer acts as an insulator. On the other hand, the oxide semiconductor layer can be regarded as a conductor for the transistor. In the on-state, it is expected to have a higher current supply capacity than semiconductor layers made of amorphous silicon. It can be done.

[0080] The substrate 220 having an insulating surface may be, for example, barium borosilicate glass or aluminophore. A glass substrate such as silicate glass can be used.

[0081] In the transistor 211, an insulating film serving as a base film is formed between the substrate 220 and the gate layer 221. The underlayer has the function of preventing the diffusion of impurity elements from the substrate, and a silicon film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film; The insulating film can be formed by a laminate structure of one or more films.

[0082] The material of the gate layer 221 is molybdenum, titanium, chromium, tantalum, tungsten, aluminum, or the like. Aluminum, copper, neodymium, scandium, and other metal materials, or alloys containing these as the main components The material can be used to form a single layer or a laminate.

[0083] The gate insulating layer 222 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. Silicon layer, silicon nitride layer, silicon oxynitride layer, silicon oxynitride layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, aluminum oxynitride layer, or oxide The hafnium layer can be formed as a single layer or a laminated layer. For example, the first gate insulating layer A silicon nitride layer (Si) with a thickness of 50 nm to 200 nm was formed by plasma CVD. N y(y>0)) is formed on the first gate insulating layer as a second gate insulating layer having a thickness of 5n. A silicon oxide layer (SiO x (x>0) can be stacked .

[0084] The conductive film used for the source layer 224a and the drain layer 224b may be, for example, Al, Cr , Cu, Ta, Ti, Mo, W, or an alloy containing the above elements Alternatively, an alloy film or the like made by combining the above elements can be used. A high melting point metal layer such as Ti, Mo, W, etc. is laminated on either the upper or lower side of the metal layer or both sides. In addition, in order to prevent the occurrence of hillocks and whiskers in the Al film, By using Al material with elements (Si, Nd, Sc, etc.) added, heat resistance is improved. This makes it possible to

[0085] In addition, the source layer 224a and the drain layer 224b (wiring layers formed from the same layers as these) The conductive film (including the conductive metal oxide) may be formed of a conductive metal oxide. Examples include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide In2O3-ZnO alloys or silicon oxide in these metal oxide materials can be used.

[0086] The insulating layer 225 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An inorganic insulating film such as an aluminum oxide nitride film or an aluminum nitride film can be used.

[0087] The protective insulating layer 226 is made of a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, a nitride An inorganic insulating film such as an aluminum oxide film can be used.

[0088] In addition, a planarizing insulating layer is formed on the protective insulating layer 226 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (low In addition, multiple insulating films made of these materials can be stacked. A planarization insulating film may be formed by performing the above-mentioned process.

[0089] <Transistor off-state current> Next, the off-state current of a transistor including a highly purified oxide semiconductor layer was measured. Explain the results.

[0090] First, the off-state current of a transistor including a highly purified oxide semiconductor layer is sufficiently small. Considering this, a transistor with a sufficiently large channel width W of 1 m was prepared and the off-current The off-state current of a transistor with a channel width W of 1 m was measured. In FIG. 6, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The off-current of the transistor is 1×10, which is the detection limit. -12 It is clear that it is below A. In addition, the off-state current of the transistor (here, the value per 1 μm of channel width) was 1 a A / μm(1×10 -18 A / μm or less.

[0091] Next, the off-state current of a transistor including a highly purified oxide semiconductor layer is measured more accurately. As described above, the results obtained by the present invention will be described. The off-state current of the transistor is 1×10, which is the detection limit of the measuring instrument. -12 A or below Therefore, we fabricated a device for characteristic evaluation and obtained a more accurate value of the off-state current (measured as above). The results of determining the concentration of benzoquinone (a value below the detection limit of the measuring instrument) are explained below.

[0092] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0093] The characteristic evaluation element shown in FIG. 7 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. The transistor 804 and the transistor 808 have high-purity A transistor including a gate-doped oxide semiconductor layer was used.

[0094] In the measurement system 800, one of the source and drain of the transistor 804 and the capacitance element One terminal of the transistor 802 and one of the source and drain of the transistor 805 are connected to a power supply (V In addition to the source and drain of the transistor 804, On the other hand, one of the source and drain of the transistor 808 and the other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected. The other of the source and drain of transistor 808 and one of the source and drain of transistor 806 The gate of the transistor 806 is electrically connected to a power supply (the power supply that provides V1). The other of the source and drain of the transistor 805 and the source of the transistor 806 The other of the source and drain is electrically connected to an output terminal.

[0095] The gate of the transistor 804 has a potential difference between the on state and the off state of the transistor 804. The gate of the transistor 808 is supplied with a potential Vext_b2 that controls the A potential Vext_b1 is supplied to control the ON and OFF states of the switch 808. The output terminal outputs a potential Vout.

[0096] Next, a current measurement method using the above characteristic evaluation element will be described.

[0097] First, an outline of the initial period during which a potential difference is applied to measure the off-state current will be described. In the initial period, the gate of the transistor 808 is connected to the ON state. A potential Vext_b1 is input to the other of the source and drain of the transistor 804. A node electrically connected to the source or drain of the transistor 808 The other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected to A potential V1 is applied to a node A, which is a node (node). Here, the potential V1 is, for example, a high potential. In addition, the transistor 804 is kept in an off state.

[0098] Thereafter, a potential V that turns off the transistor 808 is applied to the gate of the transistor 808. ext_b1 is input to turn off the transistor 808. After the transistor 804 is turned off, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initial period is over, the node A and the source and drain of the transistor 804 A potential difference occurs between node A and the source and drain of transistor 808. Since a potential difference occurs between the other drain and the transistor 804, A small amount of charge flows through the transistor 808. In other words, an off-current occurs.

[0099] Next, the measurement period of the off-state current will be briefly described. The potential (V2) of one of the source and drain of the transistor 804 and the potential (V3) of the source of the transistor 808 are connected to each other. The other potential (V1) of the source and drain is fixed at a low potential. The potential of the node A is not fixed (floating state). Charge flows through transistor 804 and transistor 808 and is held at node A over time. The amount of charge stored at node A fluctuates. In other words, the output potential Vout at the output terminal also fluctuates.

[0100] Details of the relationship between the potentials during the initial period when the potential difference is applied and the subsequent measurement period The timing chart is shown in Figure 8.

[0101] In the initial period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This sets the potential of node A to V2, that is, a low potential ( Note that it is not necessary to apply a low voltage (VSS) to node A. The potential Vext_b2 is set to a potential (low potential) that turns off the transistor 804. Then, the potential Vext_b1 is applied to the transistor 804. The potential (high potential) is set so that the transistor 808 is turned on. The potential of A becomes V1, that is, the high potential (VDD). This sets the node A to a potential that turns off the resistor 808. The initial period ends.

[0102] In the subsequent measurement period, potentials V1 and V2 are measured as charges flow into node A. Alternatively, the potential V1 and the potential V2 are set to potentials that cause charges to flow out of the node A. is the low potential (VSS). However, at the timing when the output potential Vout is measured, Since it is necessary to operate the output circuit, V1 is temporarily set to a high potential (VDD). Note that the period when V1 is at a high potential (VDD) is short enough to not affect the measurement. Between.

[0103] When a potential difference is applied as described above and the measurement period begins, the voltage at node A The amount of charge held in the transistor fluctuates, and the potential at node A fluctuates accordingly. This means that the potential at the gate of the resistor 805 fluctuates over time. The potential of the output potential Vout of the transistor also changes.

[0104] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0105] Before calculating the off-state current, the relationship between the potential VA of node A and the output potential Vout is calculated. This makes it possible to find the potential VA of the node A from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows: It is possible.

[0106]

number

[0107] The charge QA at node A is calculated by the potential VA at node A, the capacitance CA connected to node A, Using a constant (const), it is expressed as follows: The quantity CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0108]

number

[0109] The current IA at node A is the charge flowing into (or out of) node A. Since this is the time derivative of , the current IA at node A is expressed as follows:

[0110]

number

[0111] In this way, the capacitance CA connected to node A and the output potential Vout of the output terminal are The current IA of node A can be calculated.

[0112] By the method described above, the current flowing between the source and drain of the transistor in the off state The leakage current (off current) can be measured.

[0113] Here, a highly purified oxide film with a channel length L=10 μm and a channel width W=50 μm is used. A transistor 804 having an oxide semiconductor layer, a transistor 805 having a highly purified oxide semiconductor layer, In each of the paralleled measurement systems 800, a capacitance element 80 The capacitance values ​​of 2 were set to 100 fF, 1 pF, and 3 pF.

[0114] In the above measurements, VDD = 5 V and VSS = 0 V. In principle, the potential V1 is set to VSS, and a 100msec. Vout was measured as VDD for only this period. The time Δt was set to approximately 30,000 seconds.

[0115] FIG. 9 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 9, it can be seen that the potential changes over time.

[0116] FIG. 10 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. 10 shows the source-drain voltage of the transistor 804 or the transistor 808. 10 shows the relationship between V and the off-state current I. From FIG. 10, Under these conditions, the off-state current was found to be approximately 40 zA / μm. It was found that the off-state current was 10 zA / μm or less under the condition of a drain voltage of 3.1 V. 1zA is 10 -21 Represents A.

[0117] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C was FIG. 11 shows the transistor 804 or the transistor 805 in a temperature environment of 85° C. 1 shows the relationship between the source-drain voltage V and the off-state current I of the transistor 808. From 1, when the source-drain voltage is 3.1V, the off-current is 100zA / μm It was found that the following was true.

[0118] As described above, in a transistor including a highly purified oxide semiconductor layer, the off-state current It was confirmed that it was sufficiently small.

[0119] (Modification of the display device) The display device having the above-described structure is one embodiment of the present invention, and the display device is different from the above-described display device in the following points. The present invention also includes a display device having the same.

[0120] <Modification of pulse output circuit> For example, as a pulse output circuit, the pulse output circuit shown in FIG. 3(A) may be provided with a source and a drain. One of the source and drain is electrically connected to a high power supply potential line, and the other of the source and drain is connected to a transistor. The gate of transistor 32, the gate of transistor 34, the source and drain of transistor 35 the other of the source and drain of transistor 36, the other of the source and drain of transistor 38 The drain of the transistor 41 is electrically connected to one side of the drain and the gate of the transistor 41. A configuration in which a transistor 50 electrically connected to the reset terminal (Reset) is added (FIG. 12( A) can be applied to the reset terminal. A high-level potential is input during this period, and a low-level potential is input during the other periods. That is, the transistor 50 is a transistor that is turned on during the vertical blanking period. This allows the potential of each node to be initialized during the vertical blanking period. Therefore, it is possible to prevent malfunctions.

[0121] In addition, as a pulse output circuit, a transistor is used in the pulse output circuit shown in FIG. It is also possible to apply a configuration in which 36 is removed (see FIG. 12(B)). Therefore, the number of transistors constituting the pulse output circuit can be reduced. This makes it possible to reduce the layout area of ​​the output circuit and improve yield.

[0122] In addition, as a pulse output circuit, a transistor is used in the pulse output circuit shown in FIG. It is also possible to apply a configuration in which 39 is removed (see FIG. 13(A)). Therefore, the number of transistors constituting the pulse output circuit can be reduced. This makes it possible to reduce the layout area of ​​the output circuit and improve yield.

[0123] In addition, as a pulse output circuit, the pulse output circuit shown in FIG. 3(A) is provided with a source and a drain. One of the inputs is connected to the gate of transistor 33 and the other to the source and drain of transistor 39. The other of the source and drain is electrically connected to the gate of transistor 40. A transistor 51 is added, the gate of which is electrically connected to the high power supply potential line. The transistor 51 can be configured as shown in FIG. 3(B) and (C) are in the OFF state during periods t2 and t3. By adding the gate of the transistor 33, the gate of the transistor 33 is turned on during the periods t2 and t3. This allows the electrical connection between the gate of the transistor 40 and the gate of the transistor 41 to be cut off. The pulse output circuit may be provided with a transistor 51 (see FIG. 13B). The advantages of the former configuration will be described in detail below, comparing it with the former configuration (see FIG. 3(A)).

[0124] First, a case where the transistor 51 is not provided will be described. If the signal alternates between high power supply potential (Vdd) and low power supply potential (Vss), the period t2 and t3 In this case, the output signal at the terminal 28 and the output signal at the terminal 26 are both at the high power supply potential (Vdd). At this time, the potential of the gates of the transistors 33 and 40 (potential of node A) is The capacitive coupling between the source and gate of transistor 33 and the capacitive coupling between the source and gate of transistor 40 On the other hand, the signal input to the terminal 25 is When the potential of the power supply is fixed to the low potential (Vss), the output of the terminal 28 is The signal is at the high power supply potential (Vdd), and the output signal at terminal 26 is at the low power supply potential (Vss). At this time, the potential of the gates of the transistors 33 and 40 (potential of node A) is Only the capacitive coupling between the source and gate of transistor 33 causes a potential higher than the high power supply potential (Vdd). In addition, since the transistor 40 drives the scan line, the transistor 36. The gate of the transistor 40 becomes a large load when the potential is increased by the capacitive coupling. Therefore, in order to operate the pulse output circuit, the channel length of the transistor 33 must be adjusted. Therefore, the channel width (W / L) must be increased.

[0125] In contrast, when the transistor 51 is provided, the transistor The electrical connection between the gate of transistor 33 and the gate of transistor 40 is thus cut off. Only the potential of the gate of the transistor 33 can be increased by capacitive coupling. Therefore, the load on the capacitive coupling can be reduced. In addition, the channel length of the transistor 36 is Since there is no need to increase the width (W / L), the layout area can be reduced. .

[0126] In FIG. 13B, the gate of the transistor 51 is electrically connected to the high power supply potential line. The gate is electrically connected to the block terminal (Block). 14(A)) or a configuration in which the terminal 25 is electrically connected (see FIG. 14(B)). It is possible to use the block terminal (Block) as a terminal 25. Clock signal for the first scanning line driving circuit (GCK1) to clock signal for the fourth scanning line driving circuit When a signal identical to either of (GCK4) is input, a high-level potential is input, When a fixed potential (low power supply potential (Vss)) is input, if a low-level potential is input, That is, the transistor 51 receives the clock signal for the first scanning line driving circuit at the terminal 25. The clock signal (GCK1) to the fourth scanning line driving circuit clock signal (GCK4) are the same as When a signal is input, it is turned on and a fixed potential (low power supply potential (Vss)) is input. This allows the gate of the transistor 33 and the transistor 34 to be turned off. This allows the timing at which the electrical connection of the gate of the transistor 40 is cut off to be made earlier. In addition, the gate of the transistor 51 is electrically connected to the terminal 25 (see FIG. 14(B)). The advantage of this method is that it does not require the addition of any new signals.

[0127] <Modification of Transistor> In the display device described above, the transistor 17 provided in the pixel 16 is A configuration in which a transistor 211 with a bottom gate structure called a channel-etch type is applied (Fig. 5), the transistor 17 is not limited to this configuration. The transistors shown in 5(A) to 5(C) can be applied.

[0128] The transistor 510 shown in FIG. 15A is a channel protection type (also called a channel stop type). This is one of the bottom gate structures known as bottom gate structures.

[0129] The transistor 510 includes a gate layer 221, a gate insulator 222, and a gate insulating layer 223 on a substrate 220 having an insulating surface. The insulating layer 222, the oxide semiconductor layer 223, and the oxide semiconductor layer 223 are covered with a channel forming region. The insulating layer 511, which functions as a channel protection layer, the source layer 224a, and the drain layer 224b The source layer 224a, the drain layer 224b, and the insulating layer 511 are covered with a protective layer. An insulating layer 226 is formed.

[0130] The transistor 520 shown in FIG. 15B is a bottom-gate transistor. On a substrate 220 having a surface, a gate layer 221, a gate insulating layer 222, a source The source layer 224a, the drain layer 224b, and the oxide semiconductor layer 223 are included. An insulating layer 225 is provided to cover the gate electrode 224a and the drain layer 224b and to be in contact with the oxide semiconductor layer 223. A protective insulating layer 226 is further formed on the insulating layer 225.

[0131] In transistor 520, gate insulating layer 222 is formed between substrate 220 and gate layer 221. A source layer 224a and a drain layer 224b are provided on the gate insulating layer 222. The gate insulating layer 222, the source layer 224a, and the drain The oxide semiconductor layer 223 is provided over the layer 224b.

[0132] The transistor 530 shown in FIG. 15C is a top-gate transistor. The transistor 530 is formed on the substrate 220 having an insulating surface, with an insulating layer 531, an oxide The semiconductor layer 223, the source layer 224a, the drain layer 224b, the gate insulating layer 222, the gate The source layer 224a and the drain layer 224b are connected to the wiring layer 532a. The wiring layer 532b is provided adjacent to and electrically connected to the first and second wiring layers 532a and 532b.

[0133] The insulating layers 511 and 531 are typically formed of a silicon oxide film, a silicon oxynitride film, or an oxide film. An inorganic insulating film such as an aluminum nitride film or an aluminum oxynitride film can be used. The conductive film used for the wiring layer 532a and the wiring layer 532b is made of, for example, Al, C An element selected from the group consisting of r, Cu, Ta, Ti, Mo, and W, or a composite containing the above elements. Gold or an alloy film made of a combination of the above elements can be used. A high melting point metal layer such as Ti, Mo, or W is laminated on either or both of the upper and lower sides of any metal layer. In addition, in order to prevent the occurrence of hillocks and whiskers in the Al film, Heat resistance is improved by using Al material with added elements (Si, Nd, Sc, etc.). It is possible to do this.

[0134] (Regarding various electronic devices equipped with display devices) An example of an electronic device incorporating the display device disclosed in this specification will be described below with reference to FIG. 16. This will be explained in light of the above.

[0135] FIG. 16(A) shows a notebook-type personal computer, which includes a main body 2201, It is composed of a housing 2202, a display unit 2203, a keyboard 2204, and the like.

[0136] FIG. 16(B) is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 2 213, an external interface 2215, an operation button 2214, etc. are provided. In addition, a stylus 2212 is provided as an accessory for operation.

[0137] FIG. 16C shows an electronic book 2220 as an example of electronic paper. The book 2220 is made up of two cases, a case 2221 and a case 2223. 2221 and the housing 2223 are integrated by a shaft 2237. With this configuration, the electronic book 2220 can be opened and closed with the opening and closing movement of the arrows. It can be used like a paper book.

[0138] The housing 2221 incorporates a display unit 2225, and the housing 2223 incorporates a display unit 2227. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2225 in FIG. 16(C)) and An image can be displayed on the display unit (the display unit 2227 in FIG. 16C).

[0139] 16C shows an example in which an operation unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power supply 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. or on the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. Furthermore, the electronic book 2220 may be configured to have the function of an electronic dictionary. You may do so.

[0140] The electronic book 2220 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0141] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0142] 16(D) is a diagram showing a mobile phone. The mobile phone has a housing 2240 and The housing 2241 is made up of two housings, a display panel 2242 and a screen. Speaker 2243, microphone 2244, pointing device 2246, camera The housing 2240 is provided with a lens 2247, an external connection terminal 2248, etc. The mobile phone is equipped with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. The antenna is also built into the housing 2241.

[0143] The display panel 2242 has a touch panel function, and the image displayed on the display panel 2242 is shown in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output from module 2249 to the voltage required for each circuit. In addition to the above configuration, a configuration incorporating a non-contact IC chip, a small recording device, etc. It can also be done as follows.

[0144] The display direction of the display panel 2242 changes appropriately depending on the usage mode. The camera lens 2247 is located on the same surface as the lens 2242, allowing video calls. The speaker 2243 and microphone 2244 are not limited to voice calls, but are also used for video calls. Furthermore, the housing 2240 and the housing 2241 can be slid apart. As shown in Figure 16(D), it can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0145] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may also be equipped with an infrared communication function, a television receiving function, etc.

[0146] FIG. 16(E) is a diagram showing a digital camera. The digital camera has a main body 226 1, display unit (A) 2267, eyepiece 2263, operation switch 2264, display unit (B) 22 It is composed of a battery 2266, etc.

[0147] FIG. 16(F) is a diagram showing a television device. In the television device 2270, A display unit 2273 is built into the housing 2271. The display unit 2273 displays images. In this case, the housing 2271 is supported by a stand 2275. The figure shows the configuration.

[0148] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote control. This can be done by the remote control operation device 2280. The channel and volume can be controlled by the -2279, and the information displayed on the display 2273 is In addition, the remote control operation device 2280 can be used to operate the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0149] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, and two-way (between sender and receiver, or between receivers) information communication. It is possible to do so. [Explanation of symbols]

[0150] 10 Pixel section 11 Scanning line driving circuit 12 Signal line driver circuit 13 Controller 14 scan lines 15 Signal line 16 pixels 17 Transistor 18 Capacitor element 19 Liquid crystal element 20_1~20_m Pulse output circuit 20_x Pulse output circuit Terminals 21-28 31~41 Transistor 50, 51 Transistors 131 Signal generation circuit 132 Memory circuit 133 Comparison circuit 134 Selection circuit 135 Display control circuit 136 memory 211 Transistor 220 board 221 Gate Layer 222 Gate insulating layer 223 Oxide semiconductor layer 224a Source Layer 224b Drain layer 225 Insulating Layer 226 Protective Insulation Layer 510 Transistor 511 Insulating layer 520 transistor 530 Transistor 531 Insulating layer 532a wiring layer 532b wiring layer 800 measurement system 802 Capacitor element 804 transistor 805 transistor 806 Transistor 808 Transistor 2201 Main unit 2202 Case 2203 Display section 2204 keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 e-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation Key 2235 Speaker 2237 Shaft 2240 chassis 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cells 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Control

Claims

1. A multi-stage circuit, at least one circuit of the plurality of stages of circuits includes first to tenth transistors and first to fifth wirings; the first circuit has a function of outputting a first signal to the first wiring; the first wiring is always electrically connected to the gate of the transistor of the pixel; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the one of the source and the drain of the seventh transistor; a first power supply potential is supplied to the gate of the sixth transistor; the gate of the seventh transistor is always electrically connected to the fifth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the sixth transistor; a gate of the ninth transistor and a gate of the tenth transistor are input with mutually different signals; Semiconductor device.

2. A multi-stage circuit, at least one circuit of the plurality of stages of circuits includes first to tenth transistors and first to fifth wirings; the first circuit has a function of outputting a first signal to the first wiring; the first wiring is always electrically connected to the gate of the transistor of the pixel; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the one of the source and the drain of the seventh transistor; a first power supply potential is supplied to the gate of the sixth transistor; the gate of the seventh transistor is always electrically connected to the fifth wiring; one of the source and the drain of the eighth transistor is always electrically connected to the third wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is always electrically connected to the gate of the sixth transistor; a gate of the ninth transistor and a gate of the tenth transistor are input with different signals; the third wiring has a function of supplying a second power supply potential; the fourth wiring has a function of supplying a clock signal; Semiconductor device.

3. In claim 1 or claim 2, the third transistor has a function of controlling a conduction state between a gate of the first transistor and a gate of the fourth transistor; Semiconductor device.

4. In any one of claims 1 to 3, Each of the first to tenth transistors has the same polarity. Semiconductor device.

Images