Instruction generation method, processing unit, instruction generation device, and program

Abstract

To generate a data transfer instruction which can execute data transfer at low cost according to the architecture of a processor.SOLUTION: An instruction generation method which generates an instruction which makes an arithmetic processing device having a plurality of first blocks including a plurality of computation execution units execute generates at least one data transfer instruction which makes the arithmetic processing device execute at least one of a plurality of data transfers in which a transfer source is the computation execution unit and a transfer destination is the computation execution unit, or the plurality of data transfers in which the transfer source is the first block and the transfer destination is the first block, by at least one processor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an instruction generation method, an arithmetic processing device, and , instruction generation device and program Regarding. [Background technology]

[0002] Deep learning is generally performed using processors with multiple built-in cores, such as GPUs (Graphics Processing Units). Recently, processors (accelerators) specialized for deep learning have been developed to improve the calculation speed of deep learning. The architecture of processors specialized for deep learning (e.g., the number of computing units, the number of blocks including computing units, the number of block hierarchies, and instructions) may differ from the architecture of general-purpose products such as GPUs. For this reason, to efficiently operate processors specialized for deep learning, an instruction generation device such as a compiler that appropriately generates instructions to be executed by the processor is important. Summary of the Invention [Problem to be solved by the invention]

[0003] In the present disclosure, a data transfer instruction that can execute data transfer at low cost in accordance with the processor architecture is generated. [Means for solving the problem]

[0004] An instruction generation method according to an embodiment of the present invention is an instruction generation method for generating an instruction sequence to be executed by an arithmetic processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks and at least one second memory, and each of the plurality of first blocks including at least one arithmetic unit and at least one first memory, wherein at least one processor generates the instruction sequence to cause the arithmetic processing device to execute at least one of a first data transfer in parallel, a second data transfer in parallel, a third data transfer in parallel, or a fourth data transfer in parallel, wherein a source of the first data transfer is one or more of the plurality of first blocks, and a destination of the first data transfer is one or more first blocks of the plurality of first blocks, a source of the second data transfer is one or more first blocks of the plurality of first blocks, a destination of the second data transfer is one or more second blocks of the plurality of second blocks, a source of the third data transfer is one or more second blocks of the plurality of second blocks, a destination of the third data transfer is one or more first blocks of the plurality of first blocks, a source of the fourth data transfer is one or more second blocks of the plurality of second blocks, and a destination of the fourth data transfer is one or more second blocks of the plurality of second blocks. and generating the instruction sequence includes determining, by the at least one processor, a combination and an execution order of at least one multicast instruction selected from a plurality of types of multicast instructions. . [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram illustrating an example of a processing unit according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing an example of a system including a board on which the arithmetic processing device of FIG. 1 is mounted and a host, and an information processing device that generates instructions to be executed by the arithmetic processing device. [Figure 3] FIG. 10 is an explanatory diagram showing an example of classification of data transfer according to a data transfer path. [Figure 4] 3 is a flowchart showing an example of the operation of a compiler realized by the information processing device of FIG. 2. [Figure 5]FIG. 10 is a block diagram illustrating an example of a system including a board and a host according to another embodiment, and an information processing device that generates instructions to be executed by the arithmetic processing device. [Figure 6] 6 is an explanatory diagram showing an example of a data transfer instruction that can be executed by the arithmetic processing unit of FIG. 5; [Figure 7] FIG. 7 is an explanatory diagram showing an example of data transfer in response to the multicast command in FIG. 6; [Figure 8] FIG. 10 is an explanatory diagram showing an example of data transfer between eight second-level blocks BLK2 in a third-level block BLK3. [Figure 9] 6 is a flowchart showing an example of the operation of a compiler realized by the information processing device of FIG. 5. [Figure 10] 6 is a block diagram showing an example of the hardware configuration of the host and the information processing device shown in FIGS. 2 and 5. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0006] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0007] 1 is a block diagram showing an example of a processing device according to an embodiment of the present invention. For example, the processing device 100 shown in FIG. 1 may function as an accelerator that executes deep learning. The present invention may be applied to a processor such as an accelerator specialized for deep learning, or may be applied to other processors that are not specialized for deep learning.

[0008] The arithmetic processing device 100, an example of a processor, includes multiple first-level blocks BLK1, multiple second-level blocks BLK2 each including multiple first-level blocks BLK1, and multiple third-level blocks BLK3 each including multiple second-level blocks BLK2. Specifically, the arithmetic processing device 100 includes hierarchical second-level blocks BLK2 and third-level blocks BLK3 each including a predetermined number of first-level blocks BLK1. In the following description, the first-level blocks BLK1, the second-level blocks BLK2, and the third-level blocks BLK3 are simply referred to as blocks BLK when not distinguished from one another. The arithmetic processing device 100 can efficiently perform data transfers such as scatter, gather, broadcast, and contraction between the hierarchical blocks BLK by executing various data transfer instructions. Note that the number of levels is merely an example, and the arithmetic processing device 100 may be configured with four or more levels. Furthermore, the blocks BLK in each level may include at least either a memory or a computing unit, and the computing unit may perform matrix operations.

[0009] The arithmetic processing device 100 may be in the form of a chip or a package such as a CSP (Chip Size Package). The second-level block BLK2 has a memory MEM2, and the third-level block BLK3 has a memory MEM3. The first-level block BLK1 is an example of a first block, and the second-level block BLK2 and the third-level block BLK3 are examples of second blocks.

[0010] In the example shown in FIG. 1, the arithmetic processing device 100 has four third-level blocks BLK3. Each third-level block BLK3 has eight second-level blocks BLK2. Each second-level block BLK2 has 16 first-level blocks BLK1. However, the number of third-level blocks BLK3 included in the arithmetic processing device 100, the number of second-level blocks BLK2 included in each third-level block BLK3, and the number of first-level blocks BLK1 included in each second-level block BLK2 are not limited to those shown in FIG. 1. However, it is preferable that the number of third-level blocks BLK3 included in the arithmetic processing device 100, the number of second-level blocks BLK2 included in each third-level block BLK3, and the number of first-level blocks BLK1 included in each second-level block BLK2 are each 2 n (n is an integer greater than or equal to 1).

[0011] Each first-level block BLK1 has an arithmetic unit EX2 and multiple arithmetic units OPU. The arithmetic unit OPU has a memory MEM1 (FIG. 2) that holds data to be executed by the arithmetic unit EX2 and the arithmetic unit EX1 (FIG. 2), and supplies data to the arithmetic units EX1 and EX2 according to instructions. For example, the arithmetic unit EX1 (FIG. 2) may be an integer arithmetic unit. The arithmetic unit OPU is an example of an arithmetic execution unit. For example, each of the arithmetic units EX1 and EX2 can execute SIMD (Single Instruction Multiple Data) instructions. Because the multiple arithmetic units EX1 and the multiple arithmetic units EX2 can each execute instructions in parallel, each arithmetic processing device 100 or board 200 (FIG. 2) can operate as a huge SIMD execution machine.

[0012] Furthermore, when memories MEM1, MEM2, and MEM3 in each block BLK are described without distinction, they are simply referred to as memory MEM. Memory MEM1 (FIG. 2) in each arithmetic unit OPU mounted in the first-level block BLK1 may be described as the memory of the first-level block BLK1.

[0013] 2 is a block diagram showing an example of a system including a board 200 on which the arithmetic processing device 100 of FIG. 1 is mounted, a host 300, and an information processing device 400 that generates instructions to be executed by the arithmetic processing device 100. The board 200 shown in FIG. 2 has a plurality of arithmetic processing devices 100 and a memory MEM4 connected to each other. For example, the board 200 may have the form of a board on which a plurality of arithmetic processing devices 100 and a memory MEM4 are mounted. The plurality of arithmetic processing devices 100 may also be mounted in a multi-chip package. In this case, it is preferable that the plurality of arithmetic processing devices 100 are arranged side by side on a board to improve heat dissipation.

[0014] 2, the board 200 has four arithmetic processing units 100, but the number of arithmetic processing units 100 is not limited to four and may be one or more. The memory MEM4 is provided in common to the four arithmetic processing units 100, but may be provided corresponding to each of the arithmetic processing units 100. A board 200 having multiple arithmetic processing units 100 operates as a single arithmetic processing unit. When the board 200 has multiple arithmetic processing units 100, each of the arithmetic processing units 100 or the board 200 may function as a top-level second block.

[0015] In each arithmetic processing device 100, the memory MEM3 of each third-level block BLK3 is connected to the memory MEM4 and the memory MEM2 of each second-level block BLK2 in the third-level block BLK3, and data can be transferred between them. Furthermore, data transfer instructions and arithmetic instructions may be transferred from the memory MEM4 to each memory MEM3 and from each memory MEM3 to each memory MEM2, respectively.

[0016] Each memory MEM2 is connected to a memory MEM1 installed in each operation unit OPU in the second-level block BLK2, and data can be transferred between them. Data transfer instructions and operation instructions may be transferred from each memory MEM2 to the memory MEM1. Each first-level block BLK1 and each operation unit OPU may have a register.

[0017] The memory MEM4 can transfer data to and from the host memory HOSTM mounted on the host 300. Data transfer instructions and arithmetic instructions may be transferred from the host memory HOSTM to the memory MEM4. Note that, in addition to the data transfer paths shown in Fig. 2, transfer paths (not shown) may be provided for transferring data transfer instructions and arithmetic instructions from the memory MEM4 to each memory MEM3, from each memory MEM3 to each memory MEM2, and from each memory MEM2 to each memory MEM1.

[0018] The host memory HOSTM and the memory MEM4 may transmit and receive information such as data and commands via a PCIe (Peripheral Component Interconnect express) interface. Furthermore, the transfer of information between the host memory HOSTM and the memory MEM4 may be performed by DMA (Direct Memory Access).

[0019] Each arithmetic processing unit 100 on the board 200 executes arithmetic processing using data received from the host 300 based on commands (data transfer commands and arithmetic commands) received from the host 300. Various commands transmitted from the host 300 to the arithmetic processing unit 100 are generated by the information processing unit 400, transferred from the information processing unit 400 to the host 300, and stored in the host memory HOSTM. The information processing unit 400 may be, for example, a server.

[0020] The information processing device 400 functions as a compiler 500 (code generator) that generates an instruction sequence to be executed by the arithmetic processing device 100, using a program executed by a processor such as a built-in CPU (Central Processing Unit). For example, the processor of the information processing device 400 executes an instruction generation method by executing an instruction generation program stored in a memory mounted on the information processing device 400, thereby generating an instruction sequence. The information processing device 400 is an example of an instruction generation device. The dashed arrow between the information processing device 400 and the host 300 indicates that the instruction sequence generated by the compiler 500 is transferred to the host 300. Note that the instruction sequence may be transferred via a network.

[0021] For example, the compiler 500 generates instructions (instruction codes) that cause the board 200 to execute deep learning. In this case, the compiler 500 generates an instruction sequence that causes the board 200 to efficiently execute deep learning, based on a learning model generated using a general-purpose library (framework) for deep learning. For example, the compiler 500 aggregates a sequence of queries instructing the movement of data from a transfer source to a transfer destination into multiple queries that can be processed simultaneously, and generates instruction codes indicating one or multiple data transfer instructions for each of the aggregated multiple queries. This enables the board 200 to improve the calculation speed of deep learning and shorten the calculation time required for deep learning. While not particularly limited, the instruction code may be, for example, a machine language obtained by assembling a description written in assembly language.

[0022] FIG. 3 is an explanatory diagram showing an example of classification of data transfers according to data transfer paths. The data transfer instructions generated by the compiler 500 in FIG. 2 include instructions for moving data between blocks BLK in adjacent hierarchical layers. The arrows in FIG. 3 indicate the paths of data transfers according to the data transfer instructions. For example, a data transfer indicated by a single arrow is realized by one or more data transfer instructions. The black circles in FIG. 3 indicate that data passes through memory MEM during data transfer. In the plan view of the arithmetic processing device 100 shown in FIG. 3, the numbers shown for the 16 first-hierarchical blocks BLK1 in one of the second-hierarchical blocks BLK2 indicate the identifiers of the first-hierarchical blocks BLK1. The same identifiers are assigned to the 16 first-hierarchical blocks BLK1 in the other second-hierarchical blocks BLK2 for which no numbers are shown. Note that the identifiers of the first-hierarchical blocks BLK1 may be assigned in a mirror symmetric manner.

[0023] Although not shown, the four operation units OPU in each first hierarchical block BLK1 are also sequentially assigned identifiers from 0 to 3 as shown in FIG. 1. The eight second hierarchical blocks BLK2 in each third hierarchical block BLK3 are also sequentially assigned identifiers from 0 to 7. The four third hierarchical blocks BLK3 in each arithmetic processing device 100 are also sequentially assigned identifiers from 0 to 3. Furthermore, the four arithmetic processing devices 100 in the board 200 are also sequentially assigned identifiers from 0 to 3.

[0024] The identifiers assigned to each element are merely examples, and are not limited to numbers as long as they are identifiers that can identify each element. For example, addresses that can identify the location of each element may be used as identifiers. The addresses may be memory addresses. Furthermore, register numbers may be used as identifiers.

[0025] Data transfers executed by data transfer instructions include data transfers between operation units OPU within the first hierarchical block BLK1. Data transfers executed by data transfer instructions also include data transfers between first hierarchical blocks BLK1 within the second hierarchical block BLK2 and data transfers between second hierarchical blocks BLK2 within the third hierarchical block BLK3. Data transfers executed by data transfer instructions also include data transfers between third hierarchical blocks BLK3 within the arithmetic processing device 100.

[0026] Combining these data transfers realizes data transfers shown in categories 1 to 4. Note that data transfers from category 1 to category 4 are just an example. For example, if the number of block hierarchies increases, the number of categories also increases. Also, in FIG. 3, for ease of explanation, one data transfer is shown corresponding to each of categories 1 to 4, but in reality, each arithmetic processing device 100 can perform multiple data transfers for each category. Each of data transfers from category 1 to category 4 corresponds to one query that moves data in memory MEM assigned to an arbitrary address to memory MEM assigned to another address between arithmetic units OPU or between first-hierarchy blocks BLK1. Category 1 is a data transfer between arithmetic units OPU (memory MEM1 or register) within the first-hierarchy block BLK1, and the data does not pass through memories MEM2, MEM3, or MEM4.

[0027] Category 2 is data transfer between first-level blocks BLK1 within a second-level block BLK2, and the number of levels of the block BLK through which the data passes is one (second-level block BLK2). Category 3 is data transfer between first-level blocks BLK1 belonging to different second-level blocks BLK2 within a third-level block BLK3, and the number of levels of the block BLK through which the data passes is two (second-level block BLK2 and third-level block BLK3).

[0028] Category 4 is data transfer between first-level blocks BLK1 belonging to different third-level blocks BLK3 within the arithmetic processing device 100, and the number of levels of blocks BLK through which data passes is three (second-level block BLK2, third-level block BLK3, and arithmetic processing device 100 (memory MEM4)). Each of the four arithmetic processing devices 100 within the board 200 can execute data transfers of categories 1 to 4 independently of the other three arithmetic processing devices 100.

[0029] For example, the compiler 500 can generate at least one data transfer instruction that commonly executes multiple data transfers in which the identifiers of the data transfer sources are the same and the identifiers of the data transfer destinations are the same. For example, a data transfer instruction may be generated for each of data transfers in categories 1 to 4. By generating a data transfer instruction for each category, data transfers that pass through similar paths can be easily grouped together, and at least one data transfer instruction that commonly executes multiple data transfers can be easily generated. Note that a data transfer instruction may be generated for data transfers on some of the data transfer paths included in categories 2 to 4.

[0030] Furthermore, the compiler 500 may add mask information (optional information) to each data transfer instruction to disable storage of some data in the destination (memory MEM1, MEM2, MEM3, MEM4 or a storage unit such as a register). This makes it possible to prevent data from being written to the destination specified by the mask information. In other words, of the multiple data transfers that can be executed with one data transfer instruction, any data can be written to the destination. Note that masking (disabling) data transfer using mask information may be executed by masking (disabling) reading of data from the source.

[0031] For example, in category 1, data transfer between a pair of operation units OPU in each of the 512 first-hierarchical blocks BLK1 of the arithmetic processing device 100 can be executed by at least one data transfer instruction. Multiple data transfers included in category 1 can be executed by at least one common data transfer instruction if the identifiers of the operation units OPU from which data is transferred are the same and the identifiers of the operation units OPU to which data is transferred are the same. Here, the identity of the identifiers in category 1 may be determined not only by the identifier assigned to the operation unit OPU, but also by the identifier of a register within the operation unit OPU or the identifier of the memory MEM1.

[0032] In addition, a data transfer instruction that executes a data transfer of Category 1 can mask the storage of data in the destination operation unit OPU by using mask information added to the data transfer instruction. This allows data transfer between any operation units OPU even when an address indicating the data transfer source and an address indicating the data transfer destination are specified in the data transfer instruction. For example, each data transfer of Category 1 may be executed by a unicast instruction that transfers data from one source to one destination.

[0033] In category 2, data transfer from one first hierarchical block BLK1 to another first hierarchical block BLK1 in each of the 32 second hierarchical blocks BLK2 of the arithmetic processing device 100 can be executed by at least one data transfer instruction. For example, in category 2, data transfers in which the identifiers of the data transfer source and the identifiers of the data transfer destination are the same can be executed by at least one common data transfer instruction (e.g., a multicast instruction). For example, each data transfer in category 2 may be executed by a unicast instruction, or may be executed by a combination of a unicast instruction and a multicast instruction.

[0034] In Category 2, the identity of the identifier of the transfer source may be determined when the identifiers of the operation unit OPU and the first hierarchical block BLK1 from which the data is transferred are the same. Similarly, in Category 2, the identity of the identifier of the data destination may be determined when the identifiers of the operation unit OPU and the first hierarchical block BLK1 from which the data is transferred are the same. Here, the identity of the identifiers in Category 2 may be determined using, in addition to the above, the identifier of a register in the operation unit OPU, the identifier of the memory MEM1, or the identifier of the memory MEM2.

[0035] In Category 3, data transfer between the first hierarchical block BLK1 and the second hierarchical block BLK2 can be executed by at least one data transfer instruction (e.g., a unicast instruction). Also, in Category 3, data transfer between the second hierarchical blocks BLK2 in each of the four third hierarchical blocks BLK3 of the arithmetic processing device 100 can be executed by at least one data transfer instruction (e.g., a multicast instruction). For example, multiple types of multicast instructions are prepared depending on the number of transfer sources and the number of transfer destinations. Instructions such as unicast instructions and multicast instructions are also described in Figures 6 and 7. For example, in Category 3, data transfers in which the identifiers of the data transfer sources are the same and the identifiers of the data transfer destinations are the same can be executed by at least one common data transfer instruction.

[0036] In Category 3, the identity of the identifier of the source of data transfer between the first hierarchy block BLK1 and the second hierarchy block BLK2 may be determined when the identifiers of the data source operation unit OPU, the first hierarchy block BLK1, and the second hierarchy block BLK2 are the same. Similarly, in Category 3, the identity of the identifier of the destination of data transfer between the first hierarchy block BLK1 and the second hierarchy block BLK2 may be determined when the identifiers of the data destination operation unit OPU, the first hierarchy block BLK1, and the second hierarchy block BLK2 are the same.

[0037] Furthermore, in Category 3, the identity of the identifiers of the transfer sources of data transfer between second-level blocks BLK2 may be determined when the identifiers of the second-level blocks BLK2 that are the data transfer sources are the same. Similarly, in Category 3, the identity of the identifiers of the transfer destinations of data transfer between second-level blocks BLK2 may be determined when the identifiers of the second-level blocks BLK2 that are the data transfer destinations are the same. Here, the identity of the identifiers in Category 3 may be determined using the identifiers of the registers in the operation unit OPU, the identifiers of the memories MEM1, MEM2, or MEM3.

[0038] In Category 4, data transfer between the first hierarchical block BLK1 and the second hierarchical block BLK2 can be executed by at least one data transfer instruction (e.g., a unicast instruction), as in Category 3. In Category 4, data transfer between the second hierarchical block BLK2 and the third hierarchical block BLK3 can be executed by at least one data transfer instruction (e.g., a unicast instruction). Also, in Category 4, data transfer between different third hierarchical blocks BLK3 within the arithmetic processing device 100 can be executed by at least one data transfer instruction (e.g., a multicast instruction).

[0039] In category 4, the identity of the identifier of the source of data transfer between the first hierarchy block BLK1 and the second hierarchy block BLK2 may be determined when the identifiers of the data source arithmetic unit OPU, the first hierarchy block BLK1, and the second hierarchy block BLK2 are the same, as in category 3. Similarly, in category 4, the identity of the identifier of the destination of data transfer between the first hierarchy block BLK1 and the second hierarchy block BLK2 may be determined when the identifiers of the data destination arithmetic unit OPU, the first hierarchy block BLK1, and the second hierarchy block BLK2 are the same.

[0040] In category 4, the identity of the identifier of the transfer source of data transfer between the second hierarchy block BLK2 and the third hierarchy block BLK3 may be determined when the identifiers of the second hierarchy block BLK2 and the third hierarchy block BLK3 are the same. Similarly, in category 4, the identity of the identifier of the transfer destination of data transfer between the second hierarchy block BLK2 and the third hierarchy block BLK3 may be determined when the identifiers of the second hierarchy block BLK2 and the third hierarchy block BLK3 are the same.

[0041] Furthermore, in Category 4, the identity of the identifiers of the transfer sources of data transfer between third-level blocks BLK3 may be determined when the identifiers of the third-level blocks BLK3 that are the data transfer sources are the same. Similarly, in Category 4, the identity of the identifiers of the transfer destinations of data transfer between third-level blocks BLK3 may be determined when the identifiers of the third-level blocks BLK3 that are the data transfer destinations are the same. Here, the identity of the identifiers in Category 4 may be determined using the identifiers of the registers in the operation unit OPU, the identifiers of the memories MEM1, MEM2, or MEM3.

[0042] Data transferred by data transfers from category 2 to category 4 is output from an arithmetic unit OPU and input to another arithmetic unit OPU. Therefore, as explained in category 1, by masking the storage of data in the arithmetic unit OPU to which the data is to be transferred, it is possible to disable part of the data transfer executed by one data transfer instruction for each category.

[0043] Note that data transfers may be executed without classification. For example, in the data transfers of categories 2, 3, and 4 shown in FIG. 3, the identifier of the first hierarchical block BLK1, which is the data transfer source, is "4." The identifier may include, for example, a register number within the first hierarchical block BLK1. In this case, data transfer from the first hierarchical block BLK1 to the second hierarchical block BLK2 (memory MEM2) may be executed by a single data transfer instruction. Also, in the data transfers of categories 3 and 4 shown in FIG. 3, the identifier of the first hierarchical block BLK1, which is the data transfer destination, is "11." The identifier may include, for example, a register number within the first hierarchical block BLK1. In this case, data transfer from the second hierarchical block BLK2 (memory MEM2) to the first hierarchical block BLK1 may be executed by a single data transfer instruction. In this way, regardless of classification, multiple data transfer instructions with the same source and destination identifiers may be executed by at least one common data transfer instruction.

[0044] Fig. 4 is a flow diagram showing an example of the operation of the compiler 500 of Fig. 2. That is, the flow shown in Fig. 4 shows an example of an instruction generation method by the compiler 500, which is realized by the CPU or the like of the information processing device 400 executing an instruction generation program.

[0045] First, in step S10, the compiler 500 sequentially inputs from the outside a plurality of queries that cause the board 200 to execute deep learning. Next, in step S20, the compiler 500 classifies each of the input queries into one of categories 1 to 4. Next, in step S30, if the compiler 500 has classified all of the input queries, it executes step S40, and if any queries remain that have not been classified, it returns to step S20.

[0046] In step S40, the compiler 500 divides data transfers that can be executed by one data transfer instruction into groups for each classification. That is, each group corresponds to one data transfer instruction. This makes it possible to generate at least one common data transfer instruction for each group that can transfer multiple data items in parallel. In this case, the compiler 500 divides data transfers between adjacent blocks BLK in the hierarchy shown in FIG. 3 into at least one group for each classification. For example, in classification 3, the compiler 500 divides data transfers into at least one group for data transfers between the first hierarchy block BLK1 and the second hierarchy block BLK2 and data transfers between the second hierarchy block BLK2 and the third hierarchy block BLK3.

[0047] Next, in step S50, the compiler 500 generates a data transfer instruction for each data transfer group divided in step S40. For example, the data transfer instruction generated by the compiler 500 for each group includes one of multiple types of unicast instructions for transferring data to one destination, or one of multiple types of multicast instructions for transferring data to multiple destinations. By combining the unicast instructions or multicast instructions generated for each group, the compiler 500 can execute data transfer between blocks BLK in adjacent hierarchical layers with a minimum number of data transfer instructions.

[0048] For example, if data transfer between two adjacent blocks BLK can be performed using multiple types of multicast instructions, the compiler 500 may use dynamic programming to determine a combination of multicast instructions with a small number of instructions and their execution order for at least a portion of the data transfer between the blocks BLK. Dynamic programming includes a technique for recursively dividing a target problem into multiple subproblems and reusing the calculation results of the divided subproblems to solve the problem. Furthermore, if data transfer between two adjacent blocks BLK can be performed using at least one of multiple types of unicast instructions, the compiler 500 generates a unicast instruction that is executed after the multiple types of multicast instructions. The arithmetic processing device 100 executes the data transfer instructions generated by the compiler 500 and transmitted from the host 300 in the order in which the compiler 500 generated them.

[0049] Next, in step S60, if the compiler 500 has generated instructions from all queries, it executes step S70, and if there are any queries for which instructions have not been generated, it returns to step S50. In step S70, the compiler 500 outputs the instructions generated in step S50 in the order in which they were generated, and ends the operation shown in FIG.

[0050] As described above, in this embodiment, the compiler 500 can generate at least one data transfer instruction for executing multiple data transfers in parallel among the data transfers included in multiple queries, for each classification corresponding to the number of hierarchical levels of the blocks BLK through which the data passes. This allows a large amount of data to be moved between blocks BLK using fewer data transfer instructions than before in a processing device 100 in which blocks BLK including operation units OPUs are hierarchically organized. In other words, the compiler 500 can generate data transfer instructions that enable data transfers to be executed at lower cost than before, in accordance with the architecture of the board 200 and the processing device 100. As a result, the computation time required for deep learning by the processing device 100 or the board 200 can be shortened.

[0051] 3, the arithmetic processing device 100 can execute multiple data transfers from the first hierarchical block BLK1 to the second hierarchical block BLK2 and multiple data transfers from the second hierarchical block BLK2 to the first hierarchical block BLK1 with a minimum number of instructions. Also, in the data transfers of Category 3, the arithmetic processing device 100 can execute multiple data transfers between the second hierarchical blocks BLK2 via the third hierarchical block BLK3 with a minimum number of instructions.

[0052] On the other hand, for example, in a data transfer of Category 3, if data is transferred between two first-level blocks BLK1 in a third-level block BLK3 without combining queries, each data transfer is executed using four data transfer instructions. The four data transfer instructions are instructions to transfer data from the first-level block BLK1 to the second-level block BLK2, from the second-level block BLK2 to the third-level block BLK3, from the third-level block BLK3 to the second-level block BLK2, and from the second-level block BLK2 to the first-level block BLK1. In this case, four instructions are required for the data transfer of Category 3 in each third-level block BLK3.

[0053] Each arithmetic processing unit 100 has four third-level hierarchical blocks BLK3, and the board 200 has 16 third-level hierarchical blocks BLK3. Therefore, when performing data transfers of category 3 without grouping queries, each arithmetic processing unit 100 requires 16 instructions, and a board 200 having four arithmetic processing units 100 requires 64 instructions. In this embodiment, each arithmetic processing unit 100 and board 200 can execute multiple data transfers in parallel for each data transfer instruction by using at least one common data transfer instruction for each group. In this case, each arithmetic processing unit 100 may issue a SIMD-type data transfer instruction to each of the first hierarchical block BLK1, the second hierarchical block BLK2, and the second hierarchical block BLK3. In this case, multiple data transfers can be executed in parallel with fewer instructions than when individual data transfer instructions are issued to each of the first hierarchical block BLK1, the second hierarchical block BLK2, and the second hierarchical block BLK3. For example, data transfers of category 3 can be executed across the entire board 200 with four instructions. This is approximately 6% of the time required to execute data transfers of category 3 using 64 instructions across the entire board 200. Note that some of the multiple data transfers executed by one data transfer instruction may be masked (disabled) using mask information.

[0054] 5 is a block diagram showing an example of a system including a board 200 and a host 300 according to another embodiment, and an information processing device 400 that generates instructions to be executed by the arithmetic processing device 100. The configuration of the system including the board 200 and the host 300 is the same as that shown in FIG. 2. The information processing device 400 functions as a compiler 500A (code generator) that generates an instruction sequence to be executed by the arithmetic processing device 100, based on a program executed by a processor such as a built-in CPU.

[0055] As in FIG. 2, the compiler 500A generates instructions (instruction codes) that cause the board 200 to execute deep learning. In this case, the compiler 500A uses dynamic programming to determine some of the multiple data transfer instructions to be executed by the board 200. For example, the compiler 500A uses dynamic programming to determine a combination and execution order of multicast instructions that reduces the number of instructions for at least some of the data transfers between two hierarchically adjacent blocks BLK. The use of dynamic programming makes it possible to eliminate unnecessary combinations from among the combinations of data transfer instructions, which exponentially increase as the scale of data transfer increases, and therefore makes it possible to determine a combination that minimizes the number of data transfer instructions within an acceptable time. Furthermore, the use of dynamic programming makes it possible to find a combination of data transfer instructions with a small number of instructions, thereby improving the calculation speed of deep learning by the board 200 and shortening the calculation time required for deep learning.

[0056] 6 is an explanatory diagram showing an example of a data transfer instruction executable by the arithmetic processing device 100 of FIG. 5. FIG. 6 illustrates a data transfer instruction between the second hierarchy block BLK2 and the first hierarchy block BLK1, a data transfer instruction between the second hierarchy block BLK2 via the third hierarchy block BLK3, and a data transfer instruction between the second hierarchy block BLK2 and the third hierarchy block BLK3. Note that the data transfer instructions executable by the arithmetic processing device 100 are not limited to those shown in FIG. 6. For example, a data transfer instruction between the second hierarchy block BLK2 and the first hierarchy block BLK1 is supplied to the second hierarchy block BLK2, and a data transfer instruction between the second hierarchy block BLK2 and the third hierarchy block BLK3 is supplied to the third hierarchy block BLK3.

[0057] Data transfer commands between the second-level block BLK2 and the first-level block BLK1 include unicast commands. In a unicast command, data in memory MEM2 or memory MEM1 is moved in each second-level block BLK2. In a broadcast command, data in memory MEM2 is moved to memory MEM1 in each of the 16 first-level blocks BLK1 in the second-level block BLK2. Note that data movement refers to copying data; the original data remains unless it is overwritten.

[0058] Data transfer instructions between second-level hierarchical blocks BLK2 include three types of multicast instructions. Data transfer instructions between second-level hierarchical blocks BLK2 move data via third-level hierarchical block BLK3. Data movement using multicast instructions is explained in Figure 4. Data transfer instructions between second-level hierarchical blocks BLK2 and third-level hierarchical blocks BLK3 include unicast instructions. A unicast instruction that moves data from third-level hierarchical block BLK3 to second-level hierarchical block BLK2 moves data from memory MEM3 of third-level hierarchical block BLK3 to memory MEM2 of second-level hierarchical block BLK2 in each third-level hierarchical block BLK3. A unicast instruction that moves data from second-level hierarchical block BLK2 to third-level hierarchical block BLK3 moves data from memory MEM2 of second-level hierarchical block BLK2 to memory MEM3 of third-level hierarchical block BLK3 in each third-level hierarchical block BLK3.

[0059] 6 can move data in parallel among multiple first-level blocks BLK1, multiple second-level blocks BLK2, or multiple third-level blocks BLK3 using a source address, a destination address, or a relative address. Therefore, the arithmetic processing device 100 can move a large amount of data in parallel by executing one of the instructions shown in FIG. 3.

[0060] FIG. 7 is an explanatory diagram showing an example of data transfer in response to the multicast command of FIG. 6. FIG. 7 also shows an example in which each third hierarchical block BLK3 has eight second hierarchical blocks BLK2, and each second hierarchical block BLK2 has 16 first hierarchical blocks BLK1. "r" indicates the identifiers of the eight second hierarchical blocks BLK2 in each third hierarchical block BLK3. "p" indicates the address of the data source in memory MEM2 in the second hierarchical block BLK2. "q" indicates the address of the data destination in memory MEM2 in the second hierarchical block BLK2. In FIG. 7, for simplicity, it is assumed that "p" and "q" are fixed values. FIG. 7 also shows an example of operation in which "r" is "1."

[0061] The multicast instruction "1 to 7" moves data at address p in memory MEM2 of the r-th second-level block BLK2 to address q in memory MEM2 of the seven second-level blocks BLK2 other than the r-th. The multicast instruction "1 to 7" allows eight types of data transfer because there are eight possible data sources (="r") among the eight second-level blocks BLK2.

[0062] With the multicast instruction "2 to 6", data at address p in memory MEM2 of the rth second hierarchical block BLK2 is moved to address q in memory MEM2 of the 0th to 3rd (excluding the rth) second hierarchical block BLK2. Also, data at address p in memory MEM2 of the 4+rth second hierarchical block BLK2 is moved to address q in memory MEM2 of the 4th to 7th (excluding the 4+rth) second hierarchical block BLK2. The multicast instruction "2 to 6" allows four types of data transfer because there are four possible data sources (="r") for each of the four second hierarchical blocks BLK2.

[0063] The multicast instruction "4 to 4" moves data at address p in memory MEM2 of the rth, 2+rth, 4+rth, and 6+rth second-level block BLK2 to address q in memory MEM2 of the 1-rth, 3-rth, 5-rth, and 7-rth second-level block BLK2, respectively. The multicast instruction "4 to 4" allows two types of data transfer because there are two possible data transfer sources (="r") for each two second-level block BLK2. Therefore, the three types of multicast instructions shown in FIG. 7 allow 14 types (8+4+2) of data transfer. In other words, in this embodiment, the arithmetic processing device 100 can use 14 types of multicast instructions for data transfer between the second-level block BLK2 and the third-level block BLK3.

[0064] 8 is an explanatory diagram showing an example of data transfer between eight second-hierarchy blocks BLK2 in a third-hierarchy block BLK3. Below, an example is explained in which state (A) is changed to state (D), assuming that the single-source shortest path problem, a type of dynamic programming, determines that executing the multicast instructions "2 to 6" and "4 to 4" in this order will minimize the number of instructions. State (D) is a state in which data S1-S7 in memory MEM2 of second-hierarchy blocks BLK2(1)-BLK2(7) in state (A) has been moved to memory MEM2 of second-hierarchy blocks BLK2(0)-BLK(6), respectively.

[0065] First, the arithmetic processing device 100 executes the multicast instruction "2 to 6" in state (A). As a result, data S2 in second-hierarchical block BLK2(2) (k=2) is moved to second-hierarchical blocks BLK2(0), BLK2(1), and BLK2(3), and data S6 in second-hierarchical block BLK2(6) (4+k=6) is moved to second-hierarchical blocks BLK2(4), BLK2(5), and BLK2(7), resulting in state (B). Note that with each multicast instruction, data in memory MEM2 of second-hierarchical block BLK2 is transferred to memory MEM2 of another second-hierarchical block BLK2 via memory MEM3.

[0066] Next, the arithmetic processing device 100 executes the multicast instruction "4 to 4" in state (B). As a result, data S1 in second hierarchical block BLK2(1) (k=1) is moved to second hierarchical block BLK2(0), and data S3 in second hierarchical block BLK2(3) is moved to second hierarchical block BLK2(2). Data S5 in second hierarchical block BLK2(5) is moved to second hierarchical block BLK2(4), and data S7 in second hierarchical block BLK2(7) is moved to second hierarchical block BLK2(6), resulting in state (C).

[0067] Next, the arithmetic processing device 100 executes a unicast command in state (C) after all multicast commands have been executed. As a result, data S4 in second-level block BLK2(4) is moved to second-level block BLK2(3), resulting in state (D), and the target data transfer is completed. Note that, from state (C) to state (D), a unicast command to transfer data S4 to memory MEM3 in third-level block BLK3 and a unicast command to transfer data S4 from memory MEM3 to second-level block BLK2(3) are executed. As a result, the data transfer shown in FIG. 7 can be performed using two multicast commands and two unicast commands.

[0068] An example that generalizes the state changes shown in FIG. 8 will be described below. For example, let the data at address src in second-level blocks BLK2(0)-BLK2(7) be S0, S1, ..., S7, respectively. Address src is the source address. As described above, by combining multicast and unicast instructions, data D0, D1, ..., D7 are placed at address dst (an address different from src) in second-level blocks BLK2(0)-BLK2(7) with the minimum number of instructions. Address dst is the destination address. Here, "data D0, ..., D7 ∈ {data S0, ..., S7, Wild}". Wild represents data that can be placed anywhere and has no purpose. For example, "D0, ..., D7 = S1, ..., S7, Wild".

[0069] Next, scheduling based on the single-source shortest path problem, a type of dynamic programming, is explained. Unicast instructions are used for final adjustment of data transfers, and are therefore used in the final data transfer. That is, a sequence of a predetermined number of multiple types of multicast instructions is executed, followed by a sequence of a predetermined number of unicast instructions. Below, first, a rough concept is explained, and then reduction to the single-source shortest path problem is explained.

[0070] The state that changes due to a sequence of multicast instructions is represented by a set (x0, x1, ..., x7). The state of each set is x0, ..., x7∈{o, x, -}. "xk=o" (k is any value from 0 to 7) indicates that the address dst of the kth second-layer block BLK2(k) is updated by a sequence of multicast instructions and Dk is allocated thereto. "xk=x" indicates that the address dst of the kth second-layer block BLK2(k) is updated by a sequence of multicast instructions and Dk is not allocated thereto. "xk=-" indicates that the address dst of the kth second-layer block BLK2(k) is not updated by a sequence of multicast instructions.

[0071] In a single-source shortest path problem, the optimal sequence of multicast instructions is basically searched for in all patterns. However, in this case, the compiler 500A determines the order of instructions to be used first. In the actual execution order of instructions, for example, as shown in FIG. 7, the multicast instruction "2 to 6@2" (k=2) and the multicast instruction "4 to 4@1" (k=1) are used in this order. However, when using dynamic programming, the compiler 500A first considers what state will change due to the multicast instruction "4 to 4@1." For example, the state changes from "s0=(-,-,...,-)" to "S1,-,S3,-,S5,-,S7,-", resulting in the state "s1=(o,-,o,-,o,-,o,-)".

[0072] Next, the compiler 500A considers inserting the multicast instruction "2 to 6@2" before the multicast instruction "4 to 4@1." This results in "S1, S2, S3, S2, S5, S6, S7, S6," resulting in a state "s2=(o, o, o, x, o, o, o, x)." In this way, regardless of which of the multiple types of multicast instructions is inserted at the beginning, "o" and "x" do not change, and only "-" changes.

[0073] Next, reduction to a single-source shortest path problem is considered. First, a vertex corresponding to each state is prepared. Let V(s) represent the vertex corresponding to state s. Let the initial state be "s0=(-,-,...,-)", and consider reducing to a single-source shortest path problem from the initial state. Transitions are made by inserting one multicast command at the beginning.

[0074] To be precise, for each vertex V(s) and each multicast instruction m (m is one of the 14 types of multicast instructions), an edge with cost 1 is extended from V(s) to V(s'). Here, "s'" represents the state that results when multicast instruction m is inserted at the beginning of the sequence of multicast instructions to change "s0" to "s", and then multicast instruction m is executed in order on the initial state. For example, in the above example, when "s=s1" and "m=Multicast 2 to 6@2", then "s'=s2". Furthermore, any multicast sequence to change "s0" to "s" should result in the same "s'".

[0075] Compiler 500A can obtain the optimal sequence of multicast instructions to get to all possible states s by solving the single-source shortest path problem from "s0" of the weighted directed graph constructed in this way. Then, for each "s", compiler 500A obtains the one that minimizes "(number of multicast instructions to get from s0 to s) + (number of unicast instructions to get from s to (o,...,o))". The "number of unicast instructions to get from s to (o,...,o)" is equal to "(number of s that are not o) × 2".

[0076] The computational complexity and optimization are explained below. "o" and "x" can be considered the same. For "x", the cost is doubled by the number of "x"s added at the end, so the cost of the edge should be +2. Although the number of states appears to be large, by considering "o" and "x", it can be seen that there are only 15 states due to the nature of multicast instructions. The 15 states are proportional to the number of second-level blocks BLK2.

[0077] Furthermore, excluding self-loops, there are only transitions that decrease "-" and no closed loops, so the calculation can be done linearly. As a result, the amount of calculation can be further reduced. If the number of types of multicast instructions is proportional to the number of second-level blocks BLK2, the time calculation amount is proportional to "(number of second-level blocks BLK2)^2".

[0078] Fig. 9 is a flow diagram showing an example of the operation of the compiler 500A realized by the information processing device 400 of Fig. 5. That is, the flow shown in Fig. 9 shows an example of an instruction generation method by the compiler 500A realized by the CPU or the like of the information processing device 400 executing an instruction generation program. Operations similar to those in Fig. 4 are assigned the same reference numerals, and detailed description thereof will be omitted.

[0079] The processing of steps S10, S20, S30, S40, S60, and S70 is the same as that of Fig. 4. After step S40, in step S42, the compiler 500A determines whether a data transfer instruction that executes data transfer between two blocks BLK in adjacent hierarchical layers among the grouped data transfers includes a multicast instruction. If a multicast instruction is included, the compiler 500A executes step S44, and if a multicast instruction is not included, the compiler 500A executes step S46.

[0080] In step S44, the compiler 500A uses dynamic programming as described above to determine the combination and execution order of multiple multicast instructions for at least a portion of the data transfer between blocks BLK, and also determines the unicast instruction to be executed after the multicast instruction. After step S44, the compiler 500A executes step S46.

[0081] Then, in step S46, for data transfers that do not include multicast instructions, the compiler 500A generates data transfer instructions for each group of data transfers divided in step S40. Also, in step S46, for data transfers that include multicast instructions, the compiler 500A generates the multicast instructions and unicast instructions determined in step S44. After processing step S46, the compiler 500A then executes steps S60 and S70, and ends the operation shown in FIG. 9.

[0082] As described above, in this embodiment, as in the above-described embodiment, the compiler 500A can generate at least one data transfer instruction for executing multiple data transfers in parallel among the data transfers included in multiple queries, for each classification corresponding to the number of hierarchical levels of the blocks through which the data passes. This allows a large amount of data to be moved between blocks BLK using fewer data transfer instructions than before in a processing device 100 in which blocks BLK including processing units OPUs are hierarchically organized. As a result, the computation time required for deep learning by the processing device 100 or the board 200 can be shortened.

[0083] Furthermore, in this embodiment, the compiler 500A uses dynamic programming to determine a combination and execution order of data transfer instructions that minimizes the number of instructions required to transfer data between two hierarchically adjacent blocks BLK, and generates the data transfer instructions according to the determination. This allows the compiler 500A to discontinue searching for instruction sequences that require a large number of instructions, thereby gradually reducing the search space. As a result, the compiler 500A can find an appropriate combination of data transfer instructions with a small number of instructions while minimizing the amount of calculations required.

[0084] Furthermore, by searching for multicast instructions to be used in the order of latest execution in dynamic programming, it is possible to prevent data transferred by a multicast instruction with an earlier execution order from being rewritten by a multicast instruction with a later execution order. This makes it possible to prevent unnecessary data transfer by multicast instructions, and the compiler 500A can generate an appropriate combination of multicast instructions with a small number of instructions.

[0085] Furthermore, the compiler 500A determines the unicast instruction, which has a higher degree of freedom in data transfer but lower data transfer efficiency than the multicast instruction, after determining the multicast instruction to be used. This allows the compiler 500A to minimize the number of unicast instructions, which have lower data transfer efficiency, used, and to minimize the number of instructions used for data transfer between blocks BLK that are adjacent in hierarchy.

[0086] In this embodiment, an example has been described in which dynamic programming is used to minimize the number of instructions to be executed for data transfer (category 3) between first-level blocks BLK1 belonging to different second-level blocks BLK2 within a third-level block BLK3. However, the appropriate instruction sequence searched for by dynamic programming is not limited to data transfer of category 3, but may be an instruction sequence used for data transfer of category 1, category 2, or category 4. Furthermore, the instruction sequence determined by the search is not limited to multicast instructions, but may be a special instruction other than a unicast instruction. Here, the special instruction is, for example, an instruction to transfer data in parallel to multiple locations.

[0087] In the above-described embodiments, the host 300 or the information processing device 400 may be partially or entirely configured with hardware, or may be configured with software (program) information processing executed by a CPU, GPU, or the like. When configured with software information processing, software that realizes at least some of the functions of each device in the above-described embodiments may be stored on a non-transitory storage medium (non-transitory computer-readable medium) such as a CD-ROM (Compact Disc-Read Only Memory) or a USB (Universal Serial Bus) memory, and the software information processing may be executed by loading the software into a computer. The software may also be downloaded via a communications network. Furthermore, the software information processing may be executed by hardware by implementing all or part of the software processing in a circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

[0088] The storage medium that stores the software may be a removable medium such as an optical disk, or a fixed medium such as a hard disk, memory, etc. The storage medium may be provided inside the computer (main storage device, auxiliary storage device, etc.) or outside the computer.

[0089] Fig. 10 is a block diagram showing an example of the hardware configuration of the host 300 and the information processing device 400 shown in Fig. 2 and Fig. 5. As an example, the information processing device 400 may be realized as a computer including a processor 20, a main storage device 30 (for example, a memory such as a DRAM), an auxiliary storage device 40 (memory), a network interface 50, and a device interface 60, which are connected via a bus 70. For example, the processor 20 executes an instruction generation program, thereby performing the operations described in Fig. 4 or 9.

[0090] Although the information processing device 400 includes one of each component, it may also include multiple of the same component. Although FIG. 10 shows one information processing device 400, the software may be installed on multiple information processing devices 400, and each of the multiple information processing devices 400 may execute the same or different parts of the software. In this case, a distributed computing configuration may be used in which each of the information processing devices 400 communicates with one another via a network interface 50 or the like to execute processing. In other words, the information processing device 400 in the above-described embodiment may be configured as a system in which one or more information processing devices 400 execute instructions stored in one or more storage devices to realize functions. Furthermore, the system may be configured such that information transmitted from a terminal is processed by one or more information processing devices 400 provided on a cloud, and the processing results are transmitted to the terminal.

[0091] The operations described in the flow chart of Fig. 4 and the operations described in the flow chart of Fig. 9 may be executed in parallel using one or more processors 20, or using multiple computers via a network. Furthermore, various calculations may be distributed to multiple arithmetic cores in the processor 20 and executed in parallel. Furthermore, some or all of the processes, means, etc. disclosed herein may be realized by at least one of a processor and a storage device provided on a cloud that can communicate with the information processing device 400 via a network. Thus, the information processing device 400 in the above-described embodiment may be in the form of parallel computing using one or multiple computers.

[0092] The processor 20 may be an electronic circuit (processing circuit, processing circuitry, CPU, GPU, FPGA, ASIC, etc.) that performs at least one of computer control and calculation. The processor 20 may also be a general-purpose processor, a dedicated processing circuit designed to perform a specific calculation, or a semiconductor device that includes both a general-purpose processor and a dedicated processing circuit. The processor 20 may also include an optical circuit or a calculation function based on quantum computing.

[0093] The processor 20 may perform arithmetic processing based on data or software input from each device or the like configured internally of the information processing device 400, and may output arithmetic results or control signals to each device or the like. The processor 20 may control each component constituting the information processing device 400 by executing an OS (Operating System), an application, or the like of the information processing device 400.

[0094] The information processing device 400 in the above-described embodiment may be realized by one or more processors 20. Here, the processor 20 may refer to one or more electronic circuits arranged on one chip, or may refer to one or more electronic circuits arranged on two or more chips or two or more devices. When multiple electronic circuits are used, the respective electronic circuits may communicate with each other via wire or wirelessly.

[0095] The main memory device 30 may store instructions to be executed by the processor 20, various data, etc., and information stored in the main memory device 30 may be read by the processor 20. The auxiliary memory device 40 is a memory device other than the main memory device 30. Note that these memory devices refer to any electronic component capable of storing electronic information, and may be semiconductor memory. The semiconductor memory may be either volatile memory or non-volatile memory. In the information processing device 400 in the above-described embodiment, the memory device for saving various data, etc. may be realized by the main memory device 30 or the auxiliary memory device 40, or may be realized by memory built into the processor 20.

[0096] When the information processing device 400 in the above-described embodiment is configured with at least one storage device (memory) and at least one processor connected (coupled) to this at least one storage device, at least the processor 20 may be connected to one storage device. Also, at least one storage device may be connected to one processor. Also, a configuration in which at least one processor out of multiple processors is connected to at least one storage device out of multiple storage devices may be included. Also, this configuration may be realized by storage devices and processors included in multiple information processing devices 400. Furthermore, a configuration in which a storage device is integrated with a processor (for example, a cache memory including an L1 cache and an L2 cache) may be included.

[0097] The network interface 50 is an interface for connecting to a communication network 600 wirelessly or via a wire. The communication network 600 may be an appropriate interface, such as one conforming to an existing communication standard. Information may be exchanged with an external device 710 connected via the communication network 600 through the network interface 50. The communication network 600 may be any one of a wide area network (WAN), a local area network (LAN), a personal area network (PAN), etc., or a combination thereof, as long as information is exchanged between the information processing device 400 and the external device 710. An example of a WAN is the Internet, an example of a LAN is IEEE802.11 or Ethernet (registered trademark), and an example of a PAN is Bluetooth (registered trademark) or NFC (Near Field Communication), etc.

[0098] The device interface 60 is an interface such as a USB that directly connects to an external device 720 .

[0099] The external device 710 is a device connected to the information processing device 400 via a network. The external device 720 is a device directly connected to the information processing device 400.

[0100] For example, the external device 710 or the external device 720 may be an input device. The input device is, for example, a device such as a camera, a microphone, a motion capture device, various sensors, a keyboard, a mouse, or a touch panel, and provides acquired information to the information processing device 400. The external device 710 or the external device 720 may also be a device including an input unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0101] Furthermore, the external device 710 or the external device 720 may be, for example, an output device. The output device may be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) panel, or may be a speaker that outputs sound or the like. Alternatively, the output device may be a device including an output unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0102] Furthermore, the external device 710 or the external device 720 may be a storage device (memory). For example, the external device 710 may be a network storage or the like, and the external device 720 may be a storage such as an HDD.

[0103] Furthermore, the external device 710 or the external device 720 may be a device having some of the functions of the components of the information processing device 400 in the above-described embodiment. That is, the information processing device 400 may transmit some or all of the processing results to the external device 710 or the external device 720, or may receive some or all of the processing results from the external device 710 or the external device 720.

[0104] In this specification (including the claims), when the expression "at least one of a, b, and c" or "at least one of a, b, or c" (including similar expressions) is used, it includes any of a, b, c, ab, ac, bc, or abc. It may also include multiple instances of any element, such as aa, abb, aabbcc, etc. Furthermore, it also includes the addition of elements other than the enumerated elements (a, b, and c), such as having d, as in abcd.

[0105] In this specification (including claims), when expressions such as "using data as input / based on / according to / in response to data" (including similar expressions) are used, unless otherwise specified, this includes cases where the data itself is used, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of data, etc.) is used. Furthermore, when a statement is made that a result is obtained "using data as input / based on / according to / in response to data" (including similar expressions), this includes cases where the result is obtained based solely on the data, or where the result is influenced by other data, factors, conditions, and / or states other than the data itself, unless otherwise specified. Furthermore, when a statement is made that "data is output" (including similar expressions), this includes cases where the data itself is used as output, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of various data, etc.) is used as output, unless otherwise specified.

[0106] When the terms "connected" and "coupled" are used in this specification (including the claims), they are intended as open-ended terms that encompass any of direct connection / coupling, indirect connection / coupling, electrically connection / coupling, communicatively connection / coupling, functionally connection / coupling, and physically connection / coupling. These terms should be interpreted appropriately according to the context in which they are used, but any form of connection / coupling that is not intentionally or naturally excluded should be interpreted as being included in these terms without limitation.

[0107] In this specification (including the claims), the expression "A configured to B" may include the physical structure of element A having a configuration capable of performing operation B, and the permanent or temporary setting / configuration of element A being configured / set to actually perform operation B. For example, if element A is a general-purpose processor, it is sufficient that the processor has a hardware configuration capable of performing operation B, and is configured to actually perform operation B by setting a permanent or temporary program (instruction). Also, if element A is a dedicated processor, dedicated arithmetic circuit, etc., it is sufficient that the circuit structure, etc. of the processor is implemented to actually perform operation B, regardless of whether control instructions and data are actually attached.

[0108] Whenever words implying containing or possessing (e.g., "comprising / including," "having," etc.) are used in this specification (including the claims), they are intended to be open-ended terms that include the inclusion or possession of things other than the object designated by the object of the term. When the object of such words implying containing or possessing does not specify a quantity or suggests a singular number (e.g., expressions using the articles "a" or "an"), the expression should be construed as not being limited to a specific number.

[0109] In this specification (including the claims), even if expressions such as "one or more" and "at least one" are used in some places and expressions that do not specify a quantity or that imply a singular number (expressions using the articles "a" or "an") are used in other places, the latter expressions are not intended to mean "one." In general, expressions that do not specify a quantity or that imply a singular number (expressions using the articles "a" or "an") should be interpreted as not necessarily being limited to a specific number.

[0110] In this specification, when a particular advantage / result is described as being obtained with respect to a particular configuration of an embodiment, it should be understood that the same advantage / result can also be obtained with one or more other embodiments having the same configuration, unless otherwise stated. However, it should be understood that the presence or absence of the effect generally depends on various factors, conditions, and / or circumstances, and that the effect is not necessarily obtained with the configuration. The effect is merely obtained by the configuration described in the embodiment when various factors, conditions, and / or circumstances are satisfied, and the effect does not necessarily occur in a claimed invention that defines the same or a similar configuration.

[0111] When terms such as "maximize" and "maximization" are used in this specification (including the claims), they include finding a global maximum, finding an approximation of a global maximum, finding a local maximum, and finding an approximation of a local maximum, and should be interpreted appropriately according to the context in which the term is used. They also include finding approximations of these maxima probabilistically or heuristically. Similarly, when terms such as "minimize" and "minimization" are used, they include finding a global minimum, finding an approximation of a global minimum, finding a local minimum, and finding an approximation of a local minimum, and should be interpreted appropriately according to the context in which the term is used. They also include finding approximations of these minima probabilistically or heuristically. Similarly, when terms such as "optimize" and "optimization" are used, they include finding a global optimum, finding an approximation of a global optimum, finding a local optimum, and finding an approximation of a local optimum, and should be interpreted appropriately according to the context in which the term is used. It also includes finding approximations of these optimum values ​​probabilistically or heuristically.

[0112] In this specification (including claims), when multiple pieces of hardware perform a predetermined process, the pieces of hardware may cooperate to perform the predetermined process, or some of the hardware may perform all of the predetermined process. Furthermore, some of the hardware may perform part of the predetermined process, and other hardware may perform the rest of the predetermined process. In this specification (including claims), when an expression such as "one or more pieces of hardware perform a first process, and the one or more pieces of hardware perform a second process" (including similar expressions) is used, the hardware performing the first process and the hardware performing the second process may be the same or different. In other words, it is sufficient that the hardware performing the first process and the hardware performing the second process are included in the one or more pieces of hardware. Note that hardware may include electronic circuits, devices including electronic circuits, etc.

[0113] In this specification (including the claims), when multiple storage devices (memories) store data, each of the multiple storage devices may store only a portion of the data, or may store the entire data. Also, a configuration in which only some of the multiple storage devices store data may be included.

[0114] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, modifications, substitutions, partial deletions, etc. are possible within the scope of the conceptual idea and spirit of the present invention, which is derived from the content defined in the claims and their equivalents. For example, when numerical values ​​or formulas are used in the above-described embodiments, they are shown for illustrative purposes and do not limit the scope of the present disclosure. Furthermore, the order of each operation shown in the embodiments is also illustrative and does not limit the scope of the present disclosure. [Explanation of symbols]

[0115] 20 processors 30 Main memory 40 Auxiliary storage 50 Network Interface 60 Device Interfaces 70 Bus 100 Processing unit 200 boards 300 Host 400 Information processing equipment 500, 500A Compiler 600 Communication Network 710, 720 External device BLK1 1st layer block BLK2 Second layer block BLK3 3rd layer block EX1, EX2 computing unit HOSTM Host Memory MEM1, MEM2, MEM3, MEM4 memories OPU Computing Unit

Claims

1. 1. An instruction generation method for generating an instruction sequence to be executed by an arithmetic processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks and at least one second memory, and each of the plurality of first blocks including at least one arithmetic unit and at least one first memory, generating, by at least one processor, the sequence of instructions that causes the arithmetic processing unit to execute at least one of a first data transfer in parallel, a second data transfer in parallel, a third data transfer in parallel, or a fourth data transfer in parallel; a transfer source of the first data transfer is one or more first blocks among the plurality of first blocks, and a transfer destination of the first data transfer is one or more first blocks among the plurality of first blocks, a transfer source of the second data transfer is one or more first blocks among the plurality of first blocks, and a transfer destination of the second data transfer is one or more second blocks among the plurality of second blocks; a transfer source of the third data transfer is one or more second blocks among the plurality of second blocks, and a transfer destination of the third data transfer is one or more first blocks among the plurality of first blocks; a transfer source of the fourth data transfer is one or more second blocks among the plurality of second blocks, and a transfer destination of the fourth data transfer is one or more second blocks among the plurality of second blocks, generating the instruction sequence includes determining, by the at least one processor, a combination and an execution order of at least one multicast instruction selected from a plurality of types of multicast instructions; Instruction generation method.

2. the transfer source and the transfer destination are identified by at least one of an address of the first memory, an address of the second memory, a number of a register included in the first block, a number of a register included in the second block, an identifier of an arithmetic unit included in the first block, an identifier of the first memory, an identifier of the second memory, an identifier of each of the plurality of first blocks, or an identifier of each of the plurality of second blocks; The instruction generation method according to claim 1 .

3. the identifiers of the transfer sources of the data transfers executed in parallel among the first data transfer, the second data transfer, the third data transfer, and the fourth data transfer are the same as each other, and the identifiers of the transfer destinations of the data transfers executed in parallel among the first data transfer, the second data transfer, the third data transfer, and the fourth data transfer are the same as each other; 3. The instruction generation method according to claim 1.

4. a first identifier is assigned to each of the plurality of first blocks included in each of the plurality of second blocks, the first identifier being different for each of the plurality of first blocks and being common among the plurality of second blocks; a second identifier is assigned to each of the plurality of second blocks, and the second identifiers are different from one another in the plurality of second blocks; The instruction generation method according to any one of claims 1 to 3.

5. selecting, by the at least one processor, the at least one multicast instruction based on dynamic programming; The instruction generation method according to any one of claims 1 to 4.

6. determining the combinations and execution orders based on dynamic programming by the at least one processor; The instruction generation method according to any one of claims 1 to 5.

7. determining, by the at least one processor, a combination and an execution order of another data transfer instruction after determining the combination and the execution order; The instruction generation method according to any one of claims 1 to 6.

8. the at least one multicast instruction is a data transfer instruction of SIMD type; The instruction generation method according to any one of claims 1 to 7.

9. the arithmetic processing device further includes a plurality of third blocks, each of which includes the plurality of second blocks and at least one third memory; generating, by the at least one processor, a second sequence of instructions that causes the arithmetic processing unit to execute at least one of a fifth data transfer in parallel, a sixth data transfer in parallel, or a seventh data transfer in parallel; a transfer source of the fifth data transfer is one or more third blocks among the plurality of third blocks, and a transfer destination of the fifth data transfer is one or more third blocks among the plurality of third blocks, a transfer source of the sixth data transfer is one or more second blocks among the plurality of second blocks, and a transfer destination of the sixth data transfer is one or more third blocks among the plurality of third blocks; a transfer source of the seventh data transfer is one or more third blocks among the plurality of third blocks, and a transfer destination of the seventh data transfer is one or more second blocks among the plurality of second blocks; The instruction generation method according to any one of claims 1 to 8.

10. generating, by the at least one processor, the second sequence of instructions by utilizing at least one multicast instruction; The instruction generation method according to claim 9.

11. the at least one multicast instruction used to generate the second instruction sequence is an instruction that causes the arithmetic processing unit to execute the same type of data transfer in parallel in each of the plurality of third blocks; The instruction generation method according to claim 10.

12. the arithmetic processing device further includes a third block including the plurality of second blocks and at least one third memory; generating, by the at least one processor, a second sequence of instructions using at least one of the first multicast instruction or the second multicast instruction; the first multicast instruction causes the arithmetic processing unit to execute in parallel data transfer from one second block included in the plurality of second blocks of the third block to a plurality of other second blocks included in the plurality of second blocks of the third block; the second multicast instruction causes the arithmetic processing unit to execute in parallel data transfers from at least two second blocks included in the plurality of second blocks of the third block to other plurality of second blocks included in the plurality of second blocks of the third block; The instruction generation method according to any one of claims 1 to 8.

13. the first data transfer includes transferring data from one or more first blocks of the plurality of first blocks to one or more first blocks of the plurality of first blocks via the second memory; The instruction generation method according to any one of claims 1 to 12.

14. by the at least one processor Classifying data transfers based on data transfer paths; generating the instruction sequence based on the result of the classification; The instruction generation method according to any one of claims 1 to 13.

15. by the at least one processor generating the instruction sequence for each of the classifications; The instruction generation method according to claim 14.

16. by the at least one processor generating information for invalidating at least a portion of a plurality of data transfers included in at least one of the first data transfer, the second data transfer, the third data transfer, or the fourth data transfer; generating the instruction sequence including the generated information; 16. The method of generating instructions according to any one of claims 1 to 15.

17. an information processing device that is different from the arithmetic processing device and includes the at least one processor, executes the instruction generation method according to any one of claims 1 to 16 to generate the instruction sequence, and transmits the generated instruction sequence to the arithmetic processing device; Instruction generation method.

18. An arithmetic processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks and at least one second memory, and each of the plurality of first blocks including at least one arithmetic unit and at least one first memory, 18. The method of claim 1, wherein at least one of a first data transfer in parallel, a second data transfer in parallel, a third data transfer in parallel, or a fourth data transfer in parallel is executed by executing a sequence of instructions generated by the method of claim 1, a transfer source of the first data transfer is one or more first blocks among the plurality of first blocks, and a transfer destination of the first data transfer is one or more first blocks among the plurality of first blocks, a transfer source of the second data transfer is one or more first blocks among the plurality of first blocks, and a transfer destination of the second data transfer is one or more second blocks among the plurality of second blocks; a transfer source of the third data transfer is one or more second blocks among the plurality of second blocks, and a transfer destination of the third data transfer is one or more first blocks among the plurality of first blocks; a transfer source of the fourth data transfer is one or more second blocks among the plurality of second blocks, and a transfer destination of the fourth data transfer is one or more second blocks among the plurality of second blocks; Processing unit.

19. 1. An instruction generation method for generating an instruction sequence to be executed by a processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks, the method comprising: determining, by at least one processor, a combination and an execution order of data transfer instructions when at least one type of multicast instruction is used based on dynamic programming; generating, by the at least one processor, the sequence of instructions that causes the arithmetic processing device to execute at least one of a data transfer between two blocks in adjacent hierarchical levels or a data transfer between two blocks in the same hierarchical level, based on the determined combination and execution order; the determining step includes searching, by the at least one processor, for a multicast instruction to be used from the end of the execution order of the sequence of instructions based on dynamic programming; Instruction generation method.

20. 1. An instruction generation method for generating an instruction sequence to be executed by a processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks, the method comprising: determining, by at least one processor, a combination and an execution order of data transfer instructions when at least one type of multicast instruction is used based on dynamic programming; generating, by the at least one processor, the sequence of instructions that causes the arithmetic processing device to execute at least one of a data transfer between two blocks in adjacent hierarchical levels or a data transfer between two blocks in the same hierarchical level, based on the determined combination and execution order; the one or more types of multicast instructions are SIMD type data transfer instructions; Instruction generation method.

21. determining, by the at least one processor, a combination and an execution order of the data transfer instructions when at least one type of unicast instruction is used; 21. The instruction generation method according to claim 19 or claim 20.

22. the sequence of instructions causes the arithmetic processing device to execute at least one of the data transfer in parallel between the two blocks in the adjacent hierarchical levels or the data transfer in parallel between the two blocks in the same hierarchical level; 22. The method of generating instructions according to any one of claims 19 to 21.

23. an information processing device that is different from the arithmetic processing device and includes the at least one processor, executes the instruction generation method according to any one of claims 19 to 22 to generate the instruction sequence, and transmits the generated instruction sequence to the arithmetic processing device; Instruction generation method.

24. A processing device having a plurality of second blocks, each of the plurality of second blocks including a plurality of first blocks, 24. By executing the instruction sequence generated by the instruction generation method according to claim 19, at least one of data transfer between two blocks in adjacent hierarchical levels or data transfer between two blocks in the same hierarchical level is performed. Processing unit.

25. at least one memory; at least one processor; The at least one processor executes the instruction generation method according to any one of claims 1 to 17 and claims 19 to 23. Instruction generator.

26. causing at least one processor to execute the instruction generation method according to any one of claims 1 to 17 and claims 19 to 23; program.

Images