Power Conversion Device

Abstract

To provide a highly reliable power conversion device.SOLUTION: A power conversion device is provided with: a protection unit 60 which reduces current flowing in a first direction (T1→T2) when a first determination result CP1 is affirmative and applies second forward voltage and current characteristics PH to a diode function D when a second determination result CP2 is affirmative; and a bypass device 2 which bypasses between a pair of input and output terminals T1 and T2 after the protection unit 60 operates when the first determination result CP1 or the second determination result CP2 becomes affirmative.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] As background art in this technical field, the abstract of Patent Document 1 listed below states that "A power conversion device equipped with a modular multilevel converter uses a large number of cells each consisting of a plurality of switching elements and DC capacitors, and therefore conduction loss due to the switching elements is a problem. To reduce the conduction loss, a bypass circuit is connected between each terminal of a plurality of cells, and the switching elements are controlled to open and close, and the bypass circuit connected to the cell controlled to zero voltage output is controlled to be short-circuited."

[0003] Furthermore, the abstract of Patent Document 2 below states, "A semiconductor chip 5, on which an IGBT 5a and a main diode 5b are connected in anti-parallel, is equipped with a diode 5c for monitoring the current flowing through the main diode 5b, and this diode 5c is connected in parallel to the main diode 5b via an external resistor 9. If the voltage across the external resistor 9 is lower than a predetermined reference voltage value, a freewheeling mode determination means 7 determines that the system is in a freewheeling mode in which current is freewheeling through the main diode 5b. Then, a cutoff circuit 3 cuts off the drive signal sent from the input circuit 2 to the drive circuit 4. As a result, in the freewheeling mode, the IGBT 5a does not turn on, thereby suppressing an increase in the forward drop voltage of the main diode 5b."

[0004] Furthermore, the abstract of Patent Document 3 below states, "We provide a semiconductor device that has the performance of achieving both low conduction loss and low recovery loss and is capable of reducing power consumption, and a power conversion device using the same." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2017 / 077983 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-72848 [Patent Document 3] Japanese Patent Application Publication No. 2018-117044 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the above-mentioned technology, there is a demand for further improving the reliability of the power conversion device. The present invention has been made in view of the above circumstances, and has an object to provide a highly reliable power conversion device. [Means for solving the problem]

[0007] In order to solve the above problems, the power conversion device of the present invention includes a semiconductor device connected between a pair of input / output terminals and having a switching function for switching a current flowing in a first direction and a diode function with a second direction opposite to the first direction as a forward direction; a drive circuit that controls the on / off state of the switching function and applies either a first forward voltage-current characteristic or a second forward voltage-current characteristic for the diode function, in which the forward voltage is lower than the first forward voltage-current characteristic for the same forward current; The power supply comprises an overcurrent determination unit that outputs a first determination result as to whether or not the current flowing in the second direction is in a first overcurrent state and a second determination result as to whether or not the current flowing in the second direction is in a second overcurrent state; a protection unit that reduces the current flowing in the first direction when the first determination result is positive, and applies the second forward voltage-current characteristic to the diode function when the second determination result is positive; and a bypass device that bypasses the pair of input / output terminals after the protection unit operates when the first determination result or the second determination result is positive. [Effects of the Invention]

[0008] According to the present invention, a highly reliable power conversion device can be provided. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a schematic configuration of a power conversion device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram of a computer. [Figure 3] FIG. 2 is a circuit diagram of an example of a configuration of a cell. [Figure 4] FIG. 10 is a circuit diagram of another example of the configuration of the cell. [Figure 5] FIG. 2 is a circuit diagram of a gate drive circuit and its surroundings. [Figure 6] FIG. 6 is a diagram showing the relationship between voltages and the like at various parts in FIG. 5. [Figure 7] 5A and 5B are diagrams illustrating examples of waveforms of gate voltage and current of a switching element. [Figure 8] FIG. 10 is a diagram showing an example of forward voltage / current characteristics of a freewheeling diode. [Figure 9] 5A and 5B are examples of waveform diagrams of various parts when a short circuit occurs in a switching element. [Figure 10] 10A and 10B are diagrams illustrating examples of waveforms at various parts when a surge current flows through a freewheel diode. [Figure 11] FIG. 10 is a circuit diagram of a gate drive circuit and its peripheral circuitry in a second embodiment. [Figure 12] 10A and 10B are diagrams illustrating examples of waveforms of a gate voltage, an auxiliary gate voltage, and a current of a switching element. [Figure 13] 5A and 5B are examples of waveform diagrams of various parts when a short circuit occurs in a switching element. [Figure 14] FIG. 11 is a circuit diagram of a gate drive circuit and its peripheral essential parts in a third embodiment. [Figure 15] FIG. 10 is a diagram showing the relationship between each arm, the number of abnormal cells, and the applied voltage. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Outline of the embodiment] With the introduction of distributed power generation using renewable energy sources such as offshore wind and solar power, high-voltage direct current (HVDC) transmission is being applied to ensure stable and efficient transmission of generated power. In recent years, modular multilevel converters (MMCs) are often used as AC / DC converters for HVDC. In an MMC, as shown in Figure 1 (details will be described later), multiple cells 1 are connected in series. The cells 1 are also called submodules or unit converters. Each cell 1 uses a power semiconductor module as a switching element.

[0011] In addition to thyristors, the use of low-loss IGBTs (Insulated Gate Bipolar Transistors) as power semiconductors has been increasing in recent years. In HVDC, where the system DC voltage reaches several hundred kV, it is desirable to construct MMC cells using power semiconductors with as high a rated voltage as possible, reducing the number of cells connected in series and reducing costs. On the other hand, increasing the voltage resistance of power semiconductors also increases the scale of destruction when a fault occurs. In particular, when an open fault occurs within a cell, the system DC voltage is concentrated in the faulty cell, causing arcing in that cell and the ejection of electrically conductive gas.

[0012] If this causes insulation breakdown in the cell, it could lead to events such as explosion or fire. Therefore, it is common to configure the MMC system so that the failed cell can be short-circuited (bypassed) before it reaches an open circuit failure, allowing the entire system to continue operating. In this way, MMCs require high cell reliability and continuous system operation.

[0013] For example, by applying the technology described in Patent Document 1, it is possible to turn on a bypass circuit in the event of a cell failure and protect the power semiconductor from excessive current. However, Patent Document 1 does not specifically mention a method for detecting cell failure or a means for ensuring the reliability of the cell itself. Furthermore, by applying the technology described in Patent Document 2, it is possible to detect the current flowing through the power semiconductor. In other words, it is possible to detect the direction and magnitude of the current flowing through the power semiconductor by detecting the current value flowing through a current monitoring diode. However, this method requires the provision of a current monitoring diode in addition to the main diode.

[0014] Therefore, in each of the embodiments described below, a semiconductor device such as a power semiconductor module is detected before an open circuit failure occurs, providing explosion prevention and improving the reliability of MMC cells. More specifically, abnormal currents that could trigger an open circuit failure, such as destruction of semiconductor chips inside the power semiconductor module or melting of wire bonds, are detected early before the failure occurs. In each of the embodiments described below, the energy consumed by the power semiconductors is instantly reduced, improving the durability of the power semiconductors and preventing open circuit failures in the cells.

[0015] [First embodiment] <Configuration of the first embodiment> FIG. 1 is a circuit diagram showing a schematic configuration of a power conversion device 100 according to the first embodiment. In Fig. 1, a power conversion device 100 is connected between a three-phase AC system 120 and a DC system 130. The AC system 120 may be, for example, a distributed power source such as an offshore wind power generation system, or a commercial system. The DC system 130 is, for example, a DC transmission system. The power conversion device 100 of this embodiment may be connected to one end of the DC transmission system, and a DC side output terminal of another device (not shown) similar to the power conversion device 100 may be connected to the other end.

[0016] The power conversion device 100 includes U-phase, V-phase, and W-phase AC terminals 32U, 32V, and 32W, a positive-side DC terminal 34P, a negative-side DC terminal 34N, a control device 20, positive-side arms 10U, 10V, and 10W, negative-side arms 10X, 10Y, and 10Z, and reactors 30LU, 30LV, 30LW, 30LX, 30LY, and 30LZ.

[0017] In the following description, multiple components, information, etc. having the same or similar functions or meanings may be expressed by adding an alphabetical letter to the same reference numeral, such as "reactors 30LU, 30LV." However, when it is not necessary to distinguish between these multiple components, the alphabetical letter may be omitted, such as "reactor 30."

[0018] Each arm 10 includes a plurality of cells 1, which are unit converters, connected in series. In the example of Fig. 1, the number of cells connected in series is set to "3" for simplicity. A bypass device 2 is connected in parallel between the input / output terminals T1 and T2 of each cell 1.

[0019] The AC terminals 32U, 32V, and 32W are electrically connected to a three-phase AC system 120. The positive DC terminal 34P and the negative DC terminal 34N are electrically connected to a DC system . The low potential side of U-phase positive side arm 10U is electrically connected to AC terminal 32U via reactor 30LU. The high potential side of U-phase positive side arm 10U is electrically connected to positive side DC terminal 34P. The high potential side of U-phase negative side arm 10X is electrically connected to AC terminal 32U via reactor 30LX. The low potential side of U-phase negative side arm 10X is electrically connected to negative side DC terminal 34N.

[0020] Similarly, the low potential side of the V-phase positive side branch 10V is electrically connected to AC terminal 32V via reactor 30LV. The high potential side of the V-phase positive side branch 10V is electrically connected to positive side DC terminal 34P. The high potential side of the V-phase negative side branch 10Y is electrically connected to AC terminal 32V via reactor 30LY. The low potential side of the V-phase negative side branch 10Y is electrically connected to negative side DC terminal 34N.

[0021] Similarly, the low potential side of the W-phase positive side branch 10W is electrically connected to AC terminal 32W via reactor 30LW. The high potential side of the W-phase positive side branch 10W is electrically connected to positive side DC terminal 34P. The high potential side of the W-phase negative side branch 10Z is electrically connected to AC terminal 32W via reactor 30LZ. The low potential side of the W-phase negative side branch 10Z is electrically connected to negative side DC terminal 34N.

[0022] The control device 20 controls the operation of the power conversion device 100 based on command values ​​supplied from the outside and various detected values ​​detected in the power conversion device 100. To this end, various detected values ​​such as the voltage of a cell capacitor (described in detail later) included in a cell of each phase arm, the current flowing through each phase arm, and the system voltage are input to the control device 20. Then, the control device 20 outputs a gate signal to the cell 1 included in the arm 10 of each phase.

[0023] 2 is a block diagram of the computer 980. The control device 20 shown in FIG. 1 includes one or more computers 980 shown in FIG. 2, a computer 980 includes a CPU (Central Processing Unit) 981, a storage unit 982, a communication I / F (Interface) 983, an input / output I / F 984, and a media I / F 985. Here, the storage unit 982 includes a RAM (Random Access Memory) 982a, a ROM (Read Only Memory) 982b, and an HDD (Hard Disk Drive) 982c. The communication I / F 983 is connected to a communication circuit 986. The input / output I / F 984 is connected to an input / output device 987. The media I / F 985 reads and writes data from a recording medium 988. The ROM 982b stores control programs executed by the CPU, various data, and the like. The CPU 981 executes application programs loaded into the RAM 982a to realize various functions.

[0024] FIG. 3 is a circuit diagram of an example of the configuration of the cell 1. In Figure 3, cell 1 includes switching elements Qa and Qb, freewheeling diodes Da and Db, a cell capacitor C1, and gate drive circuits 3a and 3b. The switching elements Qa and Qb are connected in series, and the emitter (low potential side) of Qa is electrically connected to the collector (high potential side) of Qb. The gate drive circuits 3a and 3b drive the switching elements Qa and Qb, respectively. The collector of Qa is electrically connected to the high potential side of the cell capacitor C1. The emitter of Qb is electrically connected to the low potential side of the cell capacitor C1.

[0025] Freewheeling diodes Da and Db are connected in antiparallel to the switching elements Qa and Qb, respectively. The freewheeling diodes Da and Db have gate control terminals Gd for controlling the forward voltage. For example, the freewheeling diodes Da and Db described in Patent Document 3 can be used.

[0026] The control device 20 supplies gate drive command signals (unsigned) to the gate drive circuits 3a and 3b to control the switching elements Qa and Qb and the freewheeling diodes Da and Db. The gate drive circuits 3a and 3b control the voltages at the gate terminals G of the switching elements Qa and Qb and the gate control terminals Gd of the freewheeling diodes Da and Db in accordance with the gate drive command signals. As a result, the gate drive circuits 3a and 3b control the currents flowing through the switching elements Qa and Qb, the forward voltages of the freewheeling diodes Da and Db, and the like. Details of this will be described later.

[0027] The connection point of the switching elements Qa and Qb is connected to the input / output terminal T1. The input / output terminal T2 is connected to the low-potential side of the cell capacitor C1. As described above, the bypass device 2 is connected between the input / output terminals T1 and T2. The bypass device 2 is, for example, a bypass thyristor that can pass current in both directions, and can be configured by connecting a pair of thyristors in anti-parallel. Therefore, the following explanation will be given of an example in which a bypass thyristor is used as the bypass device 2.

[0028] The gate drive circuits 3a and 3b output drive commands SBa and SBb, which are binary signals, respectively. If at least one of the drive commands SBa and SBb is "1," the bypass device 2 electrically shorts the input / output terminals T1 and T2, preventing a significant voltage from being applied to the cell 1. On the other hand, if both the drive commands SBa and SBb are "0," the bypass device 2 enters a high-impedance state, preventing a significant current from flowing through the bypass device 2.

[0029] Fig. 4 is a circuit diagram of another example of the configuration of cell 1. That is, while Fig. 3 above shows an example in which cell 1 is configured using a chopper circuit, Fig. 4 shows an example in which cell 1 is configured using a bridge circuit. In FIG. 4, the cell 1 includes switching elements Qc, Qd, Qe, and Qf, freewheeling diodes Dc, Dd, De, and Df, a cell capacitor C2, and gate drive circuits 3c, 3d, 3e, and 3f.

[0030] Gate drive circuits 3c, 3d, 3e, and 3f drive switching elements Qc, Qd, Qe, and Qf, respectively. Switching elements Qc and Qd are connected in series, and switching elements Qe and Qf are also connected in series. That is, the emitters (low potential sides) of switching elements Qc and Qe are connected to the collectors (high potential sides) of switching elements Qd and Qf, respectively.

[0031] The collectors of the switching elements Qc and Qe are electrically connected to the high-potential side of the cell capacitor C2. The emitters of the switching elements Qd and Qf are electrically connected to the low-potential side of the cell capacitor C2. Freewheeling diodes Dc, Dd, De, and Df are connected in antiparallel to the switching elements Qc, Qd, Qe, and Qf, respectively. The connection point of the switching elements Qc and Qd is electrically connected to the input / output terminal T1, and the connection point of the switching elements Qe and Qf is electrically connected to the input / output terminal T2.

[0032] The gate drive circuits 3c, 3d, 3e, 3f apply gate drive voltages to the gate terminals G of the switching elements Qc, Qd, Qe, Qf and the gate control terminals Gd of the freewheeling diodes Dc, Dd, De, Df, respectively, based on a gate drive command signal (unsigned) supplied from the control device 20. In this way, the gate drive circuits 3c to 3f control the currents flowing through the switching elements Qc to Qf and the forward voltages of the freewheeling diodes Dc to Df.

[0033] Furthermore, the gate drive circuits 3c to 3f output drive commands SBc, SBd, SBe, and SBf, respectively, which are binary signals. If at least one of these drive commands SBc to SBf is "1," the bypass device 2 electrically shorts the input / output terminals T1 and T2, preventing a significant voltage from being applied to the cell 1. On the other hand, if all of the drive commands SBc to SBf are "0," the bypass device 2 enters a high-impedance state, preventing a significant current from flowing through the bypass device 2.

[0034] FIG. 5 is a circuit diagram of a gate drive circuit 3 and its periphery. The gate drive circuit 3 in the figure is any one of the gate drive circuits 3a to 3f (see FIGS. 3 and 4). Similarly, the switching element Q (switching function, semiconductor element) is any one of the switching elements Qa to Qf, the freewheeling diode D (diode function) is any one of the freewheeling diodes Da to Df, and the drive command SB is any one of the drive commands SBa to SBf. Also, FIG. 5 illustrates an example in which an IGBT is used as the switching element Q.

[0035] 5, the gate drive circuit 3 includes a drive circuit 40, a short-circuit / surge detection circuit 50 (overcurrent determination unit), a suppression circuit 60 (protection unit), a power supply unit 70, and an OR circuit 72. The power supply unit 70 applies a predetermined positive voltage Vp and negative voltage Vm to each unit in the gate drive circuit 3.

[0036] The switching element Q and the freewheel diode D are included in the illustrated power semiconductor module J1 (semiconductor device). A parasitic inductance LE exists between the emitter terminal of the switching element Q and the low-potential side output terminal E of the power semiconductor module J1. The parasitic inductance LE is, for example, the wiring inductance between the IGBT chip that constitutes the switching element Q or the diode chip that constitutes the freewheel diode D and the output terminal E of the power semiconductor module on which they are mounted, and typically has an inductance value of several nH. The counter electromotive force Vet generated in this parasitic inductance LE is proportional to the result of differentiating the current Ic output from the power semiconductor module J1.

[0037] The drive circuit 40 also includes a gate control unit 48, NMOSFETs 41 and 43, PMOSFETs 42 and 44, and a resistor 45 (first resistor). Here, the NMOSFET 41 and the PMOSFET 42 control the voltage at the gate terminal G of the switching element Q. The NMOSFET 43 and the PMOSFET 44 control the voltage at the gate control terminal Gd of the freewheeling diode D. Hereinafter, the NMOSFETs 41 and 43 and the PMOSFETs 42 and 44 may be simply referred to as "FETs 41 to 44."

[0038] A positive voltage Vp is applied to the source terminals of the PMOSFETs 42 and 44, and a negative voltage Vm is applied to the source terminals of the NMOSFETs 41 and 43. A connection point 46 between the resistor 45 and the NMOSFET 41 in the drive circuit 40 is connected to the gate terminal G of the switching element Q. The drain terminal of the PMOSFET 44 is connected to the drain terminal of the NMOSFET 43, and this connection point is connected to the gate control terminal Gd of the freewheeling diode D.

[0039] The gate control unit 48 is connected between the control device 20 and the gate terminals of each of the FETs 41 to 44. The gate control unit 48 complementarily turns on and off the PMOSFET 42 and the NMOSFET 41 based on a gate drive command signal (unsigned) from the control device 20. In this way, the gate control unit 48 controls the voltage of the gate terminal G with respect to the reference terminal SS of the switching element Q, i.e., the gate voltage VGE. When the gate voltage VGE exceeds a predetermined threshold voltage Vth1 (not shown), the switching element Q is turned on. On the other hand, when the gate voltage VGE becomes equal to or lower than the threshold voltage Vth1, the switching element Q is turned off and cuts off the current Ic.

[0040] Furthermore, gate control unit 48 complementarily turns on and off PMOSFET 44 and NMOSFET 43 based on a gate drive command signal (unsigned) from control device 20. In this way, gate control unit 48 controls gate voltage VGdE of freewheeling diode D (voltage at gate control terminal Gd with respect to reference terminal SS of Qb). In this way, gate control unit 48 controls forward voltage VF of freewheeling diode D when current is conducted.

[0041] When the gate voltage VGdE exceeds a predetermined threshold voltage Vth2 (not shown) while the freewheeling diode D is conducting current, the amount of minority carriers (holes) injected from the anode decreases, suppressing conductivity modulation within the device and resulting in a higher forward voltage VF. Also, when the gate voltage VGdE falls below the threshold voltage Vth2 while the freewheeling diode D is conducting current, the amount of hole injection increases, promoting conductivity modulation within the device and resulting in a lower forward voltage VF.

[0042] The short circuit / surge detection circuit 50 also includes voltage dividing resistors 51 and 52, an integration circuit 54 (integration signal output section), comparators 56 and 57 (determination section) for determining abnormal current, and variable voltage sources 58 and 59.

[0043] The voltage-dividing resistors 51 and 52 are connected in series, and this series circuit is connected to the reference terminal SS of the switching element Q and the output terminal E of the power semiconductor module J1. The connection point of the voltage-dividing resistors 51 and 52 is connected to the input terminal of an integrating circuit 54. The voltage-dividing resistors 51 and 52 have resistance values ​​R1 and R2, respectively, and divide the counter electromotive force Vet generated in the parasitic inductance LE of the power semiconductor module J1, and output the result as an input voltage Vin to the integrating circuit 54.

[0044] The counter electromotive force Vet generated in the parasitic inductance LE is expressed by the following equation (1). Vet = -LE × dIc / dt …(1)

[0045] Furthermore, if the ratio (R1 / R2) of the resistance values ​​R1 and R2 of the voltage dividing resistors 51 and 52 is a voltage dividing ratio α, the input voltage Vin of the integrating circuit 54 is expressed by the following equation (2). Vin = α × Vet …(2)

[0046] The integrating circuit 54 includes a resistor 542, a capacitor 544, and an operational amplifier 546. The resistor 542 is connected to the connection point of the voltage-dividing resistors 51 and 52 and to the inverting input terminal (-) of the operational amplifier 546. The non-inverting input terminal (+) of the operational amplifier 546 is connected to the reference terminal SS of the switching element Q. This allows the integrating circuit 54 to integrate the input voltage Vin over time and output the result as an output voltage Vout (integrated signal).

[0047] If the resistance value of resistor 542 is R and the capacitance of capacitor 544 is C, then the output voltage Vout is as shown in the following equation (3). Since the input voltage Vin is proportional to the result of differentiating the current Ic of the power semiconductor module J1, the output voltage Vout becomes a voltage proportional to the current Ic flowing through the switching element Q or the freewheeling diode D. Vout = - (1 / RC) × ∫ Vin dt …(3)

[0048] A negative voltage Vm is applied to the negative terminals of variable voltage sources 58 and 59. The sum of the output voltage of variable voltage source 58 and the negative voltage Vm becomes a short-circuit determination voltage Vref1, which is a positive value. The sum of the output voltage of variable voltage source 59 and the negative voltage Vm becomes a surge determination voltage Vref2, which is a negative value. The short-circuit determination voltage Vref1 is applied to the inverting input terminal (-) of comparator 56, and the surge determination voltage Vref2 is applied to the non-inverting input terminal (+) of comparator 57. The output terminal of integrator circuit 54 is connected to the non-inverting input terminal (+) of comparator 56 and the inverting input terminal (-) of comparator 57.

[0049] As a result, the comparator 56 compares the short-circuit determination voltage Vref1 with the output voltage Vout, and outputs a comparison signal CP1 (first determination result) that is "1" if "Vout≧Vref1" and "0" otherwise. Also, the comparator 57 compares the surge determination voltage Vref2 with the output voltage Vout, and outputs a comparison signal CP2 (second determination result) that is "1" if "Vref2≧Vout" and "0" otherwise.

[0050] The comparison signals CP1 and CP2 are supplied to the suppression circuit 60 and the OR circuit 72. The OR circuit 72 supplies the logical sum of the comparison signals CP1 and CP2 as a drive command SB to the bypass device 2. In this way, the short-circuit / surge detection circuit 50 detects the magnitude and direction of the current Ic flowing through the switching element Q or the freewheeling diode D based on the back electromotive force Vet generated in the parasitic inductance LE, and determines whether or not an abnormal current is flowing therethrough.

[0051] In this embodiment, the magnitude and direction of the current Ic are determined using the parasitic inductance LE. This parasitic inductance LE is parasitically provided as wiring inductance of the power semiconductor module J1. Therefore, this embodiment eliminates the need to provide an IGBT or diode for current monitoring, resulting in an advantage of reduced costs.

[0052] FIG. 6 is a diagram showing the relationship between voltages and the like at various parts in FIG. FIG. 6 shows the relationship between voltages and other factors for cases #1 to #4. Case #1 is a case in which a short circuit occurs in switching element Q. In this case, a current Ic that exceeds the current Ic that flows through switching element Q during normal turn-on operation (case #2) flows. The rate of increase (di / dt) of current Ic is defined as positive when the current increases in the direction of Ic shown in FIG. 5. As this current Ic increases over time, the polarity of the back electromotive force Vet becomes negative and the polarity of the output voltage Vout becomes positive. Then, as the output voltage Vout becomes equal to or greater than the short-circuit determination voltage Vref1, the comparator 56 determines that an abnormality has occurred and the comparison signal CP1 becomes "1." This activates the suppression circuit 60.

[0053] Case #2 is a case in which switching element Q is turned on. In this case, the current Ic flowing through switching element Q increases over time. Therefore, the polarity of the back electromotive force Vet becomes negative and the polarity of the output voltage Vout becomes positive. However, in a normal turn-on operation, the output voltage Vout is less than the short-circuit determination voltage Vref1, so it is determined to be normal, and both comparison signals CP1 and CP2 become "0." Therefore, the suppression circuit 60 does not operate.

[0054] Furthermore, case #3 is a case in which switching element Q is turned off. In this case, the current Ic flowing through switching element Q decreases over time. Therefore, the polarity of the back electromotive force Vet becomes positive and the polarity of the output voltage Vout becomes negative. Then, since the output voltage Vout exceeds the surge determination voltage Vref2 (because the absolute value of the output voltage Vout is smaller than the absolute value of the surge determination voltage Vref2), it is determined to be normal, and both comparison signals CP1 and CP2 become "0." Therefore, the suppression circuit 60 does not operate.

[0055] Case #4 is a case in which a surge current flows into the freewheeling diode D. This surge current occurs, for example, when the high-potential side and low-potential side of the cell capacitor C1 in FIG. 3 are electrically short-circuited. That is, the assumed surge current is an excessive forward current that exceeds the rated current and flows through the freewheeling diode D. In this case, the current Ic decreases over time (its absolute value increases), so the polarity of the back electromotive force Vet becomes positive and the polarity of the output voltage Vout becomes negative. When a surge current flows, the output voltage Vout fluctuates beyond the normal turn-off range, and the output voltage Vout falls below the surge determination voltage Vref2 (the absolute value of the output voltage Vout becomes greater than or equal to the surge determination voltage Vref2). This causes the comparator 57 to determine that an abnormality has occurred, the comparison signal CP2 becomes "1," and the suppression circuit 60 is activated.

[0056] Returning to FIG. 5, the suppression circuit 60 includes an NMOSFET 63, a gate control unit 64, and a resistor 66 (second resistor).

[0057] A negative voltage Vm is applied to the source terminal of NMOSFET 63, and a drain terminal of NMOSFET 63 is connected to gate terminal G of switching element Q via resistor 66. Comparison signals CP1 and CP2 output from comparators 56 and 57 are input to gate control unit 64. In addition, output terminals of gate control unit 64 are connected to the gate terminals of NMOSFET 43 and NMOSFET 63, respectively.

[0058] When the comparison signal CP1 becomes "1," the gate control unit 64 holds the NMOSFET 63 in the on state for a predetermined hold time T11. At this time, the switching element Q is in a conductive state, so the PMOSFET 42 that controls the gate terminal G is also in the on state. Therefore, during the hold time T11, both the PMOSFET 42 and the NMOSFET 63 are in the on state. While the comparison signal CP1 was "0," the gate voltage VGE was the positive voltage Vp. However, when the comparison signal CP1 rises to "1," the gate voltage VGE drops to the suppression voltage Vsup shown in the following equation (4).

[0059] Vsup = (Rsup / (Ron+Rsup))×(Vp-Vm)+Vm …(4) However, in Equation (4), the resistance value Rsup is the resistance value of resistor 66, and the resistance value Ron is the resistance value of resistor 45. Note that it is preferable that the suppression voltage Vsup is higher than the threshold voltage Vth1 (not shown) of the switching element Q and lower than the positive-side voltage Vp (that is, "Vth1 < Vsup < Vp").

[0060] Also, when the comparison signal CP2 becomes "1", the gate control unit 64 holds the NMOSFET 43 in the on state for a predetermined holding time T11. As a result, the gate voltage VGdE of the freewheeling diode D is held at a negative-side voltage Vm lower than the threshold voltage Vth2 for a predetermined holding time T12. Thereby, in the freewheeling diode D, the injection of holes from the anode increases and the conductivity modulation inside the element is promoted, resulting in a decrease in the forward voltage VF.

[0061] Due to the decrease in the forward voltage VF, the power consumption generated in the freewheeling diode D through which the surge current is flowing can be significantly reduced. Thereby, since the withstand capacity of the freewheeling diode D is improved, it is possible to detect the possibility before the power semiconductor module J1 reaches an open-circuit fault and prevent explosion, enhancing the reliability of cell 1.

[0062] The OR circuit 72 also supplies the bypass device 2 with the logical sum of the comparison signals CP1 and CP2 as the drive command SB. As described above, the drive command SB shown in FIG. 5 is one of the drive commands SBa to SBf (see FIGS. 3 and 4). The bypass device 2 is in a non-conductive state if all the supplied drive commands SB are "0." On the other hand, if any of the drive commands SB becomes "1," the bypass device 2 electrically shorts the input / output terminals T1 and T2 to prevent a significant voltage from being applied to the power semiconductor module J1. As a result, even if an abnormality occurs in any of the cells 1 constituting the power conversion device 100 shown in FIG. 1, the bypass device 2 provided in the cell 1 bypasses the input and output, allowing the power conversion device 100, which is an MMC system, to continue operating.

[0063] FIG. 7 is a diagram showing an example of the waveforms of the gate voltage VGE and the current Ic of the switching element Q. The horizontal axis in Figure 7 represents time t, and the vertical axis represents voltage and current. In the solid-line voltage waveform PV1 shown in Figure 7, the gate voltage VGE is below the threshold voltage Vth1 before time t10. Therefore, in the solid-line current waveform PI1, the current Ic is "0" before time t10. When the gate voltage VGE exceeds the threshold voltage Vth1 at time t10, the current Ic increases as the gate voltage VGE increases. When the gate voltage VGE reaches the positive voltage Vp at time t12, the current Ic reaches the saturation current Ic1. Thereafter, as the gate voltage VGE is reduced, the current Ic decreases accordingly. When the gate voltage VGE reaches the suppression voltage Vsup at time t14, the current Ic becomes the saturation current Ic2.

[0064] 7 is the voltage waveform when the gate voltage VGE is maintained at the positive voltage Vp after time t12, and the current waveform PI2 is the current waveform in that case. The saturation current of the switching element Q is (VGE-Vth1). 2The current Ic in the diagram is the saturation current of switching element Q. Therefore, by lowering the gate voltage VGE from the positive side voltage Vp to the suppression voltage Vsup, the saturation current of switching element Q can be reduced by "Ic1 - Ic2." This significantly reduces the power consumption of switching element Q and improves its withstand capability. Therefore, it is possible to detect the possibility of an open circuit failure in power semiconductor module J1 before it occurs, preventing explosion and improving the reliability of cell 1.

[0065] FIG. 8 is a diagram showing an example of the forward voltage / current characteristics of the freewheeling diode D. The horizontal axis of Figure 8 represents the forward voltage VF, and the vertical axis represents the forward current IF. The low injection characteristic PL (first forward voltage-current characteristic) in the figure represents the characteristics when the gate voltage VGdE of the freewheeling diode D is set to the positive voltage Vp, i.e., in low injection mode. The high injection characteristic PH (second forward voltage-current characteristic) represents the characteristics when the gate voltage VGdE is set to the negative voltage Vm, i.e., in high injection mode. As is clear from the figure, the high injection characteristic PH can lower the forward voltage VF for the same forward current IF compared to the low injection characteristic PL. The power consumption of the freewheeling diode D is proportional to the square of the forward voltage VF. Therefore, for example, when a surge current is generated in the freewheeling diode D, the high injection characteristic PH can significantly reduce the power consumption of the freewheeling diode D compared to the low injection characteristic PL.

[0066] FIG. 9 is an example of a waveform diagram of each part when a short circuit occurs in the switching element Q. 9, voltage waveforms PV22 and PV26 indicated by solid lines are the waveforms of the back electromotive force Vet and the output voltage Vout when a short circuit occurs in switching element Q. Voltage waveforms PV24 and PV28 indicated by dashed lines are the waveforms of the back electromotive force Vet and the output voltage Vout during normal operation when no short circuit occurs in switching element Q.

[0067] Assume that a short circuit occurs in the switching element Q (see FIG. 5) at time t20 in FIG. 9. Then, as shown in voltage waveform PV22, the back electromotive force Vet in the parasitic inductance LE falls in the negative direction (the absolute value of the back electromotive force Vet increases). As a result, the output voltage Vout of the integrator circuit 54 in FIG. 5 rises over time, as shown in voltage waveform PV26. This output voltage Vout assumes a value proportional to the current Ic. At time t22, when the output voltage Vout exceeds the short-circuit determination voltage Vref1, the comparison signal CP1 (see FIG. 5) becomes "1." Then, the suppression circuit 60 changes the gate voltage VGE of the switching element Q from the positive voltage Vp to the suppression voltage Vsup. This instantly reduces the energy consumed by the switching element Q, enabling the switching element Q to have a high withstand voltage.

[0068] Furthermore, when the comparison signal CP1 becomes "1", the drive command SB supplied to the bypass device 2 also becomes "1" at time t22. In Fig. 9, the operation mode MD of the bypass device 2 is either an open mode MDO that puts the bypass device 2 into a high impedance state, or a short-circuit mode MDS that puts the bypass device 2 into a short-circuit state. Normally (in the illustrated example, after time t20), the operation mode MD is the open mode MDO. However, at time t24, when the operation delay time Td has elapsed since time t22, the operation mode MD of the bypass device 2 becomes the short-circuit mode MDS.

[0069] It is desirable that the timing at which the suppression circuit 60 starts operating (time t22 in the illustrated example) be earlier than the timing at which the bypass device 2 enters the short-circuit mode MDS (time t24 in the illustrated example). In the configuration shown in Fig. 5, this requirement is usually met because there is an operation delay time Td for the bypass device 2 to turn on. This makes it possible to suppress the energy consumed by the switching element Q at an early timing, and increases the possibility of preventing the power semiconductor module J1 from exploding before it experiences an open circuit failure.

[0070] After the bypass device 2 ensures the short-circuit mode of the cell 1, the gate voltage VGE may be lowered to the negative voltage Vm at an arbitrary timing (time t26 in the illustrated example), thereby shutting off the switching element Q. That is, in the gate control unit 64 of FIG. 5, the holding time T11 for suppressing the switching element Q may be set such that "Td < T11". In other words, as shown in the figure, the relationship of each time may be "t22 < t24 < t26".

[0071] Also, as shown in the voltage waveform PV28 in the figure, even during normal operation, when the switching element Q is turned on, a reverse electromotive force Vet with a negative polarity is generated in the parasitic inductance LE as seen from the reference terminal SS. However, as shown in the voltage waveform PV28, during normal operation, the output voltage Vout, which is the integration result of the reverse electromotive force Vet, is less than the short-circuit determination voltage Vref1. That is, the constants in the integration circuit 54 (see FIG. 5) are set so as to obtain the characteristics of the voltage waveform PV28 in FIG. 9. Therefore, during normal operation, the suppression circuit 60 and the bypass device 2 do not operate, and the cell 1 continues to operate normally.

[0072] FIG. 10 is an example of a waveform diagram of each part when a surge current (excessive current) flows through the freewheeling diode D. The voltage waveforms PV32 and PV36 shown by solid lines in FIG. 10 are the waveforms of the reverse electromotive force Vet and the output voltage Vout when a surge current occurs. The voltage waveforms PV34 and PV38 shown by broken lines are the waveforms of the reverse electromotive force Vet and the output voltage Vout during normal operation when no surge current occurs.

[0073] At time t30 in FIG. 10, it is assumed that a surge current flows through the freewheeling diode D. Then, as shown in the voltage waveform PV32, the reverse electromotive force Vet in the parasitic inductance LE rises in the positive direction. As a result, as shown in the voltage waveform PV36, the output voltage Vout decreases with the passage of time. As described above, this output voltage Vout is a value proportional to the current Ic.

[0074] When the output voltage Vout becomes less than the surge determination voltage Vref2 at time t32 (when the absolute value of Vout exceeds the absolute value of Vref2), the comparison signal CP2 (see FIG. 5) becomes "1". Then, the gate voltage VGdE of the reflux diode D is held at the negative voltage Vm that is less than the threshold voltage Vth2 (not shown) for the holding time T12 by the suppression circuit 60. As a result, for this holding time T12, the forward voltage / current characteristic of the reflux diode D changes from the low injection characteristic PL (see FIG. 8) to the high injection characteristic PH. That is, the energy consumed by the reflux diode D is instantaneously suppressed, and the reflux diode D instantaneously has a higher breakdown voltage.

[0075] As described above, the operation mode MD of the bypass device 2 is usually (after time t30 in the illustrated example) the open mode MDO. However, at time t34 when the operation delay time Td has elapsed since time t32, the operation mode MD of the bypass device 2 becomes the short-circuit mode MDS. It is desirable that the timing (time t32 in the illustrated example) at which the suppression circuit 60 changes the gate voltage VGdE of the reflux diode D to the negative voltage Vm is earlier than the timing (time t34 in the illustrated example) at which the bypass device 2 becomes the short-circuit mode MDS. In the configuration shown in FIG. 5, since there is an operation delay time Td for the bypass device 2 to turn on, this requirement is usually satisfied.

[0076] After the short-circuit mode of the cell 1 is ensured by the bypass device 2, it is preferable to return the gate voltage VGdE of the reflux diode D to the positive voltage Vp at an arbitrary timing (time t36 in the illustrated example) to return the characteristic of the reflux diode D to the low injection characteristic PL. That is, in the gate control unit 64 of FIG. 5, the holding time T12 for holding the gate voltage VGdE at the negative voltage Vm may be set so that "Td < T12". In other words, as shown in the figure, the relationship of each time may be "t32 < t34 < t36".

[0077] Furthermore, as shown by the dashed voltage waveforms PV34 and PV38 in Figure 10, even during normal operation, when current flows back through the freewheeling diode D, a positive back electromotive force Vet is generated across the parasitic inductance LE as viewed from the reference terminal SS. However, during normal operation, the output voltage Vout, which is the integration result of the back electromotive force Vet, remains above the surge determination voltage Vref2. In other words, the constants of the integration circuit 54 are set to achieve the voltage waveform PV38 shown in the figure. Therefore, during normal operation, the suppression circuit 60 and the bypass device 2 do not operate, and the cell 1 continues to operate normally.

[0078] 3 to 5, a bypass thyristor capable of passing a current in both directions is used as the bypass device 2. However, a circuit other than a bypass thyristor may be used as the bypass device 2. In other words, any circuit may be used as long as it can bypass between the input / output terminals T1 and T2 in response to the drive command SB supplied from the gate drive circuit 3.

[0079] For example, if sufficient current can be passed, a mechanical switch such as a relay switch may be used as the bypass device 2. Generally, mechanical switches have a longer operation delay time Td (see FIGS. 9 and 10 ) than semiconductor switches such as bypass thyristors, making it difficult to perform short-circuit (bypass) processing before a failed cell 1 experiences an open circuit fault. In contrast, according to this embodiment, the suppression circuit 60 can enhance the withstand capability of the switching element Q or the freewheeling diode D prior to the operation of the bypass device 2. Therefore, even if a bypass device 2 with a long operation delay time Td is used, it is possible to protect the power semiconductor module J1 from explosion and ensure a short-circuit mode before the cell 1 experiences an open circuit fault. Therefore, even when an inexpensive mechanical switch is used, a highly reliable power conversion device 100 can be configured, and its cost can be reduced.

[0080] [Second embodiment] Next, a second embodiment will be described. In the following description, parts corresponding to those in the first embodiment described above will be given the same reference numerals, and their description may be omitted. The overall configuration of the power conversion device 100 and the configuration of the cell 1 according to the second embodiment are the same as those in the first embodiment (FIGS. 1 to 4). However, as will be described below, the configuration of the gate drive circuit 3 differs from that of the first embodiment.

[0081] FIG. 11 is a circuit diagram of the gate drive circuit 3 and its peripheral circuitry in the second embodiment. In this embodiment, a power semiconductor module J7 (semiconductor device) is used instead of the power semiconductor module J1 (see FIG. 5). In the power semiconductor module J7, a switching element Q7 (switching function, semiconductor element) and a free wheel diode D are connected in anti-parallel. The switching element Q7 has two gate terminals that can be controlled independently of each other. These are called a gate terminal Gs (first gate terminal) and an auxiliary gate terminal Gc (second gate terminal).

[0082] Therefore, the power semiconductor module J7 includes a gate control terminal Gd of the freewheeling diode D, a gate terminal Gs of the switching element Q7, and an auxiliary gate terminal Gc of the switching element Q7. To control the voltages applied to these three terminals, the gate drive circuit 3 includes a drive circuit 80 instead of the drive circuit 40 of the first embodiment. The drive circuit 80 includes a gate control unit 88, NMOSFETs 81, 83, and 85, and PMOSFETs 82, 84, and 86.

[0083] Here, NMOSFET 81 and PMOSFET 82 control the voltage of gate terminal Gs of switching element Q7 relative to reference terminal SS, i.e., gate voltage VGsE. NMOSFET 83 and PMOSFET 84 control the voltage of auxiliary gate terminal Gc of switching element Q7 relative to reference terminal SS, i.e., auxiliary gate voltage VGcE. NMOSFET 85 and PMOSFET 86 control the voltage of gate control terminal Gd of freewheeling diode D relative to reference terminal SS, i.e., gate voltage VGdE. Hereinafter, NMOSFETs 81, 83, 85 and PMOSFETs 82, 84, 86 may be simply referred to as "FETs 81 to 86."

[0084] A negative voltage Vm is applied to the source terminals of NMOSFETs 81, 83, and 85, and a positive voltage Vp is applied to the source terminals of PMOSFETs 82, 84, and 86. The drain terminals of NMOSFETs 81, 83, and 85 are connected to the drain terminals of PMOSFETs 82, 84, and 86, respectively, and these connection points are connected to the gate terminal Gs of switching element Q7, the auxiliary gate terminal Gc of switching element Q7, and the gate control terminal Gd of freewheeling diode D, respectively. The gate terminals of each of FETs 81 to 86 are connected to gate control unit 88.

[0085] In this embodiment, a suppression circuit 90 is provided instead of the suppression circuit 60 (see FIG. 5) of the first embodiment, and the suppression circuit 90 includes a gate control unit 98. The gate control unit 98 controls the gate voltages of the NMOSFETs 81, 83, and 85 in priority to the gate control unit 88 in the drive circuit 80.

[0086] The configuration of the gate drive circuit 3 other than that described above is the same as that of the first embodiment. Similarly to the gate control unit 48 (see FIG. 5) of the first embodiment, the gate control unit 88 of this embodiment complementarily drives the PMOSFET 82 and the NMOSFET 81 on and off based on a gate drive command signal from the control device 20. This allows the gate control unit 88 to control the gate voltage VGsE of the gate terminal Gs of the switching element Q7 relative to the reference terminal SS, thereby controlling the current conduction state of the switching element Q7 between on and off. The method of controlling the gate control terminal Gd of the freewheeling diode D is the same as that of the first embodiment.

[0087] FIG. 12 is a diagram showing an example of waveforms of the gate voltage VGsE, the auxiliary gate voltage VGcE, and the current Ic of the switching element Q7. The horizontal axis in Figure 12 represents time t, and the vertical axis represents voltage and current. The gate voltage VGsE in Figure 12 is below the threshold voltage Vth1 before time t40. Similarly, in the solid line voltage waveform PV41, the auxiliary gate voltage VGcE is below the threshold voltage Vth1 before time t40. Therefore, in the solid line current waveform PI41, the current Ic is "0" before time t40.

[0088] At time t40, when the gate voltage VGsE and the auxiliary gate voltage VGcE exceed the threshold voltage Vth1, the current Ic increases as the gate voltage VGsE and the auxiliary gate voltage VGcE increase. At time t42, when the gate voltage VGsE and the auxiliary gate voltage VGcE reach the positive voltage Vp, the current Ic reaches a saturation current Ic41. Thereafter, as the auxiliary gate voltage VGcE is lowered while maintaining the positive voltage Vp, the current Ic decreases. At time t44, when the auxiliary gate voltage VGcE reaches the negative voltage Vm, the current Ic becomes a saturation current Ic42.

[0089] The dashed voltage waveform PV42 in Figure 12 represents the voltage waveform when the auxiliary gate voltage VGcE is maintained at the positive voltage Vp after time t42, and the current waveform PI42 represents the current waveform in that case. Therefore, by lowering the auxiliary gate voltage VGcE from the positive voltage Vp to the negative voltage Vm, the saturation current of switching element Q7 can be reduced by Ic41 - Ic42. This significantly reduces the power consumption of switching element Q7 and improves its durability. Therefore, the possibility of an open circuit fault in power semiconductor module J7 can be detected before it occurs, preventing explosion and improving the reliability of cell 1.

[0090] FIG. 13 is an example of a waveform diagram of each part when a short circuit occurs in the switching element Q7. 13, voltage waveforms PV52 and PV56 indicated by solid lines are the waveforms of the back electromotive force Vet and the output voltage Vout when a short circuit occurs in switching element Q. Voltage waveforms PV54 and PV58 indicated by dashed lines are the waveforms of the back electromotive force Vet and the output voltage Vout during normal operation when no short circuit occurs in switching element Q.

[0091] Assume that a short circuit occurs in switching element Q7 (see FIG. 11) at time t50 in FIG. 13. Then, as shown in voltage waveform PV52, the back electromotive force Vet in parasitic inductance LE falls in the negative direction. As a result, the output voltage Vout of integration circuit 54 in FIG. 11 rises over time as shown in voltage waveform PV56. This output voltage Vout becomes proportional to the current Ic. At time t52, when output voltage Vout exceeds short-circuit determination voltage Vref1, comparison signal CP1 (see FIG. 11) becomes "1." Then, at time t52, the suppression circuit 90 reduces auxiliary gate voltage VGcE, which is the voltage at auxiliary gate terminal Gc of switching element Q7, from Vp to Vm.

[0092] At this time, among the two gate terminals of the switching element Q7, the electron current supplied to the switching element Q7 by the auxiliary gate terminal Gc becomes zero, and only the gate terminal Gs supplies an electron current to the switching element Q7. Then, as shown in FIG. 12, the saturation current can be decreased from Ic41 to Ic42. Thereby, the energy consumed by the switching element Q7 is instantaneously suppressed, and the switching element Q7 has a higher breakdown voltage. Also, when the comparison signal CP1 becomes "1", the drive command SB supplied to the bypass device 2 also becomes "1" at time t52.

[0093] In FIG. 13, the operation mode MD of the bypass device 2 is the open mode MDO after time t50. However, at time t54 when the operation delay time Td has elapsed from time t52, the operation mode MD of the bypass device 2 becomes the short - circuit mode MDS. After the short - circuit mode of the cell 1 is ensured by the bypass device 2, the switching element Q may be cut off by lowering the gate voltage VGsE to the negative voltage Vm at an arbitrary timing (time t56 in the illustrated example). That is, in the gate control unit 98 of FIG. 11, the holding time T21 for suppressing the switching element Q7 may be set such that "Td < T21". In other words, as shown in the figure, the relationship of each time may be "t52 < t54 < t56". Note that, in the present embodiment, the operation for preventing the open - circuit failure of the cell 1 due to the surge current of the free - wheeling diode D is the same as that of the first embodiment (see FIG. 10).

[0094] In the first embodiment described above, the gate voltage VGE (see FIG. 9) was set to the suppression voltage Vsup to suppress the saturation current of the switching element Q. However, since the saturation current of the switching element Q is proportional to (VGE - Vth1), the saturation current Ic2 (see FIG. 7) is affected by the variation in the threshold voltage Vth1 of the switching element Q. On the other hand, according to the present embodiment, since the saturation current Ic42 (see FIG. 12) can be determined regardless of the variation in the threshold voltage Vth1, more robust control can be realized. 2 to.

[0095] [Third embodiment] Next, a third embodiment will be described. In the following description, parts corresponding to those in the other embodiments described above will be given the same reference numerals, and their description may be omitted. The overall configuration of the power conversion device 100 and the configuration of the cell 1 according to the third embodiment are the same as those in the first embodiment (FIGS. 1 to 4). However, as will be described below, the configuration around the gate drive circuit 3 differs from that of the first embodiment.

[0096] FIG. 14 is a circuit diagram of the gate drive circuit 3 and its peripheral essential parts in the third embodiment. The third embodiment differs from the first embodiment in that the gate drive circuit 3 supplies a drive command SB to the control device 20. As described above, the control device 20 includes the computer 980 (see FIG. 2). In FIG. 14, the inside of the control device 20 shows functions realized by application programs of the computer 980.

[0097] That is, the control device 20 in this embodiment includes a drive command tallying unit 22, a cell voltage calculation unit 24, and a system voltage setting unit 26. The drive command tallying unit 22 adds up the number of commands that are "1" among the drive commands SB received from each cell 1 (see FIG. 1), that is, the number of cells in which an abnormal current has been detected, for each arm 10. The addition results for each arm 10 are set as the numbers of abnormal cells N1, N2, N3, N4, N5, and N6 (see FIG. 15), respectively.

[0098] Here, the number of cells connected in series in each arm 10 is Ncell, and the system DC voltage in the DC system 130 is Vsys. The cell voltage calculation unit 24 calculates the applied voltages V1, V2, V3, V4, V5, and V6 (see FIG. 15) per normal cell in each arm 10 based on the following formula (5):

[0099] Vk=Vsys / (Ncell-Nk) ...Equation (5) (where k=1 to 6)

[0100] FIG. 15 is a diagram showing the relationship between each arm 10, the number of abnormal cells Nk (k=1 to 6), and the applied voltage Vk. As shown in the figure, the control device 20 obtains the number of abnormal cells Nk and the applied voltage Vk for each arm 10.

[0101] In the cell 1 where an abnormal current is detected, the input / output terminals T1 and T2 are bypassed by the bypass device 2 (see FIG. 14), and no significant voltage is applied to the cell 1. As a result, the applied voltage Vk per normal cell increases. If the applied voltage Vk per normal cell exceeds the rated voltage of the switching element Q or the freewheeling diode D, there is a risk of dielectric breakdown in the semiconductor elements, which could reduce the reliability of the normal cells.

[0102] The maximum of the applied voltages Vk (k=1 to 6) is called the maximum applied voltage Vmax. When the maximum applied voltage Vmax exceeds a predetermined specified voltage Vcrit, the system voltage setting unit 26 reduces the system DC voltage Vsys so that "Vmax≦Vcrit" holds. Here, the specified voltage Vcrit is preferably lower than the rated withstand voltages of the switching element Q and the freewheel diode D. This prevents a decrease in the reliability of normal cells even when a cell 1 detects an abnormal current, allowing the power conversion device 100 to continue operating until maintenance is required to replace the abnormal cell with a normal cell.

[0103] [Effects of the embodiment] As described above, according to the embodiment, the power conversion device 100 includes semiconductor devices (J1, J7) connected between a pair of input / output terminals T1, T2 and having a switching function (Q, Q7) for switching a current flowing in a first direction (T1 → T2) and a diode function (D) whose forward direction is a second direction (T2 → T1) opposite to the first direction (T1 → T2); drive circuits 40, 80 that control the on / off state of the switching function (Q, Q7) and apply to the diode function (D) either a first forward voltage-current characteristic (PL) or a second forward voltage-current characteristic (PH) in which the forward voltage VF is lower than the first forward voltage-current characteristic (PL) for the same forward current IF; and a protection unit (60, 90) that reduces the current flowing in the first direction (T1 → T2) when the first determination result (CP1) is affirmative, and applies a second forward voltage-current characteristic (PH) to the diode function (D) when the second determination result (CP2) is affirmative. The protection unit (60, 90) also includes: an overcurrent determination unit (50) that outputs a first determination result (CP1) of whether a current flowing in a first direction (T1 → T2) is in a first overcurrent state (Vout≧Vref1) or not, and a second determination result (CP2) of whether a current flowing in a second direction (T2 → T1) is in a second overcurrent state (Vref2≧Vout); a protection unit (60, 90) that reduces the current flowing in the first direction (T1 → T2) when the first determination result (CP1) is affirmative, and applies a second forward voltage-current characteristic (PH) to the diode function (D); and a bypass device (2) that bypasses the pair of input / output terminals T1, T2 after the protection unit (60, 90) operates when the first determination result (CP1) or the second determination result (CP2) is affirmative.

[0104] This reduces power consumption in the semiconductor devices (J1, J7) and appropriately protects the semiconductor devices (J1, J7) from explosion when the current flowing in the first direction (T1 → T2) reaches the first overcurrent state (Vout≧Vref1) and when the current flowing in the second direction (T2 → T1) reaches the second overcurrent state (Vref2≧Vout). This improves the reliability of the cell 1 and the power conversion device 100.

[0105] Furthermore, it is more preferable that the switching function (Q) is realized by a voltage-controlled semiconductor element (Q) having a gate terminal G, and that the protection unit (60) reduces the current flowing through the semiconductor element (Q) by lowering the gate voltage VGE applied to the gate terminal G when the first determination result (CP1) is positive. In this way, when the current flowing in the first direction (T1 → T2) reaches a first overcurrent state (Vout≧Vref1), the gate voltage VGE is lowered, thereby reducing the power consumption in the semiconductor devices (J1, J7).

[0106] More preferably, the drive circuit 40 includes a PMOSFET (42), a first resistor (45), and a first NMOSFET (41) connected in series between a positive voltage Vp and a negative voltage Vm, with a junction 46 between the first resistor (45) and the first NMOSFET (41) connected to a gate terminal G, and the protection unit 60 includes a second resistor (66) and a second NMOSFET (63) connected in series between the junction 46 and the negative voltage Vm, and the PMOSFET (42) and the second NMOSFET (63) are simultaneously turned on for a predetermined time to apply a voltage corresponding to the resistance values ​​of the first and second resistors (45, 66) to the gate terminal G, thereby lowering the gate voltage VGE. This allows the gate voltage VGE to be controlled with a simple circuit.

[0107] Furthermore, as in the second embodiment, it is more preferable that the switching function (Q7) is realized by a voltage-controlled semiconductor element (Q7) having a first gate terminal (Gs) and a second gate terminal (Gc) that can be controlled independently, and that the protection unit (90) reduces the current flowing through the semiconductor element (Q7) by cutting off the second gate terminal (Gc) when the first determination result (CP1) is positive. This suppresses the influence of variations in the threshold voltage Vth1, thereby realizing more robust control of the gate voltage VGE.

[0108] Furthermore, it is more preferable that the overcurrent determination unit (50) includes an integral signal output unit (54) that outputs an integral signal (Vout) obtained by time-integrating the back electromotive force Vet generated in the parasitic inductance LE present on the low potential side of the semiconductor devices (J1, J7), and determination units (56, 57) that output first and second determination results (CP1, CP2) based on the polarity and magnitude of the integral signal (Vout). This allows the first and second determination results (CP1, CP2) to be output using the parasitic inductance LE provided in the semiconductor devices (J1, J7), thereby achieving cost reduction of the power conversion device 100.

[0109] More preferably, the bypass device 2 includes a bypass thyristor or a mechanical switch that allows current to flow in both directions, thereby allowing the cell 1 to be bypassed appropriately.

[0110] Furthermore, the power conversion device 100 includes a plurality of arms 10 each having a plurality of cells 1 connected in series and a plurality of bypass devices 2 connected to each of the cells 1, and a control device 20 that controls the plurality of cells 1, and more preferably, the plurality of cells 1 each include a semiconductor device (J1, J7), a drive circuit 40, 80, an overcurrent determination unit (50), and a protection unit (60, 90). This allows the power conversion device 100 to function as a modular multilevel converter (MMC).

[0111] Furthermore, it is more preferable that the control device 20 includes a cell voltage calculation unit 24 that calculates the applied voltage Vk per normal cell 1 in each arm 10 based on the number of bypass devices 2 that have entered the bypass state in each arm 10, and a system voltage setting unit 26 that sets the system DC voltage Vsys to be applied to each arm 10 so that the applied voltage Vk is equal to or less than a predetermined specified voltage Vcrit. This makes it possible to set an appropriate system DC voltage Vsys based on the number of bypass devices 2 that have entered the bypass state.

[0112] [Variations] The present invention is not limited to the above-described embodiments and various modifications are possible. The above-described embodiments are provided as examples to facilitate understanding of the present invention and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to delete part of the configuration of each embodiment, or to add or replace other configurations. Furthermore, the control lines and information lines shown in the figures are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for the product. In reality, it is acceptable to consider that almost all components are interconnected. Possible modifications of the above-described embodiments include, for example, the following:

[0113] (1) In each of the above-described embodiments, the power conversion device 100 (see FIG. 1) is provided with a total of three pairs of arms 10 for the U phase, V phase, and W phase to accommodate the three-phase AC system 120. However, the power conversion device 100 may be provided with a pair of upper and lower arms 10 that are compatible with a single-phase AC system (not shown).

[0114] (2) In addition, in each of the above-described embodiments, an example has been described in which a power semiconductor module in which a switching element and a free wheel diode are included in one package is applied as the "semiconductor device." However, the "semiconductor device" is not limited to this, and may be applied as a semiconductor device having a switching element and a free wheel diode mounted in separate packages.

[0115] (3) Furthermore, the switching element constituting the semiconductor device is not limited to an IGBT, and may be a power MOSFET. Furthermore, the freewheeling diode constituting the semiconductor device may be any of a variety of diodes, such as a pn junction diode, a Schottky barrier diode, or a diode using both a pn junction and a Schottky junction, as long as the forward voltage can be controlled by a control terminal. Furthermore, silicon (Si) can be used as the semiconductor material constituting the switching element and the freewheeling diode, and wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) can also be used.

[0116] (4) Furthermore, each of the above-described embodiments employs a combination of normal (unidirectional current-conducting) switching elements Q and Q7 and a freewheeling diode D. In other words, in each of the above-described embodiments, the switching element Q and Q7 realizes the "switching function," and the freewheeling diode D realizes the "diode function." However, a reverse-conducting IGBT may be applied instead of both. In other words, the reverse-conducting IGBT may realize both the "switching function" and the "diode function."

[0117] (5) Furthermore, the cell 1 in each of the above-described embodiments includes the gate drive circuit 3 that is separate from the power semiconductor modules J1 and J7. However, the gate drive circuit 3 may be housed inside the power semiconductor modules J1 and J7.

[0118] (6) Furthermore, the freewheeling diode D in each of the above-described embodiments includes a gate control terminal Gd (see FIG. 5), and selects between high injection characteristics PH and low injection characteristics PL (see FIG. 8) depending on the gate voltage VGdE applied thereto. However, even a normal (two-terminal) diode has the characteristic that the higher the element temperature of the diode, the lower the forward voltage VF for the same forward current IF. Therefore, this characteristic may be utilized to select between high injection characteristics PH and low injection characteristics PL. Specifically, a normal (two-terminal) diode may be used instead of the freewheeling diode D in each of the above-described embodiments, and the high injection characteristics PH or low injection characteristics PL may be selected depending on whether the diode is heated by a heater or the like.

[0119] (7) Since the hardware of the control device 20 in the above embodiment can be realized by a general computer, programs that execute the various processes of the control device 20 described above may be stored on a storage medium or distributed via a transmission path.

[0120] (8) In the above embodiment, the above-mentioned processes of the control device 20 are described as software processes using a program, but some or all of them may be replaced with hardware processes using an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array), etc.

[0121] (9) The various processes executed by the control device 20 may be executed by a server computer via a network (not shown), and the various data stored in the above embodiment may also be stored in the server computer. [Explanation of symbols]

[0122] 1 cell 2. Bypass device 10 Arm 20 Control device 24 Cell voltage calculation section 26 System voltage setting section 40,80 drive circuit 45 Resistor (first resistor) 46 Connection Points 50 Short circuit / surge detection circuit (overcurrent detection section) 54 Integration circuit (integral signal output section) 56,57 Comparator (judgment section) 60,90 Suppression circuit (protection section) 66 Resistor (Second Resistor) 100 Power conversion device D Freewheeling diode (diode function) Gate terminal Gc Auxiliary gate terminal (second gate terminal) Gs Gate terminal (first gate terminal) IF forward current J1 Power semiconductor module (semiconductor device) J7 Power Semiconductor Module (Semiconductor Device) LE Parasitic inductance PH High injection characteristics (second forward voltage-current characteristics) PL low injection characteristics (first forward voltage-current characteristics) VF forward voltage Vk applied voltage Vm Negative voltage Vp Positive voltage CP1 Comparison signal (first judgment result) CP2 Comparison signal (second judgment result) VGE Gate voltage Vet back emf Q, Q7 Switching element (switching function, semiconductor element) Vout Output voltage (integrated signal) Vsys System DC voltage J1, J7 Power semiconductor module (semiconductor device) T1,T2 input / output terminals Vcrit specified voltage

Claims

1. a semiconductor device connected between a pair of input / output terminals, the semiconductor device having a switching function of switching a current flowing in a first direction and a diode function of having a second direction opposite to the first direction as a forward direction; a drive circuit that controls the on / off state of the switching function and applies, to the diode function, either a first forward voltage-current characteristic or a second forward voltage-current characteristic that provides a lower forward voltage than the first forward voltage-current characteristic for the same forward current; an overcurrent determination unit that outputs a first determination result as to whether or not the current flowing in the first direction is in a first overcurrent state, and a second determination result as to whether or not the current flowing in the second direction is in a second overcurrent state; a protection unit that reduces the current flowing in the first direction when the first determination result is positive, and applies the second forward voltage-current characteristic to the diode function when the second determination result is positive; a bypass device that bypasses the pair of input / output terminals after the protection unit is activated when the first determination result or the second determination result becomes positive. A power conversion device characterized by:

2. the switching function is realized by a voltage-controlled semiconductor element having a gate terminal; The protection unit reduces a gate voltage applied to the gate terminal when the first determination result is positive, thereby reducing a current flowing through the semiconductor element.

2. The power conversion device according to claim 1.

3. the drive circuit includes a PMOSFET, a first resistor, and a first NMOSFET connected in series in this order between a positive voltage and a negative voltage, and a connection point between the first resistor and the first NMOSFET is connected to the gate terminal; The protection unit includes a second resistor and a second NMOSFET connected in series between the connection point and the negative voltage, and reduces the gate voltage by simultaneously turning on the PMOSFET and the second NMOSFET for a predetermined time and applying a voltage corresponding to each resistance value of the first and second resistors to the gate terminal.

3. The power conversion device according to claim 2.

4. the switching function is realized by a voltage-controlled semiconductor element having independently controllable first and second gate terminals; The protection unit reduces a current flowing through the semiconductor device by cutting off the second gate terminal when the first determination result is affirmative.

2. The power conversion device according to claim 1.

5. The overcurrent determination unit an integral signal output unit that outputs an integral signal obtained by time-integrating a back electromotive force generated in a parasitic inductance present on a low potential side of the semiconductor device; a determination unit that outputs the first and second determination results based on the polarity and magnitude of the integrated signal.

2. The power conversion device according to claim 1.

6. The bypass device Includes bypass thyristors or mechanical switches that allow current to flow in both directions 2. The power conversion device according to claim 1.

7. a plurality of arms each having a plurality of cells connected in series and a plurality of bypass devices connected to each of the cells; a control device that controls the plurality of cells; Each of the plurality of cells includes the semiconductor device, the drive circuit, the overcurrent determination unit, and the protection unit.

7. The power conversion device according to claim 1, wherein:

8. The control device a cell voltage calculation unit that calculates an applied voltage per normal cell in each of the arms based on the number of bypass devices that are in a bypass state in each of the arms; a system voltage setting unit that sets a system DC voltage to be applied to each of the arms so that the applied voltage is equal to or less than a predetermined specified voltage.

8. The power conversion device according to claim 7.

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