Semiconductor package, semiconductor package manufacturing method, and interposer group

Abstract

This semiconductor package comprises: a first interposer including a first surface and a second surface; a second interposer including a third surface and a fourth surface and disposed alongside the first interposer in a first direction; a third interposer including a fifth surface and a sixth surface and positioned between the first interposer and the second interposer in the first direction; a first semiconductor element overlapping the first surface and the fifth surface in plan view; and a second semiconductor element overlapping the third surface and the fifth surface in plan view. The third interposer includes wiring electrically connecting the first semiconductor element and the second semiconductor element.

Description

[Technical Field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to a semiconductor package, a method for manufacturing the semiconductor package, and an interposer group. [Background technology]

[0002] Three-dimensional packaging technology is known, which combines multiple semiconductor elements each having an integrated circuit. In the three-dimensional packaging technology, a substrate with through electrodes is used. The substrate with through electrodes is also called an interposer. For example, Patent Documents 1 and 2 disclose a semiconductor package that includes an interposer including through electrodes or wiring, and a semiconductor element mounted on the interposer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6014907 [Patent Document 2] Patent No. 6159820 DISCLOSURE OF THE INVENTION

[0004] The more semiconductor elements included in a semiconductor package, the higher the performance of the semiconductor package. However, the larger the interposer, the more likely it is to warp or undergo other deformations.

[0005] An object of the embodiments of the present disclosure is to provide a semiconductor package and an interposer group that can effectively solve such problems.

[0006] One embodiment of the present disclosure is a semiconductor package, comprising: a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; a first semiconductor element overlapping the first surface and the fifth surface in a plan view; a second semiconductor element overlapping the third surface and the fifth surface in a plan view, The third interposer is a semiconductor package that includes wiring that electrically connects the first semiconductor element and the second semiconductor element.

[0007] In a semiconductor package according to one embodiment of the present disclosure, the first interposer may include a first cavity, and the semiconductor package may include a first internal semiconductor element located in the first cavity.

[0008] In a semiconductor package according to one embodiment of the present disclosure, the first cavity may be formed in the first surface, and the first internal semiconductor element may be electrically connected to the first semiconductor element.

[0009] In a semiconductor package according to one embodiment of the present disclosure, the second interposer may include a second cavity, and the semiconductor package may include a second internal semiconductor element located in the second cavity.

[0010] In a semiconductor package according to one embodiment of the present disclosure, the second cavity may be formed in the third surface, and the second internal semiconductor element may be electrically connected to the second semiconductor element.

[0011] The semiconductor package according to the embodiment of the present disclosure may include a third semiconductor element that overlaps the second surface, the fourth surface, and the sixth surface in a plan view.

[0012] A semiconductor package according to an embodiment of the present disclosure may include a wiring board including a substrate and a pad electrically connected to the third semiconductor element.

[0013] In the semiconductor package according to an embodiment of the present disclosure, the substrate may include an organic material.

[0014] In a semiconductor package according to one embodiment of the present disclosure, the first interposer may include a cavity formed on the second surface, and the semiconductor package may include a first internal element located in the cavity formed on the second surface and electrically connected to the third semiconductor element.

[0015] In a semiconductor package according to one embodiment of the present disclosure, the second interposer may include a cavity formed on the fourth surface, and the semiconductor package may include a second internal element located in the cavity formed on the fourth surface and electrically connected to the third semiconductor element.

[0016] In the semiconductor package according to the embodiment of the present disclosure, the first interposer may include a first through electrode.

[0017] In the semiconductor package according to the embodiment of the present disclosure, the second interposer may include a second through electrode.

[0018] In the semiconductor package according to the embodiment of the present disclosure, the third interposer may include a third through electrode.

[0019] In a semiconductor package according to one embodiment of the present disclosure, the third interposer may be located on the fifth surface and may have a redistribution layer including an insulating layer and wiring, and the insulating layer may include an organic insulating material.

[0020] In the semiconductor package according to the embodiment of the present disclosure, the organic insulating material may include polyimide, epoxy resin, or acrylic resin.

[0021] In the semiconductor package according to the embodiment of the present disclosure, the insulating layer may contain a filler made of an inorganic material.

[0022] In a semiconductor package according to one embodiment of the present disclosure, the first interposer may include a first substrate made of an inorganic material, and the surface of the first substrate of the first interposer may not be provided with an insulating layer containing an organic insulating material, and the second interposer may include a second substrate made of an inorganic material, and the surface of the second substrate of the second interposer may not be provided with an insulating layer containing an organic insulating material.

[0023] In a semiconductor package according to one embodiment of the present disclosure, the first interposer may comprise a first substrate made of an inorganic material and a redistribution layer located on the surface of the first substrate and including an insulating layer and wiring, and the second interposer may comprise a second substrate made of an inorganic material and a redistribution layer located on the surface of the second substrate and including an insulating layer and wiring.

[0024] One embodiment of the present disclosure is a method for manufacturing a semiconductor package, comprising: a placement step of placing a first interposer including a first surface and a second surface located opposite to the first surface, a second interposer including a third surface and a fourth surface located opposite to the third surface, and a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface; a first mounting step of mounting a first semiconductor element so as to overlap the first surface and the fifth surface in a plan view; a second mounting step of mounting a second semiconductor element so as to overlap the third surface and the fifth surface in a plan view, the second interposer is aligned with the first interposer in a first direction; the third interposer is located between the first interposer and the second interposer in the first direction; The third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element.

[0025] In a method for manufacturing a semiconductor package according to one embodiment of the present disclosure, the first interposer may include a first cavity, and the first mounting process may include a process of placing a first internal semiconductor element connected to the first semiconductor element in the first cavity.

[0026] In a method for manufacturing a semiconductor package according to one embodiment of the present disclosure, the second interposer may include a second cavity, and the second mounting process may include a process of placing a second internal semiconductor element connected to the second semiconductor element in the second cavity.

[0027] A method for manufacturing a semiconductor package according to one embodiment of the present disclosure may include a preparation step of preparing a third semiconductor element, and in the placement step, the first interposer, the second interposer, and the third interposer may be positioned so that the second surface, the fourth surface, and the sixth surface overlap the third semiconductor element in a planar view.

[0028] A method for manufacturing a semiconductor package according to an embodiment of the present disclosure may include a step of positioning a wiring board including a substrate and pads so that the pads of the wiring board are electrically connected to the third semiconductor element.

[0029] A method for manufacturing a semiconductor package according to one embodiment of the present disclosure may include a step of mounting a first internal element on the third semiconductor element, and the placement step may include a step of placing the first interposer so that the first internal element is positioned in a cavity formed in the second surface.

[0030] In the method for manufacturing a semiconductor package according to the embodiment of the present disclosure, the first interposer may include a first through electrode.

[0031] One embodiment of the present disclosure is an interposer group on which a first semiconductor element and a second semiconductor element are mounted, a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; the first semiconductor element is mounted so as to overlap the first surface and the fifth surface in a plan view; the second semiconductor element is mounted so as to overlap the third surface and the fifth surface in a plan view, The third interposer is an interposer group including wiring that electrically connects the first semiconductor element and the second semiconductor element.

[0032] According to the embodiments of the present disclosure, it is possible to prevent deformation such as warping from occurring in the interposer. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a plan view showing a semiconductor package according to a first embodiment. [Figure 2] 2 is a cross-sectional view of the semiconductor package taken along line AA in FIG. 1. [Figure 3] 3 is an enlarged cross-sectional view of the first interposer of FIG. 2. FIG. [Figure 4] 3 is an enlarged cross-sectional view showing the third interposer of FIG. 2. FIG. [Figure 5] 5 is an enlarged cross-sectional view showing the wiring of the third interposer of FIG. 4. FIG. [Figure 6]FIG. 10 is a diagram schematically illustrating warpage that occurs in a comparative example. [Figure 7] FIG. 3 is a diagram schematically illustrating warpage that occurs in the first embodiment. [Figure 8] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 9] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 13] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 14] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 15] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 16] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 17] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 18] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 19] FIG. 10 is a plan view showing a semiconductor package according to a second embodiment. [Figure 20] 20 is a cross-sectional view of the semiconductor package taken along line BB in FIG. 19. [Figure 21] 21 is an enlarged cross-sectional view showing the first interposer of FIG. 20. FIG. [Figure 22] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 23] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 24] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 25] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 26] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 27] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 28] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 29] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 30] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 31] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 32] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 33] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 34] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 35] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor package. [Figure 36] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 37] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 38] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 39] FIG. 2 is a cross-sectional view showing an example of a through electrode. [Figure 40] FIG. 2 is a cross-sectional view showing an example of a through electrode. [Figure 41] 1A and 1B are diagrams illustrating examples of products in which a semiconductor package is mounted. [Figure 42] FIG. 1 is a diagram showing the results of a thermal cycle test in Example 1 and Comparative Example 1. [Figure 43] FIG. 1 is a diagram showing the results of a thermal cycle test in Example 2 and Comparative Example 2. [Figure 44] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a sixth embodiment. [Figure 45]FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a sixth embodiment. [Figure 46] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a seventh embodiment. [Figure 47] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a seventh embodiment. [Figure 48A] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to an eighth embodiment. [Figure 48B] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to an eighth embodiment. [Figure 49] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to an eighth embodiment. [Figure 50] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a ninth embodiment. [Figure 51] FIG. 13 is a cross-sectional view showing an example of a semiconductor package according to a ninth embodiment. [Figure 52] FIG. 23 is a cross-sectional view showing an example of a semiconductor package according to a tenth embodiment. [Figure 53] FIG. 23 is a cross-sectional view showing an example of a semiconductor package according to a tenth embodiment. [Figure 54A] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54B] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54C] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54D] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54E] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54F] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54G] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54H] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54I] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54J] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54K] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 54L] 1A to 1C are diagrams illustrating an example of a method for forming a rewiring layer. [Figure 55A] 10A to 10C are diagrams illustrating an example of a method for connecting a redistribution layer to a first semiconductor element. [Figure 55B] 10A to 10C are diagrams illustrating an example of a method for connecting a redistribution layer to a first semiconductor element. [Figure 56] FIG. 10 is a plan view showing a laminate according to Comparative Example 3. [Figure 57] FIG. 10 is a cross-sectional view showing a laminate according to Comparative Example 3. [Figure 58] FIG. 10 is a plan view showing a laminate according to Example 3. [Figure 59] FIG. 10 is a cross-sectional view showing a laminate according to Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0034] The configuration of a semiconductor package and a manufacturing method thereof will be described in detail below with reference to the drawings. The following embodiments are merely examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. In this specification, terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the term "substrate" encompasses components that may be called sheets or films. The term "surface" refers to a surface that coincides with the planar direction of a target plate-like component when viewed holistically and comprehensively. The normal direction used with respect to a plate-like component refers to the normal direction to the component's surface. Terms such as "parallel" and "orthogonal," as well as length and angle values, that specify shape, geometric conditions, and their degrees, as used in this specification, are not limited to their strict meanings but are interpreted to encompass a range within which similar functions can be expected.

[0035] In this specification, when multiple upper limit candidates and multiple lower limit candidate values ​​are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit candidate with any one lower limit candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0036] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0037] (First embodiment) 1 is a plan view showing a semiconductor package 1 according to a first embodiment. The semiconductor package 1 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the semiconductor package 1. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the semiconductor package 1. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0038] The semiconductor package 1 includes a first interposer 10, a second interposer 20, a third interposer 30, a first semiconductor element 40, a second semiconductor element 45, and a third semiconductor element 50. As shown in Fig. 1, the first interposer 10, the second interposer 20, and the third interposer 30 are aligned in a first direction D1. The third interposer 30 is located between the first interposer 10 and the second interposer 20 in the first direction D1.

[0039] As shown in FIG. 1 , the first semiconductor element 40 is mounted on the first interposer 10 and the third interposer 30. Specifically, the first semiconductor element 40 is electrically connected to both the first interposer 10 and the third interposer 30. For example, the first interposer 10 includes a through electrode 14 electrically connected to the first semiconductor element 40. The third interposer 30 includes wiring 35 electrically connected to the first semiconductor element 40. The third interposer 30 may also include a through electrode 34 electrically connected to the first semiconductor element 40. In the following description, the through electrode 14 of the first interposer 10 will also be referred to as the first through electrode 14, and the through electrode 34 of the third interposer 30 will also be referred to as the third through electrode 34.

[0040] As shown in FIG. 1 , the second semiconductor element 45 is mounted on the second interposer 20 and the third interposer 30. Specifically, the second semiconductor element 45 is electrically connected to both the second interposer 20 and the third interposer 30. For example, the second interposer 20 includes a through electrode 24 electrically connected to the second semiconductor element 45. In the following description, the through electrode 24 of the second interposer 20 will also be referred to as the second through electrode 24. The third interposer 30 includes wiring 35 electrically connected to the second semiconductor element 45. The wiring 35 electrically connects the first semiconductor element 40 and the second semiconductor element 45. The third interposer 30 may also include a third through electrode 34 electrically connected to the second semiconductor element 45.

[0041] A group of multiple interposers on which the first semiconductor element 40 and the second semiconductor element 45 are mounted is also referred to as an interposer group. In this embodiment, the first interposer 10, the second interposer 20, and the third interposer 30 constitute the interposer group.

[0042] The distance S1 between the first interposer 10 and the third interposer 30 in the first direction D1 is, for example, 0.03 mm or more, or may be 0.05 mm or more, or may be 0.1 mm or more. The distance S1 is, for example, 3.0 mm or less, or may be 1.0 mm or less, or may be 0.5 mm or less.

[0043] The range of the spacing S2 between the second interposer 20 and the third interposer 30 in the first direction D1 can be the same as the range of the spacing S1 described above.

[0044] 2 is a cross-sectional view of the semiconductor package 1 of FIG. 1 taken along line AA. The first interposer 10 includes a first surface 11 and a second surface 12. The second surface 12 is located on the opposite side of the first surface 11. The second interposer 20 includes a third surface 21 and a fourth surface 22. The fourth surface 22 is located on the opposite side of the third surface 21. The third interposer 30 includes a fifth surface 31 and a sixth surface 32. The sixth surface 32 is located on the opposite side of the fifth surface 31. The first surface 11, the third surface 21, and the fifth surface 31 are located on the same side. The second surface 12, the fourth surface 22, and the sixth surface 32 are located on the same side.

[0045] The first semiconductor element 40 is mounted on the first surface 11 and the fifth surface 31. Therefore, the first semiconductor element 40 overlaps the first surface 11 and the fifth surface 31 in a plan view. The second semiconductor element 45 is mounted on the third surface 21 and the fifth surface 31. Therefore, the second semiconductor element 45 overlaps the third surface 21 and the fifth surface 31 in a plan view. A plan view means a view along the normal direction of the surface of the component.

[0046] 1 and 2, the semiconductor package 1 may include a third semiconductor element 50. The first interposer 10, the second interposer 20, and the third interposer 30 may be mounted on the third semiconductor element 50. The third semiconductor element 50 faces the second surface 12, the fourth surface 22, and the sixth surface 32. Therefore, the third semiconductor element 50 overlaps the second surface 12, the fourth surface 22, and the sixth surface 32 in a plan view.

[0047] 1 and 2, the semiconductor package 1 may include a wiring board 80. The wiring board 80 may be electrically connected to the third semiconductor element 50.

[0048] Each component of the semiconductor package 1 will now be described in detail.

[0049] 3 is an enlarged cross-sectional view of the first interposer 10 of FIG. 2. The first interposer 10 includes a substrate 101 and a first through electrode 14 located in a through hole penetrating the substrate 101. The first through electrode 14 is conductive. The first interposer 10 may include a pad 16 located on the first surface 11. The first interposer 10 may include a pad 17 located on the second surface 12. Although not shown, the first interposer 10 may include wiring and an insulating layer located on the first surface 11, and may also include wiring and an insulating layer located on the second surface 12. In this case, the first surface 11 and the second surface 12 of the first interposer 10 may be formed by the surface of an insulating layer. Resins such as polyimide, epoxy resins, and acrylic resins can be used as materials for forming the insulating layer. The first interposer 10 may not include an insulating layer located on the first surface 11 or the second surface 12. For example, the first interposer 10 may not include an insulating layer containing polyimide located on the first surface 11 or the second surface 12. In other words, an insulating layer containing an organic insulating material may not be provided on the surface of the substrate 101. This can prevent warping of the substrate 101 due to internal stress of the insulating layer. The substrate 101 of the first interposer 10 is also referred to as the first substrate 101.

[0050] The substrate 101 may be made of an inorganic material. For example, the substrate 101 may be a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, or a laminate of these substrates. The substrate 101 may partially include a substrate made of a conductive material, such as an aluminum substrate or a stainless steel substrate. The thickness of the substrate 101 is, for example, 0.1 mm or more, or may be 0.2 mm or more, or may be 0.5 mm or more. The thickness of the substrate 101 is, for example, 2.0 mm or less, or may be 1.5 mm or less, or may be 1.0 mm or less.

[0051] The first through electrode 14 extends from one surface to the other surface of the substrate 101 in a through hole of the substrate 101. The first through electrode 14 may be located over the entire area of ​​the through hole of the substrate 101. That is, the first through electrode 14 may be a so-called filled via that is filled in the through hole of the substrate 101. As will be described later, the first through electrode 14 does not have to fill the through hole of the substrate 101.

[0052] The first through electrode 14 may include multiple layers. For example, the first through electrode 14 may include a first layer located on the side surface of the through hole in the substrate 101 and a second layer located on the first layer. The second layer may extend to the center of the through hole in the substrate 101 in a plan view.

[0053] The first layer is formed on the side surface of the through-hole by a physical film formation method such as sputtering or vapor deposition. The thickness of the first layer is, for example, 0.05 μm or more. The thickness of the first layer is 1.0 μm or less. Note that other layers may be provided between the first layer and the side surface of the through-hole. The material constituting the first layer may be metal such as titanium, chromium, nickel, copper, or an alloy using these, or a laminate of these.

[0054] The second layer may contain copper as a main component. For example, the second layer may contain 80 mass % or more of copper. The second layer may also contain a metal such as gold, silver, platinum, rhodium, tin, aluminum, nickel, or chromium, or an alloy using any of these metals. The second layer is formed on the first layer by, for example, electrolytic plating.

[0055] The pads 16 and 17 include a conductive layer. As shown in FIG. 3, the pad 16 may be located on the first through electrode 14 on the first surface 11 side. The pad 17 may be located on the first through electrode 14 on the second surface 12 side. The materials constituting the pads 16 and 17 may be the same as those listed for the first through electrode 14. The thickness of the pads 16 and 17 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The thickness of the pads 16 and 17 is, for example, 10.0 μm or less, and may be 5.0 μm or less.

[0056] 3, a pillar 161 may be formed on the pad 16. The thickness of the pillar 161 is greater than the thickness of the pad 16. The materials exemplified for the first through electrode 14 can be used as the material for forming the pillar 161.

[0057] The second interposer 20 includes a substrate 201 and a second through electrode 24 located in a through hole penetrating the substrate 201. The second interposer 20 may include a pad 26 located on the third surface 21. The second interposer 20 may include a pad 27 located on the fourth surface 22. A pillar 261 may be formed on the pad 26. Although not shown, the second interposer 20 may include wiring and an insulating layer located on the third surface 21, or may include wiring and an insulating layer located on the fourth surface 22. In this case, the third surface 21 and the fourth surface 22 of the second interposer 20 may be formed by the surface of an insulating layer. The insulating layer may be made of a resin such as polyimide, epoxy resin, or acrylic resin. The second interposer 20 may not include an insulating layer located on the third surface 21 or the fourth surface 22. For example, the second interposer 20 may not include an insulating layer located on the third surface 21 or the fourth surface 22 and containing polyimide. In other words, an insulating layer containing an organic insulating material may not be provided on the surface of the substrate 201. This can prevent warping of the substrate 201 due to internal stress of the insulating layer. The substrate 201 of the second interposer 20 is also referred to as the second substrate 201.

[0058] The configuration of the substrate 201, second through electrode 24, pad 26, pillar 261, and pad 27 of the second interposer 20 can be the same as the configuration of the substrate 101, first through electrode 14, pad 16, pillar 161, and pad 17 of the first interposer 10 described above.

[0059] FIG. 4 is an enlarged cross-sectional view of the third interposer 30 of FIG. 2. The third interposer 30 includes a substrate 301, an insulating layer 302 located on the substrate 301, and wiring 35 in contact with the insulating layer 302. The insulating layer 302 may form the fifth surface 31. The insulating layer 302 and the wiring 35 may form a so-called rewiring layer. Although not shown, an insulating layer may also be provided on the substrate 301 on the sixth surface 32 side. In this case, the insulating layer may form the sixth surface 32. The above-mentioned third through electrode 34 penetrates the substrate 301. The substrate 301 of the third interposer 30 is also referred to as the third substrate 301.

[0060] 4, the third interposer 30 may include pads 36 located on a fifth surface 31. The third interposer 30 may include pads 37 located on a sixth surface 32.

[0061] The substrate 301, the third through electrode 34, the pads 36, and the pads 37 may be configured in the same manner as the substrate 101, the first through electrode 14, the pads 16, and the pads 17 of the first interposer 10 described above. Resins such as polyimide, epoxy resin, and acrylic resin can be used as materials for the insulating layer 302. The insulating layer 302 may contain a filler dispersed in a resin such as an epoxy resin. The filler may be made of an inorganic material such as silica or alumina. The filler may be made of silicon oxide or silicon nitride. The silicon oxide or silicon nitride may contain fluorine or nitrogen. Resins such as polyimide, epoxy resin, and acrylic resin can also be used as materials for the insulating layer on the sixth surface 32 side and the insulating layers of the first interposer 10 and the second interposer 20. Like the insulating layer 302, these insulating layers may contain a filler dispersed in a resin such as an epoxy resin. The filler may be made of, for example, silica, alumina, or the like. The filler may be made of silicon oxide or silicon nitride. The silicon oxide or silicon nitride may contain fluorine or nitrogen.

[0062] As shown in FIG. 4 , the wiring 35 may include a first end connected to the first pad 36 and a second end connected to the second pad 36. FIG. 5 is a cross-sectional view showing an example of the wiring 35. The wiring 35 may include a first portion 351 extending parallel to the in-plane direction of the fifth surface 31 and a second portion 352 extending in a direction including a component of the third direction D3. The second portion 352 may extend parallel to the third direction D3. The second portion 352 may be connected to the pad 36. In this case, the second portion 352 constitutes the first end and the second end of the wiring 35.

[0063] The thickness of the first portion 351 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The thickness of the pads 16, 17 is, for example, 20.0 μm or less, and may be 5.0 μm or less. The materials exemplified for the first through electrode 14 can be used as materials for forming the wiring 35.

[0064] The width of the first portion 351 is, for example, 0.1 μm or more, and may be 0.5 μm or more. The width of the first portion 351 is, for example, 20.0 μm or less, and may be 10.0 μm or less, or 5.0 μm or less. The width of the first portion 351 is the dimension of the first portion 351 in a direction perpendicular to the direction in which the first portion 351 extends in a plan view.

[0065] The third interposer 30 includes the insulating layer 302 and the rewiring layer including the wiring 35, which allows for greater freedom in arranging the pads 36.

[0066] When an insulating layer containing an organic insulating material such as resin is provided on a substrate made of an inorganic material such as glass or silicon, warping occurs in the substrate due to stress inside the insulating layer. An insulating layer 302 is located on the fifth surface 31 of the third interposer 30, but an insulating layer does not have to be located on the first surface 11 of the first interposer 10 or the third surface 21 of the second interposer 20. This reduces the total amount of warping that occurs in the interposer group compared to when an insulating layer is provided over the entire area of ​​the interposer group including the first interposer 10, the second interposer 20, and the third interposer 30.

[0067] The first semiconductor element 40 includes a transistor formed of a semiconductor such as silicon. The first semiconductor element 40 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The first semiconductor element 40 may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, or a memory are divided according to function. The first semiconductor element 40 may include multiple stacked substrates.

[0068] The first semiconductor element 40 may include a first pad 41 electrically connected to the first interposer 10. The first pad 41 may be electrically connected to the first through electrode 14 via, for example, a pillar 161 and a pad 16. A bump may be provided between the first interposer 10 and the first pad 41.

[0069] The first semiconductor element 40 may include a second pad 42 electrically connected to the third interposer 30. The second pad 42 may be electrically connected to the wiring 35 via a pad 37, for example. A bump may be provided between the third interposer 30 and the second pad 42.

[0070] The second semiconductor element 45 includes a transistor formed of a semiconductor such as silicon. The second semiconductor element 45 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, etc. The second semiconductor element 45 may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, etc. are divided according to function. The second semiconductor element 45 may include multiple stacked substrates.

[0071] The second semiconductor element 45 may include a fourth pad 46 electrically connected to the second interposer 20. The fourth pad 46 may be electrically connected to the second through electrode 24 via, for example, a pillar 261 and a pad 26. A bump may be provided between the second interposer 20 and the fourth pad 46.

[0072] The second semiconductor element 45 may include a fifth pad 47 electrically connected to the third interposer 30. The fifth pad 47 may be electrically connected to the wiring 35 via the pad 37, for example. A bump may be provided between the third interposer 30 and the fifth pad 47.

[0073] The third semiconductor element 50 includes a transistor formed of a semiconductor such as silicon. The third semiconductor element 50 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The third semiconductor element 50 may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, or a memory are divided according to function. As shown in FIG. 2 , the third semiconductor element 50 may include a substrate 56 and an insulating layer 57 located on the substrate 56. The third semiconductor element 50 may include an electrode 58 penetrating the substrate 56. Although not shown, the third semiconductor element 50 may also include wiring located in the insulating layer 57, an electrode penetrating the insulating layer 57, and the like.

[0074] The third semiconductor element 50 may include an eleventh pad 51 electrically connected to the first interposer 10. A pillar may be formed on the eleventh pad 51, and a bump may be formed on the pillar. The eleventh pad 51 may be electrically connected to the first through electrode 14 via, for example, the pillar, the bump, and the pad 17.

[0075] The third semiconductor element 50 may include a twelfth pad 52 electrically connected to the second interposer 20. A pillar may be formed on the twelfth pad 52, and a bump may be formed on the pillar. The twelfth pad 52 may be electrically connected to the second through electrode 24 via, for example, the pillar, the bump, and the pad 27.

[0076] The third semiconductor element 50 may include a thirteenth pad 53 electrically connected to the third interposer 30. A pillar may be formed on the thirteenth pad 53, and a bump may be formed on the pillar. The thirteenth pad 53 may be electrically connected to the pad 37 via, for example, the pillar and the bump.

[0077] The wiring board 80 includes a substrate 81 and a pad 82 located on the substrate 81. The pad 82 may be electrically connected to the third semiconductor element 50.

[0078] The substrate 81 may include a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, or the like. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The resin substrate may include a filler dispersed in a resin such as an epoxy-based resin. The filler may be made of, for example, silica, alumina, or the like. The resin substrate may include multiple laminated layers of organic materials. The thickness of the substrate 81 is, for example, 100 μm or more, or may be 200 μm or more, or may be 500 μm or more. The thickness of the substrate 81 is, for example, 2 mm or less, or may be 1.5 mm or less, or may be 1 mm or less.

[0079] The wiring substrate 80 may include a pad 82 electrically connected to the third semiconductor element 50. A pillar or a bump may be formed on the pad 82. When a pillar is formed on the pad 82, a bump may be formed on the pillar. The pad 82 may be electrically connected to the third semiconductor element 50 via, for example, a pillar and a bump.

[0080] The semiconductor package 1 may include an underfill 91 located between the first interposer 10, the second interposer 20, or the third interposer 30 and the third semiconductor element 50. The underfill 91 may contain a thermosetting resin such as an epoxy resin. The underfill 91 can function as an adhesive that bonds the first interposer 10, the second interposer 20, or the third interposer 30 to the third semiconductor element 50.

[0081] The semiconductor package 1 may include a mold 98 that covers the first interposer 10, the second interposer 20, and the third interposer 30. The mold 98 may be located between the first interposer 10 and the third interposer 30, and between the second interposer 20 and the third interposer 30. The mold 98 may contain a thermosetting resin such as an epoxy resin.

[0082] The semiconductor package 1 may include an underfill 92 located between the first semiconductor element 40 or the second semiconductor element 45 and the first interposer 10, the second interposer 20, or the third interposer 30. The underfill 92 may contain a thermosetting resin such as an epoxy resin. The underfill 92 can function as an adhesive that bonds the first semiconductor element 40 or the second semiconductor element 45 to the first interposer 10, the second interposer 20, or the third interposer 30.

[0083] The semiconductor package 1 may include an underfill 93 located between the third semiconductor element 50 and the wiring board 80. The underfill 93 may contain a thermosetting resin such as an epoxy resin. The underfill 93 can function as an adhesive that bonds the third semiconductor element 50 and the wiring board 80 together.

[0084] Next, the operation of the semiconductor package 1 according to this embodiment will be described.

[0085] When the temperature of the semiconductor package 1 changes, the components of the semiconductor package 1 expand or contract. For example, when the temperature of the semiconductor package 1 increases, the components of the semiconductor package 1 expand according to their thermal expansion coefficients. When the temperature of the semiconductor package 1 decreases, the components of the semiconductor package 1 contract according to their thermal expansion coefficients. In general, the thermal expansion coefficient of inorganic materials is smaller than that of organic materials. For example, the thermal expansion coefficient of the inorganic material constituting the substrates 101, 201, and 301 is smaller than that of the organic material constituting the insulating layer. In this case, when the temperature of the semiconductor package 1 changes, warping occurs in the substrates 101, 201, and 301 of the interposers 10, 20, and 30 due to the difference in the thermal expansion coefficients of the components.

[0086] 6 is a diagram schematically illustrating warpage that occurs in a semiconductor package 100 according to a comparative example. The semiconductor package 100 includes one interposer 104, and a first semiconductor element and a second semiconductor element (not shown) that are mounted on the interposer 104. The interposer 104 includes wiring 105 that electrically connects the first semiconductor element and the second semiconductor element.

[0087] 6, warping occurs in the interposer 104 in response to temperature changes in the semiconductor package 100. In this case, stress caused by the warping of one interposer 104 is applied to the wiring 105.

[0088] 7 is a diagram schematically illustrating warpage that occurs in the semiconductor package 1 of this embodiment. As described above, the semiconductor package 1 includes the first interposer 10, the second interposer 20, and the third interposer 30. The semiconductor package 1 also includes a first semiconductor element 40 (not shown) mounted on the first interposer 10 and the third interposer 30, and a second semiconductor element 45 (not shown) mounted on the second interposer 20 and the third interposer 30.

[0089] In this embodiment, the dimensions of the first interposer 10, the second interposer 20, and the third interposer 30 are smaller than the dimensions of the interposer 104 in the comparative embodiment. Therefore, the curvature of the warp occurring in the first interposer 10, the second interposer 20, and the third interposer 30 can be smaller than the curvature of the warp occurring in the interposer 104. This reduces the stress generated due to the warp of the third interposer 30. Therefore, the stress applied to the wiring 35 is reduced, and damage to the wiring 35 can be suppressed. This improves the reliability of the semiconductor package 1. An example of damage to the wiring 35 is, for example, a break occurring at the boundary between the first portion 351 and the second portion 352 in FIG. 5.

[0090] Next, a method for manufacturing the semiconductor package 1 will be described.

[0091] 8, a preparation step is performed to prepare a third semiconductor element 50. The substrate 56 may be, for example, a silicon wafer. The electrode 58 may include an end portion that is not exposed on the surface of the substrate 56.

[0092] Next, an arrangement process is performed to arrange the first interposer 10, the second interposer 20, and the third interposer 30 on the third semiconductor element 50. For example, as shown in FIG. 9, the first interposer 10 and the second interposer 20 are arranged on the third semiconductor element 50. Then, as shown in FIG. 10, the third interposer 30 is arranged between the first interposer 10 and the second interposer 20 on the third semiconductor element 50. The arrangement process is performed so that the second surface 12, the fourth surface 22, and the sixth surface 32 overlap the third semiconductor element 50 in a plan view.

[0093] In the placement process, multiple sets may be placed on the third semiconductor element 50. One set includes, for example, one first interposer 10, one second interposer 20, and one third interposer 30.

[0094] Subsequently, as shown in FIG. 11, underfill 91 may be filled between the first interposer 10, the second interposer 20, and the third interposer 30 and the third semiconductor element 50.

[0095] 12, a mold 98 may be formed to cover the first interposer 10, the second interposer 20, and the third interposer 30. At this time, the first interposer 10, the second interposer 20, and the third interposer 30 may not be exposed on the surface of the mold 98. In this case, as shown in FIG. 13, a step of polishing the mold 98 may be performed until components of the interposers 10, 20, and 30, such as the pillars 161, 261, and pads 36, are exposed on the surface of the mold 98.

[0096] 14, a first mounting process is performed in which a first semiconductor element 40 is mounted on the first interposer 10 and the third interposer 30. The first mounting process is performed so that the first semiconductor element 40 overlaps the first surface 11 and the fifth surface 31 in a plan view. In addition, a second mounting process is performed in which a second semiconductor element 45 is mounted on the second interposer 20 and the third interposer 30. The second mounting process is performed so that the second semiconductor element 45 overlaps the third surface 21 and the fifth surface 31 in a plan view.

[0097] Subsequently, as shown in FIG. 15, underfill 92 may be filled between the first semiconductor element 40, the second semiconductor element 45 and the first interposer 10, the second interposer 20 and the third interposer 30.

[0098] 16, a step of polishing the substrate 56 may be carried out until the electrodes 58 are exposed on the surface of the substrate 56. Thereafter, pads may be formed on the electrodes 58.

[0099] When the substrate 56 of the third semiconductor element 50 is a silicon wafer, a dicing process may be performed to cut the substrate 56 into multiple pieces, as shown in Fig. 17. In the dicing process, for example, the substrate 56 is cut so that one of the above-described sets is located on one piece of the substrate 56. A structure including one piece of the substrate 56 and one of the above-described sets is also referred to as a chip 2.

[0100] 18, a wiring board 80 is prepared. Then, a chip 2 is mounted on the wiring board 80. In this manner, the semiconductor package 1 is manufactured.

[0101] According to this embodiment, one chip 2 includes multiple interposers 10, 20, and 30 that are spaced apart from one another. This reduces the curvature of the warp that occurs in the interposer compared to the comparative embodiment, where one chip includes only one interposer. This prevents defects such as breaks in the wiring that electrically connects two semiconductor elements included in one chip 2.

[0102] The above-described embodiment can be modified in various ways. Hereinafter, other embodiments will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for the corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in other embodiments, the descriptions may be omitted.

[0103] (Second embodiment) Fig. 19 is a plan view showing a semiconductor package 1 according to the second embodiment, and Fig. 20 is a cross-sectional view of the semiconductor package 1 taken along line BB in Fig. 19.

[0104] 19 and 20, the first interposer 10 may include a first cavity 13 located on the first surface 11. FIG. 21 is an enlarged cross-sectional view of the first interposer 10 of FIG.

[0105] The first cavity 13 is a recess formed in the first surface 11. In this case, the semiconductor package 1 may include a semiconductor element 60 located in the first cavity 13. The semiconductor element 60 is electrically connected to the first semiconductor element 40. For example, the first semiconductor element 40 may include a third pad 43 electrically connected to the semiconductor element 60. In the following description, the semiconductor element 60 located in the first cavity 13 is also referred to as a first internal semiconductor element 60.

[0106] The first internal semiconductor element 60 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, etc. When the first semiconductor element 40 includes a processing circuit such as a CPU, a GPU, or an FPGA, the first internal semiconductor element 60 may also include a memory used by the processing circuit of the first semiconductor element 40. The memory is, for example, an SRAM, a DRAM, etc.

[0107] 20 and 21 , the first cavity 13 may penetrate from the first surface 11 to the second surface 12. In this case, the semiconductor package 1 may include an element 70 located in the first cavity 13. The element 70 is electrically connected to the third semiconductor element 50. For example, the third semiconductor element 50 may include a fourteenth pad 54 electrically connected to the element 70. In the following description, the element 70 located in the cavity will also be referred to as the first internal element 70.

[0108] The first internal element 70 may be an active element or a passive element. Examples of active elements include a CPU, a GPU, an FPGA, a sensor, and a memory. Examples of passive elements include a capacitor, a resistor, and an inductor. When the third semiconductor element 50 includes a processing circuit such as a CPU, a GPU, or an FPGA, the first internal element 70 may include a passive element electrically connected to the processing circuit of the third semiconductor element 50.

[0109] 19 and 20 , the second interposer 20 may include a second cavity 23 located on the third surface 21. The second cavity 23 is a recess formed on the third surface 21, similar to the first cavity 13. In this case, the semiconductor package 1 may include a second internal semiconductor element 65 located in the second cavity 23. The second internal semiconductor element 65 is electrically connected to the second semiconductor element 45. For example, the second semiconductor element 45 may include a sixth pad 48 electrically connected to the second internal semiconductor element 65.

[0110] 20 , the second cavity 23 may penetrate from the third surface 21 to the fourth surface 22. In this case, the semiconductor package 1 may include a second internal element 75 located in the second cavity 23. The second internal element 75 is electrically connected to the third semiconductor element 50. For example, the third semiconductor element 50 may include a fifteenth pad 55 electrically connected to the second internal element 75.

[0111] The second internal semiconductor element 65 and the second internal element 75 may have the same configuration as the first internal semiconductor element 60 and the first internal element 70 described above.

[0112] Next, a method for manufacturing the semiconductor package 1 will be described.

[0113] 22, a preparation step is performed to prepare a third semiconductor element 50. The substrate 56 may be, for example, a silicon wafer. The electrode 58 may include an end portion that is not exposed on the surface of the substrate 56.

[0114] 23, the first internal element 70 and the second internal element 75 are placed on the third semiconductor element 50. Then, as shown in FIG. 24, an underfill 94 may be filled between the first internal element 70 and the second internal element 75 and the third semiconductor element 50.

[0115] Next, an arrangement step is performed to arrange the first interposer 10, the second interposer 20, and the third interposer 30 on the third semiconductor element 50. For example, as shown in FIG. 25, the first interposer 10 and the second interposer 20 are arranged on the third semiconductor element 50. At this time, the arrangement step is performed so that the first internal element 70 is located in the first cavity 13 of the first interposer 10, and the second internal element 75 is located in the second cavity 23 of the second interposer 20. Next, as shown in FIG. 26, the third interposer 30 is arranged between the first interposer 10 and the second interposer 20 on the third semiconductor element 50.

[0116] In the placement process, multiple sets may be placed on the third semiconductor element 50. One set may include one first interposer 10, one second interposer 20, and one third interposer 30.

[0117] Subsequently, as shown in FIG. 27, underfill 91 may be filled between the first interposer 10, the second interposer 20, and the third interposer 30 and the third semiconductor element 50.

[0118] Next, as shown in FIG. 28, a mold 98 may be formed to cover the first interposer 10, the second interposer 20, and the third interposer 30. At this time, the first interposer 10, the second interposer 20, and the third interposer 30 may not be exposed on the surface of the mold 98. In this case, as shown in FIG. 29, a step of polishing the mold 98 may be performed until components of the interposers 10, 20, and 30, such as the pillars 161, 261, and pads 36, are exposed on the surface of the mold 98. Next, as shown in FIG. 30, a step of removing the mold 98 located in the first cavity 13 and the second cavity 23 is performed.

[0119] 31, a first mounting process is performed in which a first semiconductor element 40 is mounted on the first interposer 10 and the third interposer 30. The first mounting process is performed so that the first semiconductor element 40 overlaps the first surface 11 and the fifth surface 31 in a plan view. In addition, a second mounting process is performed in which a second semiconductor element 45 is mounted on the second interposer 20 and the third interposer 30. The second mounting process is performed so that the second semiconductor element 45 overlaps the third surface 21 and the fifth surface 31 in a plan view.

[0120] 31 , the first internal semiconductor element 60 may be mounted in advance on the first semiconductor element 40. In this case, the first mounting step is performed so that the first internal semiconductor element 60 is placed in the first cavity 13.

[0121] Similarly, the second internal semiconductor element 65 may be mounted in advance on the second semiconductor element 45. In this case, the second mounting step is performed so that the second internal semiconductor element 65 is placed in the second cavity 23.

[0122] Subsequently, as shown in FIG. 32, underfill 92 may be filled between the first semiconductor element 40, the second semiconductor element 45 and the first interposer 10, the second interposer 20 and the third interposer 30.

[0123] 33, a step of polishing the substrate 56 may be carried out until the electrodes 58 are exposed on the surface of the substrate 56. Thereafter, pads may be formed on the electrodes 58.

[0124] When the substrate 56 of the third semiconductor element 50 is a silicon wafer, a dicing step may be performed to cut the substrate 56 into a plurality of pieces, as shown in Fig. 34. This allows a plurality of chips 2 to be obtained.

[0125] 35, a wiring board 80 is prepared. Then, a chip 2 is mounted on the wiring board 80. In this manner, the semiconductor package 1 is manufactured.

[0126] According to this embodiment, by providing a first cavity 13 in the first interposer 10, the first internal semiconductor element 60 can be placed in the first cavity 13. This allows the distance between the first semiconductor element 40 and the first internal semiconductor element 60 to be reduced on one surface of the first semiconductor element 40. A heat sink (not shown) or the like may be placed on the other surface of the first semiconductor element 40. Similarly, according to this embodiment, the second internal semiconductor element 65 can be placed in the second cavity 23. This allows the distance between the third semiconductor element 50 and the second internal semiconductor element 65 to be reduced on one surface of the third semiconductor element 50.

[0127] According to this embodiment, by providing the first cavity 13 in the first interposer 10, the first internal element 70 can be placed in the first cavity 13. This makes it possible to reduce the distance between the third semiconductor element 50 and the first internal element 70 on one side of the third semiconductor element 50. Similarly, according to this embodiment, the second internal element 75 can be placed in the second cavity 23. This makes it possible to reduce the distance between the third semiconductor element 50 and the second internal element 75 on one side of the third semiconductor element 50.

[0128] (Third embodiment) Fig. 36 is a cross-sectional view showing a semiconductor package 1 according to a third embodiment. As shown in Fig. 36, the first cavity 13 of the first interposer 10 does not have to penetrate from the first surface 11 to the second surface 12. In this case, a cavity 18 that is not connected to the first cavity 13 may be formed on the second surface 12. The first internal element 70 may be located in the cavity 18.

[0129] Similarly, the second cavity 23 of the second interposer 20 may not penetrate from the third surface 21 to the fourth surface 22. In this case, a cavity 28 that is not connected to the second cavity 23 may be formed in the fourth surface 22. The second internal element 75 may be located in the cavity 28.

[0130] (Fourth embodiment) 37 is a cross-sectional view showing a semiconductor package 1 according to a fourth embodiment. As shown in FIG. 37, a cavity 38 may be formed in the sixth surface 32 of the third interposer 30. In this case, the semiconductor package 1 may include a third internal element 78 located in the cavity 38. The third internal element 78 may be electrically connected to the third semiconductor element 50. For example, the third semiconductor element 50 may include a pad electrically connected to the third internal element 78.

[0131] The third internal element 78 may have the same configuration as the first internal element 70 described above.

[0132] Although not shown, a cavity may be formed on the fifth surface 31 of the third interposer 30. In this case, the semiconductor package 1 may include a third internal semiconductor element located in the cavity on the fifth surface 31. The third internal semiconductor element may be electrically connected to the first semiconductor element 40 or the second semiconductor element 45.

[0133] (Fifth embodiment) Fig. 38 is a cross-sectional view showing a semiconductor package 1 according to a fifth embodiment. As shown in Fig. 38, the first cavity 13 of the first interposer 10 does not have to penetrate from the first surface 11 to the second surface 12. The second surface 12 does not have to have a cavity. In this case, the semiconductor package 1 does not have to include a first internal element.

[0134] Similarly, the second cavity 23 of the second interposer 20 does not have to penetrate from the third surface 21 to the fourth surface 22. No cavity may be formed in the fourth surface 22. In this case, the semiconductor package 1 does not have to include a second internal element.

[0135] (Other forms) In the above-described embodiment, an example has been shown in which the first through electrode 14 is located throughout the entire through hole of the substrate 101. That is, an example has been shown in which the first through electrode 14 is a filled via. However, as long as it extends from one surface of the substrate 101 to the other surface, the structure of the first through electrode 14 is arbitrary. For example, as shown in FIGS. 39 and 40, the first through electrode 14 does not have to fill the center of the through hole. In this case, the inside of the first through electrode 14 may be filled with a material different from the material of the first through electrode 14. That is, the first interposer 10 may include a portion located inside the first through electrode 14 and filled with an inorganic material, an organic material, or a conductive material. The inorganic material is, for example, an inorganic oxide such as silica or alumina. The inside of the first through electrode 14 may be filled with an organic material and an inorganic filler. The conductive material is, for example, a metal such as copper, gold, or nickel. The inside of the first through electrode 14 may be filled with a paste-like material containing particles of a conductive material and a binder.

[0136] 39 , the first through electrode 14 may include a conductive layer covering the through hole along the first surface 11. In this case, a pad 16 or a pillar may be located on the conductive layer covering the through hole. Although not shown, the first through electrode 14 may include a conductive layer covering the through hole along the second surface 12. This conductive layer may form wiring located on the second surface 12. A pad 17 or a pillar may be located on the conductive layer covering the through hole along the second surface 12. 40 , the first through electrode 14 may not include a conductive layer covering the through hole along the first surface 11 or the second surface 12. In this case, the first through electrode 14 may be connected to a pad 16 located on the first surface 11 and a pad 17 located on the second surface 12.

[0137] Although not shown, the second through electrode 24 may not be filled to the center of the through hole, similar to the first through electrode 14. In this case, the second through electrode 24 may include a conductive layer covering the through hole along the third surface 21, similar to the first through electrode 14 in FIG. 39 . In this case, a pad 26 or a pillar may be located on the conductive layer covering the through hole. Although not shown, the second through electrode 24 may include a conductive layer covering the through hole along the fourth surface 22. A pad 27 or a pillar may be located on the conductive layer covering the through hole along the fourth surface 22. Alternatively, the second through electrode 24 may not include a conductive layer covering the through hole along the third surface 21 or the fourth surface 22, similar to the first through electrode 14 in FIG.

[0138] (Examples of products equipped with semiconductor packages) 41 is a diagram showing an example of a product equipped with the semiconductor package 1. The semiconductor package 1 can be used in a variety of products. For example, the semiconductor package 1 is equipped in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0139] (Sixth embodiment) 44 and 45 are cross-sectional views showing a semiconductor package 1 according to a sixth embodiment. The first internal semiconductor element 60 located in the first cavity 13 may be electrically connected to the third semiconductor element 50. As shown in FIG. 44, the first internal semiconductor element 60 may include a plurality of laminated insulating layers and conductive layers. As shown in FIG. 45, the first internal semiconductor element 60 may be a semiconductor package sealed with a molding resin or the like.

[0140] Similar to the first internal semiconductor element 60, the second internal semiconductor element 65 located in the second cavity 23 may be electrically connected to the third semiconductor element 50. As shown in Fig. 44, the second internal semiconductor element 65 may include a plurality of laminated insulating layers and conductive layers. As shown in Fig. 45, the second internal semiconductor element 65 may be a semiconductor package sealed with a molding resin or the like.

[0141] (Seventh embodiment) 46 and 47 are cross-sectional views showing a semiconductor package 1 according to the seventh embodiment. The third semiconductor element 50 may include a plurality of semiconductor elements 50A and 50B. That is, the third semiconductor element 50 may be divided into a plurality of semiconductor elements 50A and 50B.

[0142] The positions at which the third semiconductor element 50 is divided are not particularly limited. For example, as shown in FIG. 46, a semiconductor element 50A may be electrically connected to a first interposer 10 and a third interposer 30, and a semiconductor element 50B may be electrically connected to a second interposer 20 and a third interposer 30. 47, a semiconductor element 50A may be electrically connected to the first interposer 10 and the third interposer 30, and a semiconductor element 50B may be electrically connected to the second interposer 20. The semiconductor element 50B may not be electrically connected to the third interposer 30. For example, the semiconductor element 50B may not overlap the third interposer 30 in a plan view.

[0143] (Eighth embodiment) 48A, 48B, and 49 are cross-sectional views showing a semiconductor package 1 according to an eighth embodiment. The semiconductor package 1 may include a redistribution layer 85 including a conductive layer 86 and an insulating layer 87. The redistribution layer 85 may face the second surface 12 of the first interposer 10, the fourth surface 22 of the second interposer 20, and the sixth surface 32 of the third interposer 30. The conductive layer 86 of the redistribution layer 85 may be electrically connected to the first interposer 10, the second interposer 20, and the third interposer 30.

[0144] Metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys using these metals, can be used as materials for forming the conductive layer 86. Organic insulating materials such as polyimide, epoxy resin, and acrylic resin can be used as materials for forming the insulating layer 87.

[0145] The redistribution layer 85 may be provided in place of the third semiconductor element 50. For example, the first interposer 10, the second interposer 20, and the third interposer 30 may be mounted on the redistribution layer 85. The redistribution layer 85 may be electrically connected to the wiring substrate 80.

[0146] 48A and 48B, one redistribution layer 85 may overlap the first interposer 10, the second interposer 20, and the third interposer 30 in a planar view. For example, the redistribution layer 85 may include an insulating layer 87 that extends to overlap the first interposer 10, the second interposer 20, and the third interposer 30 in a planar view.

[0147] As shown in FIG. 48B , the conductive layer 86 of the redistribution layer 85 may include a first wiring 86a that electrically connects the first semiconductor element 40 and the second semiconductor element 45. The first wiring 86a may function as a power supply line, a ground line, or a signal line. As shown in FIG. 48B , the first wiring 86a may extend in the first direction D1 from a position where it overlaps the first through electrode 14 of the first interposer 10 in a plan view to a position where it overlaps the second through electrode 24 of the second interposer 20 in a plan view. The first semiconductor element 40 and the second semiconductor element 45 may be electrically connected via the first through electrode 14, the first wiring 86a, and the second through electrode 24.

[0148] 48B, the conductive layer 86 of the redistribution layer 85 may include second wiring 86b that electrically connects the first internal element 70 and the second internal element 75. The second wiring 86b may function as a power supply line, a ground line, or a signal line. As shown in FIG. 48B, the second wiring 86b may extend in the first direction D1 from a position overlapping the electrode 71 of the first internal element 70 in a planar view to a position overlapping the electrode 76 of the second internal element 75 in a planar view.

[0149] 49, the redistribution layer 85 may include a plurality of redistribution layers 85A and 85B. That is, the redistribution layer 85 may be divided into a plurality of redistribution layers 85A and 85B.

[0150] There are no particular limitations on the position at which the third semiconductor element 50 is divided. For example, as shown in Figure 49, the redistribution layer 85A may be electrically connected to the first interposer 10 and the third interposer 30, and the redistribution layer 85B may be electrically connected to the second interposer 20 and the third interposer 30.

[0151] (Ninth embodiment) 50 and 51 are cross-sectional views showing a semiconductor package 1 according to the ninth embodiment. The wiring substrate 80 may be electrically connected to the second interposer 20 or the second semiconductor element 45 without the third semiconductor element 50 or the rewiring layer 85 interposed therebetween.

[0152] 50, the semiconductor package 1 may include a conductor 89 extending in the third direction D3 between a pad 82 of the wiring substrate 80 and a pad 27 of the second interposer 20. The conductor 89 does not have to overlap the third semiconductor element 50 in a plan view.

[0153] 51, the semiconductor package 1 may include a conductor 90 extending in the third direction D3 between a pad 82 of the wiring substrate 80 and a fourth pad 46 of the second semiconductor element 45. The conductor 90 does not need to overlap the second interposer 20 and the third semiconductor element 50 in a plan view.

[0154] (Tenth embodiment) 52 and 53 are cross-sectional views showing a semiconductor package 1 according to a tenth embodiment. The first interposer 10 may include a redistribution layer located on the first surface 11 or the second surface 12. 52, the first interposer 10 may include a redistribution layer 121 located on the first surface 11. The redistribution layer 121 includes a conductive layer 122 and an insulating layer 123. The conductive layer 122 may extend from a position overlapping the first semiconductor element 40 to a position not overlapping the first semiconductor element 40 in a plan view. 53, the first interposer 10 may include a redistribution layer 131 located on the second surface 12. The redistribution layer 131 includes a conductive layer 132 and an insulating layer 133.

[0155] The second interposer 20 may include a redistribution layer located on the third surface 21 or the fourth surface 22 . 52, the second interposer 20 may include a redistribution layer 126 located on the third surface 21. The redistribution layer 126 includes a conductive layer 127 and an insulating layer 128. The conductive layer 127 may extend from a position overlapping the second semiconductor element 45 to a position not overlapping the second semiconductor element 45 in a plan view. 53, the second interposer 20 may include a redistribution layer 141 located on the fourth surface 22. The redistribution layer 141 includes a conductive layer 142 and an insulating layer 143.

[0156] Metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys thereof, can be used to form the conductive layers 122, 127, 132, and 142. Organic insulating materials such as polyimide, epoxy resin, and acrylic resin can be used to form the insulating layers 123, 128, 133, and 143.

[0157] 53, the third interposer 30 may include a redistribution layer 151 located on the sixth surface 32. The redistribution layer 151 includes a conductive layer and an insulating layer.

[0158] The conductive layer may be made of a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, or chromium, or an alloy thereof. The insulating layer may be made of an organic insulating material such as polyimide, epoxy resin, or acrylic resin.

[0159] An example of a method for forming the rewiring layer 121 shown in FIGS. 52 and 53 will be described.

[0160] As shown in FIG. 54A, a substrate 101 having a first cavity 13 and a first through electrode 14 is prepared. Next, a first insulating layer 123a is formed on the substrate 101. The first insulating layer 123a includes the organic insulating material described above. The thickness of the first insulating layer 123a is, for example, 2 μm or more, and may be 5 μm or more. The thickness of the first insulating layer 123a is, for example, 20 μm or less, and may be 15 μm or less. The first insulating layer 123a may be formed by attaching a film including an organic insulating material to the substrate 101. The first insulating layer 123a may be formed by applying a liquid including an organic insulating material onto the substrate 101. When the first cavity 13 is formed in the substrate 101, it is preferable to form the first insulating layer 123a using a film.

[0161] Next, as shown in FIG. 54B, a first opening 123b overlapping the first through electrode 14 in a plan view is formed in the first insulating layer 123a. The first opening 123b is formed, for example, by subjecting the first insulating layer 123a to an exposure process and a development process. As shown in FIG. 54B, the first insulating layer 123a overlapping the first cavity 13 may be removed. After the exposure process and the development process, a step of baking the first insulating layer 123a may be performed. The baking temperature is, for example, 200°C, and the baking time is, for example, one hour.

[0162] Next, as shown in FIG. 54C, a first seed layer 122a is formed on the surface of the first through electrode 14 overlapping the first opening 123b. The first seed layer 122a may also be formed on the surface of the first insulating layer 123a. The first seed layer 122a may include a metal such as titanium or copper, an alloy using these, or a laminate of these. The first seed layer 122a is formed by a physical film formation method such as sputtering or vapor deposition. The thickness of the first seed layer 122a is, for example, 0.05 μm or more, and may be 0.10 μm or more. The thickness of the first seed layer 122a is, for example, 0.50 μm or less, and may be 0.30 μm or less.

[0163] 54D, a first resist layer 125a is formed partially on the first seed layer 122a. The first resist layer 125a includes an opening that overlaps the first opening 123b in a plan view. The first resist layer 125a is formed, for example, by subjecting a film containing an organic insulating material to an exposure process and a development process.

[0164] Next, as shown in FIG. 54E, a first plating layer 122b is formed on the first seed layer 122a in the openings of the first resist layer 125a by electrolytic plating. The first plating layer 122b may contain copper as a main component. For example, the first plating layer 122b may contain 80 mass % or more of copper. The thickness of the first plating layer 122b is, for example, 2 μm or more, and may be 3 μm or more. The thickness of the first plating layer 122b is, for example, 10 μm or less, and may be 5 μm or less.

[0165] Next, as shown in FIG. 54F, the first resist layer 125a is removed. For example, the first resist layer 125a may be removed using an organic solvent. Furthermore, the first seed layer 122a that overlaps the first resist layer 125a is removed. The first seed layer 122a containing titanium may be removed using an alkaline chemical solution. The first seed layer 122a containing copper may be removed using an acidic chemical solution.

[0166] Next, as shown in FIG. 54G, a second insulating layer 123c is formed on the first insulating layer 123a and the first plating layer 122b. Like the first insulating layer 123a, the second insulating layer 123c may be formed using a film containing an organic insulating material or a liquid containing an organic insulating material. The thickness of the second insulating layer 123c is, for example, 2 μm or more, and may be 5 μm or more. The thickness of the second insulating layer 123c is, for example, 20 μm or less, and may be 15 μm or less.

[0167] Next, as shown in FIG. 54H, a second opening 123d is formed in the second insulating layer 123c, overlapping the first plating layer 122b in a plan view. Similar to the first opening 123b, the second opening 123d is formed, for example, by subjecting the second insulating layer 123c to an exposure process and a development process. As shown in FIG. 54H, the second insulating layer 123c overlapping the first cavity 13 may be removed. After the exposure process and the development process, a step of baking the second insulating layer 123c may be performed. The baking temperature is, for example, 200°C, and the baking time is, for example, one hour.

[0168] Next, as shown in FIG. 54I, a second seed layer 122c is formed on the surface of the first plating layer 122b that overlaps the second opening 123d. The second seed layer 122c may also be formed on the surface of the second insulating layer 123c. Like the first seed layer 122a, the second seed layer 122c may contain a metal such as titanium or copper, an alloy using these, or a laminate of these. The second seed layer 122c is formed by a physical film formation method such as sputtering or vapor deposition. The thickness of the second seed layer 122c is, for example, 0.05 μm or more, and may be 0.10 μm or more. The thickness of the second seed layer 122c is, for example, 0.50 μm or less, and may be 0.30 μm or less.

[0169] 54J, a second resist layer 125b is formed partially on the second seed layer 122c. The second resist layer 125b includes an opening that overlaps the second opening 123d in a plan view. Similar to the first resist layer 125a, the second resist layer 125b is formed by, for example, subjecting a film containing an organic insulating material to an exposure process and a development process.

[0170] Next, as shown in FIG. 54K, a second plating layer 122d is formed on the second seed layer 122c in the openings of the second resist layer 125b by electrolytic plating. The second plating layer 122d may contain copper as a main component. For example, the second plating layer 122d may contain 80 mass % or more of copper. The thickness of the second plating layer 122d is, for example, 2 μm or more, and may be 3 μm or more. The thickness of the second plating layer 122d is, for example, 10 μm or less, and may be 5 μm or less.

[0171] The second plating layer 122d may protrude in the third direction D3 from the insulating layer 123. The second plating layer 122d can function as a pad.

[0172] As shown in FIG. 54K, a surface layer 122e may be formed on the second plating layer 122d. The surface layer 122e may include a metal such as nickel or gold, an alloy using these, or a laminate of these. For example, the surface layer 122e may include a nickel layer and a gold layer positioned on the nickel layer. The nickel layer may have a thickness of, for example, 0.2 μm. The gold layer may have a thickness of, for example, 0.1 μm. The surface layer 122e may be formed by electroplating.

[0173] Next, as shown in FIG. 54L, the second resist layer 125b is removed. For example, the second resist layer 125b may be removed using an organic solvent. Furthermore, the second seed layer 122c that overlapped the second resist layer 125b is removed. The second seed layer 122c containing titanium may be removed using an alkaline chemical solution. The second seed layer 122c containing copper may be removed using an acidic chemical solution. In this manner, the redistribution layer 121 including the conductive layer 122 and the insulating layer 123 is formed. 54A to 54L, conductive layer 122 includes at least first seed layer 122a, first plating layer 122b, second seed layer 122c, and second plating layer 122d. Conductive layer 122 may also include surface layer 122e. In FIG. 54L, first seed layer 122a, first plating layer 122b, second seed layer 122c, and second plating layer 122d are depicted as an integrated layer. 54A to 54L, insulating layer 123 includes at least first insulating layer 123a and second insulating layer 123c. In Fig. 54L, first insulating layer 123a and second insulating layer 123c are depicted as an integral layer.

[0174] FIG. 55A illustrates an example of a method for connecting the rewiring layer 121 to the first semiconductor element 40. The conductive layer 122 of the rewiring layer 121 may be electrically connected to the first pad 41 of the first semiconductor element 40 via the bump 41b. In this case, the conductive layer 122 may include a surface layer 122e located on the second plating layer 122d. The surface layer 122e may be in contact with the bump 41b. Similarly, the first pad 41 of the first semiconductor element 40 may include a surface layer 41a in contact with the bump 41b. Like the surface layer 122e, the surface layer 41a may include a metal such as nickel or gold, an alloy using these, or a laminate of these. For example, the surface layer 122e may include a nickel layer and a gold layer located on the nickel layer.

[0175] 55B is a diagram illustrating an example of a method for connecting the redistribution layer 121 to the first semiconductor element 40. The conductive layer 122 of the redistribution layer 121 may be directly connected to the first pad 41 of the first semiconductor element 40. For example, the second plating layer 122d of the conductive layer 122 may be directly connected to the first pad 41 of the first semiconductor element 40. In this case, the first pad 41 may contain 80 mass % or more of copper, similar to the second plating layer 122d.

[0176] It is also possible to combine the multiple components disclosed in the above-described embodiments and modifications as needed, or to delete some of the components disclosed in the above-described embodiments and modifications. [Example]

[0177] Next, the present disclosure will be described in more detail with reference to examples. However, the present disclosure is not limited to the following examples as long as it does not depart from the gist of the disclosure.

[0178] Example 1 20, a semiconductor package 1 was fabricated that includes a first interposer 10 including a first cavity 13, a second interposer 20 including a second cavity 23, a third interposer 30, a first semiconductor element 40, and a second semiconductor element 45. The specific structure of each component is as follows: Dimension of the first interposer 10 in the first direction D1: 20 mm Dimension of the second interposer 20 in the first direction D1: 20 mm Dimension of the third interposer 30 in the first direction D1: 5 mm Spacing S1 between the first interposer 10 and the third interposer 30: 0.1 mm or more and 0.5 mm or less Spacing S2 between the second interposer 20 and the third interposer 30: 0.1 mm or more and 0.5 mm or less Material of interposer 10, 20, 30 substrate: Glass Thickness of interposer 10, 20, 30 board: 0.4mm Width of the first portion 351 of the wiring 35: 0.4 μm to 20 μm Length of the first portion 351 of the wiring 35: 3 mm Thickness of the first portion 351 of the wiring 35: 3 μm Dimension of the second portion 352 of the wiring 35: 5 μm The width of the first portion 351 is the dimension of the first portion 351 in a direction perpendicular to the direction in which the first portion 351 extends in a planar view. The length of the first portion is the dimension of the first portion 351 in the direction in which the first portion 351 extends in a planar view. The dimension of the second portion 352 is the maximum dimension of the second portion 352 in a planar view. When the second portion 352 has a circular shape in a planar view, the dimension of the second portion 352 is the diameter of the second portion 352 in a planar view.

[0179] Subsequently, a thermal cycle test was performed on the semiconductor package 1 for 1000 cycles. One cycle included a temperature increase process from -55°C to 125°C and a temperature decrease process from 125°C to -55°C.

[0180] Next, it was inspected whether the first semiconductor element 40 and the second semiconductor element 45 were electrically connected via the wiring 35. In other words, it was inspected whether or not a break occurred in the wiring 35. The results are shown by circle markers in FIG. 42. The horizontal axis is the width of the first portion 351. The vertical axis is the defect rate. The defect rate is the ratio of semiconductor packages 1 that experienced a break when a thermal cycle test was performed on multiple semiconductor packages 1 having the same width of the first portion 351. As shown in FIG. 42, no breaks occurred when the width of the first portion 351 was 0.8 μm or more.

[0181] (Comparative Example 1) A semiconductor package 1 was fabricated in the same manner as in Example 1, except that the first interposer 10, the second interposer 20, and the third interposer 30 included a single common substrate. Also, as in Example 1, a thermal cycle test was performed on the semiconductor package 1 for 1000 cycles. The results are indicated by triangular markers in FIG. 42. As shown in FIG. 42, when the dimension of the second portion 352 was less than 3 μm, disconnections occurred.

[0182] Example 2 A semiconductor package 1 was fabricated in the same manner as in Example 1, except that the width of the first portion 351 of the wiring 35 was set to 2 μm and the dimensions of the second portion 352 were varied within a range of 0.4 μm to 20 μm. Also, as in Example 1, a thermal cycle test was performed on the semiconductor package 1 for 1000 cycles. The results are shown by circular markers in FIG. 43 . The horizontal axis represents the dimensions of the second portion 352. The vertical axis represents the defect rate. The defect rate is the ratio of semiconductor packages 1 that experienced disconnection when a thermal cycle test was performed on multiple semiconductor packages 1 having the same dimensions of the second portion 352. As shown in FIG. 43 , no disconnection occurred when the dimensions of the second portion 352 were 1.0 μm or greater.

[0183] (Comparative Example 2) A semiconductor package 1 was fabricated in the same manner as in Example 2, except that the first interposer 10, the second interposer 20, and the third interposer 30 included a single common substrate. Also, as in Example 2, a thermal cycle test was performed on the semiconductor package 1 for 1000 cycles. The results are indicated by triangular markers in FIG. 43. As shown in FIG. 43, when the dimension of the second portion 352 was less than 10 μm, breaks occurred.

[0184] (Comparative Example 3) The amount of warpage that occurs in the laminate 200 shown in Fig. 56 was calculated based on a simulation. The shape of the laminate 200 is a rectangle in plan view that includes a first side having a length L1 and a second side having a length L2. Both the length L1 and the length L2 are 40 mm.

[0185] 57 is a cross-sectional view of the laminate 200. The laminate 200 includes a substrate 205 having a thickness T1 and an insulating layer 220 having a thickness T2. The insulating layer 220 extends over the entire area of ​​the substrate 205. The substrate 205 is made of glass. The insulating layer 220 is made of polyimide. The thickness T1 is 400 μm. The thickness T2 is 35 μm.

[0186] The maximum amount of warpage that occurred in the laminate 200 was 361 μm.

[0187] Example 3 The amount of warpage that occurs in laminate 210 shown in Fig. 58 was calculated based on a simulation. Fig. 59 is a cross-sectional view of laminate 210. Laminate 210 differs from laminate 200 shown in Fig. 56 in that the substrate is divided into three substrates 211, 212, and 213, and that insulating layer 220 is not provided on substrates 211 and 212. Width L3 of substrate 213 on which insulating layer 220 is provided is 5 mm. Lengths L1 and L2 and thicknesses T1 and T2 are the same as those of laminate 200.

[0188] The maximum amount of warpage that occurred in the laminate 210 was 183 μm. By dividing the substrate and limiting the area of ​​the insulating layer, the amount of warpage was able to be reduced compared to the laminate 200. [Explanation of symbols]

[0189] 1. Semiconductor package 10 First Interposer 11 Page 1 12 Side 2 13 First cavity 14 First through electrode 18 cavities 20 Second Interposer 21 Page 3 22 Page 4 23 Second Cavity 24 Second through electrode 28 Cavity 30 Third Interposer 31 Page 5 32 Page 6 34 Third through electrode 35 Wiring 38 Cavity 40 First semiconductor element 45 Second semiconductor element 50 Third semiconductor element 56 Circuit Board 57 Insulating layer 58 electrode 60 First internal semiconductor element 65 Second internal semiconductor element 70 First internal element 75 Second internal element 80 Wiring board 81 Circuit Board 82 pads 85 Redistribution layer 86 Conductive Layer 87 Insulating Layer 89 Conductors 90 Conductors

Claims

1. A semiconductor package comprising: a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; a first semiconductor element overlapping the first surface and the fifth surface in a plan view; a second semiconductor element overlapping the third surface and the fifth surface in a plan view, the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; the first interposer includes a first cavity formed in the first surface; the semiconductor package includes a first internal semiconductor element located in the first cavity; The first internal semiconductor device is electrically connected to the first semiconductor device.

2. the second interposer includes a second cavity; The semiconductor package of claim 1 , further comprising a second internal semiconductor device located in the second cavity.

3. the second cavity is formed in the third surface; The semiconductor package of claim 2 , wherein the second internal semiconductor device is electrically connected to the second semiconductor device.

4. The semiconductor package according to claim 1 , further comprising a third semiconductor element that overlaps the second surface, the fourth surface, and the sixth surface in a plan view.

5. The semiconductor package according to claim 4 , further comprising a wiring substrate including a substrate and a pad electrically connected to the third semiconductor element.

6. The semiconductor package of claim 5 , wherein the substrate comprises an organic material.

7. the first interposer includes a cavity formed in the second surface; 7. The semiconductor package according to claim 4, further comprising a first internal element located in the cavity formed on the second surface and electrically connected to the third semiconductor element.

8. A semiconductor package, a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; a first semiconductor element overlapping the first surface and the fifth surface in a plan view; a second semiconductor element overlapping the third surface and the fifth surface in a plan view; a third semiconductor element overlapping the second surface, the fourth surface, and the sixth surface in a plan view, the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; the first interposer includes a cavity formed in the second surface; The semiconductor package includes a first internal element located in the cavity formed in the second surface and electrically connected to the third semiconductor element.

9. the second interposer includes a cavity formed in the fourth surface; 9. The semiconductor package according to claim 7, further comprising a second internal element located in the cavity formed in the fourth surface and electrically connected to the third semiconductor element.

10. The semiconductor package according to claim 1 , wherein the first interposer includes a first through electrode.

11. The semiconductor package according to claim 10 , wherein the second interposer includes a second through-electrode.

12. The semiconductor package according to claim 1 , wherein the third interposer includes a third through electrode.

13. the third interposer is located on the fifth surface and includes a rewiring layer including an insulating layer and wiring; The semiconductor package according to claim 1 , wherein the insulating layer comprises an organic insulating material.

14. The semiconductor package according to claim 13 , wherein the organic insulating material includes polyimide, epoxy resin, or acrylic resin.

15. The semiconductor package according to claim 13 or 14, wherein the insulating layer contains a filler made of an inorganic material.

16. the first interposer includes a first substrate made of an inorganic material; an insulating layer containing an organic insulating material is not provided on a surface of the first substrate of the first interposer; the second interposer includes a second substrate made of an inorganic material; The semiconductor package according to claim 1 , wherein an insulating layer containing an organic insulating material is not provided on a surface of the second substrate of the second interposer.

17. the first interposer includes a first substrate made of an inorganic material and a rewiring layer located on a surface of the first substrate and including an insulating layer and wiring; 16. The semiconductor package of claim 1, wherein the second interposer comprises a second substrate made of an inorganic material and a redistribution layer located on the surface of the second substrate and including an insulating layer and wiring.

18. A method for manufacturing a semiconductor package, comprising: a placement step of placing a first interposer including a first surface and a second surface located opposite to the first surface, a second interposer including a third surface and a fourth surface located opposite to the third surface, and a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface; a first mounting step of mounting a first semiconductor element so as to overlap the first surface and the fifth surface in a plan view; a second mounting step of mounting a second semiconductor element so as to overlap the third surface and the fifth surface in a plan view, the second interposer is aligned with the first interposer in a first direction; the third interposer is located between the first interposer and the second interposer in the first direction; the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; the first interposer includes a first cavity formed in the first surface; The manufacturing method, wherein the first mounting step includes a step of placing a first internal semiconductor element connected to the first semiconductor element in the first cavity.

19. the second interposer includes a second cavity; The manufacturing method according to claim 18 , wherein the second mounting step includes the step of placing a second internal semiconductor element connected to the second semiconductor element in the second cavity.

20. a preparation step of preparing a third semiconductor element; 20. The manufacturing method of claim 18, wherein in the placement process, the first interposer, the second interposer, and the third interposer are placed so that the second surface, the fourth surface, and the sixth surface overlap the third semiconductor element in a planar view.

21. The manufacturing method according to claim 20 , further comprising the step of: positioning a wiring substrate including a substrate and pads such that the pads of the wiring substrate are electrically connected to the third semiconductor element.

22. mounting a first internal element on the third semiconductor element; The manufacturing method according to claim 20 or 21, wherein the placing step includes a step of placing the first interposer so that the first internal element is located in a cavity formed in the second surface.

23. A method for manufacturing a semiconductor package, comprising: a placement step of placing a first interposer including a first surface and a second surface located opposite to the first surface, a second interposer including a third surface and a fourth surface located opposite to the third surface, and a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface; a first mounting step of mounting a first semiconductor element so as to overlap the first surface and the fifth surface in a plan view; a second mounting step of mounting a second semiconductor element so as to overlap the third surface and the fifth surface in a plan view, the second interposer is aligned with the first interposer in a first direction; the third interposer is located between the first interposer and the second interposer in the first direction; the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; the manufacturing method includes a preparation step of preparing a third semiconductor element; and a step of mounting a first internal element on the third semiconductor element; In the arranging step, the first interposer, the second interposer, and the third interposer are arranged so that the second surface, the fourth surface, and the sixth surface overlap the third semiconductor element in a plan view; The manufacturing method, wherein the placing step includes a step of placing the first interposer so that the first internal element is located in a cavity formed in the second surface.

24. The manufacturing method according to claim 18 , wherein the first interposer includes a first through-electrode.

25. An interposer group on which a first semiconductor element and a second semiconductor element are mounted, a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; the first semiconductor element is mounted so as to overlap the first surface and the fifth surface in a plan view, the second semiconductor element is mounted so as to overlap the third surface and the fifth surface in a plan view, the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; An interposer group, wherein the first interposer includes a first cavity formed on the first surface and in which a first internal semiconductor element electrically connected to the first semiconductor element is located.

26. An interposer group on which a first semiconductor element, a second semiconductor element, and a third semiconductor element are mounted, a first interposer including a first surface and a second surface opposite the first surface; a second interposer including a third surface and a fourth surface located opposite the third surface, the second interposer being aligned with the first interposer in the first direction; a third interposer including a fifth surface and a sixth surface located opposite to the fifth surface, the third interposer being located between the first interposer and the second interposer in the first direction; the first semiconductor element is mounted so as to overlap the first surface and the fifth surface in a plan view, the second semiconductor element is mounted so as to overlap the third surface and the fifth surface in a plan view, the third semiconductor element is mounted so as to overlap the second surface, the fourth surface, and the sixth surface in a plan view; the third interposer includes wiring that electrically connects the first semiconductor element and the second semiconductor element; an interposer group, wherein the first interposer includes a cavity formed on the second surface in which a first internal element electrically connected to the third semiconductor element is located;

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