Program loading method, device, computer-readable medium and electronic device

Abstract

The present disclosure relates to a program loading method, an apparatus, a computer-readable medium, and an electronic device. The method includes: loading a bin file in a flash memory at a first program loading speed; adjusting the program loading speed to a second speed higher than the first speed based on a configuration parameter in the bin file; and loading an FSBL at the second program loading speed. Implementing the configuration parameter in the bin file adjusts the speed at which Bootrom loads the FSBL from the flash memory, shortening the time it takes Bootrom to load the FSBL, which is applicable when an embedded system supports various flash memories and is concerned about boot time.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from a Chinese patent application bearing application number 202210055209.2, filed on January 18, 2022, and entitled "Program Loading Method, Apparatus, Computer-Readable Medium, and Electronic Device," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to hardware program loading, and more particularly to a program loading method, apparatus, computer-readable medium and electronic device. [Background technology]

[0003] Bootrom, or Boot ROM (Read-Only Memory), is a small piece of mask ROM or write-protected flash memory embedded in a CPU chip and cannot be flexibly modified. If the First Stage BootLoader (FSBL) of an embedded system (e.g., various accelerator cards in servers) resides in Serial Peripheral Interface Flash (SPI) memory, Bootrom must load the FSBL into Static Random-Access Memory (SRAM) after powering on the CPU, verify the FSBL, and execute it. For security reasons, even in-place execution (XIP), the entire FSBL must be loaded and verified before jumping to execution.

[0004] Because embedded systems support a variety of SPI Nor flash (non-volatile flash memory), the clock rate of Bootrom's SPI controller is relatively low (usually around 10MHz), which means that it takes time to load the FSBL, making it unsuitable for systems where boot time is a priority. Summary of the Invention

[0005] The Summary is intended to introduce concepts in a simplified form, which will be described in detail in the Specific Embodiments section below. The Summary is not intended to identify key features or essential elements of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] According to a first aspect, the present disclosure provides a program loading method applicable to an electronic device, the method including the steps of: loading a bin file at a first program load speed, the bin file including a setting parameter for adjusting the program load speed; adjusting the program load speed to a second speed greater than the first speed based on the setting parameter in the bin file; and loading an FSBL of a first stage load program at the program load speed adjusted to the second speed.

[0007] According to a second aspect, the present disclosure provides a program loading device applicable to an electronic device, the device comprising: a load module for loading a bin file at a first program load speed, the bin file including a setting parameter for adjusting the program load speed; and a processing module for adjusting the program load speed to a second speed greater than the first speed based on the setting parameter in the bin file, the load module being further used to load an FSBL of a first stage load program at the program load speed adjusted to the second speed.

[0008] According to a third aspect, the present disclosure provides a computer-readable medium having stored thereon a computer program which, when executed by a processing device, implements the aforementioned program loading method.

[0009] According to a fourth aspect, the present disclosure provides a computer device including a storage device in which a computer program is stored and a processing device for executing the computer program in the storage device, thereby realizing the above-mentioned program loading method.

[0010] According to the above technical solution, a bin file in flash memory is loaded at a first program loading speed, and the program loading speed is adjusted to a second speed higher than the first speed based on the setting parameters in the bin file, and the FSBL is loaded at the second program loading speed. By implementing the setting parameters in the bin file, the speed at which Bootrom loads the FSBL from flash memory can be adjusted, thereby shortening the time it takes Bootrom to load the FSBL. This allows embedded systems to support various flash memories and is applicable when boot time is a priority.

[0011] Other features and advantages of the present disclosure are described in detail in the specific embodiments section below. [Brief explanation of the drawings]

[0012] The above and other features, advantages, and aspects of the embodiments herein will become more apparent with reference to the accompanying drawings and the following specific embodiments. It should be understood that the same or identical reference numerals refer to the same or identical elements throughout the accompanying drawings. The drawings are schematic, and the proportions of the dimensions do not necessarily correspond to the actual objects and elements. [Figure 1] FIG. 1 is a schematic diagram illustrating the configuration of an electronic device according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 is a flow diagram of a program loading method according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a parameter allocation diagram of a status register according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a program loading device according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram illustrating the configuration of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] [Explanation of symbols] 100 - electronic equipment; 10 - boot ROM; 20 - SPI flash memory; 20 - program load device; 201 - load module; 203 - processing module; 600 - computer equipment; 601 - processing unit; 602 - ROM; 603 - RAM; 604 - bus; 605 - I / O interface; 606 - input device; 607 - output device; 608 - storage device; 609 - communication device.

[0014] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the accompanying drawings show specific embodiments of the present disclosure, it should be understood that the present disclosure can be realized in various forms and should not be construed as being limited to the embodiments described herein, but rather, these embodiments are provided for a thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are used for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0015] It should be understood that the steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. Additionally, method embodiments may include additional steps and / or omit performing illustrated steps. The scope of the present disclosure is not limited in this respect.

[0016] The term "comprises" and variations thereof herein are open-ended, i.e., "including but not limited to." The term "based on" means "based at least in part on." Definitions of other terms are provided below.

[0017] It should be noted that the concepts of "first," "second," etc. referred to in this disclosure are used only to distinguish between different devices, modules, or units, and are not used to limit the order or interdependence of functions performed by these devices, modules, or units.

[0018] It should be noted that the modifications "one" and "multiple" referred to in this disclosure are intended to be exemplary rather than limiting, and should be understood by those skilled in the art as "one or more" unless the context dictates otherwise.

[0019] The names of messages or information exchanged between devices in the embodiments of the present disclosure are not intended to limit the scope of these messages or information and are used for illustrative purposes only.

[0020] BootROM (Bootrom) is code hardened in the CPU's internal ROM, and contains the initial code executed when a process is powered on or reset. The location of specific ribbon pins or internal fuses can determine where the next piece of code to be executed is loaded from and how the correctness or validity of the code to be executed is verified. BootROM may also contain other functions used by user code during or after booting. For example, an iPhone® boots from a ROM, and the code embedded in the mask ROM cannot be corrected. The ROM loads the next-level boot loader program from flash memory or USB, verifies the signature of the boot loader program using a built-in RSA algorithm, and provides accelerated decryption functionality for the next-level boot loader program.

[0021] SPI flash is a flash storage device that operates via the serial peripheral interface (SPI). Flash is typically divided into two types, Nor flash and Nand flash, based on the internal storage configuration, and SPI flash is a type of Nor flash. Because SPI flash has slow read / write speeds and limited read / write cycles, it is typically used for storage that requires infrequent changes. Previously, Nor flash's interface was parallel, connecting data and address lines to integrated circuit (IC) pins side-by-side. However, experts later discovered that Nor flash of different capacities was incompatible in hardware. Due to the unequal number of data and address lines, the package size was large, and it took up a lot of space on the printed circuit board (PCB), SPI Nor flash was gradually replaced by SPI Nor flash. At the same time, SPI Nor flash of different capacities has pin compatibility and a smaller package, so many experts are now directly replacing Nor flash with SPI flash.

[0022] XIP means that the application can be executed directly in flash without loading the code into system RAM (Random Access Memory). Flash execution means that the code can be executed directly in flash without initializing nor flash. However, often only part of the code is executed, e.g., RAM is initialized.

[0023] If the FSBL of an embedded system is stored in SPI flash, Bootrom must load the FSBL into SRAM after powering on the CPU, and then verify the signature of the FSBL before executing it for security reasons. Even in the XIP method, the entire FSBL must be loaded and its signature verified before executing it.

[0024] SPI controllers that support high-speed clocks (CLK) (high-speed here usually refers to clock frequencies above 25 MHz, i.e., CLK > 25 MHz) usually come with a port physical layer (PHY). The PHY registers must be adapted according to board wiring, flash parameters, etc. The BootROM is hard-wired into the CPU chip and does not allow flexible customization of these PHY register values. In other words, even if a high-speed SPI controller can adjust the PHY register values ​​using jumpers, this does not necessarily cover all relevant PHY registers. Therefore, BootROM cannot set the SPI controller's clock rate higher when loading the FSBL; for example, it usually cannot exceed 25 MHz.

[0025] SPI is divided into three modes: Single SPI (standard SPI, transmits one bit per clock), Dual SPI (double SPI, transmits two bits per clock), and Quad SPI (quad SPI, transmits four bits per clock), which correspond to 3-wire, 4-wire, and 6-wire, respectively. The more lines there are at the same clock, the higher the data transfer rate. Most SPI flash supports QSPI (Quad SPI), but the CPU must read the Serial Flash Discoverable Parameter (flash SFDP) before determining the method to enable QSPI. This logic is cumbersome and not suitable for inclusion in Bootrom.

[0026] Therefore, in order to allow embedded systems to support various SPI Nor flash, the clock rate of Bootrom's SPI controller is relatively conservative (around 10MHz), and the SPI QSPI mode is rarely turned on, which makes the time to load the FSBL too long.

[0027] For the above reasons, the application of SPI flash is significantly limited when boot time is critical. For example, for a Peripheral Component Interconnect Express (PCIe) board, the PCIe specification requires that the time from system power-on to PCIe initialization completion must be within 120 ms. Assuming the FSBL size is 50 KB and a 10 MHz SPI clock is used, the FSBL loading speed is 50 KB x 8 / 10 MHz = 40 ms. If it takes 40 ms just to load the FSBL, the hardware and software initialization speed before PCIe power-on is too high.

[0028] For the reasons mentioned above, the conventional method of loading FSBL is not suitable for the case where boot time is sensitive. To solve this problem, the present disclosure presents a program loading method for Bootrom applicable to embedded systems, which reduces the time it takes for Bootrom to load FSBL from SPI flash. The method is described in detail below.

[0029] FIG. 1 is a schematic diagram illustrating the configuration of an electronic device according to an exemplary embodiment of the present disclosure.

[0030] The electronic device 100 includes a boot ROM 10 and an SPI flash memory 20. Here, the SPI flash memory 20 may be an SPI Nor flash.

[0031] The SPI flash memory 20 may store a bin file.

[0032] After the CPU of the electronic device is powered on, Bootrom establishes a communication connection with the SPI flash memory 20. Bootrom first verifies the security of the SPI flash memory 20. After the SPI flash memory 20 passes the security verification, Bootrom reads and executes relevant code in the SPI flash memory 20 to obtain relevant parameters and adapt the PHY registers or adjust the clock rate of the SPI controller. Then, Bootrom reads the FSBL from the SPI flash memory 20 to perform security verification. After the FSBL passes the security verification, Bootrom executes the FSBL.

[0033] Referring to Figure 2, Figure 2 is a flow diagram of a program loading method according to an exemplary embodiment of the present disclosure, which includes the following steps:

[0034] In step S101, a bin file is loaded at a first program loading speed.

[0035] In order to accommodate various SPI Nor flash in embedded systems, the clock rate of Bootrom's SPI controller is relatively low, about 10 MHz. Therefore, the first speed in this step is a reasonable value in the art, and the value may be obtained based on artificial experience or other possible methods. For example, the first speed may be, but is not limited to, a clock rate of the SPI controller of 10 MHz.

[0036] The bin file is stored in the SPI flash and includes configuration parameters for adjusting the program load speed. The configuration parameters include at least one of a PHY register configuration parameter, a flash memory adaptation parameter, and an SPI clock rate parameter. The PHY register configuration parameter is used to adjust the PHY register settings of the board-level wiring of the embedded system to enable normal SPI operation. Specifically, it is used to adjust the phase relationship between each SPI signal. The SPI clock rate parameter is used to adjust the clock rate of the SPI controller, and the flash memory adaptation parameter is used to enable the QSPI mode of the SPI.

[0037] In step S102, the program loading speed is adjusted to a second speed based on the setting parameters in the bin file.

[0038] For example, to enable the SPI to operate normally, the PHY register settings of the board-level wiring of the embedded system are adjusted based on the PHY register setting parameters in the bin file, specifically, the phase relationship between each SPI signal is adjusted.

[0039] The value of the second speed is greater than the first speed, and the second speed is a reasonable value in the art. The value may be obtained through artificial experience or in other possible ways. For example, the second speed may be, but is not limited to, a clock rate value of the SPI controller of 50 MHz.

[0040] The method of adjusting the program load speed to the second speed based on the setting parameters in the bin file may be to enable the QSPI mode of the SPI based on the flash memory adaptation parameters in the bin file so as to set the program load speed to the second speed. As mentioned above, SPI is divided into three modes: Single SPI, Dual SPI, and Quad SPI, corresponding to 3-wire, 4-wire, and 6-wire, respectively. For the same clock, the more lines there are, the higher the data transmission rate. Flash memory manufactured by different companies supports different adjustment methods. Specifically, specific adjustment methods can be obtained according to the flash manual provided by the company, but this disclosure is not limited to these. For example, a flash memory manufactured by a certain company will be used as an example. Figure 3 shows a parameter layout diagram of the status register. Bits 0 to 7 are all registers, and QE (Quad Enable) is usually controlled by bit 6 register, i.e., the QSPI mode is controlled by bit 6 register. The value of this bit is 0 or 1 and is used to indicate whether QSPI is enabled or not (i.e., 1 = Quad Enable, 0 = not Quad Enable). Therefore, by adjusting the bit 6 register parameter of the Status Register, the QSPI mode of SPI can be enabled.

[0041] Alternatively, the method of adjusting the program loading speed to the second speed based on the setting parameters in the bin file may further include adjusting the clock rate of the SPI controller based on the SPI clock rate parameters in the bin file to set the program loading speed to the second speed. In a preferred embodiment, the clock rate of the SPI controller can be adjusted to 50 MHz.

[0042] Alternatively, the manner of adjusting the program load speed to the second speed based on the setting parameters in the bin file may further include enabling the QSPI mode of the SPI based on the flash memory adaptation parameters in the bin file, and adjusting the clock rate of the SPI controller based on the SPI clock rate parameters in the bin file so as to set the program load speed to the second speed. In a preferred embodiment, the clock rate of the SPI controller can be adjusted to 50 MHz.

[0043] In step S103, the FSBL of the first stage load program is loaded at the program load speed adjusted to the second speed.

[0044] Bootrom loads FSBL from SPI flash at the second speed program loading speed, and usually adjusts the second speed to 4-5 times faster than the first speed to achieve the goal of loading FSBL at high speed.

[0045] For example, for the PCIe board mentioned above, the PCIe specification requires that the time from system power-on to PCIe initialization completion must be within 120 ms. Assuming the FSBL is 50 KB, if a first-speed SPI clock rate (e.g., 10 MHz) is used, loading the FSBL requires 50K×8 / 10 MHz = 40 ms. When using the program loading method proposed in this disclosure, the bin file is first loaded at the first speed. Assuming the size of the bin file is 500 bytes, if the SPI QSPI mode is enabled and the program loading speed is set to a second speed (e.g., 50 MHz), loading the FSBL requires 500×8 / 10 MHz + 50K×8 / (4×50 MHz) = 0.4 ms + 2 ms = 2.4 ms. This saves approximately 90% of the time required to load the FSBL.

[0046] The above method allows you to adjust the speed at which Bootrom loads FSBL from flash memory by executing the setting parameters in the bin file, shortening the time it takes for Bootrom to load FSBL. This method is applicable when embedded systems support various flash memories and boot time is important. Products that are forced to use SD / MMC-related registers due to limitations in Bootrom's boot speed can switch to SPI flash, reducing hardware costs.

[0047] Furthermore, the above method further includes the following steps:

[0048] In step S104, the security of the FSBL is verified.

[0049] It should be noted that various possible encryption algorithms can be employed to verify the security of the FSBL, and this disclosure is not limited thereto.

[0050] For example, the MD5 algorithm is used to verify the security of the FSBL. Typically, the FSBL and its first encrypted signature are packaged together and stored in the SPI flash. The first encrypted signature is the FSBL signature encrypted with a private key. In step S103, the FSBL and its first encrypted signature are obtained from the loaded FSBL. The first encrypted signature is then decrypted with a public key corresponding to the private key stored in the Bootrom to obtain the decrypted first signature. The FSBL signature is then calculated to obtain the second signature. The first and second signatures are then compared. If the first and second signatures are identical, it is determined that the FSBL has passed security verification.

[0051] In step S105, if the FSBL passes the security verification, the FSBL is executed.

[0052] A specific embodiment of the program loading method according to the present disclosure may involve adding a plug-in to the bootROM. This plug-in is not limited to fast loading of the FSBL, and other purposes may be achieved by adjusting the code in the plug-in. For example, a flash memory that can only access the previous 16M address space without special configuration can be expanded to 4G address space after configuring the plug-in boot in the corresponding access address space.

[0053] In summary, the program loading method according to the present disclosure includes loading a bin file from an SPI flash at a first program loading speed, adjusting the program loading speed to a second speed greater than the first speed based on a setting parameter in the bin file, and loading an FSBL at the second program loading speed. By implementing the setting parameter in the bin file, the speed at which Bootrom loads the FSBL from the SPI flash is adjusted, shortening the time it takes Bootrom to load the FSBL, enabling embedded systems to support various SPI flashes and being applicable when boot time is a priority.

[0054] 4 is a block diagram of a program loading device according to an exemplary embodiment of the present disclosure. Referring to FIG. 4, the device 20 includes a load module 201 and a processing module 203.

[0055] The load module 201 is used to load the bin file at a first program load speed, and the bin file includes a setting parameter for adjusting the program load speed.

[0056] The processing module 203 is used to adjust the program loading speed to a second speed greater than the first speed based on the setting parameters in the bin file.

[0057] The load module 201 is further used to load the FSBL of the first stage load program at the program load speed adjusted to the second speed.

[0058] Preferably, the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

[0059] Preferably, the processing module 203 comprises: Obtain the PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; or enabling the QSPI mode of the SPI based on the flash memory adaptation parameters so as to set the program loading speed to the second speed; or adjusting the clock rate of the SPI in the flash memory based on the SPI clock rate parameter so as to set the program loading speed to the second speed; Alternatively, the flash memory adaption parameter is used to enable the QSPI mode of the SPI, and the SPI clock rate in the flash memory is adjusted based on the SPI clock rate parameter so that the program load speed is the second speed.

[0060] Preferably, the processing module 203 further comprises: used to verify the security of the FSBL; If the FSBL passes security verification, it executes the FSBL.

[0061] Preferably, the processing module 203 comprises: Obtaining a first encrypted signature of the FSBL from the loaded FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; Computing a signature of the FSBL to obtain a second signature of the FSBL; comparing the first signature with the second signature; If the first signature and the second signature are the same, this is used to determine that the FSBL has passed the security verification.

[0062] FIG. 5 is a schematic diagram illustrating the configuration of an electronic device 600 for implementing an embodiment of the present disclosure. Examples of terminal devices in the embodiment of the present disclosure include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (portable Android® devices), PMPs (portable media players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The electronic device illustrated in FIG. 5 is merely an example and does not limit the functions or scope of use of the embodiment of the present disclosure.

[0063] 5, electronic device 600 may include a processing unit (e.g., a central processor, a graphics processor, etc.) 601 that can perform various appropriate operations and processes based on programs stored in read-only memory (ROM) 602 or programs loaded from storage device 608 into random access memory (RAM) 603. RAM 603 further stores various types of programs and data necessary for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0064] Typically, the I / O interface 605 may be connected to input devices 606, such as a touch screen, touch panel, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 607, such as a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 608, such as a magnetic tape, hard disk, etc.; and communication devices 606. The communication devices 606 may allow the electronic device 600 to communicate and exchange data with other devices wirelessly or via wires. While FIG. 5 illustrates the electronic device 600 with various devices, it should be understood that it is not necessary to implement or include all of the devices shown. More or fewer devices may alternatively be implemented or included.

[0065] In particular, according to embodiments of the present disclosure, the processes described with reference to the flow diagrams may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the methods shown in the flow diagrams. In such embodiments, the computer program may be downloaded or installed from a network via the communication device 606, installed from the storage device 608, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0066] It should be noted that the computer-readable medium of the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination thereof. The computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer-readable storage medium include, but are not limited to, an electrical connector having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM, flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, the computer-readable storage medium may be any tangible medium that includes or stores a program usable by or in combination with an instruction execution system, device, or appliance. In the present disclosure, the computer-readable signal medium may comprise a data signal carrying computer-readable program code, propagated in baseband or as part of a carrier. Such a propagated data signal may take various forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transmit a program usable by or in combination with an instruction execution system, apparatus, or device. The program code contained in the computer-readable medium may be transmitted over any suitable medium, including, but not limited to, electrical wire, fiber optic cable, RF (radio), etc., or any suitable combination of the above.

[0067] The computer-readable medium may be included in the electronic device, or may exist separately from the electronic device.

[0068] Computer program code for carrying out the operations of the present disclosure can be written in one or more program programming languages, or a combination thereof, including, but not limited to, object-oriented program programming languages ​​such as Java, Smalltalk, C++, etc., as well as conventional procedural program programming languages ​​such as "C" or similar program programming languages. The program code may be executed entirely on the user computer, partially on the user computer, as a standalone software package, partially on the user computer and partially on a remote computer, or entirely on a remote computer or server. When a remote computer is used, the remote computer may be connected to the user computer via any type of network, such as a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet via an Internet Service Provider).

[0069] The flow diagrams and block diagrams in the accompanying drawings illustrate possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams may represent a module, program segment, or portion of code, including one or more executable instructions for implementing a given logical function. It should also be noted that, in some alternative embodiments, the functions shown in the blocks may occur in a different order than that shown in the accompanying drawings. For example, two blocks shown in succession may actually be executed substantially in parallel, but may be executed in the reverse order, depending on the related functionality. It should be noted that each block in the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, may be implemented by a system of dedicated hardware that performs a given function or operation, or by a combination of dedicated hardware and computer instructions.

[0070] The modules described in the embodiments of the present disclosure may be realized in software or hardware, and the names of the modules may not be limiting.

[0071] The functionality described herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary hardware logic components that may be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0072] In the context of this disclosure, a machine-readable medium may be a tangible medium capable of containing or storing a program used by or in combination with an instruction execution system, device, or machine. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of these contents. More specific examples of machine-readable storage media include an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0073] According to one or more embodiments of the present disclosure, Example 1 comprises: A method applied to an electronic device in which a preset bin file is stored in a flash memory of the electronic device, comprising: loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; adjusting the program loading speed to a second speed greater than the first speed based on the setting parameters in the bin file; loading a first stage load program FSBL at the program load speed adjusted to the second speed.

[0074] According to one or more embodiments of the present disclosure, Example 2 comprises: 10. The method according to claim 1, wherein the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

[0075] According to one or more embodiments of the present disclosure, Example 3 comprises: adjusting the program loading speed to a second speed based on the setting parameters in the bin file; obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters so that the program loading speed is a second speed; or adjusting the clock rate of the SPI in the flash memory according to the SPI clock rate parameter so that the program loading speed is a second speed; Alternatively, a method as described in Example 1 is provided, which includes a step of enabling a QSPI mode of the SPI based on the flash memory adaptation parameter, and adjusting the clock rate of the SPI in the flash memory based on the SPI clock rate parameter, so that the program load speed becomes the second speed.

[0076] According to one or more embodiments of the present disclosure, Example 4 comprises: After the step of loading the FSBL at the program load speed adjusted to the second speed, performing security verification of the FSBL; The method according to Example 1 is further provided, which includes executing the FSBL if the FSBL passes security verification.

[0077] According to one or more embodiments of the present disclosure, Example 5 comprises: The step of performing security verification of the FSBL includes: obtaining a first encrypted signature of the FSBL from the loaded FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; calculating a signature of the FSBL to obtain a second signature of the FSBL; comparing the first signature with the second signature; If the first signature is identical to the second signature, determining that the FSBL passes the security verification is provided.

[0078] According to one or more embodiments of the present disclosure, Example 6 comprises: The method according to Example 1 is provided, wherein the flash memory of the electronic device is an SPI flash memory.

[0079] According to one or more embodiments of the present disclosure, Example 7 comprises: A program loading device applied to an electronic device in which a preset bin file is stored in a flash memory of the electronic device, a load module for loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; a processing module for adjusting the program loading speed to a second speed greater than the first speed based on the setting parameters in the bin file; The load module further provides a program load device used to load a first stage load program FSBL at the program load speed adjusted to the second speed.

[0080] According to one or more embodiments of the present disclosure, Example 8 comprises: The processing module is used for: obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters so that the program load speed is the second speed; or adjusting the clock rate of the SPI in the flash memory based on the SPI clock rate parameter so that the program loading speed becomes the second speed; Alternatively, the present invention provides an apparatus as described in Example 7, which includes a step of enabling a QSPI mode of the SPI based on the flash memory adaptation parameters and adjusting the SPI clock rate in the flash memory based on the SPI clock rate parameters so that the program load speed becomes the second speed.

[0081] According to one or more embodiments of the present disclosure, Example 9 comprises: A computer-readable medium having a computer program stored thereon, A computer readable medium is provided which, when executed by a processor, implements the program loading method.

[0082] According to one or more embodiments of the present disclosure, Example 10 comprises: a storage device storing a computer program; a processing device that executes the computer program in the storage device, An electronic device that implements the program loading method is provided.

[0083] The above description is merely an example of the preferred embodiments and applied technical principles of the present disclosure. Those skilled in the art should understand that the scope of the present disclosure is not limited to the technical solutions that combine the specific technical features described above, but also includes other technical solutions that combine the above technical features or the same features in any way without departing from the concept of the above description, for example, replacing the above features with technical features having similar functions disclosed in this specification (but not limited to).

[0084] Additionally, although operations have been described in a particular order, these operations should not be construed as requiring the operations to be performed in the particular order or sequence described. Multitasking and parallel processing may be advantageous in certain environments. Similarly, although the above description includes several specific implementation details, these should not be construed as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, each feature described in the context of a single embodiment may be implemented in multiple embodiments, either individually or in any suitable subcombination.

[0085] Although the present subject matter has been described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined by the appended claims is not necessarily limited to the specific features or operations described above. Rather, the specific features and operations described above are merely example forms of implementing the claims.

[0086] In the above-described embodiment of the apparatus, the specific implementation of each module performing the operations has been described in detail in the embodiment of the method, but will not be described in detail here.

Claims

1. A program loading method performed by an electronic device, wherein a preset bin file is stored in a flash memory of the electronic device, and the program loading method comprises: loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; adjusting the program loading speed to a second speed greater than the first speed based on the setting parameters in the bin file; loading a first-stage load program FSBL at the program load speed adjusted to the second speed; adjusting the program loading speed to a second speed based on the setting parameters in the bin file; obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters so that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory based on the SPI clock rate parameter so that the program load speed is the second speed; or enabling a QSPI mode of the SPI based on the flash memory adaptation parameter and adjusting a clock rate of the SPI in the flash memory based on the SPI clock rate parameter so that the program load speed is the second speed; and a program loading method including:

2. 2. The method of claim 1, wherein the configuration parameters include at least one of a port physical layer PHY register configuration parameter, a flash memory adaptation parameter, and a serial peripheral interface SPI clock rate parameter.

3. After the step of loading the FSBL at the program load speed adjusted to the second speed, performing security verification of the FSBL; The method of claim 1 , further comprising: if the FSBL passes security verification, executing the FSBL.

4. The step of performing security verification of the FSBL includes: obtaining from the loaded FSBL a first encrypted signature of the FSBL; decrypting the first encrypted signature with a pre-stored public key to obtain a decrypted first signature; computing a signature of the FSBL to obtain a second signature of the FSBL; comparing the first signature with the second signature; 4. The method of claim 3, further comprising determining that the FSBL passes the security verification if the first signature is identical to the second signature.

5. The method of claim 1 , wherein the flash memory of the electronic device is an SPI flash memory.

6. A program loading device, the program loading device being incorporated into an electronic device, the flash memory of the electronic device storing a preset bin file, the program loading device: a load module for loading the bin file at a first program load speed, the bin file including configuration parameters for adjusting the program load speed; a processing module for adjusting the program loading speed to a second speed greater than the first speed based on the setting parameters in the bin file; Equipped with the load module is further used to load a first stage load program FSBL at the program load speed adjusted to the second speed; The processing module includes: obtaining PHY register setting parameters, flash memory adaptation parameters, and SPI clock rate parameters in the bin file; adjusting board-level interconnect PHY register settings in the flash memory based on the PHY register setting parameters; enabling a QSPI mode of the SPI based on the flash memory adaptation parameters so that the program load speed is the second speed; or adjusting a clock rate of an SPI in the flash memory based on the SPI clock rate parameter so that the program load speed is the second speed; or enabling a QSPI mode of the SPI based on the flash memory adaptation parameter and adjusting a clock rate of the SPI in the flash memory based on the SPI clock rate parameter so that the program load speed is the second speed; and a program load device further configured to execute the program.

7. A computer-readable medium having a computer program stored thereon, A computer readable medium which, when executed by a processing device, implements the method of any one of claims 1 to 5.

8. a storage device storing a computer program; a processing device that executes the computer program in the storage device, An electronic device that implements the method according to any one of claims 1 to 5.

Images