Bandwidth control method and system, electronic device, vehicle, and storage medium

Abstract

To provide a bandwidth control method and system, an electronic device, a vehicle, and a storage medium relating to the technical field of integrated circuits.SOLUTION: A method includes the steps of: obtaining a state of use of a cache queue, the cache queue being used for caching accesses of multiple operating systems to a second hardware unit; determining a throttling parameter for each of the operating systems based on the state of use of the cache queue; and controlling, based on the throttling parameter of each of the operating systems, bandwidth for each of the operating systems for accessing the second hardware unit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to bandwidth control methods and systems, electronic devices, vehicles, and storage media. [Background technology]

[0002] Some integrated circuits, such as systems on chips (SoCs), can run multiple operating systems (OSs), which share the bandwidth resources of the integrated circuit, such as memory bandwidth.

[0003] Currently, when multiple operating systems run on an integrated circuit, there is a problem that the bandwidth resources allocated to the integrated circuit are not reasonable, which affects the performance of each operating system. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present disclosure provide a bandwidth control method, device, integrated circuit, electronic device, and vehicle, which, when multiple operating systems run on an integrated circuit, can dynamically allocate the resources of the integrated circuit to each operating system, thereby improving the business performance and resource utilization of each operating system. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present disclosure provides a bandwidth control method, the method including steps of: acquiring a usage status of a cache queue, the cache queue being for caching accesses to a second hardware unit by a plurality of operating systems run by a first hardware unit; determining a first throttling parameter of the first operating system based on the usage status of the cache queue; and controlling the bandwidth of accesses of the first operating system to the second hardware unit based on the first throttling parameter.

[0006] In a second aspect, an embodiment of the present disclosure provides a bandwidth control device, the device including a first throttling module communicatively connected to a first hardware unit on which multiple operating systems are running, the first throttling module corresponding to the first operating system, and configured to acquire a usage status of a cache queue for caching accesses to a second hardware unit by the multiple operating systems run by the first hardware unit, determine a first throttling parameter for the first operating system based on the usage status of the cache queue, and control the bandwidth of accesses of the first operating system to the second hardware unit based on the first throttling parameter.

[0007] In a third aspect, an embodiment of the present disclosure provides an integrated circuit, the integrated circuit including: a first hardware unit running a plurality of operating systems; and a plurality of throttling modules communicatively connected to the first hardware unit and disposed in one-to-one correspondence with the plurality of operating systems, at least one of the throttling modules configured to implement the function of the first throttling module of the second aspect, for example, to perform steps of the bandwidth control method provided in the first aspect.

[0008] In a fourth aspect, an embodiment of the present disclosure provides an electronic device including the integrated circuit provided in the third aspect.

[0009] In a fifth aspect, an embodiment of the present disclosure provides a vehicle including the integrated circuit provided in the third aspect or the electronic device provided in the fourth aspect. [Effects of the Invention]

[0010] The technical solution provided in the embodiments of the present disclosure can control the access bandwidth of each operating system to the second hardware unit based on the usage status of the cache queue, thereby realizing dynamic allocation of bandwidth resources to the second hardware unit, which can not only improve the business performance of each operating system, but also improve the utilization rate of bandwidth resources and reduce the waste of bandwidth resources. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram of the structure of a cockpit-driving integrated system provided in an exemplary embodiment of the present disclosure. [Figure 2] FIG. 1 is a structural schematic diagram of a bandwidth control system provided in an exemplary embodiment of the present disclosure; [Figure 3] 1 is a flowchart of a bandwidth control method provided in an exemplary embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of dynamically controlling access bandwidth provided in an exemplary embodiment of the present disclosure. [Figure 5] 1 is a flowchart of step S120 of a bandwidth control method provided in an exemplary embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram of determining a target bandwidth threshold provided in an exemplary embodiment of the present disclosure. [Figure 7] FIG. 1 is a structural schematic diagram of a bandwidth control device provided in an exemplary embodiment of the present disclosure; [Figure 8]1 is a structural schematic diagram of an integrated circuit provided in an exemplary embodiment of the present disclosure; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. It is clear that the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0013] It should be noted that the scope of the present disclosure is not limited to the relative arrangements of components and steps, formulas and numerical values ​​described in these examples unless specifically stated otherwise.

[0014] First, some technical terms related to the embodiments of the present disclosure will be interpreted and explained.

[0015] Bandwidth is the amount of data transmitted within a unit of time. Bandwidth can be measured in bits per second (bps), kilobits per second (kbps), megabits per second (Mbps), gigabits per second (Gbps), etc.

[0016] Memory is a device in a computer system for temporarily storing data and instructions to facilitate rapid access and execution by the processor. Memory may include random access memory (RAM), such as dynamic random access memory (DRAM) and static random access memory (SRAM).

[0017] Memory bandwidth, also known as memory bandwidth resources, is the amount of data that a memory can transmit within a unit of time. The unit of memory bandwidth may be bps, kbps, Mbps, Gbps, etc.

[0018] An SoC is an integrated circuit that integrates multiple modules / units of a computer system on a single chip, including a central processing unit (CPU), a graphics processing unit (GPU), SRAM, an I / O interface, a digital signal processing unit (DSP), a deep learning processing unit (DPU), a neural processing unit (NPU) and / or a tensor processing unit (TPU), an image signal processing unit (ISP), a memory controller, etc.

[0019] <Application Summary> An operating system may be running on an integrated circuit. For example, the integrated circuit may include a processor, and the operating system may run on the processor. The processor may establish communication with memory (e.g., DRAM, SRAM, etc.). Thus, during operation of the operating system, the operating system may load instructions into the memory, and the processor may read instructions and data from the memory and perform various operations, such as arithmetic operations, logical operations, and data transfer, in response to the instructions, and write the results of the instruction execution to the memory.

[0020] Multiple operating systems can run on a high performance integrated circuit, such as a high performance SoC.

[0021] FIG. 1 is a block diagram of the structure of a cockpit-driving integrated system provided in an exemplary embodiment of the present disclosure.

[0022] In an embodiment of the present disclosure, the cockpit-driving integrated system includes a hardware portion and a software portion. Here, the hardware portion of the cockpit-driving integrated system includes an integrated circuit, and the software portion includes a cockpit operating system (hereinafter referred to as the cockpit system) and an intelligent driving operating system (hereinafter referred to as the intelligent driving system) that run simultaneously on the integrated circuit. That is, the cockpit-driving integrated system is a system that simultaneously runs a cockpit system and an intelligent driving system on an integrated circuit. Here, the intelligent driving system is primarily responsible for the autonomous driving and safety of the vehicle, including environmental sensing, route planning, decision-making, and control. The cockpit system is primarily responsible for the driving and riding experience and human-computer interaction within the vehicle, including information and entertainment, meter display, media playback, and environmental control. Compared to independent cockpit systems and intelligent driving systems, the cockpit-driving integrated system has a higher degree of integration and intelligence, which is advantageous for improving the driving safety, comfort, and driving and riding experience of the vehicle.

[0023] Here, the cockpit-driving integrated system can be applied to autonomous vehicles, such as cars (intelligent connected vehicles), ships, trains, subways, and airplanes, as well as various robots, such as service robots, transport robots, automated guided vehicles (AGVs), unmanned ground vehicles (UGVs), and various construction machines.

[0024] As shown in FIG. 1 , in one embodiment, the cockpit-driving integrated system may include SoC 100. In one example, SoC 100 may include one or more processors, such as one or more CPUs, one or more GPUs, one or more ISPs, one or more DSPs, one or more DPUs, one or more NPUs, and / or one or more TPUs. These processors may be used to provide computing resources to multiple operating systems to support each operating system in implementing its functionality.

[0025] In one embodiment, the cockpit-driving integrated system may further include a memory device 200. The memory device 200 may store instructions and data, and the processor may read and execute instructions in the memory device 200 and write the execution results to the memory device 200. In one example, the memory device 200 may include memory, such as DRAM and / or SRAM. Here, the memory device 200 may be integrated into the SoC 100, such as an SRAM, and may be part of the SoC 100, or the memory device 200 may be an independent device outside the SoC 100, such as a DRAM, although the embodiments of the present disclosure are not specifically limited thereto. In one example, the SoC may further include a memory controller 110 that may manage and coordinate access to memory (e.g., SRAM and DRAM) by each processor.

[0026] In one embodiment, multiple operating systems, for example, OS1 to OSN, may be running on the SoC 100. Illustratively, the multiple operating systems may include at least a cockpit operating system and an intelligent drive operating system.

[0027] During operation, multiple operating systems can call on the processor to access memory, for example, to read instructions in memory or to write the results of executing instructions to memory, i.e., multiple operating systems share memory bandwidth, for example, DRAM bandwidth and / or SRAM bandwidth.

[0028] In one implementation, memory bandwidth can be pre-allocated to each operating system. For example, assume that three operating systems, OS1, OS2, and OS3, are running on an SoC and the DRAM bandwidth is 100 Gbps. For example, 50 Gbps of DRAM bandwidth can be allocated to OS1, 30 Gbps of DRAM bandwidth can be allocated to OS2, and 20 Gbps of DRAM bandwidth can be allocated to OS3. However, because different operating systems have different functions and perform different tasks, the DRAM bandwidth required by each operating system differs. Furthermore, as the tasks performed by each operating system change, the DRAM bandwidth required by each operating system also changes dynamically.

[0029] Take for example that the multiple operating systems include an intelligent drive system and a cockpit system.

[0030] For example, when the vehicle is in an intelligent driving state, the intelligent driving system needs to execute an intelligent driving task. In this case, a large amount of instructions and data related to the intelligent driving task is loaded into the DRAM by the intelligent driving system, read and executed by the processor, and the processor also writes a large amount of instruction execution results to the DRAM. Therefore, the DRAM bandwidth required by the intelligent driving system is large. In a parking scenario, the intelligent driving system does not need to execute an intelligent driving task, so the instructions and data written to the DRAM by the intelligent driving system are small, and the DRAM bandwidth required by the intelligent driving system is small.

[0031] For example, when a vehicle plays media, the cockpit system needs to perform the media playback task. In this case, instructions and media data are loaded into DRAM by the cockpit system, read and executed by the processor, and the processor writes the instruction execution results to DRAM. For example, the processor can decode the read media data and write the decoded media data to DRAM. Therefore, the DRAM bandwidth required by the cockpit system is large. In a standby scenario, the cockpit system does not need to perform tasks such as media playback, navigation, or games, so the instructions and data written to DRAM by the cockpit system are small, and the DRAM bandwidth required by the cockpit system is small.

[0032] Because the memory bandwidth required by each operating system changes dynamically, the method of pre-allocating memory bandwidth cannot realize rational utilization of memory bandwidth, and further leads to memory bandwidth waste, and the memory bandwidth allocated to the operating system cannot meet the business requirements of the operating system.

[0033] Take for example that the multiple operating systems include an intelligent drive system and a cockpit system.

[0034] For example, assume that the DRAM bandwidth allocated to the intelligent drive system is 50 Gbps and the DRAM bandwidth allocated to the cockpit system is 30 Gbps. When the vehicle is parked, the intelligent drive system does not need to perform intelligent drive tasks and can enter an idle state, resulting in, for example, 40 Gbps of idle DRAM bandwidth. In this case, even if the cockpit system is running a game application that requires 40 Gbps of DRAM bandwidth, the cockpit system can only use the allocated 30 Gbps of DRAM bandwidth and cannot use the idle DRAM bandwidth of the intelligent drive system. In other words, the DRAM bandwidth allocated to one operating system cannot be used by the operations of other operating systems, which not only fails to improve the performance of the operations of the other operating systems but also results in wasted DRAM bandwidth.

[0035] For example, if the DRAM bandwidth allocated to OS1 is 50 Gbps and OS1's current business requires a DRAM bandwidth of 60 Gbps, the DRAM bandwidth that OS1 has cannot meet its own business requirements, which will affect the business performance of OS1.

[0036] As can be seen, when multiple operating systems are running on an integrated circuit, the bandwidth resources corresponding to the integrated circuit, such as memory bandwidth, have the problem of being allocated in an unreasonable manner, which affects the business performance of each operating system.

[0037] The embodiments of the present disclosure provide a bandwidth control method, device, integrated circuit, electronic device, and vehicle, which can more rationally allocate bandwidth resources corresponding to an integrated circuit when multiple operating systems are running on the integrated circuit, improve the performance of the operating systems, and reduce resource waste.

[0038] Exemplary Systems FIG. 2 is a structural schematic diagram of a bandwidth control system provided in an exemplary embodiment of the present disclosure.

[0039] As shown in FIG. 2, the bandwidth control system may include a first hardware unit 10, a second hardware unit 20 communicatively connected to the first hardware unit 10, a bandwidth sharing module 30, and multiple throttling modules 40.

[0040] The bandwidth sharing module 30 is installed between the first hardware unit 10 and the second hardware unit 20, and includes a cache queue for caching access instructions to the second hardware unit 20 by multiple operating systems, and the bandwidth sharing module 30 is used to generate a status value indicating the usage status of the cache queue.

[0041] A plurality of throttling modules 40 are installed in one-to-one correspondence with a plurality of operating systems, and each throttling module 40 is installed between the first hardware unit 10 and the bandwidth sharing module 30. Each throttling module 40 is used to determine a target bandwidth threshold corresponding to each operating system run by the first hardware unit 10 based on the state value and a plurality of throttling parameters preset for each operating system, and is also used to control the bandwidth of access to the second hardware unit 20 by each operating system run by the first hardware unit 10 based on the target bandwidth threshold corresponding to each operating system.

[0042] The first hardware unit 10 may include multiple functional modules 11 in an integrated circuit (e.g., an SoC). Each functional module 11 is used to realize one or more functions of the integrated circuit (e.g., an SoC). For example, the functional module 11 may be a CPU, a GPU, an NPU, a DPU, a TPU, an ISP, a DSP, etc. Also, the functional module 11 may be a core of a CPU, a streaming processor of a GPU, a computing unit of an NPU, etc. That is, each core of a CPU may be a functional module 11, each streaming processor of a GPU may be a functional module 11, and each computing unit of an NPU may be a functional module 11.

[0043] A plurality of operating systems, such as an intelligent drive system, a cockpit system, and / or other operating systems, may be running on the first hardware unit 10. Here, a plurality of operating systems are running on the first hardware unit 10. Different operating systems can run in different functional modules 11, in other words, different functional modules 11 can be managed by different operating systems.

[0044] For example, the first hardware unit 10 includes three operating systems, OS1 to OS3, and the CPU includes eight cores, core 1 to core 8. OS1 runs on core 1 and core 2 (in other words, core 1 and core 2 are managed by OS1), OS2 runs on core 3 to core 6 (in other words, core 3 to core 6 are managed by OS2), and OS3 runs on core 7 and core 8 (in other words, core 7 and core 8 are managed by OS3). Similarly, one operating system can manage one or more streaming processors of a GPU, and one operating system can manage one or more computing units of an NPU.

[0045] If an ISP includes multiple ISP units, one operating system can manage at least one ISP unit, and different ISP units can be managed by different operating systems. Similarly, if a DSP includes multiple DSP units, one operating system can manage at least one DSP unit, and different DSP units can be managed by different operating systems.

[0046] In one implementation, each functional module 11 of the first hardware unit 10 can communicate with, eg, access, another hardware unit (eg, the second hardware 20).

[0047] Illustratively, the first hardware unit 10 and the second hardware unit 20 can communicate via a bus, where the bus may specifically be an AXI (advanced extensible interface) bus, and the AXI bus may include five channels, for example, as follows: A read address channel (AR) for transmitting addresses for read accesses. A read data channel (R) for transmitting data for read accesses. A write address channel (AW) for transmitting addresses for write accesses. A write data channel (W) for transmitting data for write accesses. A write response channel (B) for transmitting responses to write accesses.

[0048] Of course, other bus protocols, such as an advanced high-performance bus (AHB), an inter-integrated circuit (I2C) bus, or a HyperTransport bus, may also be used, and the embodiments of the present disclosure are not limited thereto.

[0049] The second hardware unit 20 may include a memory or another hardware unit that communicates with the first hardware unit 10. Illustratively, the second hardware unit 20 may be a DRAM and / or an SRAM. Accordingly, the bus may be a DRAM bus for a functional module 11 (e.g., a CPU) in the SoC to access the DRAM, or an SRAM bus for accessing the SRAM. Accordingly, the memory bandwidth is the bandwidth of the DRAM bus (abbreviated as DRAM bandwidth) and / or the bandwidth of the SRAM bus (abbreviated as SRAM bandwidth).

[0050] In the embodiment of the present disclosure, the first hardware unit 10 and the second hardware unit 20 may be located on different chips, for example, the first hardware unit 10 may be located on an SoC and the second hardware unit 20 may be a DRAM installed independently of the SoC, or the first hardware unit 10 and the second hardware unit 20 may be located on the same chip, for example, the first hardware unit 10 may be located on an SoC and the second hardware unit 20 may be an SRAM integrated into the SoC.

[0051] Note that when the first hardware unit 10 includes multiple operating systems, each operating system calls the functional module 11 managed by it to realize the corresponding function. Accordingly, each functional module 11 can access the second hardware unit 20 (e.g., memory) to read instructions and data, or write the results of instruction execution, in order to realize its function. Therefore, the access of each functional module 11 to the second hardware unit 20 can be described as each operating system accessing the second hardware unit 20, or as each operating system calling the functional module 11 managed by it to access the second hardware unit 20. For example, the access of core 1 and core 2 of the CPU to the DRAM can be described as OS1 accessing the DRAM, and the access of a DSP managed by OS2 to the DRAM can be described as OS2 accessing the DRAM.

[0052] To easily explain the communication connection relationship between each module / unit in the bandwidth control system, the functional module 11 of the first hardware unit 10 accesses the second hardware unit 20 as an example, and the transmission direction of this access is called the downstream direction, and the opposite direction of the transmission of this access is called the upstream direction.

[0053] In one implementation, the bandwidth control system may further include a bandwidth sharing module 30. The bandwidth sharing module 30 is located downstream of each functional module 11 and upstream of the second hardware unit 20. The bandwidth sharing module 30 is communicatively connected to each functional module 11 and the second hardware unit 20. In this way, accesses from each functional module 11 can first reach the bandwidth sharing module 30 before being transmitted to the second hardware unit 20.

[0054] In one implementation, the bandwidth sharing module 30 includes a cache queue that can be used to cache accessed instructions and / or data. When an access from each functional module 11 arrives at the bandwidth sharing module 30, it can be first queued and cached in the cache queue. The bandwidth sharing module 30 then schedules the access in the cache queue according to a preset scheduling policy and transmits the access to the second hardware unit 20. The preset scheduling policy can include, for example, first-in-first-out (FIFO) scheduling, priority scheduling, round-robin scheduling, etc. Here, the cache queue can include a read queue and a write queue, where instructions and / or data for read accesses from each functional module 11 can be queued in the read queue, and instructions and / or data for write accesses from each functional module 11 can be queued in the write queue. Of course, the read queue and the write queue can be merged into one queue, and instructions and / or data for both read accesses and write accesses from the functional modules 11 can be queued in this queue. Here, the cache queue can be a parallel queue or a serial queue, and the embodiment of the present disclosure is not limited thereto.

[0055] In one implementation, the bandwidth sharing module 30 may include, for example, a memory controller, or the functionality of the bandwidth sharing module 30 may be implemented by, a memory controller. Here, the memory controller may be, for example, a DDR controller (DDRC) or another type of memory controller. Accordingly, the cache queue may be a read queue (read_queue) or a write queue (write_queue) in the memory controller.

[0056] As can be seen from this, the bandwidth sharing module 30 can manage and schedule the access of each functional module 11, thereby allowing each functional module 11 to efficiently utilize memory bandwidth and also avoiding conflicts between each module when accessing the second hardware unit 20, thereby improving system stability.

[0057] Each functional module 11 can be classified based on the correspondence between each functional module 11 and each operating system. For example, it can be understood that modules that run OS1 and modules that are managed by OS1 are classified as OS1 functional modules 11, modules that run OS2 and modules that are managed by OS2 are classified as OS2 functional modules 11, and modules that run OSN and modules that are managed by OSN are classified as OSN functional modules 11.

[0058] In an embodiment of the present disclosure, the bandwidth control system may further include a plurality of throttling modules 40, e.g., throttling module 40-1 to throttling module 40-N, which are installed in one-to-one correspondence with a plurality of operating systems. Here, a throttling module 40 may be installed in a communication link between a functional module 11 of a corresponding operating system and the bandwidth sharing module 30. That is, the throttling module 40 is installed downstream of the functional module 11, and the bandwidth sharing module 30 is installed downstream of the throttling module 40. For example, the throttling module 40-1 may be installed in the communication link between the functional module 11 of OS1 and the bandwidth sharing module 30, the throttling module 40-2 may be installed in the communication link between the functional module 11 of OS2 and the bandwidth sharing module 30, and so on. That is, the throttling modules 40 and the functional modules 11 corresponding to the same operating system communicate with each other.

[0059] In this way, when an operating system accesses the second hardware unit 20, the access (e.g., instructions, data, etc.) first passes through the throttling module 40 corresponding to the operating system, and then is transmitted to the second hardware unit 20 via the bandwidth sharing module 30. Here, when the access passes through the throttling module 40, the throttling module 40 can throttle the access. In this way, the transmission bandwidth of the access downstream can be controlled. That is, the bandwidth of the access of the operating system to the second hardware unit 20 is controlled.

[0060] In one implementation, each throttling module 40 can control the bandwidth of access by its corresponding operating system to the second hardware unit 20 based on the usage status of the cache queue. For example, when the number of cached accesses in the cache queue is high, i.e., when the cache queue is congested, the throttling module 40 can control the corresponding operating system to access the second hardware unit 20 at a low bandwidth, i.e., allocate a low memory bandwidth to the operating system. When the number of cached accesses in the cache queue is low, i.e., when the cache queue is idle, the throttling module 40 can allow the corresponding operating system to access the second hardware unit 20 at a higher bandwidth, i.e., allocate a higher memory bandwidth to the operating system.

[0061] As can be seen from this, in the bandwidth scheduling system provided in the embodiment of the present disclosure, a throttling module 40 is installed corresponding to each operating system, and the throttling module 40 dynamically controls the access bandwidth of each operating system to the second hardware unit 20 according to the usage status of the cache queue, so as to make the allocation of bandwidth resources of the second hardware unit 20 more rational, which can not only improve the business performance of each operating system, but also improve the utilization rate of bandwidth resources and reduce the waste of bandwidth resources.

[0062] Exemplary Methods FIG. 3 is a flowchart of a bandwidth control method provided in an exemplary embodiment of the present disclosure.

[0063] Hereinafter, each step of this method will be exemplarily described with reference to Fig. 3. Hereinafter, each step of this method can be performed by any throttling module 40 in the bandwidth control system. For ease of description, any operating system among the multiple operating systems running on the first hardware unit 10 will be referred to as a first operating system, and the throttling module 40 corresponding to the first operating system will be referred to as a first throttling module.

[0064] In one embodiment, the method may include steps S110 to S130.

[0065] In step S110, the usage status of the cache queue is acquired.

[0066] Here, the cache queue may be any queue in the bandwidth sharing module 30. The cache queue is used to cache accesses to the second hardware unit 20 by multiple operating systems, for example, caching instructions and / or data of the accesses. The usage status of the cache queue may include any parameter value or indication information that can characterize the idle / congested state of the cache queue.

[0067] In one implementation, the usage status of the cache queue may be indicated by the status value of the cache queue, or may be indicated by other information such as a status level, a flag bit, etc., which are not specifically limited herein.

[0068] Exemplarily, when the bandwidth sharing module 30 includes a read queue and a write queue, the cache queue may include a read queue and / or a write queue, where the read queue is used to cache read access instructions of the multiple operating systems to the second hardware unit 20, and the write queue is used to cache write access instructions of the multiple operating systems to the second hardware unit 20. Accordingly, the status value of the cache queue may include a status value of the read queue and / or a status value of the write queue.

[0069] Illustratively, if a read queue and a write queue are merged into a read-write queue, the state value of the cache queue may include the state value of the read-write queue.

[0070] Here, the cache queue status value may characterize the idleness or congestion of the cache queue, which in turn relates to the access bandwidth to the second hardware unit 20 by each operating system.

[0071] For example, when each operating system is busy, its accesses to the second hardware unit 20 increase. Therefore, a large number of accesses enter the cache queue, and the number of accesses entering the cache queue becomes greater than the number of accesses leaving the cache queue. This increases the number of accesses cached in the cache queue, and reduces the idleness of the cache queue. Accordingly, the bandwidth of each operating system's access to the second hardware unit 20 also increases, and the idle bandwidth resources of the second hardware unit 20 decrease.

[0072] Similarly, when the operations of each operating system are idle, the accesses of each operating system to the second hardware unit 20 are reduced. Therefore, only a small number of accesses enter the cache queue, and the number of accesses entering the cache queue is less than the number of accesses leaving the cache queue. As a result, the number of accesses cached in the cache queue decreases, and the idleness of the cache queue increases. At the same time, the bandwidth of each operating system's access to the second hardware unit 20 also decreases, and the idle bandwidth resources of the second hardware unit 20 increase.

[0073] In one implementation, a cache queue may include multiple entries, each of which can cache one access instruction. Here, in a read queue, the entries may be read entries, and each read entry can cache one read access instruction, and in a write queue, the entries may be write entries, and each write entry can cache one write access instruction and can also cache data to be written. Accordingly, the status value of a cache queue may include the number of available entries (also referred to as the number of idle entries) or the number of unavailable entries (also referred to as the number of non-idle entries) in the cache queue.

[0074] Illustratively, if the cache queue contains 10 entries and instructions are cached in 8 entries, the number of available entries in the cache queue is 2 and the number of unavailable entries is 8; if instructions are cached in 2 entries, the number of available entries in the cache queue is 8 and the number of unavailable entries is 2.

[0075] It can be seen that when the state value of the cache queue includes the number of available entries in the cache queue, a larger state value indicates more idle bandwidth resources in the second hardware unit 20, and a smaller state value indicates fewer idle bandwidth resources in the second hardware unit 20. When the state value of the cache queue includes the number of unavailable entries in the cache queue, a larger state value indicates fewer idle bandwidth resources in the second hardware unit 20, and a smaller state value indicates more idle bandwidth resources in the second hardware unit 20.

[0076] In one implementation, the bandwidth sharing module 30 may send a status value of the cache queue to the first throttling module, such as sending the number of available or unavailable entries in the cache queue to the first throttling module, where if the bandwidth sharing module 30 includes a read queue and a write queue, the bandwidth sharing module 30 may send the status value of the read queue and / or the status value of the write queue to the first throttling module.

[0077] In one example, the bandwidth sharing module 30 can monitor a state value of the cache queue, such as the number of available or unavailable entries in the cache queue. When the state value of the cache queue changes, the bandwidth sharing module 30 sends the changed state value to the first throttling module; for example, if the number of available or unavailable entries in the cache queue changes, the bandwidth sharing module 30 sends the changed number of available or unavailable entries to the first throttling module.

[0078] In one example, the bandwidth sharing module 30 may periodically transmit the state value of the cache queue to the first throttling module. For example, a timer may be provided in the bandwidth sharing module 30, and the timer may periodically time out at a preset time, and the bandwidth sharing module 30 may transmit the state value of the cache queue to the first throttling module in response to a timeout signal from the timer.

[0079] In one example, both the entry and exit of accesses into the cache queue change the number of available entries and the number of unavailable entries in the cache queue, so the bandwidth sharing module 30 can monitor the entry and exit of accesses into the cache queue, and when the entry and exit of accesses into the cache queue are monitored, the bandwidth sharing module 30 can obtain the latest number of available entries and the latest number of unavailable entries in the cache queue and send the obtained number of available entries and the latest number of unavailable entries to the first throttling module.

[0080] In step S120, a first throttling parameter of the first operating system is determined based on the usage status of the cache queue.

[0081] Here, the first throttling parameter throttles the access of the first operating system to the second hardware unit 20 to control the bandwidth of the access of the first operating system to the second hardware unit 20 .

[0082] In one implementation, a first throttling parameter of the first operating system can be determined based on the state value of the cache queue, where the first throttling parameter can include a target bandwidth threshold of the first operating system.

[0083] In one implementation, multiple throttling parameters can be preset for the first operating system, and each throttling parameter can include a preset bandwidth threshold. A correspondence relationship between multiple state values ​​and multiple throttling parameters of the first operating system can also be preset. After obtaining the state value of the cache queue, the throttling parameter corresponding to the state value of the cache queue can be determined as the first throttling parameter based on the correspondence relationship.

[0084] In addition, in a scenario with multiple operating systems, the operations of different operating systems may be different, and the requirements for the bandwidth of the second hardware unit 20 may also be different. Therefore, for the same state value, the throttling parameters of each operating system may be the same or different. Specifically, they can be reasonably set based on the business requirements of each operating system, and are not specifically limited here.

[0085] For example, a correspondence between the number of available entries (or the number of unavailable entries) in the cache queue and the bandwidth threshold of each operating system can be preset, and this correspondence can be stored in a register corresponding to the first throttling module 40. Here, each throttling module 40 can correspond to one register, or multiple throttling modules 40 can share a register, and this is not limited here.

[0086] Illustratively, if the cache queue state value includes the number of available entries in the cache queue, the bandwidth threshold for each operating system may increase as the number of available entries in the cache queue increases. Similarly, if the cache queue state value includes the number of unavailable entries in the cache queue, the bandwidth threshold for each operating system may decrease as the number of unavailable entries in the cache queue increases. That is, the more idle bandwidth resources in the second hardware unit 20, the higher the bandwidth threshold for each operating system; and the fewer idle bandwidth resources in the second hardware unit 20, the lower the bandwidth threshold for each operating system.

[0087] Here, increasing the bandwidth threshold of each operating system as the number of available entries in the cache queue increases may include continuously increasing the bandwidth threshold of each operating system as the number of available entries in the cache queue increases, or intermittently increasing the bandwidth threshold of each operating system as the number of available entries in the cache queue increases.Decreasing the bandwidth threshold of each operating system as the number of unavailable entries in the cache queue increases may include continuously decreasing the bandwidth threshold of each operating system as the number of unavailable entries in the cache queue increases, or intermittently decreasing the bandwidth threshold of each operating system as the number of unavailable entries in the cache queue increases.

[0088] In other words, the correspondence between the number of available entries in the cache queue and the bandwidth threshold of each operating system can be flexibly set according to the actual throttling requirements, and the embodiments of the present disclosure are not limited thereto.

[0089] For example, assume that the bandwidth resource of the second hardware unit 20 is 100 Gbps and the number of entries in the cache queue is 100. The correspondence between the number of available entries in the cache queue and the bandwidth threshold of each operating system is as shown in Table 1. Note that the values ​​disclosed in Table 1 are for illustrative purposes only and do not specifically limit the embodiments of the present disclosure.

[0090] [Table 1]

[0091] In this way, the first throttling module can determine a target bandwidth threshold corresponding to the obtained number of available entries from a plurality of bandwidth thresholds corresponding to the first operating system based on the number of available entries sent from the bandwidth sharing module 30.

[0092] Exemplarily, when the number of available entries in the cache queue is 10, throttling module 40-1 may determine that the target bandwidth threshold for OS1 is 50 Gbps, throttling module 40-2 may determine that the target bandwidth threshold for OS2 is 30 Gbps, and throttling module 40-3 may determine that the target bandwidth threshold for OS3 is 20 Gbps. When the number of available entries in the cache queue is 50, throttling module 40-1 may determine that the target bandwidth threshold for OS1 is 70 Gbps, throttling module 40-2 may determine that the target bandwidth threshold for OS2 is 50 Gbps, and throttling module 40-3 may determine that the target bandwidth threshold for OS3 is 30 Gbps.

[0093] In one implementation, when the cache queue includes a read queue and a write queue, throttling parameters can be set for the read access and the write access of the first operating system, respectively, where the throttling parameters for the read access and the write access corresponding to the same state value may be the same or different.

[0094] For example, as shown in Table 2, a correspondence between the number of available entries in the read queue and the read bandwidth threshold of each operating system can be preset.

[0095] [Table 2]

[0096] For example, as shown in Table 3, the correspondence between the number of available entries in the write queue and the write bandwidth threshold of each operating system can be preset.

[0097] [Table 3]

[0098] It should be noted that the values ​​disclosed in Tables 2 and 3 are merely illustrative and do not specifically limit the embodiments of the present invention.

[0099] In this way, it is possible to throttle the read access and write access of the first operating system.

[0100] In step S130, the bandwidth of the first operating system's access to the second hardware unit is controlled based on the first throttling parameter.

[0101] In one implementation, when the first operating system accesses the second hardware unit 20 via the first throttling module, the first throttling module can throttle the access based on a target bandwidth threshold of the first operating system so that the bandwidth of the first operating system's access to the second hardware unit 20 is equal to or less than the target bandwidth threshold.

[0102] For example, referring to Table 1, when the number of available entries in the cache queue is 10, the target bandwidth threshold of OS1 is 50 Gbps, so the throttling module 40-1 can throttle the bandwidth of OS1's access to the second hardware unit 20 to 50 Gbps or less. In comparison, when the number of available entries in the cache queue is 50, the target bandwidth threshold of OS1 is 70 Gbps, so the throttling module 40-1 can throttle the bandwidth of OS1's access to the second hardware unit 20 to 70 Gbps or less.

[0103] In addition, while each operating system is running, the amount of access by each operating system to the second hardware unit 20 changes dynamically, and accordingly, the number of available entries in the cache queue changes dynamically, so the target bandwidth threshold of the first operating system also changes dynamically. In other words, the first throttling module dynamically controls the bandwidth of the first operating system's access to the second hardware unit 20.

[0104] FIG. 4 is a schematic diagram of dynamically controlling access bandwidth provided in an exemplary embodiment of the present disclosure.

[0105] For example, when the number of available entries in the cache queue is 50, the target bandwidth threshold for OS1 is 70 Gbps and the target bandwidth threshold for OS2 is 50 Gbps. Therefore, when OS1 accesses the second hardware unit 20, the throttling module 40-1 can throttle the bandwidth of OS1's access to the second hardware unit 20 to 70 Gbps. At this time, when OS2 also accesses the second hardware unit 20, the access of OS2 also enters the cache queue, so the number of accesses entering the cache queue increases and the number of available entries in the cache queue decreases, for example, the number of available entries decreases to 10. At this time, the bandwidth sharing module 30 can send the new number of available entries, 10, to each throttling module 40. After receiving the new number of available entries, 10, the throttling module 40-1 determines to reduce the target bandwidth threshold for OS1 to 50 Gbps, and therefore reduces the bandwidth of OS1's access to the second hardware unit 20 to 50 Gbps. Similarly, after receiving the new number of available entries, 10, the throttling module 40-2 determines to reduce the target bandwidth threshold for OS2 to 30 Gbps, and therefore reduces the bandwidth of OS2's access to the second hardware 20 to 30 Gbps.

[0106] As can be seen, when the number of available entries in the cache queue is small, i.e., when the idle bandwidth resources of the second hardware unit 20 are small, the first throttling module can control the first operating system to access the second hardware unit 20 at a low bandwidth to balance with the demands of other operating system operations on bandwidth resources. When the number of available entries in the cache queue is large, i.e., when the idle bandwidth resources of the second hardware unit 20 are large, the first throttling module can control the first operating system to access the second hardware unit 20 at a high bandwidth to fully utilize the bandwidth resources of the second hardware unit 20 and improve the operation performance of the first operating system.

[0107] In addition, when the first throttling parameters include the number of available entries in the write queue and the number of available entries in the read queue, the first throttling module throttles the read access and the write access of the first operating system, respectively, that is, it can control the bandwidth of the write access by the first operating system to the second hardware unit 20, and it can also control the bandwidth of the read access by the first operating system to the second hardware unit 20.

[0108] As can be seen from the above technical solutions, the method provided in the embodiments of the present disclosure dynamically controls the access bandwidth of each operating system to the second hardware unit 20 based on the usage status of the cache queue, making the allocation of bandwidth resources of the second hardware unit 20 more rational, which not only improves the business performance of each operating system, but also improves the utilization rate of bandwidth resources and reduces the waste of bandwidth resources.

[0109] In one implementation, the state value of the cache queue may include multiple state value intervals, where the multiple state value intervals are separated by multiple state thresholds, and in some examples, the state thresholds may also be referred to as watermarks, and the state value intervals may also be referred to as watermark intervals.

[0110] The number of state thresholds may be m, where m is an integer equal to or greater than 1. Then, the m state thresholds may form m+1 state value intervals in ascending or descending order of numerical values, which will be specifically described below with reference to examples.

[0111] Exemplarily, the state threshold may be an available entry number threshold. If the cache queue contains 100 entries, the value range of the available entry number threshold should be 0 to 100. For example, there are m available entry number thresholds W1 to W m are W1 90, W2 80, …, W m-1 is 20 and W m is 10. The m available entry number thresholds can form a total of m+1 state value intervals, where, for example, a number of available entries greater than or equal to 90 corresponds to state value interval 1, a number of available entries less than or equal to 90 and greater than or equal to 80 corresponds to state value interval 2, a number of available entries less than or equal to 20 and greater than or equal to 10 corresponds to state value interval m, and a number of available entries less than or equal to 10 corresponds to state value interval m+1.

[0112] For example, the state thresholds can be stored in registers, and each throttling module 40 can read the state thresholds from the registers. Here, each throttling module 40 can have a register, and each throttling module 40 can have a state threshold set, and the state thresholds set for each throttling module 40 can be the same or different. Of course, each throttling module 40 can share a register, and each throttling module 40 can use the same state thresholds. Furthermore, the state thresholds can be flexibly set by changing the contents of the registers to meet different bandwidth control requirements.

[0113] Here, different state value intervals may correspond to different throttling parameters. For the same state value interval, the throttling parameters set for different operating systems may be the same or different. Table 4 shows an example of the relationship between each bandwidth threshold and each state value interval for each operating system, taking the bandwidth resource of the second hardware unit 20 as an example of 100 Gbps, where W represents the number of available entries in the cache queue.

[0114] [Table 4]

[0115] It should be noted that the values ​​disclosed in Table 4 are merely illustrative and do not specifically limit the embodiments of the present disclosure.

[0116] For example, the relationship between the bandwidth threshold and the state value interval for each operating system may be stored in a register. Here, each throttling module 40 may have its own register, or the throttling modules 40 may share a register; this is not a specific limitation. Furthermore, the relationship between the bandwidth threshold and the state value interval for each operating system may be flexibly set by changing the contents of the register to meet different bandwidth control requirements.

[0117] FIG. 5 is a flowchart of step S120 of the bandwidth control method provided in an exemplary embodiment of the present disclosure.

[0118] As shown in FIG. 5, in one implementation, step S120 may include step S121 and step S122.

[0119] In step S121, a first interval corresponding to the state value of the cache queue is determined from a plurality of state value intervals.

[0120] Illustratively, the state value of the cache queue can be numerically compared with at least one state threshold, and a state value interval in which the state value is located is determined based on the numerical relationship between the state value and the at least one state threshold, and this state value interval is designated as the first interval.

[0121] In step S122, the throttling parameter corresponding to the first interval is determined as the first throttling parameter.

[0122] Exemplarily, the first throttling module may determine a throttling threshold of a first operating system corresponding to the first interval as the target bandwidth threshold of the first operating system. For example, the throttling module 40-1 may determine a bandwidth threshold of OS1 corresponding to the first interval as the target bandwidth threshold of OS1, and the throttling module 40-2 may determine a bandwidth threshold of OS2 corresponding to the first interval as the target bandwidth threshold of OS2.

[0123] FIG. 6 is a schematic diagram of determining a target bandwidth threshold provided in an exemplary embodiment of the present disclosure.

[0124] For example, as shown in FIG. 6, referring to Table 4, the m available entry number thresholds are W1=90, W2=80, ..., W m-1 is 20 and W m For example, if the number of available entries W in the cache queue is 91, it can be determined by comparison that W is greater than or equal to W1, so the first interval is state value interval 1, and the target bandwidth threshold of OS1 is then 90 Gbps, the target bandwidth threshold of OS2 is 70 Gbps, and the target bandwidth threshold of OS3 is 60 Gbps. If the number of available entries W in the cache queue is 85, it can be determined by comparison that W1 is greater than W and W is greater than or equal to W2, so the first interval is state value interval 2, and the target bandwidth threshold of OS1 is then 85 Gbps, the target bandwidth threshold of OS2 is 65 Gbps, and the target bandwidth threshold of OS3 is 55 Gbps. If the number of available entries W in the cache queue is 8, it can be determined by comparison that W is greater than or equal to W2, so the first interval is state value interval 2, and the target bandwidth threshold of OS1 is then 85 Gbps, the target bandwidth threshold of OS2 is 65 Gbps, and the target bandwidth threshold of OS3 is 55 Gbps. m Therefore, the first interval is state value interval m+1, and the target bandwidth threshold of OS1 is 50 Gbps, the target bandwidth threshold of OS2 is 30 Gbps, and the target bandwidth threshold of OS3 is 20 Gbps.

[0125] In one implementation, the first throttling module may further determine a target bandwidth threshold for the first operating system by sequentially comparing the number of available entries in the cache queue with each available entry threshold, in order of highest or lowest available entry threshold.

[0126] Referring to Table 4, take the throttling module 40-1 determining the target bandwidth threshold for OS1 as an example. If the number of available entries W is 95, the throttling module 40-1 first compares the number of available entries W with the available entry number threshold W1. Because W is greater than or equal to W1, the throttling module 40-1 can determine that the target bandwidth threshold for OS1 is 90 Gbps without performing any subsequent comparisons. If the number of available entries W is 85, the throttling module 40-1 first compares the number of available entries W with the available entry number threshold W2. Because W is greater than or equal to W2, the throttling module 40-1 can determine that the target bandwidth threshold for OS1 is 85 Gbps without performing any subsequent comparisons.

[0127] As can be seen, this implementation can reduce the number of comparisons, improve the speed at which the first throttling module determines the target bandwidth threshold, and reduce the delay in controlling the bandwidth by the first throttling module.

[0128] In the embodiment of the present disclosure, the first throttling module may employ a bandwidth throttling scheme to control the bandwidth of the first operating system's access to the second hardware unit 20, or may employ an outstanding request throttling scheme to control the bandwidth of the first operating system's access to the second hardware unit 20. Alternatively, the first throttling module may employ a combined scheme of bandwidth throttling and outstanding request throttling to control the bandwidth of the first operating system's access to the second hardware unit 20. Naturally, the first throttling module may employ other restriction schemes to control the bandwidth of the first operating system's access to the second hardware unit 20, and the embodiment of the present disclosure is not limited thereto.

[0129] In another embodiment of the present disclosure, the present disclosure provides a bandwidth control method, comprising: determining a status value indicating a usage status of a cache queue for caching access instructions to the second hardware unit 20 by each of the operating systems operated by the first hardware unit 10; determining a target bandwidth threshold for each operating system run by the first hardware unit 10 based on the state value and a plurality of throttling parameters preset for each operating system; and controlling the bandwidth of access to the second hardware unit 20 by each operating system run by the first hardware unit 10 based on a target bandwidth threshold value corresponding to each operating system.

[0130] In one implementation, the step of controlling the bandwidth of access to the second hardware unit 20 by each operating system run by the first hardware unit 10 based on a target bandwidth threshold corresponding to each operating system includes a step of controlling the bandwidth of access to the second hardware unit 20 by each operating system run by the first hardware unit 10 based on a target bandwidth threshold corresponding to each operating system so that it is equal to or less than the target bandwidth threshold corresponding to each operating system.

[0131] In one implementation, the step of determining a state value indicating the usage status of the cache queue includes the steps of determining the number of available entries of a plurality of entries in the cache queue for caching access instructions, and determining the state value based on the number of available entries of the plurality of entries.

[0132] In one implementation, the step of determining a target bandwidth threshold corresponding to each operating system run by the first hardware unit 10 based on the state value and a plurality of throttling parameters preset for each operating system includes the steps of determining a first throttling parameter corresponding to each operating system from a plurality of throttling parameters preset for each operating system based on the state value, and determining a target bandwidth threshold corresponding to each operating system based on the first throttling parameter corresponding to each operating system.

[0133] In one implementation, the step of determining a first throttling parameter corresponding to each operating system from a plurality of throttling parameters preset for each operating system based on the state value includes the steps of determining a first interval corresponding to the state value from a plurality of preset state value intervals, and determining a first throttling parameter of the first interval corresponding to each operating system from a plurality of throttling parameters preset for each operating system.

[0134] The implementation of any of the steps in this embodiment has been described above, so a description thereof will be omitted here.

[0135] Exemplary Devices The bandwidth control method provided in the embodiments of the present disclosure has been introduced above. An integrated circuit (e.g., an SoC) or a first hardware unit in the SoC may include corresponding hardware and software for implementing the hardware functions to implement each function of the bandwidth control method.

[0136] Those skilled in the art can easily recognize that the embodiments of the present disclosure can be implemented in the form of hardware or in a combined form of software driving hardware by referring to the steps of the bandwidth control method described in the embodiments of the present disclosure. Whether a function is implemented in hardware or software driving hardware is determined by the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0137] FIG. 7 is a structural schematic diagram of a bandwidth control device provided in an exemplary embodiment of the present disclosure.

[0138] 7 , in one embodiment, the bandwidth control device 300 includes a first throttling module 310 communicatively connected to a first hardware unit. For example, the first throttling module 310 may be communicatively connected to at least one first functional module in the first hardware unit. Here, the first hardware unit runs multiple operating systems, and the first throttling module 310 corresponds to the first operating system. The first functional modules may include a functional module that runs the first operating system and a functional module managed by the first operating system. The first throttling module 310 is configured to acquire a usage status of a cache queue for caching accesses to a second hardware unit by the multiple operating systems run by the first hardware unit, determine a first throttling parameter for the first operating system based on the usage status of the cache queue, and control the bandwidth of accesses of the first operating system to the second hardware unit based on the first throttling parameter.

[0139] Here, the cache queue is used to cache accesses to the second hardware unit by multiple operating systems, for example, the cache queue is used to cache read access instructions and / or write access instructions to the second hardware unit by multiple operating systems.

[0140] In one implementation, the first throttling parameter includes a target bandwidth threshold for the first operating system, and the first throttling module 310 is configured to control the bandwidth of the first operating system's access to the second hardware unit so that it is equal to or less than the target bandwidth threshold.

[0141] In one implementation, the bandwidth control device 300 may further include a cache module 320. The cache module 320 is communicatively coupled to the first throttling module 310 and the second hardware unit. The cache module 320 may include a cache queue. The usage status of the cache queue may be indicated by a state value of the cache queue, the magnitude of the state value characterizing how idle or busy the cache queue is. The cache module 320 is configured to transmit the state value of the cache queue to the first throttling module 310.

[0142] In one example, the cache module 320 may be, for example, a bandwidth sharing module.

[0143] In one implementation, the cache queue may include multiple entries, each used to cache one access instruction, and the cache queue status value includes the number of available or unavailable entries in the cache queue. The cache module 320 is configured to send the number of available or unavailable entries in the cache queue to the first throttling module 310.

[0144] In one implementation, the first throttling module 310 is configured to determine a first throttling parameter from a plurality of throttling parameters of the first operating system based on the state value, where each throttling parameter includes a bandwidth threshold.

[0145] In one implementation, the first throttling module 310 is configured to determine a first interval corresponding to a state value from a plurality of state value intervals, where each state value interval corresponds to one throttling parameter, and determine the throttling parameter corresponding to the first interval as the first throttling parameter.

[0146] In one implementation, the plurality of state value intervals are separated by a plurality of state thresholds, and the first throttling module 310 is configured to determine the first interval based on a numerical relationship between the state value and the at least one state threshold.

[0147] As can be seen from the above technical solutions, the device provided in the embodiments of the present disclosure can dynamically control the access bandwidth of each operating system to the second hardware unit based on the usage status of the cache queue, making the allocation of bandwidth resources of the second hardware unit more rational, which can not only improve the business performance of each operating system, but also improve the utilization rate of bandwidth resources and reduce the waste of bandwidth resources.

[0148] Exemplary Integrated Circuits An embodiment of the present disclosure further provides an integrated circuit, which may be, for example, an SoC.

[0149] FIG. 8 is a structural schematic diagram of an integrated circuit provided in an exemplary embodiment of the present disclosure.

[0150] As shown in FIG. 8 , in one embodiment, the integrated circuit 1000 includes a first hardware unit 10 on which multiple operating systems run. Here, the first hardware unit 10 may include multiple functional modules in the integrated circuit 1000. Each functional module is used to implement one or more functions of the integrated circuit 1000. For example, the functional module may be a CPU, a GPU, an NPU, an ISP, a DSP, etc. Alternatively, the functional module may be a core of a CPU, a streaming processor of a GPU, a computing unit of an NPU, etc.

[0151] In one implementation, each functional module of the first hardware unit 10 can communicate with, eg, access, another hardware unit (eg, the second hardware unit 20).

[0152] Here, the second hardware unit 20 may include a storage device (e.g., memory) or another hardware unit that communicates with the first hardware unit 10. Illustratively, the second hardware unit 20 may be a DRAM and / or an SRAM. In one example, the second hardware unit 20 may be located on the integrated circuit 1000, for example, the second hardware unit 20 may be an SRAM integrated into the SoC. In another example, the second hardware unit 20 may be provided independently of the integrated circuit 1000, for example, the second hardware unit 20 may be a DRAM provided independently of the SoC.

[0153] In one embodiment, the integrated circuit 1000 further includes a plurality of throttling modules 40 communicatively connected to the first hardware unit 10 and arranged in one-to-one correspondence with a plurality of operating systems, and at least one throttling module 40 is configured to perform the function of the first throttling module in the bandwidth control device, for example, steps for implementing the bandwidth control method provided in an embodiment of the present disclosure.

[0154] In one example, the throttling module 40 can obtain the usage status of the cache queue, and determine the throttling parameters of the operating system corresponding to this throttling module 40 based on the usage status of the cache queue, and then the throttling module 40 can control the bandwidth of access to the second hardware unit 20 of the operating system corresponding to this throttling module 40 based on the throttling parameters of the operating system corresponding to it.

[0155] In one implementation, the integrated circuit 1000 may further include a bandwidth sharing module 30, which may also be referred to as a cache module.

[0156] In one example, the bandwidth sharing module 30 includes a cache queue. The usage status of the cache queue may be indicated by a status value of the cache queue, and the bandwidth sharing module 30 may transmit the status value of the cache queue to each throttling module 40.

[0157] As can be seen from the above technical solutions, the integrated circuit provided in the embodiments of the present disclosure can dynamically control the access bandwidth of each operating system to the second hardware unit based on the usage status of the cache queue, making the allocation of bandwidth resources of the second hardware unit more rational, which can not only improve the business performance of each operating system, but also improve the utilization rate of bandwidth resources and reduce the waste of bandwidth resources.

[0158] <Example Electronic Devices> An embodiment of the present disclosure provides an electronic device that can be used in a vehicle, for example, an intelligent connected vehicle, and may be, for example, an in-vehicle computing device, an in-vehicle computing platform, an in-vehicle computing unit, an intelligent drive computing platform, or the like.

[0159] In one embodiment, the electronic device may include an integrated circuit provided in the embodiments of the present disclosure, which may operate at least one operating system, such as an intelligent drive system and a cockpit system, to implement related functions of the cockpit-driving integrated system.

[0160] In one embodiment, the electronic device further comprises: a housing for accommodating and mounting each device of the electronic device to protect the devices from dust and water and improve the reliability of the electronic device; a power supply module for supplying power to each hardware unit of the electronic device; a heat dissipation module, such as a heat dissipation fan or a liquid-cooled heat dissipation device, for dissipating heat from devices in the electronic device, thereby reducing the operating temperature of each device and improving the operating stability of each device; The vehicle may include an external interface that is connected to each sensor in the vehicle, such as a camera, laser radar, millimeter-wave radar, ultrasonic radar, etc., and is used to send commands to each sensor or receive data returned from the sensor, and that is further connected to each actuator in the vehicle, such as a drive system, braking system, steering system, etc., and is capable of sending control commands to each system and receiving feedback from each system.

[0161] <Example vehicles> An embodiment of the present disclosure provides a vehicle, which may include a land vehicle, an air vehicle, a water vehicle, an underwater vehicle, a space vehicle, etc. For specific details of the vehicle, please refer to the previous embodiments, and further description will be omitted here. The vehicle may include an integrated circuit or electronic device provided in an embodiment of the present disclosure to implement the bandwidth control method provided in an embodiment of the present disclosure.

[0162] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the above methods and apparatuses, the embodiments of the present disclosure may also be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the bandwidth control methods of various embodiments of the present disclosure described in the "<Exemplary Methods>" section above of this specification.

[0163] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on a user's computing device, partially on a user's device, as a separate software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or a server.

[0164] In addition, the embodiments of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, cause the processor to perform the steps of the bandwidth control methods of the various embodiments of the present disclosure described in the "<Exemplary Method>" section above.

[0165] A computer-readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0166] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, it should be noted that the benefits, advantages, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and that these benefits, advantages, effects, etc. cannot be considered to be essential for each embodiment of the present disclosure. Furthermore, the specific details disclosed above are merely for illustrative purposes and to facilitate understanding, and are not limiting, and the details above do not limit the present disclosure to the specific details that must be implemented.

[0167] Block diagrams of devices, apparatus, instruments, and systems according to the present disclosure are merely illustrative examples and are not intended to require or imply that they be connected, arranged, or configured in the manner shown in the block diagrams. Those skilled in the art will recognize that these devices, apparatus, instruments, and systems can be connected, arranged, or configured in any manner. For example, words such as "comprise," "contain," and "have" are open-ended terms and can be used interchangeably to mean "including but not limited to." As used herein, "or" and "and" mean and can be used interchangeably with "and / or" unless the context clearly dictates otherwise. As used herein, "for example," means and can be used interchangeably with "such as, but not limited to."

[0168] It should also be noted that in the devices, apparatuses, and methods of the present disclosure, each component or step may be separated and / or recombined, and such separation and / or recombination should be considered as equivalent means of the present disclosure.

[0169] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0170] The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. While several example forms and embodiments have been discussed above, those skilled in the art may recognize certain variations, modifications, variations, additions, and subcombinations thereof.

Claims

1. a first hardware unit running a plurality of operating systems; a second hardware unit communicatively coupled to the first hardware unit; a bandwidth sharing module installed between the first hardware unit and the second hardware unit, the bandwidth sharing module including a cache queue for caching access instructions from a plurality of the operating systems to the second hardware unit, the bandwidth sharing module being used to generate a status value indicating a usage status of the cache queue; a plurality of throttling modules that correspond one-to-one to a plurality of the operating systems, are installed between the first hardware unit and the bandwidth sharing module, and are used to determine target bandwidth thresholds corresponding to each of the operating systems run by the first hardware unit based on the state value and a plurality of throttling parameters that are preset for each of the operating systems, and are used to control the bandwidth of access to the second hardware unit by each of the operating systems run by the first hardware unit based on the target bandwidth thresholds corresponding to each of the operating systems.

2. the first hardware unit includes a plurality of functional modules, and a plurality of the operating systems run in different functional modules; Each of the throttling modules is installed between the functional module of the first hardware unit and the bandwidth sharing module, and the throttling module and the functional module corresponding to the same operating system communicate with each other; 2. The bandwidth control system according to claim 1, wherein each of the functional modules is used to generate an access instruction to the second hardware unit by the operating system corresponding to the functional module.

3. 1. A method for controlling bandwidth, the method being performed by a throttling module in a bandwidth control system, comprising: The bandwidth control method is determining a status value indicating a usage status of a cache queue, the cache queue being for caching access instructions to a second hardware unit by a plurality of operating systems run by the first hardware unit; determining a target bandwidth threshold value corresponding to each of the operating systems run by the first hardware unit based on the state value and a plurality of throttling parameters preset for each of the operating systems; and controlling the bandwidth of access to the second hardware unit by each of the operating systems run by the first hardware unit based on a target bandwidth threshold corresponding to each of the operating systems.

4. The step of controlling the bandwidth of access to the second hardware unit by each of the operating systems operated by the first hardware unit based on a target bandwidth threshold value corresponding to each of the operating systems includes:

4. The bandwidth control method according to claim 3, further comprising a step of controlling the bandwidth of access to the second hardware unit by each of the operating systems run by the first hardware unit based on a target bandwidth threshold corresponding to each of the operating systems so that the bandwidth is equal to or less than the target bandwidth threshold corresponding to each of the operating systems.

5. The step of determining a status value indicating a usage status of the cache queue includes: determining an available number of entries in the cache queue for caching the access instruction; and determining the state value based on a number of available entries in the plurality of entries.

6. determining a target bandwidth threshold value corresponding to each of the operating systems operated by the first hardware unit based on the state value and a plurality of throttling parameters preset for each of the operating systems, determining a first throttling parameter corresponding to each of the operating systems from a plurality of throttling parameters preset for each of the operating systems based on the state value; and determining a target bandwidth threshold corresponding to each of the operating systems based on a first throttling parameter corresponding to each of the operating systems.

7. determining a first throttling parameter corresponding to each of the operating systems from a plurality of throttling parameters preset for each of the operating systems based on the state value, determining a first interval corresponding to the state value from a plurality of preset state value intervals; and determining the first throttling parameter for the first interval corresponding to each of the operating systems from a plurality of throttling parameters preset for each of the operating systems.

8. The step of determining a first interval corresponding to the state value from a plurality of preset state value intervals includes: determining a plurality of state thresholds for dividing the plurality of state value intervals; and determining the first interval from the plurality of state value intervals based on a numerical relationship between the state value and at least one state threshold value among the plurality of state threshold values.

9. 3. An electronic device comprising the bandwidth control system according to claim 1 or 2.

10. A vehicle including a bandwidth control system according to claim 1 or claim 2.

11. A vehicle including the electronic device described in claim 9.

12. A computer-readable storage medium storing a computer program for causing the throttling module in the bandwidth control system to execute the bandwidth control method according to any one of claims 3 to 8.

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