Time detection circuit

Abstract

To reduce a detection error of detected time.SOLUTION: A time detection circuit 15A comprises: a voltage adjustment unit 24 which outputs voltage obtained by level-shifting voltage Vds of a switching element; comparators 25H, 25L in which threshold voltage Vth_H identical to each other is input in an inverted input terminal; and a detection unit 26 which detects detected time on the basis of each output signal of the comparators 25H, 25L. Divided voltage VDIV corresponding to the voltage Vds is input in a non-inverted input terminal of the comparator 25H, and the output voltage of the voltage adjustment unit 24 is input in a non-inverted input terminal of the comparator 25L. Values of the threshold voltage Vth_H, Vth_L and a level shift amount in the voltage adjustment unit 24 are set so that an output signal of the comparator 25L is inverted at a first point of time when the voltage Vds reaches first reference voltage and an output signal of the comparator 25H is inverted at a second point of time when the voltage Vds reaches second reference voltage.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a time detection circuit that detects a detected time, which is the time from a first point in time when a main terminal voltage of a switching element reaches a first reference voltage to a second point in time when the main terminal voltage reaches a second reference voltage. [Background technology]

[0002] Conventionally, there has been a demand for gate drive circuits that drive the gates of switching elements such as IGBTs and MOSFETs, such as technologies to suppress surges that occur during switching and technologies to control dV / dt, which is the rate of change per unit time of the main terminal voltage of the switching element. Non-Patent Document 1 discloses a technology that controls dV / dt to a desired value by manipulating the timing of turning on one of two types of gate resistors based on the observation results of the drain-source voltage Vds of the switching element. Note that hereinafter, such a technology will also be referred to as the prior art.

[0003] In the prior art, a time detection circuit is provided to detect the dV / dt, or slew rate, of the switching element. In this case, the time detection circuit is configured to determine the fluctuation time of the voltage Vds by comparing the voltage Vds, which is reduced by a voltage divider circuit or the like, with a comparator, and convert the fluctuation time into an analog voltage. Specifically, the time detection circuit is configured with a voltage divider circuit consisting of a pair of capacitors for reducing the voltage Vds, and two comparators that compare the output voltage of the voltage divider circuit with a threshold voltage. [Prior art documents] [Patent documents]

[0004] [Non-Patent Document 1] "A 4.5V / ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs", 2019 IEEE International Solid-State Circuits Conference ,SESSION 15 POWER FOR 5G, WIRELESS POWER, AND GAN CONVERTERS 15.8 Summary of the Invention [Problem to be solved by the invention]

[0005] The fluctuation time of the voltage Vds, i.e., the transition time of the voltage Vds, is the time from a first point in time when the voltage Vds reaches a first reference voltage to a second point in time when the voltage Vds reaches a second reference voltage different from the first reference voltage. Therefore, in the prior art, the threshold voltage of one of the two comparators corresponds to the first reference voltage, and the threshold voltage of the other of the two comparators corresponds to the second reference voltage. In other words, in the prior art, different threshold voltages are input to the two comparators.

[0006] In the prior art, when a switching element is switched at a relatively high speed, i.e., during high-speed switching, the transition time of the voltage Vds is very short, for example, on the order of a few nanoseconds, and the difference in delay time due to the difference in threshold voltage between the two comparators becomes significant, which can result in an error in detecting the transition time of the voltage Vds. If an error occurs in detecting the transition time of the voltage Vds, an error also occurs in the value of dV / dt calculated based on the transition time and the first and second reference voltages, making it impossible to control the surge or dV / dt during switching to a desired value.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a time detection circuit that can reduce detection errors in the time to be detected. [Means for solving the problem]

[0008] The time detection circuit described in claim 1 is a circuit that detects a detected time, which is the time from a first point in time when a main terminal voltage, which is the voltage at the main terminal of a switching element (5, 5A, 5B), reaches a first reference voltage to a second point in time when the main terminal voltage reaches a second reference voltage different from the first reference voltage. The time detection circuit includes a voltage adjustment unit (24, 32, 82) that outputs a voltage obtained by level-shifting or dividing a voltage corresponding to the main terminal voltage, two comparators (25H, 25L) that have first and second input terminals and to which the same threshold voltage is input, and a detection unit (26, 62) that detects the detected time based on the output signals of the two comparators.

[0009] A voltage corresponding to the main terminal voltage is input to the second input terminal of one of the two comparators. An output voltage of the voltage adjustment unit is input to the second input terminal of the other of the two comparators. In the above configuration, the value of the threshold voltage and the level shift amount or voltage division ratio of the voltage adjustment unit are set so that an output signal of one of the two comparators is inverted at a first time point when the main terminal voltage reaches the first reference voltage, and an output signal of the other of the two comparators is inverted at a second time point when the main terminal voltage reaches the second reference voltage.

[0010] This configuration makes it possible to detect the detection time from the first point in time when the main terminal voltage reaches the first reference voltage to the second point in time when the main terminal voltage reaches the second reference voltage, i.e., the transition time of the main terminal voltage. Furthermore, in the above configuration, the same threshold voltage is input to each of the two comparators used for such detection. Therefore, in the above configuration, the two comparators operate at the same threshold voltage, and the difference in delay time between the two comparators is negligible. As a result, it is possible to achieve the excellent effect of reducing detection errors in the transition time of the main terminal voltage, i.e., the detection time. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a gate drive device and a half-bridge circuit according to a first embodiment. [Figure 2] FIG. 2 is a diagram schematically illustrating waveforms of a load current and currents and voltages related to a switching element according to the first embodiment; [Figure 3] FIG. 1 is a diagram schematically illustrating a specific configuration example of a gate driving device according to a first embodiment. [Figure 4] FIG. 1 is a diagram schematically illustrating a first specific configuration example of a time detection circuit according to a first embodiment; [Figure 5] FIG. 10 is a diagram schematically illustrating a second specific configuration example of the time detection circuit according to the first embodiment; [Figure 6] FIG. 1 is a diagram schematically illustrating a specific configuration example of a voltage adjustment unit according to a first embodiment; [Figure 7] 1 is a timing chart for explaining the timing of specific operations performed by the time detection circuit according to the first embodiment; [Figure 8] FIG. 1 is a diagram schematically illustrating a configuration of a time detection circuit according to a comparative example. [Figure 9] 10 is a timing chart for explaining the timing of specific operations performed by a time detection circuit according to a comparative example; [Figure 10] FIG. 10 is a diagram schematically illustrating a specific configuration example of a time detection circuit according to a second embodiment. [Figure 11]FIG. 10 is a diagram schematically illustrating a specific configuration example of a time detection circuit according to a third embodiment. [Figure 12] 10 is a timing chart for explaining the timing of specific operations performed by the time detection circuit according to the third embodiment; [Figure 13] FIG. 10 is a diagram schematically illustrating a specific configuration example of a gate driving device according to a fourth embodiment. [Figure 14] FIG. 10 is a diagram illustrating waveforms of the voltage Vds in two cases where the power supply voltages are different from each other according to the fourth embodiment. [Figure 15] FIG. 13 is a diagram schematically illustrating a specific configuration example of a time detection circuit according to a fifth embodiment. [Figure 16] 10 is a timing chart for explaining the timing of specific operations performed by the time detection circuit according to the fifth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in each embodiment will be denoted by the same reference numerals, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0013] <Outline of gate driver configuration> As shown in Fig. 1, a gate drive device 1A of this embodiment drives a switching element 5A that constitutes the upper arm of a half-bridge circuit 4 connected between a pair of DC power supply lines 2 and 3. A gate drive device 1B of this embodiment drives a switching element 5B that constitutes the lower arm of the half-bridge circuit 4. In this case, the gate drive devices 1A and 1B have the same configuration, and the switching elements 5A and 5B also have the same configuration. Therefore, in this specification, when it is not necessary to distinguish between the gate drive devices 1A and 1B and the switching elements 5A and 5B, the final alphabetical characters will be omitted and they will be referred to collectively.

[0014] The half-bridge circuit 4 is included in an inverter that drives a motor (not shown). A power supply voltage Va is supplied to the half-bridge circuit 4 from a DC power supply (not shown), such as a battery, via DC power supply lines 2 and 3. The switching element 5 is a power element, and in this case, includes an N-channel MOSFET and a freewheeling diode connected between the drain and source of the MOSFET with the source side as the anode, i.e., connected in anti-parallel to the MOSFET. In this case, the freewheeling diode is provided as a separate element from the MOSFET, but the body diode of the MOSFET may also be used as the freewheeling diode.

[0015] One main terminal or drain of the switching element 5A is connected to the high-potential side DC power supply line 2. The other main terminal or source of the switching element 5A is connected to one main terminal or drain of the switching element 5B. The other main terminal or source of the switching element 5B is connected to the low-potential side DC power supply line 3. A node N1, which is an interconnection node between the switching elements 5A and 5B, is connected to the above-mentioned motor (not shown). As a result, a load current IL, which is an output current of the half-bridge circuit 4, is supplied to the motor. A controller 6 controls the operation of the half-bridge circuit 4 that constitutes the inverter, thereby controlling the drive of the motor.

[0016] A detection signal Sc indicating the detected value of the load current IL output from a current detection unit (not shown) is provided to the controller 6. Based on the detection signal Sc, the controller 6 generates and outputs a command signal Sa for commanding the operation of the gate drive device 1A and a command signal Sb for commanding the operation of the gate drive device 1B so that the load current IL coincides with a desired target current. The gate drive device 1A performs PWM control of the drive of the switching element 5A based on the command signal Sa provided by the controller 6. Furthermore, the gate drive device 1B performs PWM control of the drive of the switching element 5B based on the command signal Sb provided by the controller 6. Note that PWM is an abbreviation for Pulse Width Modulation.

[0017] In this case, switching element 5A and switching element 5B are turned on and off complementarily. Therefore, during the period when switching element 5A is on, switching element 5B is turned off, and during the period when switching element 5B is turned on, switching element 5A is turned off. In the above configuration, during the period when load current IL flows from node N1 to the motor, switching element 5A is driven to pass a current in the forward direction from drain to source, and switching element 5B is driven to pass a current in the reverse direction from source to drain. Also, in the above configuration, during the period when load current IL flows from the motor to node N1, switching element 5B is driven to pass a current in the forward direction from drain to source, and switching element 5A is driven to pass a current in the reverse direction from source to drain.

[0018] The waveforms of each part when switching element 5 is turned off are as shown in Figure 2. Note that Figure 2 illustrates the waveforms of each part corresponding to switching element 5B, but similar waveforms apply to switching element 5A. In Figure 2, Id represents the drain current of switching element 5B, Vds represents the drain-source voltage of switching element 5B, and Vgs represents the gate-source voltage of switching element 5B. The off-voltage Vds_off, which is the drain-source voltage Vds when switching element 5B is off, is approximately equal to the power supply voltage Va.

[0019] In this case, the drain-source voltage Vds of switching element 5B corresponds to the main terminal voltage, and the slope of the fluctuation of the drain-source voltage Vds corresponds to the rate of change of the main terminal voltage. In this specification, the drain-source voltage Vds may be simply referred to as voltage Vds. In this specification, the slope of the fluctuation of voltage Vds may be referred to as dV / dt. In this case, ΔVds, which is the difference between the peak voltage, Vds_p, of voltage Vds at turn-off, and the off-voltage Vds_off, corresponds to the surge voltage superimposed on switching element 5B.

[0020] <Specific configuration of the gate driver> As a specific configuration of the gate drive device 1, for example, a configuration example shown in Fig. 3 can be adopted. In this case, it is assumed that the gate drive device 1 is used in an automobile or other vehicle, and the power supply voltage Va applied to the switching element 5 is a relatively high voltage of, for example, several hundred volts. Note that Fig. 3 shows the specific configuration of the gate drive device 1 using the gate drive device 1B that drives the switching element 5B as an example, but a similar configuration can also be adopted for the gate drive device 1A that drives the switching element 5A.

[0021] In this case, the gate driver 1 is configured as a semiconductor device, i.e., an IC, and includes a detection circuit 11, a current calculation unit 12, a gate driver circuit 13, and the like. Note that the gate driver 1 does not necessarily need to be configured as an IC, and some of its components may be provided outside the IC. The voltage at node N1, i.e., the drain voltage of switching element 5B, is input to the detection circuit 11. The detection circuit 11 inputs the drain voltage of switching element 5B relative to the potential of the source of switching element 5B, i.e., voltage Vds, and detects dV / dt, which is the rate of change of voltage Vds of switching element 5B, based on voltage Vds. The detection circuit 11 outputs a signal Sd that represents the detected value of the rate of change dV / dt.

[0022] The detection circuit 11 includes a voltage-dividing circuit 14, a time detection circuit 15, and a rate-of-change calculation unit 16. The voltage-dividing circuit 14 includes two capacitors C1 and C2. The capacitors C1 and C2 can be built into the IC or external to the IC, i.e., external components such as ceramic capacitors can be used. One terminal of the capacitor C1 is connected to the node N1, and the other terminal is connected to the power supply line 17 via the capacitor C2. The power supply line 17 is supplied with the ground, which is the reference potential of the circuit, and is at the same potential as the DC power supply line 3 to which the source of the switching element 5B is connected. Thus, the voltage-dividing circuit 14 includes the capacitors C1 and C2 connected in series.

[0023] In this case, capacitors C1 and C2 function as a pair of voltage-dividing capacitors and are configured to withstand high voltages so as not to break down even when a relatively high voltage generated at node N1 is applied. With the above configuration, voltage-dividing circuit 14 divides voltage Vds, which is the main terminal voltage of switching element 5B, using capacitors C1 and C2 and outputs the divided voltage. Specifically, voltage-dividing circuit 14 divides voltage Vds based on the capacitance ratio of capacitors C1 and C2 and outputs the divided voltage from node N2, which is the interconnection node of capacitors C1 and C2. In this case, the divided voltage VDIV output from voltage-dividing circuit 14 corresponds to the voltage corresponding to the main terminal voltage of switching element 5.

[0024] The time detection circuit 15 detects a detection time, which is the time during which the voltage Vds fluctuates, based on the divided voltage VDIV. Specifically, the detection time is the time from a first point in time at which the voltage Vds reaches a first reference voltage Vr1 to a second point in time at which the voltage Vds reaches a second reference voltage Vr2 when the switching element 5 is turned off. The first reference voltage Vr1 and the second reference voltage Vr2 are both preset voltages.

[0025] The second reference voltage Vr2 is different from the first reference voltage Vr1. Specifically, the first reference voltage Vr1 is set to a predetermined voltage higher than 0 V and lower than the second reference voltage Vr2, and the second reference voltage Vr2 is set to a predetermined voltage higher than the first reference voltage Vr1 and lower than the off-voltage Vds_off. The time detection circuit 15 outputs a signal Se that indicates a detected value of the fluctuation time of the voltage Vds.

[0026] The change rate calculation unit 16 receives the signal Se output from the time detection circuit 15 and the command signal Sb output from the controller 6. Although not shown, signals representing the voltage values ​​of the first reference voltage Vr1 and the second reference voltage Vr2 are also input to the change rate calculation unit 16. The change rate calculation unit 16 calculates the change rate dV / dt when the switching element 5 is turned off based on the signal Se, the command signal Sb, and the voltage values ​​of the first reference voltage Vr1 and the second reference voltage Vr2. The change rate calculation unit 16 outputs the signal Sd described above as a signal representing the result of this calculation.

[0027] The current calculation unit 12 receives the signal Sd output from the rate of change calculation unit 16. The current calculation unit 12 performs the following calculation to control the rate of change dV / dt at the turn-off of the switching element 5 to the target rate of change dV / dt*. That is, based on the detected value of the rate of change dV / dt represented by the signal Sd and the target rate of change dV / dt*, the current calculation unit 12 calculates the current value of the gate current Ig_off such that the rate of change dV / dt of the voltage Vds at the turn-off is equal to the target rate of change dV / dt*. The gate current Ig_off is a gate current that turns off the gate of the switching element 5. The current calculation unit 12 outputs a signal Sf that represents the current value of the gate current Ig_off obtained as a result of this calculation.

[0028] Gate drive circuit 13 is configured to drive the gate of switching element 5 with a constant current. That is, gate drive circuit 13 includes current sources 18 and 19, switches 20 and 21, and a logic circuit 22. An upstream terminal of current source 18 is connected to power supply line 23 to which power supply voltage Vb is supplied, and a downstream terminal thereof is connected to the gate of switching element 5B via switch 20. Power supply voltage Vb is a voltage based on the potential of power supply line 17 connected to the source of switching element 5B, and is a voltage that is sufficiently higher than the gate threshold voltage of switching element 5B.

[0029] Current source 18 is a constant current circuit that generates a constant current to be supplied to the gate of switching element 5 when it is turned on, i.e., a gate current Ig_on that turns on the gate of switching element 5. Note that a resistor having a constant resistance value may be provided as a configuration on the turn-on side of gate drive circuit 13 instead of current source 18. In other words, the turn-on side of gate drive circuit 13 does not need to be configured to drive with a constant current. Switch 20 includes a semiconductor switching element such as a P-channel MOS transistor, and opens and closes the connection between current source 18 and the gate of switching element 5B.

[0030] The downstream terminal of current source 19 is connected to power supply line 17, and its upstream terminal is connected to the gate of switching element 5B via switch 21. Current source 19 is a constant current circuit that generates a constant current to be drawn from the gate of switching element 5B when it is turned off, i.e., a gate current Ig_off for turning off the gate of switching element 5B. In this case, current source 19 is configured to be able to change its current value based on signal Sf output from current calculation unit 12. Switch 21 includes a semiconductor switching element such as an N-channel MOS transistor, and opens and closes the connection between the gate of switching element 5B and current source 19.

[0031] The logic circuit 22 complementarily turns on and off the switches 20 and 21 based on the command signal Sb. However, in this case, a period during which both the switches 20 and 21 are off, known as a dead time, is provided. According to the above configuration, the switching element 5B is turned on when the switch 20 is turned on, and the switching element 5B is turned off when the switch 21 is turned on. Furthermore, in the above configuration, the current value of the current source 19, i.e., the gate current Ig_off when the switching element 5B is turned off, is changed in response to the signal Sf. In this case, the current value of the gate current Ig_off calculated based on the detection values ​​during the previous switching is applied during the next switching, thereby changing the gate drive speed when the switching element 5B is turned off during the next switching.

[0032] <Specific configuration of the time detection circuit> As a specific configuration of the time detection circuit 15, for example, a first configuration example as shown in FIG. 4 or a second configuration example as shown in FIG. 5 can be adopted. [1] First configuration example 4, the time detection circuit 15A of the first configuration example includes a voltage adjustment unit 24, comparators 25H and 25L, and a detection unit 26. The voltage adjustment unit 24 outputs a voltage obtained by level-shifting the divided voltage VDIV, and is configured as a level shift circuit that level-shifts the divided voltage VDIV. Each of the two comparators 25H and 25L has an inverting input terminal corresponding to the first input terminal and a non-inverting input terminal corresponding to the second input terminal.

[0033] The same threshold voltage Vth_H is input to the inverting input terminals of the comparators 25H and 25L. The threshold voltage Vth_H is a voltage corresponding to the second reference voltage Vr2, and specifically, corresponds to a voltage obtained by dividing the second reference voltage Vr2 by the capacitance ratio of the capacitors C1 and C2 of the voltage-dividing circuit 14, i.e., the voltage-dividing ratio of the voltage-dividing circuit 14. The divided voltage VDIV is input to the non-inverting input terminal of the comparator 25H, which is one of the two comparators 25H and 25L. The output voltage of the voltage adjusting unit 24 is input to the non-inverting input terminal of the comparator 25L, which is the other of the two comparators 25H and 25L.

[0034] The comparator 25H outputs an output signal OUT_H representing the result of comparison between the divided voltage VDIV and the threshold voltage Vth_H. The comparator 25L outputs an output signal OUT_L representing the result of comparison between the output voltage of the voltage adjustment unit 24 and the threshold voltage Vth_H. The output signals OUT_H and OUT_L are both binary signals. In the following description, a relatively low level of the binary signal will be referred to as a low level, and a relatively high level will be referred to as a high level.

[0035] In this case, the voltage adjustment unit 24 is configured to increase the level of the divided voltage VDIV, and the level shift amount LS1 is expressed by the following equation (1): where the threshold voltage Vth_L is a voltage corresponding to the first reference voltage Vr1, and specifically, corresponds to the voltage obtained by dividing the first reference voltage Vr1 by the voltage division ratio of the voltage divider circuit 14. LS1=Vth_H-Vth_L …(1)

[0036] 7, the output signal OUT_L of the comparator 25L changes from low to high at time t1 when the divided voltage VDIV reaches the threshold voltage Vth_L. Also, as shown in FIG. 7, the output signal OUT_H of the comparator 25H changes from low to high at time t2 when the divided voltage VDIV reaches the threshold voltage Vth_H. Time t1 corresponds to the first time point when the voltage Vds reaches the first reference voltage Vr1. Time t2 corresponds to the second time point when the voltage Vds reaches the second reference voltage Vr2.

[0037] In this way, in the above configuration, the values ​​of the threshold voltages Vth_L and Vth_H and the level shift amount LS1 in the voltage adjustment unit 24 are set so that the output signal OUT_L of the comparator 25L is inverted at the first point in time when the voltage Vds reaches the first reference voltage Vr1, and the output signal OUT_H of the comparator 25H is inverted at the second point in time when the voltage Vds reaches the second reference voltage Vr2.

[0038] The detection unit 26 detects the detection time based on the output signals OUT_H and OUT_L of the two comparators 25H and 25L, and includes an EX-OR circuit 27, a current source 28, a switch 29, and a capacitor 30. The output signal OUT_H is input to one input terminal of the EX-OR circuit 27, and the output signal OUT_L is input to the other input terminal. The EX-OR circuit 27 performs an exclusive OR operation on the input output signals OUT_H and OUT_L, and outputs a signal Sg representing the operation result.

[0039] 7, signal Sg is at a low level when both output signals OUT_H and OUT_L are at a high level or a low level, and is at a high level when only one of output signals OUT_H and OUT_L is at a high level. Current source 28 is configured as a constant current circuit that outputs a constant current. An upstream terminal of current source 28 is connected to power supply line 31 to which power supply voltage Vc is supplied, and its downstream terminal is connected to node N3 via switch 29.

[0040] The capacitor 30 is connected between the node N3 and the power supply line 17 to which the reference potential of the circuit is applied. The switch 29 is turned on and off in response to the signal Sg output from the EX-OR circuit 27. Specifically, the switch 29 is turned on while the signal Sg is at a high level, and turned off while the signal Sg is at a low level. With this configuration, the capacitor 30 is charged by the current from the current source 28 while the signal Sg is at a high level.

[0041] In other words, the capacitor 30 is charged by the current from the current source 28 during the period when only one of the output signals OUT_H and OUT_L is at a high level, i.e., the period from time t1 to time t2. The terminal voltage of the capacitor 30 after such charging, i.e., the voltage Vd at the node N3, is a voltage corresponding to the fluctuation time of the voltage Vds, which is the detection time. In other words, the time detection circuit 15A is configured as a time-voltage conversion circuit. In the above configuration, the voltage Vd is output as a signal Se, which is a voltage signal representing the detected value of the fluctuation time of the voltage Vds.

[0042] [2] Second configuration example 5, time detection circuit 15B of the second configuration example differs from time detection circuit 15A of the first configuration example in that it includes voltage adjustment unit 32 instead of voltage adjustment unit 24 and in that the threshold voltages input to comparators 25H and 25L are changed. Like voltage adjustment unit 24, voltage adjustment unit 32 outputs a voltage obtained by level-shifting divided voltage VDIV, and is configured as a level shift circuit that level-shifts divided voltage VDIV.

[0043] In this case, the same threshold voltage Vth_L is input to the inverting input terminals of the comparators 25H and 25L. The divided voltage VDIV is input to the non-inverting input terminal of the comparator 25L, which is one of the two comparators 25H and 25L. The output voltage of the voltage adjustment unit 32 is input to the non-inverting input terminal of the comparator 25H, which is the other of the two comparators 25H and 25L.

[0044] The comparator 25L outputs an output signal OUT_L representing the result of comparison between the divided voltage VDIV and the threshold voltage Vth_L. The comparator 25H outputs an output signal OUT_H representing the result of comparison between the output voltage of the voltage adjustment unit 32 and the threshold voltage Vth_L. In this case, the voltage adjustment unit 32 is configured to level-down the divided voltage VDIV, and the level shift amount LS1 is expressed by the above equation (1), similar to the voltage adjustment unit 24.

[0045] With the above configuration, as with the time detection circuit 15A of the first configuration example, the output signal OUT_L of the comparator 25L changes from low level to high level at time t1 when the divided voltage VDIV reaches the threshold voltage Vth_L, and the output signal OUT_H of the comparator 25H changes from low level to high level at time t2 when the divided voltage VDIV reaches the threshold voltage Vth_H.

[0046] In this way, with the above configuration, similar to the time detection circuit 15A of the first configuration example, the values ​​of the threshold voltages Vth_L and Vth_H and the level shift amount LS1 in the voltage adjustment unit 32 are set so that the output signal OUT_L of the comparator 25L is inverted at the first point in time when the voltage Vds reaches the first reference voltage Vr1, and the output signal OUT_H of the comparator 25H is inverted at the second point in time when the voltage Vds reaches the second reference voltage Vr2.

[0047] <Specific configuration of the voltage adjustment unit> As a specific configuration of the voltage adjustment unit 24, for example, a configuration example as shown in Fig. 6 can be adopted. Note that Fig. 6 shows a specific configuration of the voltage adjustment unit 24 provided in the time detection circuit 15A of the first configuration example, but a similar configuration can also be adopted for the voltage adjustment unit 32 provided in the time detection circuit 15B of the second configuration example. As shown in Fig. 6, the voltage adjustment unit 24 is configured as a capacitive level shift circuit including switches 33, 34, 35 and a capacitor 36.

[0048] The switches 33 to 35 are configured by semiconductor switching elements such as MOS transistors. One terminal of the capacitor 36 is connected to a node N4 to which the divided voltage VDIV is applied via the switch 33. In addition, one terminal of the capacitor 36 is connected to a voltage line 37 to which a threshold voltage Vth_H is applied via a switch 34. The other terminal of the capacitor 36 is connected to a voltage line 38 to which a threshold voltage Vth_L is applied via a switch 35. In addition, the other terminal of the capacitor 36 is connected to a non-inverting input terminal of the comparator 25L.

[0049] In the above configuration, the switches 34 and 35 are turned on and off at the same timing. Also, in the above configuration, the switch 33 and the switches 34 and 35 are turned on and off complementarily. In this case, the switches 34 and 35 are turned on first. As a result, a charge equivalent to a voltage of "Vth_H-Vth_L", that is, a charge equivalent to the level shift amount LS1 in the voltage adjustment unit 24, is charged between the two terminals of the capacitor 36. Next, the switch 33 is turned on. As a result, a voltage obtained by raising the divided voltage VDIV by "Vth_H-Vth_L", that is, by the level shift amount LS1, is input to the non-inverting input terminal of the comparator 25L.

[0050] With this configuration, at time t1 when the divided voltage VDIV reaches the threshold voltage Vth_L, the voltage input to the non-inverting input terminal of the comparator 25L reaches the threshold voltage Vth_H. Therefore, with the above configuration, the comparator 25L can function similarly to a conventional configuration that compares the divided voltage VDIV with the threshold voltage Vth_L. In this way, the voltage adjustment unit 24 shown in FIG. 6 applies a voltage corresponding to the level shift amount LS1 between the two terminals of the capacitor 36 to charge it, and applies the divided voltage VDIV corresponding to the main terminal voltage to one terminal of the charged capacitor 36, thereby outputting a voltage obtained by level-shifting the divided voltage VDIV from the other terminal of the capacitor 36.

[0051] Next, specific operation timings in the above configuration will be described with reference to Fig. 7. Note that the description will be given here using an example in which the first configuration example shown in Fig. 4 is used as the specific configuration of time detection circuit 15, and the configuration example shown in Fig. 6 is used as the specific configuration of voltage adjustment unit 24. In Fig. 7 and the following description, with regard to command signal Sb, a state in which a command to turn on switching element 5 is expressed as an "ON command," and a state in which a command to turn off switching element 5 is expressed as an "OFF command."

[0052] In FIG. 7 and the following description, the on state of the switches 33 to 35 is represented as "ON" and the off state as "OFF." In FIG. 7 and the following description, the voltage at the non-inverting input terminals of the comparators 25H and 25L is represented as "voltage VIN+." In FIG. 7, regarding the level of a binary signal, a high level is represented as "H" and a low level is represented as "L." In this case, although not shown in the drawing, it is assumed that in the period before time ta, "command signal Sb = OFF command, switches 34 and 35 = OFF, and switch 33 = ON."

[0053] At time ta, the command signal Sb changes from an OFF command to an ON command. Then, the switches 34 and 35 change from OFF to ON, and the switch 33 changes from ON to OFF. This causes the voltage VIN+ of the comparator 25L to rise from zero and eventually reach a voltage "Vth_H-Vth_L" corresponding to the level shift amount LS1 of the voltage adjustment unit 24. At time tb, a predetermined time after time ta, the switches 34 and 35 change from ON to OFF, and the switch 33 changes from OFF to ON.

[0054] Then, at time tc, the command signal Sb changes from an ON command to an OFF command. The gate drive circuit 13 then turns off the switching element 5B. After a predetermined delay time has elapsed since time tc, the voltage Vds, and hence the divided voltage VDIV, begin to rise from zero. Then, at time t1, the voltage Vds reaches the first reference voltage Vr1, i.e., the divided voltage VDIV reaches the threshold voltage Vth_L.

[0055] At this time, the voltage VIN+ of the comparator 25L reaches the threshold voltage Vth_H, causing the output signal OUT_L of the comparator 25L to transition from low to high. As a result, at time t1, the signal Sg output from the EX-OR circuit 27 transitions from low to high. Then, the signal Se, which is the voltage Vd that represents the detected value of the fluctuation time of the voltage Vds, begins to rise from zero.

[0056] Thereafter, at time t2, voltage Vds reaches second reference voltage Vr2, i.e., divided voltage VDIV reaches threshold voltage Vth_H. At this time, voltage VIN+ of comparator 25H reaches threshold voltage Vth_H, causing output signal OUT_H of comparator 25H to transition from low to high. Therefore, at time t2, signal Sg output from EX-OR circuit 27 transitions from high to low. Then, signal Se, which is voltage Vd representing the detected value of the fluctuation time of voltage Vds, stops rising and is thereafter maintained at the voltage value at time t2.

[0057] According to the present embodiment described above, the following effects can be obtained. The time detection circuit 15 of this embodiment includes a voltage adjustment unit 24 or 32 that outputs a voltage obtained by level-shifting a divided voltage VDIV corresponding to the voltage Vds, two comparators 25H and 25L, and a detection unit 26 that detects the fluctuation time of the voltage Vds, which is the detection time, based on the output signals OUT_H and OUT_L of the two comparators 25H and 25L. The same threshold voltage is input to the inverting input terminals of the two comparators 25H and 25L. The divided voltage VDIV is input to the non-inverting input terminal of one of the comparators 25H and 25L. The output voltage of the voltage adjustment unit 24 or 32 is input to the other non-inverting input terminal of the comparators 25H and 25L.

[0058] In the above configuration, the values ​​of the threshold voltages Vth_H and Vth_L and the level shift amount LS1 in the voltage adjustment unit 24 or 32 are set so that the output signal OUT_L of the comparator 25L is inverted at a first point in time when the voltage Vds reaches the first reference voltage Vr1, and the output signal OUT_H of the comparator 25H is inverted at a second point in time when the voltage Vds reaches the second reference voltage Vr2.

[0059] This configuration makes it possible to detect the transition time of the voltage Vds, that is, the detection time from the first point in time when the voltage Vds reaches the first reference voltage Vr1 to the second point in time when the voltage Vds reaches the second reference voltage Vr2. Furthermore, in the above configuration, the same threshold voltage is input to each of the two comparators 25H, 25L used for this detection. Therefore, in this configuration, the two comparators 25H, 25L operate at the same threshold voltage, and the difference in delay time between the two comparators 25H, 25L is negligibly small. As a result, it is possible to achieve the excellent effect of reducing the detection error of the transition time of the voltage Vds, that is, the detection time.

[0060] The effects obtained by this embodiment become more apparent when compared with a comparative example corresponding to the prior art. That is, as shown in Fig. 8, a time detection circuit 41 of the comparative example differs from the time detection circuit 15A of the embodiment shown in Figs. 4 and 6 in that the voltage adjustment unit 24 is omitted and the voltages input to the input terminals of the comparator 25L are changed. In this case, the divided voltage VDIV is input to the non-inverting input terminal of the comparator 25L, and the threshold voltage Vth_L is input to the inverting input terminal thereof.

[0061] As shown in FIG. 9, in the configuration of the comparative example, the comparators 25H and 25L operate at different threshold voltages, resulting in a large difference in delay time between the comparators 25H and 25L. Specifically, the delay time tdL of the comparator 25L is longer than the delay time of the comparator 25H. Note that in this case, for ease of explanation, the delay time tdH is assumed to be approximately zero. Therefore, in the comparative example, the rising timing of the output signal OUT_L is delayed. As a result, the period during which the signal g output from the EX-OR circuit 27 is at a high level, i.e., the period during which the capacitor 30 is charged, is shorter than the intended time by the difference in delay time.

[0062] Therefore, in the comparative example, as shown by the dashed line in FIG. 9, the voltage value of the signal Se, which is the voltage Vd that represents the detected value of the fluctuation time of the voltage Vds, is smaller than the true value shown by the solid line in FIG. 9, resulting in a detection error of the fluctuation time of the voltage Vds. The detection error that occurs in this comparative example becomes more pronounced when the switching element 5 is switched at a relatively high speed, i.e., when high-speed switching is performed. In contrast, according to this embodiment, the comparators 25H and 25L operate at the same threshold voltage, so the difference in delay time between the comparators 25H and 25L is kept small. As a result, the detection error of the fluctuation time of the voltage Vds can be reduced even when the switching element 5 is switched at high speed.

[0063] In this embodiment, the voltage adjustment units 24 and 32 are configured as capacitive level shift circuits including switches 33 to 35 and a capacitor 36, as shown in FIG. 6 . The voltage adjustment unit 24 is not limited to a capacitive level shift circuit, and can also be configured as a level shift circuit using a resistive voltage divider, a diode, a buffer, or the like. However, in such other configurations, the resistance component lengthens the charging time for the parasitic capacitance, which may result in a decrease in transient response regarding detection of the detection time. In contrast, the voltage adjustment units 24 and 32 of this embodiment configured as capacitive level shift circuits have significantly fewer resistance components than the other configurations described above, thereby improving transient response regarding detection of the detection time.

[0064] (Second embodiment) The second embodiment will be described below with reference to FIG. In this embodiment, the specific configuration of the time detection circuit is different from that of the first embodiment. As shown in Fig. 10, a time detection circuit 51 of this embodiment differs from the time detection circuit 15A of the first embodiment shown in Fig. 6 in that a voltage adjustment unit 52 is added, and that the output voltage of the voltage adjustment unit 52 is input to the non-inverting input terminal of the comparator 25H, which is one of the two comparators 25H and 25L, instead of the divided voltage VDIV.

[0065] In this case, voltage adjustment unit 24 functions as a first voltage adjustment unit, and voltage adjustment unit 52 functions as a second voltage adjustment unit. Voltage adjustment unit 52 is configured as a level shift circuit similar to voltage adjustment unit 24, that is, a capacitive level shift circuit including switches 33, 34, and 35 and capacitor 36. However, in this case, switch 34 is connected between node N4 and one terminal of capacitor 36, that is, between both terminals of switch 33. Also, in this case, switch 35 is connected between node N4 and the non-inverting input terminal of comparator 25H.

[0066] With this configuration, the level shift amount LS2 of the voltage adjustment unit 52 is 0 V. In other words, the voltage adjustment unit 52 is configured to output a voltage obtained by level-shifting the divided voltage VDIV by 0 V. Therefore, the voltage value of the output voltage of the voltage adjustment unit 52 is substantially the same as the voltage value of the divided voltage VDIV.

[0067] For this reason, in the above configuration, the values ​​of the threshold voltages Vth_L and Vth_H and the level shift amount LS1 in the voltage adjustment unit 24 and the level shift amount LS2 by the voltage adjustment unit 52 are set so that the output signal OUT_L of the comparator 25L is inverted at the first point in time when the voltage Vds reaches the first reference voltage Vr1, and the output signal OUT_H of the comparator 25H is inverted at the second point in time when the voltage Vds reaches the second reference voltage Vr2.

[0068] The configuration of this embodiment described above also makes it possible to detect the transition time of the voltage Vds, as in the first embodiment. Furthermore, as in the first embodiment, the configuration of this embodiment also makes it possible for the two comparators 25H and 25L to operate at the same threshold voltage, making the difference in delay time between the two comparators 25H and 25L negligible. As a result, it is possible to obtain the excellent effect of reducing detection errors in the detection time. Furthermore, this embodiment also provides the following effects.

[0069] That is, in each configuration example of the first embodiment, the voltage adjustment unit 24 or 32 configured as a capacitive level shift circuit was provided only in the path leading to the non-inverting input terminal of one of the two comparators 25H, 25L, which could cause a parasitic capacitance imbalance between the two comparators 25H, 25L. Note that the parasitic capacitance imbalance occurs due to the parasitic capacitance of the MOS transistors that configure the switches 33 to 35, the parasitic capacitance of the wiring that connects the switches 33 to 35 and the capacitor 36, etc.

[0070] If a parasitic capacitance imbalance occurs between the two comparators 25H, 25L, a difference in delay time will occur between the two comparators 25H, 25L, which may result in an error in detecting the detection time. In contrast, in the configuration of this embodiment, voltage adjustment units 24, 52 configured as identical capacitive level shift circuits are provided in the paths leading to the non-inverting input terminals of both comparators 25H, 25L. Therefore, with the configuration of this embodiment, the parasitic imbalance between the two comparators 25H, 25L is reduced, further minimizing the difference in delay time, and as a result, the detection error in the detection time can be further reduced.

[0071] (Third embodiment) The third embodiment will be described below with reference to FIGS. In this embodiment, the specific configuration of the time detection circuit is different from that of the first embodiment. As shown in Fig. 11, a time detection circuit 61 of this embodiment differs from the time detection circuit 15A of the first embodiment shown in Fig. 4 in that it includes a detection unit 62 instead of the detection unit 26. In addition to the components included in the detection unit 26, the detection unit 62 includes two latches 63 and 64.

[0072] The two latches 63, 64 receive the output signals OUT_H, OUT_L of the two comparators 25H, 25L, respectively. The output signals LOUT_H, LOUT_L of the two latches 63, 64 are received by the input terminals of the EX-OR circuit 27. The latches 63, 64 are reset by a reset signal RESET. With this configuration, the detection unit 62 detects the detection time based on the output signals LOUT_H, LOUT_L obtained after latching the output signals OUT_H, OUT_L of the comparators 25H, 25L.

[0073] Next, specific operation timings of the above configuration will be described with reference to FIG. 12. Note that while the command signal Sb is not shown in FIG. 12, the command signal Sb is assumed to be the same as that in FIG. 7. At time tc, when the command signal Sb changes from an ON command to an OFF command, the gate drive circuit 13 drives the switching element 5B to OFF. After a predetermined delay time has elapsed from time tc, the voltage Vds, and therefore the divided voltage VDIV, begin to rise from zero. Thereafter, at time t1, the voltage Vds reaches the first reference voltage Vr1, that is, the divided voltage VDIV reaches the threshold voltage Vth_L.

[0074] At this time, the voltage VIN+ of the comparator 25L reaches the threshold voltage Vth_H, causing the output signal OUT_L of the comparator 25L to transition from low to high. This causes the output signal LOUT_L of the latch 64 to transition from low to high. Therefore, at time t1, the signal Sg output from the EX-OR circuit 27 transitions from low to high. Then, the signal Se, which is the voltage Vd that represents the detected value of the fluctuation time of the voltage Vds, begins to rise from zero.

[0075] After that, at time t2, the voltage Vds reaches the second reference voltage Vr2, that is, the divided voltage VDIV reaches the threshold voltage Vth_H. At this time, the voltage VIN+ of the comparator 25H reaches the threshold voltage Vth_H, causing the output signal OUT_H of the comparator 25H to transition from low to high. This causes the output signal LOUT_H of the latch 63 to transition from low to high. Therefore, at time t2, the signal Sg output from the EX-OR circuit 27 transitions from high to low.

[0076] Then, the signal Se, which is the voltage Vd representing the detected value of the fluctuation time of the voltage Vds, stops rising and is then maintained at the voltage value at time t2. Thereafter, during the period Ta, the voltage IN+ of the comparator 25H repeatedly rises and falls around the threshold voltage Vth_H due to ringing at the time of turn-off. Therefore, during the period Ta, the output signal OUT_H of the comparator 25H repeatedly erroneously goes low and then erroneously goes high again.

[0077] That is, during the period Ta, the comparator 25H experiences an erroneous response due to ringing. However, despite this erroneous response of the comparator 25H, the output signal LOUT_H of the latch 63 remains at a high level even during the period Ta. Therefore, as shown by the solid line in FIG. 12, the signal Sg output from the EX-OR circuit 27 also remains at a low level, and the voltage value of the signal Se remains correctly held at the voltage value at time point t2.

[0078] The configuration of this embodiment described above also makes it possible to detect the transition time of the voltage Vds, as in the first embodiment. Furthermore, as in the first embodiment, the configuration of this embodiment also makes it possible for the two comparators 25H and 25L to operate at the same threshold voltage, making the difference in delay time between the two comparators 25H and 25L negligible. As a result, it is possible to obtain the excellent effect of reducing detection errors in the detection time. Furthermore, this embodiment also provides the following effects.

[0079] That is, in the configuration of the first embodiment, if the voltage VIN+ of the comparators 25H and 25L changes so as to cross the threshold voltages Vth_H and Vth_L due to ringing at turn-off or the like, the comparators 25H and 25L may erroneously react, resulting in an error in the detected value of the detected time. Specifically, in the configuration of the first embodiment, if the comparator 25H erroneously reacts due to ringing, as shown by the dashed line in Fig. 12, the voltage value of the signal Se may increase by an amount corresponding to the period during which the output signal OUT_H erroneously went low, i.e., the period during which the signal Sg erroneously went high, and the detected value of the detected time may become higher than the actual value.

[0080] In contrast, in the configuration of this embodiment, even if the voltage VIN+ of the comparators 25H, 25L changes to cross the threshold voltages Vth_H, Vth_L due to ringing at turn-off or the like, the levels of the output signals LOUT_H, LOUT_L of the latches 63, 64 do not change to erroneous levels. Therefore, according to the configuration of this embodiment, even if an erroneous reaction occurs in the comparators 25H, 25L due to ringing, the voltage value of the signal Se remains correctly held at the voltage value at time point t2, thereby reducing the possibility of a detection error occurring in the detected time.

[0081] (Fourth embodiment) The fourth embodiment will be described below with reference to FIGS. In this embodiment, the specific configuration of the gate drive device is different from that of Embodiment 1. As shown in Fig. 13, a gate drive device 71 of this embodiment differs from the gate drive device 1B of the first embodiment shown in Fig. 3 in that it includes a time detection circuit 72 instead of the time detection circuit 15.

[0082] The time detection circuit 72 includes a voltage detection unit 73 and a threshold value variation unit 74 in addition to the same configuration as the time detection circuit 15. In FIG. 13, the same configuration as the time detection circuit 15 in the time detection circuit 72 is represented as a time detection unit 75. The divided voltage VDIV output from the voltage divider circuit 14 is input to the voltage detection unit 73. Based on the divided voltage VDIV, the voltage detection unit 73 detects the power supply voltage Va applied to the drain, which is the main terminal of the switching element 5B.

[0083] The voltage detection unit 73 includes amplifiers 76 and 77, a switch 78, and a capacitor 79. The divided voltage VDIV is input to the non-inverting input terminal of the amplifier 76. The inverting input terminal and output terminal of the amplifier 76 are connected together. In this manner, the amplifier 76 is configured as a voltage follower and functions as a buffer that receives and outputs the divided voltage VDIV. The output terminal of the amplifier 76 is connected to a node N5 via the switch 78. The capacitor 79 is connected between the node N5 and the power supply line 17 to which the reference potential of the circuit is applied.

[0084] The switch 78 is turned on and off in response to the signal Sh output from the rate-of-change calculation unit 16. The rate-of-change calculation unit 16 generates the signal Sh based on the command signal Sb. The signal Sh is at a high level while the command signal Sb is at a low level, i.e., while the switching element 5 is turned off, and is at a low level during other periods. The switch 78 is turned on while the signal Sh is at a high level, and is turned off while the signal Sh is at a low level. With this configuration, the capacitor 79 is charged by the output voltage of the amplifier 76 while the signal Sh is at a high level. As a result, the capacitor 79 holds a charge equivalent to the off-voltage Vds_off, i.e., the divided voltage VDIV corresponding to the power supply voltage Va.

[0085] The voltage at node N5, i.e., the voltage Ve held by capacitor 79, is input to the non-inverting input terminal of amplifier 77. The inverting input terminal and output terminal of amplifier 77 are also connected. In this way, amplifier 77 is configured as a voltage follower, and functions as a buffer that inputs and outputs voltage Ve. With the above configuration, voltage Vf output from amplifier 77 is a voltage that represents the detected value of power supply voltage Va. Threshold value varying unit 74 varies threshold voltages Vth_H, Vth_L in accordance with the value of power supply voltage Va detected by voltage detecting unit 73, and includes resistors R1, R2, R3, etc.

[0086] Resistors R1, R2, and R3 are connected in series in this order between the output terminal of amplifier 77 and power line 17 to form a resistor voltage divider circuit. In this case, the voltage at node N6, which is the interconnection node between resistors R1 and R2, is the threshold voltage Vth_H, and the voltage at node N7, which is the interconnection node between resistors R2 and R3, is the threshold voltage Vth_L. The resistance values ​​of resistors R1 to R3 are set so that the threshold voltages Vth_L and Vth_H generated by the resistor voltage divider circuit correspond to the first reference voltage Vr1 and the second reference voltage Vr2, respectively.

[0087] As will be described in detail later, the optimum voltage values ​​of the first reference voltage Vr1 and the second reference voltage Vr2 change depending on the off-state voltage Vds_off, i.e., the voltage value of the power supply voltage Va. In the above configuration, when the power supply voltage Va fluctuates, the threshold voltage Vth_L becomes a voltage value that corresponds to the optimum first reference voltage Vr1, and the threshold voltage Vth_H becomes a voltage value that corresponds to the optimum second reference voltage Vr2, in accordance with the fluctuation.

[0088] The threshold voltages Vth_H, Vth_L output from the threshold value varying unit 74 are input to the time detecting unit 75 and also to the rate of change calculating unit 16. Furthermore, the voltage Vf representing the detected value of the power supply voltage Va output from the amplifier 77 of the voltage detecting unit 73 is input to the rate of change calculating unit 16. In this case, the rate of change calculating unit 16 calculates the rate of change dV / dt when the switching element 5 is turned off, based on the signal Se, the command signal Sb, the voltage value of the power supply voltage Va represented by the voltage Vf, and the threshold voltages Vth_H, Vth_L.

[0089] The configuration of this embodiment described above also makes it possible to detect the transition time of the voltage Vds, as in the first embodiment. Furthermore, as in the first embodiment, the configuration of this embodiment also makes it possible for the two comparators 25H and 25L to operate at the same threshold voltage, making the difference in delay time between the two comparators 25H and 25L negligible. As a result, it is possible to obtain the excellent effect of reducing detection errors in the detection time. Furthermore, this embodiment also provides the following effects.

[0090] That is, the off-voltage Vds_off of the switching element 5, i.e., the voltage value of the power supply voltage Va applied to the switching element 5, is not necessarily constant and may fluctuate due to various factors. When the threshold voltages Vth_H and Vth_L are constant voltage values ​​as in the configuration of the first embodiment, fluctuations in the voltage value of the power supply voltage Va may cause errors in the detection of the rate of change dV / dt, which is detected using the detection time. In order to accurately detect the rate of change dV / dt, it is desirable to set the fluctuation time of the voltage Vds, which is the detection time, to the time during which the rising slope of the voltage Vds at turn-off is a constant linear waveform.

[0091] For example, as shown by the solid line waveform in Figure 14, when the power supply voltage Va is a relatively high voltage, the voltage Vds has a linear waveform with a constant slope from the time when the voltage Vds reaches the first reference voltage Vr1 to the time when the voltage Vds reaches the second reference voltage Vr2. If this period is detected as the detection time, the rate of change dV / dt can be detected with high accuracy. Therefore, in this case, the first reference voltage Vr1 and the second reference voltage Vr2 can be said to be optimal voltage values ​​that can improve detection accuracy.

[0092] In contrast, as shown by the dashed waveform in Figure 14, when the power supply voltage Va is a relatively low voltage value, the slope of the voltage Vds waveform changes during the period from when the voltage Vds reaches the first reference voltage Vr1 to when the voltage Vds reaches the second reference voltage Vr2. If such a period is detected as the detection time, an error may occur in the detection of the rate of change dV / dt.

[0093] Therefore, the time detection circuit 72 of this embodiment is configured to include a voltage detection unit 73 that detects the power supply voltage Va and a threshold adjustment unit 74 that adjusts the threshold voltages Vth_H and Vth_L in accordance with the value of the power supply voltage Va detected by the voltage detection unit 73. With this configuration, when the power supply voltage Va varies, the threshold voltage Vth_L can be adjusted to a voltage value corresponding to an optimal first reference voltage Vr1, and the threshold voltage Vth_H can be adjusted to a voltage value corresponding to an optimal second reference voltage Vr2, in accordance with the variation of the power supply voltage Va. Therefore, with the configuration of this embodiment, the detection accuracy of the detection time, and therefore the detection accuracy of the rate of change dV / dt, can be maintained at a high level regardless of variations in the power supply voltage Va.

[0094] (Fifth embodiment) The fifth embodiment will be described below with reference to FIGS. In this embodiment, the specific configuration of the time detection circuit differs from that of the first embodiment. As shown in Fig. 15, a time detection circuit 81 of this embodiment differs from the time detection circuit 15B of the first embodiment shown in Fig. 5 in that it includes a voltage adjustment unit 82 instead of the voltage adjustment unit 32. The voltage adjustment unit 82 outputs a voltage obtained by dividing the divided voltage VDIV, and is configured as a voltage divider circuit that divides the divided voltage VDIV.

[0095] In this case, the voltage adjustment unit 82 includes capacitors C3 and C4. One terminal of the capacitor C3 is connected to the node N2, and the other terminal is connected to the power supply line 17 via the capacitor C4. In this case, the capacitors C3 and C4 function as a pair of voltage-dividing capacitors. With the above configuration, the voltage adjustment unit 82 divides the divided voltage VDIV using the capacitors C3 and C4 and outputs the divided voltage. Specifically, the voltage adjustment unit 82 divides the voltage VDIV in accordance with the capacitance ratio of the capacitors C3 and C4, and outputs the divided voltage from a node N8, which is the interconnection node of the capacitors C3 and C4. The voltage output from the voltage adjustment unit 82, i.e., the voltage at the node N8, is input to the non-inverting input terminal of the comparator 25H.

[0096] According to the above configuration, as shown in Fig. 16, the output signal OUT_L of the comparator 25L changes from low to high at time t1 when the divided voltage VDIV reaches the threshold voltage Vth_L. Furthermore, according to the above configuration, as shown in Fig. 16, the output signal OUT_H of the comparator 25H changes from low to high at time t2 when the divided voltage VDIV reaches the threshold voltage Vth_H. Time t1 corresponds to the first time point when the voltage Vds reaches the first reference voltage Vr1. Time t2 corresponds to the second time point when the voltage Vds reaches the second reference voltage Vr2.

[0097] In this way, in the above configuration, the values ​​of the threshold voltages Vth_L and Vth_H and the voltage division ratio in the voltage adjustment unit 82 are set so that the output signal OUT_L of the comparator 25L is inverted at the first point in time when the voltage Vds reaches the first reference voltage Vr1, and the output signal OUT_H of the comparator 25H is inverted at the second point in time when the voltage Vds reaches the second reference voltage Vr2.

[0098] Next, specific operation timings of the above configuration will be described with reference to FIG. 16. Note that while the command signal Sb is not shown in FIG. 16, the command signal Sb is assumed to be the same as that in FIG. 7. At time tc, when the command signal Sb changes from an ON command to an OFF command, the gate drive circuit 13 drives the switching element 5B to OFF. After a predetermined delay time has elapsed from time tc, the voltage Vds, and therefore the divided voltage VDIV, begin to rise from zero. Thereafter, at time t1, the voltage Vds reaches the first reference voltage Vr1, that is, the divided voltage VDIV reaches the threshold voltage Vth_L.

[0099] At this time, the voltage VIN+ of the comparator 25L reaches the threshold voltage Vth_L, causing the output signal OUT_L of the comparator 25L to transition from low to high. As a result, at time t1, the signal Sg output from the EX-OR circuit 27 transitions from low to high. Then, the signal Se, which is the voltage Vd that represents the detected value of the fluctuation time of the voltage Vds, begins to rise from zero.

[0100] Thereafter, at time t2, voltage Vds reaches second reference voltage Vr2. At this time, as shown by the dashed line in FIG. 16, voltage VIN+ of comparator 25H, which is the voltage obtained by dividing divided voltage VDIV by voltage adjustment unit 82, reaches threshold voltage Vth_L, causing output signal OUT_H of comparator 25H to transition from low to high. Therefore, at time t2, signal Sg output from EX-OR circuit 27 transitions from high to low. Then, signal Se, which is voltage Vd representing the detected value of the fluctuation time of voltage Vds, stops rising and is thereafter maintained at the voltage value at time t2.

[0101] The configuration of this embodiment described above also makes it possible to detect the transition time of the voltage Vds, as in Embodiment 1. Furthermore, as in Embodiment 1, the configuration of this embodiment also makes it possible for the two comparators 25H and 25L to operate at the same threshold voltage, making the difference in delay time between the two comparators 25H and 25L negligible, resulting in an excellent effect of reducing detection errors in the detection time.

[0102] (Other embodiments) The present invention is not limited to the embodiments described above and illustrated in the drawings, but can be arbitrarily modified, combined, or expanded without departing from the spirit of the invention. The numerical values ​​and the like shown in the above embodiments are examples and are not limited to these.

[0103] The gate driver in each of the above embodiments is not limited to driving an N-channel MOSFET, but can also drive various other switching elements such as a P-channel MOSFET or an IGBT. The present invention is not limited to a gate drive device that drives the gate of a switching element 5 that constitutes a half-bridge circuit 4 included in an inverter that drives a motor, but can be applied to all gate drive devices that drive the gate of a switching element, such as a gate drive device that drives the gate of a switching element included in a converter such as a power supply circuit.

[0104] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0105] 1, 1A, 1B, 71...gate driving device, 5, 5A, 5B...switching element, 15, 15A, 15B, 51, 61, 72, 81...time detection circuit, 24, 32, 82...voltage adjustment unit, 25H, 25L...comparator, 26...detection unit, 36...capacitor, 52...voltage adjustment unit, 62...detection unit, 63, 64...latch, 73...voltage detection unit, 74...threshold change unit.

Claims

1. A time detection circuit that detects a detected time, which is a time from a first point in time when a main terminal voltage, which is a voltage at a main terminal of a switching element (5, 5A, 5B), reaches a first reference voltage to a second point in time when the main terminal voltage reaches a second reference voltage different from the first reference voltage, a voltage adjusting unit (24, 32, 82) that outputs a voltage obtained by level-shifting or dividing a voltage corresponding to the main terminal voltage; Two comparators (25H, 25L) each having a first input terminal and a second input terminal, the first input terminal receiving the same threshold voltage; a detection unit (26, 62) that detects the detection time based on the output signals of the two comparators; Equipped with a voltage corresponding to the main terminal voltage is input to the second input terminal of one of the two comparators; the output voltage of the voltage adjusting unit is input to the second input terminal of the other of the two comparators; a time detection circuit in which the value of the threshold voltage and the amount of level shift or voltage division ratio in the voltage adjustment unit are set so that an output signal of one of the two comparators is inverted at a first time point when the main terminal voltage reaches the first reference voltage, and an output signal of the other of the two comparators is inverted at a second time point when the main terminal voltage reaches the second reference voltage.

2. 2. The time detection circuit according to claim 1, wherein the voltage adjustment unit (24, 32) is configured as a level shift circuit that shifts the level of a voltage corresponding to the main terminal voltage.

3. The voltage adjusting unit a capacity (36); 3. The time detection circuit according to claim 2, wherein a voltage corresponding to the level shift amount is applied between the two terminals of the capacitor to charge it, and a voltage corresponding to the main terminal voltage is applied to one terminal of the charged capacitor, thereby outputting a voltage obtained by level-shifting the voltage corresponding to the main terminal voltage from the other terminal of the capacitor.

4. If the voltage adjustment unit (24) is a first voltage adjustment unit, Further, a second voltage adjusting unit (52) configured as the level shift circuit similar to the first voltage adjusting unit is provided, an output voltage of the second voltage adjusting unit is input to the second input terminal of one of the two comparators, instead of a voltage corresponding to the main terminal voltage; 4. The time detection circuit according to claim 3, wherein the value of the threshold voltage, the amount of level shift in the first voltage adjustment unit, and the amount of level shift in the second voltage adjustment unit are set so that an output signal of one of the two comparators is inverted at a first time point when the main terminal voltage reaches the first reference voltage, and an output signal of the other of the two comparators is inverted at a second time point when the main terminal voltage reaches the second reference voltage.

5. 2. The time detection circuit according to claim 1, wherein the voltage adjustment unit (82) is configured as a voltage dividing circuit that divides a voltage corresponding to the main terminal voltage.

6. The detection unit (62) two latches (63, 64) for receiving the output signals of the two comparators, respectively; 6. The time detection circuit according to claim 1, wherein the detected time is detected based on the output signals of the two latches.

7. moreover, a voltage detection unit (73) that detects a power supply voltage applied to a main terminal of the switching element; a threshold value varying unit (74) that varies the threshold voltage in accordance with the value of the power supply voltage detected by the voltage detection unit; 6. A time detection circuit according to claim 1, comprising:

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