Identifying Uncorrectable Errors Using Error Pattern Analysis

Abstract

Techniques are described for identifying patterns of memory cells in a memory array that predict uncorrectable errors ("corruption patterns"). The techniques described herein identify patterns of cell errors that may produce errors that cannot be corrected by an error correction code (ECC). Identifying uncorrectable cells is achieved by identifying patterns of cell errors that store bit values ​​that deviate from corresponding expected values. These memory cell patterns and various combinations of cells in the patterns are compared to patterns of cells known to be correctable using ECC. If the error pattern, or one or more combinations of erroneous cells in the pattern, are not associated with a pattern that is correctable via ECC, the error pattern is identified as predicting a potentially uncorrectable error.

Description

[Technical Field]

[0001] Technical Field The present disclosure relates to detecting errors in memory devices, and more particularly to pattern-based identification of uncorrectable memory errors in memory devices. [Background technology]

[0002] background Dynamic random access memory (DRAM) is typically constructed from an ordered array of memory cells (e.g., deep trench capacitors), each of which stores a charge state representing a single bit of data that is either a "1" or a "0." A single DRAM device (i.e., an electronically packaged integrated circuit die) may contain millions or even billions of individual cells. The individual cells within each device may be arranged in a hierarchy of blocks of cells.

[0003] In some cases, the charge state stored in a memory cell may unintentionally switch from a stored (written) state to an erroneous state different from the stored state, thereby unintentionally creating an erroneous bit value in the cell. These so-called "soft errors" may be caused, for example, by an encounter between a memory cell and a cosmic particle or by naturally occurring radiation resulting from the breakdown of materials used in the manufacture of electronic devices. A processor in communication with a memory device may execute an error correcting code (ECC) algorithm that uses metadata stored in the memory device to identify errors in corresponding stored data. For example, an ECC algorithm may identify a cell in a memory region that stores a bit value different from the bit value originally written to that cell. Some errors are correctable in that various techniques can be used to restore the written value to the memory cell. Other errors are not correctable.

[0004] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Thus, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Summary of the Invention

[0005] BRIEF DESCRIPTION OF THE DRAWINGS Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which: References to "an" or "one" embodiment in this disclosure do not necessarily refer to the same embodiment, but rather to at least one. [Brief explanation of the drawings]

[0006] [Figure 1A] FIG. 1 illustrates a system according to one or more embodiments. [Figure 1B] FIG. 2 illustrates an exemplary memory region including a memory block made up of an array of individual memory cells, according to one or more embodiments. [Figure 2] FIG. 10 illustrates an exemplary set of operations for detecting uncorrectable memory errors by comparing a subset of erroneous memory cells to a pattern of correctable memory errors, in accordance with one or more embodiments. [Figure 3] FIG. 1 illustrates a relationship between a set of potential corruption pattern combinations and a set of correctable error patterns that meet vulnerability criteria for a memory region, in accordance with one or more embodiments. [Figure 4] FIG. 10 illustrates an exemplary set of operations for detecting uncorrectable memory errors by comparing a subset of erroneous memory cells to a pattern of uncorrectable memory errors, in accordance with one or more embodiments. [Figure 5]FIG. 10 illustrates the minimum overlap between the set of potential corruption pattern combinations and the set of uncorrectable error patterns required to meet vulnerability criteria for a memory region, according to one or more embodiments. [Figure 6] FIG. 1 illustrates an exemplary region of a memory in which individual memory cells are labeled to indicate whether their corresponding stored bit values ​​deviate from an expected value or are correct, according to one or more embodiments. [Figure 7] 7A-7C illustrate a subset of combinations of individual erroneous memory cells (potential corruption patterns) based on the error patterns of the memory region shown in FIG. 6, according to one or more embodiments. [Figure 8A] FIG. 7 illustrates uncorrectable error patterns associated with the memory regions shown in FIG. 6, as determined by analysis of the corresponding error correction codes. [Figure 8B] 8B illustrates a subset of the potential error patterns shown in FIG. 7 that meet a similarity criterion with the uncorrectable error pattern shown in FIG. 8A, in accordance with one or more embodiments. [Figure 9] FIG. 1 shows a block diagram illustrating a computer system according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0007] Detailed Description In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding. One or more embodiments may be practiced without these specific details. Features described in one embodiment may be combined with features described in different embodiments. In some instances, well-known structures and devices are described with reference to block diagram form in order to avoid unnecessarily obscuring the present invention. 1. General overview 2. System Architecture 3. Memory Device Structure and Error Correction Code 4. Use error pattern analysis to predict uncorrectable errors 4.1 Predicting Uncorrectable Errors Using Correctable Corruption Pattern Comparison 4.2 Predicting Uncorrectable Errors Using Uncorrectable Corruption Pattern Comparison 5. Exemplary Embodiments 6. Computer Networks and Cloud Networks 7. Other; Extensions 8. Hardware Overview 1. General overview One or more embodiments include a technique for identifying a pattern of memory cells in a memory array associated with uncorrectable errors. While conventional techniques use memory cell error count totals or error count rates to identify uncorrectable errors, the technique described herein instead identifies patterns of memory cell errors (i.e., a group of one or more memory cells that store bit values ​​that deviate from expected or written bit values) that are associated with a pattern that is unlikely to be correctable (e.g., using an error correction code (ECC)) or that is correctable but likely to generate uncorrectable errors in the future. The system first identifies an initial pattern of erroneous memory cells in a memory region. The system generates additional patterns formed by various combinations of cells included in the initial pattern. The initial pattern and the additional patterns are collectively referred to as potential corruption patterns. The system compares the potential corruption patterns with patterns of cells known to be correctable using ECC. If all of the potential corruption patterns (equivalently referred to as "error patterns") are determined to be correctable using ECC, no further action needs to be taken other than running ECC to correct the erroneous bits. However, if one or more of the combinations of erroneous cells associated with the corruption pattern are not associated with an ECC correctable pattern, the system determines that the memory array (or the region of memory having the erroneous cells) meets the vulnerability criteria for data corruption associated with an uncorrectable error pattern.

[0008] One or more embodiments described and / or claimed herein may not be included in this General Summary section.

[0009] 2. System Architecture FIG. 1A illustrates a memory management system 100 according to one or more embodiments. In the illustrated embodiment, memory management system 100 includes a memory module 102, a memory management engine 128, and a data repository 164. In one or more embodiments, system 100 may include more components than those illustrated in FIG. 1A. The components illustrated in FIG. 1A may be local to or remote from other components used by system 100. The components illustrated in FIG. 1A may be implemented in software and / or hardware and may be distributed across one or more applications and / or machines. Operations described with respect to the components illustrated in FIG. 1A may instead be performed by one or more other components.

[0010] The memory module 102 may include any type of memory type, whether DRAM, SRAM, or magnetic. While the examples described below are presented in the context of DRAM memory, the embodiments described herein are applicable to any other memory type in which error correction codes may be used. The memory module 102 may include one or more memory regions, as described below in the context of FIG. 1B. In some examples, the memory module 102 includes multiple interconnected memory devices. For example, the memory module 102 may include multiple DRAM devices (i.e., electronically packaged DRAM dies) implemented on a substrate. Common configurations of memory modules are single in-line memory modules (SIMMs) or dual in-line memory modules (DIMMs). While the memory module 102 is used for the following description, it will be understood that these techniques are applicable to any size or configuration of memory regions, whether a single memory bank (e.g., a region on a DRAM die), an entire DRAM die, some or all of a DRAM SIMM or DIMM, or a group of many SIMMs or DIMMs. The term "region" as used herein is applicable to any of these memory assembly levels.

[0011] The memory management engine 128 may identify one or more memory cells in the memory module 102 that store bit values ​​that deviate from expected bit values ​​(i.e., erroneous memory cells). The memory management engine 128 may further determine whether the erroneous cells form a pattern that is correctable using an error correction code (ECC).

[0012] The memory management engine 128 includes a memory cell error detector 132 , a potential error pattern generator 136 , a processor 140 , an error correction code store 144 , a pattern comparison engine 156 , and a repair engine 160 .

[0013] Memory cell error detector 132 may detect erroneous memory cells in memory module 102 using metadata stored in memory module 102 in association with error correction codes stored in error correction code store 144. Once detected, memory cell error detector 132 may pass the addresses of the erroneous cells and / or the addresses of the correct cells to potential error pattern generator 136.

[0014] Potential error pattern generator 136 generates mathematical combinations of memory cells in which errors have been detected (using the erroneous cell only once in each combination), thereby generating multiple potential error patterns. As described below, the potential error patterns are generated in preparation for comparison with patterns known to be uncorrectable using ECC. The generation of these patterns predicts possible future error patterns because memory cells are presumed to operate independently of one another, and because memory cells that exhibit current errors are presumed to be more likely to exhibit future errors.

[0015] The processor 140 may communicate with an error-correcting code store 144 that stores one or more error-correcting codes. The processor 140 may communicate with the error-correcting code store 144 and use the stored error-correcting codes to generate representations of one or both of the correctable and uncorrectable cell patterns. In some embodiments, generating representations of one or both of the correctable and uncorrectable cell patterns may be achieved by analyzing characteristics associated with the stored error-correcting codes to efficiently generate approximate representations of one or both of the aforementioned patterns (e.g., using a computationally efficient probabilistic data structure in which the patterns are searched using a Bloom filter). While using code characteristics to generate cell patterns is computationally efficient, this process may generate correctable or uncorrectable error pattern sets that over- or under-represent the actual set of correctable and / or uncorrectable error patterns. These over- or under-inclusive sets may result in false positive or false negative analysis results when compared to the actual error patterns. Thus, in other embodiments, processor 140, in communication with error correction code store 144, may perform various ECCs to generate accurate maps of some or all of the correctable and / or uncorrectable error patterns. Regardless of the technique, processor 140 may compare patterns of correctable memory cells and / or patterns of uncorrectable memory cells as described herein. These generated patterns are stored in correctable error pattern store 148 and uncorrectable error pattern store 152, respectively.

[0016] Stores 148, 152 are memory areas in or in communication with processor 140. Stores 148, 152 may store their associated patterns generated according to the techniques described herein. While shown as elements of processor 140, in another embodiment, these memory areas may be stored in data repository 164. Optional additional and / or alternative storage locations are represented in FIG. 1 using dashed lines to outline stores 148, 152 in data repository 164.

[0017] In one or more embodiments, the various stores (e.g., correctable error pattern store 148, uncorrectable error pattern store 152, error-correcting code store 144) and data repository 164 may be any type of storage unit and / or device for storing data (e.g., a file system, a database, a collection of tables, or any other storage mechanism). Furthermore, these stores and data repositories may include multiple different storage units and / or devices. The multiple different storage units and / or devices may or may not be of the same type, or may or may not be located in the same physical location. Furthermore, these stores may be implemented or executed on the same computing system as memory management engine 128 and / or system 100. In another embodiment, a data store may be implemented or executed on a computing system separate from memory management engine 128 and / or system 100. A data store may be communicatively coupled to system 100 and / or memory management engine 128 via a direct connection or via a network.

[0018] Although not shown in FIG. 1, the data repository may further store aspects such as, for example, potential corruption patterns, executable code for implementing the techniques described herein, and the like.

[0019] The pattern comparison engine 156 may compare one or both of the patterns stored in the correctable error pattern store 148 and the uncorrectable error pattern store 152 with the corresponding (erroneous cell or correct cell) patterns stored in the potential error pattern generator 136.

[0020] The detection of an uncorrectable error is sent to repair engine 160, which may send a notification about repair actions to be taken or may initiate the repair actions itself.

[0021] The information describing techniques for identifying uncorrectable errors using error pattern analysis may be implemented across any of the components in system 100. However, for purposes of clarity and explanation, Figure 1 illustrates memory management engine 128 implementing an embodiment of error pattern analysis.

[0022] In one or more embodiments, memory management engine 128 refers to hardware and / or software configured to perform the operations described herein for identifying uncorrectable errors using error pattern analysis. Examples of operations for identifying uncorrectable errors using error pattern analysis are described below with reference to Figures 2 and 4.

[0023] In one embodiment, memory management engine 128 is implemented on one or more digital devices. The term "digital device" generally refers to any hardware device that includes a processor. A digital device may refer to a physical device that runs applications or virtual machines. Examples of digital devices include computers, tablets, laptops, desktops, netbooks, servers, web servers, network policy servers, proxy servers, general-purpose machines, function-specific hardware devices, hardware routers, hardware switches, hardware firewalls, hardware network address translators (NATs), hardware load balancers, mainframes, televisions, content receivers, set-top boxes, printers, mobile handsets, smartphones, personal digital assistants ("PDAs"), wireless receivers and / or transmitters, base stations, communication management devices, routers, switches, controllers, access points, and / or client devices.

[0024] In one or more embodiments, memory management engine 128 includes one or more interfaces (e.g., generated by repair engine 160), regardless of hardware and / or software configured to facilitate communication between a user and memory management engine 128. Such interfaces render user interface elements and receive input via user interface elements. Examples of interfaces include graphical user interfaces (GUIs), command line interfaces (CLIs), tactile interfaces, and voice command interfaces. Examples of user interface elements include check boxes, radio buttons, drop-down lists, list boxes, buttons, toggles, text fields, date and time selectors, command lines, sliders, pages, and forms.

[0025] In one embodiment, different components of the interface are specified in different languages. The behavior of the user interface elements is specified in a dynamic programming language such as JavaScript. The content of the user interface elements is specified in a markup language such as HyperText Markup Language (HTML) or XML User Interface Language (XUL). The layout of the user interface elements is specified in a style sheet language such as Cascading Style Sheets (CSS). Alternatively, the interface may be specified in one or more other languages ​​such as Java, C, or C++.

[0026] 3. Memory Device Structure and Error Correction Code FIG. 1B shows a more detailed diagram of memory module 102 according to one or more embodiments. As shown in FIG. 1B, memory module 102 is a 32-bit DRAM memory region. Memory module 102 includes two memory blocks 104 and 108 (sometimes equivalently referred to as "memory banks" or "memory regions"). Each of memory blocks 104 and 108 is formed from an array of 16 memory cells. As shown in FIG. 1B, memory block 104 includes cells 112A-112H arranged in a first column 110 and memory cells 116A-116H arranged in a second column 114. Memory block 108 includes cells 120A-120H arranged in a first column 118 and memory cells 124A-124H arranged in a second column 122. Since each memory cell of the exemplary memory module 102 is capable of storing a single bit (eg, as a high or low charge state on a capacitor), each of the blocks 104, 108 can store 16 bits.

[0027] In some embodiments, each column 110, 114, 118, 122 is associated with a corresponding input / output (I / O) pin of an electronically packaged DRAM device (not shown) of which memory module 102 is a component. In some embodiments, each row of memory cells (e.g., 112A, 116A, 120A, 124A) can be read and / or written during a single clock cycle of a computer system of which memory module 102 is a component.

[0028] Memory regions and devices may have a hierarchical organization, with the size of a memory block based on the number of rows and columns of memory cells in the memory block. The rows and columns of blocks are generally accessible by bit lines (reading and writing to the columns of memory cells) and word lines (reading and writing to the rows of memory cells). A memory region may be formed from multiple blocks that are accessible via buses or other interconnects fabricated between the blocks.

[0029] In one or more embodiments, memory module 102 may include more or fewer components than those shown in FIG. 1B, which is provided for convenience and clarity of explanation. For example, a single DRAM die (i.e., a patterned and functional silicon chip) may have millions, billions, or trillions of individual memory cells.

[0030] The techniques described herein refer to the use of error correction codes (ECCs) to determine whether a pattern of cells in which one or more errors are detected is correctable or uncorrectable. An error correction code is an algorithm that may use, for example, metadata stored along with a bit value to determine whether the bit value stored in a memory cell (e.g., a high or low charge state in a DRAM capacitor) is the expected value. A bit value stored in a cell that is unexpected or otherwise does not match the value predicted by the ECC is identified as an error. In some examples, running the ECC may correct the erroneous bit value in a cell and restore it to the expected (i.e., written) value.

[0031] The degree to which errors can be corrected by ECC can vary depending, for example, on the algorithm itself (e.g., Golay, multidimensional parity, Hamming) and the microprocessor used in the computing system. In some cases, certain types of error patterns are commonly correctable by many different ECC algorithms. For example, many different ECC algorithms are designed to correct erroneous bit values ​​in cells associated with a common I / O pin. In the context of the example shown in FIG. 1B, an exemplary error pattern associated with the common I / O pin includes one or more erroneous cells in cell column 110 (or equivalently, an error exclusively in any one of columns 114, 118, or 122). Many other patterns of errors are correctable during execution of an ECC algorithm.

[0032] The techniques of this disclosure use ECC to generate patterns known to be correctable, and then compare patterns formed from combinations of erroneous cells in a memory region with these known correctable patterns. If any error patterns (i.e., groups of one or more memory cells storing bit values ​​that deviate from expected or written bit values) exhibited in a region of memory (or any subset thereof) are dissimilar to the correctable error patterns, the system identifies the memory region as vulnerable. In some examples, the error pattern may be correctable but includes one or more cells associated with an uncorrectable error. In response, the system may generate a notification recommending a remedial action or may directly implement the remedial action.

[0033] As described herein, using error pattern analysis to identify a set of vulnerable memory cells in creating an uncorrectable memory cell error pattern has many advantages over conventional techniques for identifying vulnerable memory regions. In part, conventional techniques may erroneously identify some memory regions as vulnerable to permanent memory failures ("false positives") and may erroneously identify some memory regions as not vulnerable to permanent memory failures ("false negatives"). False positive and false negative error identifications can be generated by conventional techniques that rely on simple error counting schemes to identify vulnerable memory regions. For example, if a particular region has a number of errors that exceeds a threshold count, the system identifies that particular region as vulnerable to permanent memory failures. Thus, conventional error counting schemes can generate false positives when high error counts are associated with patterns that are correctable using ECC. Similarly, conventional error counting schemes can generate false negative results when memory regions that are not correctable using ECC generate errors that do not exceed a threshold.

[0034] 4. Use error pattern analysis to predict uncorrectable errors Two example techniques for identifying uncorrectable errors in a memory region are described below. The first technique (described in Section 4.1) compares the pattern of errors in the memory region and various combinations of erroneous cells in the pattern with patterns of memory cells known to be correctable when ECC is applied. If either the memory region corruption pattern or the combinations of cells in the pattern (generated by the system as part of the techniques herein) deviate from the known correctable patterns, the system assumes that the memory region is vulnerable to generating uncorrectable errors in the future. The second technique (described in Section 4.2) applies the inverse of the first technique. The system compares the pattern of errors in the memory region (i.e., a set of potential corruption patterns) and various combinations of erroneous cells in the pattern (generated by the system) with error patterns known to be uncorrectable based on ECC analysis. If either the memory region error pattern or its system-generated combinations match any of the known uncorrectable error patterns, the system assumes that the memory region is vulnerable to generating uncorrectable errors in the future.

[0035] 4.1 Predicting Uncorrectable Errors Using Correctable Corruption Pattern Comparison 2 illustrates an exemplary set of operations as a method 200 for identifying memory regions that may contain uncorrectable errors and require repair, in accordance with one or more embodiments. One or more of the operations illustrated in FIG. 2 may be modified, rearranged, or omitted altogether. Thus, the particular sequence of operations illustrated in FIG. 2 should not be construed as limiting the scope of one or more embodiments.

[0036] Method 200 may begin by the system identifying memory cells in a memory region associated with at least one error (operation 204). The system may use ECC to identify memory regions containing at least one error and determine whether bit values ​​associated with particular memory cells in the memory region (e.g., low or high charge states of capacitors in a DRAM device) match expected values. If the stored bit value differs from the bit value expected for a particular memory cell, the system identifies the particular memory cell as storing an erroneous bit value (i.e., associating the cell with an error). The system may analyze cells in a particular region of memory to identify a pattern of memory cells in the region that store bit values, some of which store the correct bit value and others of which store the erroneous bit value.

[0037] The pattern of correct and / or erroneous bit values ​​corresponding to the memory region may correspond to an “instantaneous” pattern generated as a snapshot when operation 204 is performed. The pattern may be used to generate an error vector to represent the erroneous cells. In some examples, the system may repeatedly perform operation 204 over a period of time to accumulate (or “assemble”) patterns of correct and erroneous memory cells in the memory region (operation 208). The system may generate an error vector having erroneous memory cells accumulated over time. The error vector may accumulate memory cell identifiers associated with errors over time by combining sets of erroneous cells generated by repeated executions of operation 204 (e.g., using an “OR” operation). In other examples, errors are accumulated in one or more error vectors (e.g., each error vector associated with a region or set of memory cells, or each error vector associated with a single region at a particular detection time or a single region within a particular detection time). In various examples, the error vector is a representation of all memory cells associated with errors during a measurement period. The error vectors may then be combined to form a combined error vector. In some examples, the combined set may be referred to as a "superset." Similarly, the combined error vectors may be used to generate a superset of potential corruption patterns. The superset may then be analyzed to determine similarities with correctable or uncorrectable error patterns, as described herein.

[0038] The aforementioned embodiments of the error vector may associate an error with a cell once an erroneous bit value is detected. By using the occurrence of a single error in a cell to identify an error, it is assumed that a memory cell exhibiting an error at one time is more likely to exhibit an error in the future. Other embodiments of the error vector may further operate with the additional assumption that some errors are random events (e.g., resulting from cosmic particles) that may not necessarily predict future failure of the cell. Assuming a random event error model may mean that some exemplary error vectors may accumulate errors using a filter that does not identify a memory cell as erroneous until a minimum threshold number of errors are identified for the cell (operation 212). In one embodiment, the total number of errors may be accumulated toward the threshold during the measurement period. In another embodiment, errors may be accumulated and simultaneously decremented during the measurement period using a removal rate per unit time (e.g., a “leaky bucket” counter).

[0039] In some examples, error vectors associated with distinct memory regions may be stored separately in a table of error vectors. Entries in the error vector table (e.g., corresponding to distinct memory regions and / or corresponding error vectors) may be identified by unique identifiers, allowing the system to access any stored error vector associated with a particular memory region.

[0040] Regardless of the error accounting technique used, once the system identifies memory cells in a memory region as erroneous, it generates multiple subsets of cells associated with the errors. In some embodiments, each subset is a different combination of erroneous memory cells (or their corresponding identifiers) (operation 216). These different combinations represent potential corruption patterns. That is, because cells are assumed to operate independently of one another, any combination of cells associated with errors is identified as a possible future corruption pattern, even if the identified corruption pattern is itself correctable. In some embodiments, each of the different combinations of erroneous memory cells may be represented as one or more error vectors. Representing error patterns and potential corruption patterns as error vectors facilitates similarity analysis, as described below. The subsets of the different combinations of erroneous memory cells may include sets of individual cells or groups of cells. In one example, the subsets include all of the erroneous memory cells.

[0041] The system then identifies patterns of erroneous memory cells that are known to be correctable via the ECC algorithm used by the system (operation 220). These techniques are described above in the context of FIG.

[0042] The system then compares the various potential corruption patterns to the patterns of correctable memory cells generated via the ECC algorithm to determine whether at least one potential corruption pattern does not meet a similarity threshold with any correctable error patterns (operation 224). The system may perform the comparison by performing a similarity comparison (e.g., cosine similarity) between the vector representation of each potential corruption pattern and the vector representation of each correctable error pattern (e.g., using the corresponding error vector).

[0043] If at least one potential corruption pattern does not meet a similarity threshold with any of the correctable error patterns (operation 224), the memory region is determined to be capable of generating uncorrectable errors (operation 228). A vulnerability threshold may be met, and remedial action beyond ECC execution may be recommended (operation 230). The system may optionally correct any errors that are capable of being corrected (operation 238).

[0044] However, if the pattern meets a similarity threshold with a correctable error pattern (operation 224), the error is determined to be correctable (operation 234) and may optionally be corrected by applying ECC (operation 238). In other words, if the set of potential corruption patterns forms a subset of the set of correctable patterns, the error is presumed to be correctable. The vulnerability threshold is not met, and the error may be corrected using ECC (operation 232). The system may optionally continue to monitor for errors by restarting method 200 at operation 204.

[0045] In some instances, repair actions consume significant resources than simply running ECC. Examples of repair actions include reallocating data to a different memory region, duplicating a region of memory in a different memory region or a different memory device, or even physically replacing a memory region (e.g., a DIMM or SIMM). All of these repair actions consume computing and / or monetary resources, and some of the repair actions may only be deployed a fixed number of times before more significant action is taken. The improved accuracy of the techniques described herein improves the operation of a computing device by avoiding the use of repair actions when they are not actually needed.

[0046] 3 is a Venn diagram 300 that graphically illustrates the relationship between the set of correctable corruption patterns 304 and the set of potential corruption patterns 308. As shown, the set of correctable corruption patterns 304 encompasses most, but not all, of the set of potential corruption patterns 308. Instead, portions of the set of potential corruption patterns 308 (indicated by shading) lie outside the set of correctable corruption patterns 304. The shaded portions indicate a subset 312 of potential corruption patterns that do not meet a similarity criterion with any of the set of correctable corruption patterns 304. Ben The portion of diagram 300 representing subset 312 is exaggerated for clarity. In some examples, only a single potential corruption pattern (or a single memory cell in a single potential corruption pattern) needs to be dissimilar to the set of correctable corruption patterns 304 to exceed the vulnerability criterion.

[0047] 4.2 Predicting Uncorrectable Errors Using Uncorrectable Corruption Pattern Comparison FIG. 4 illustrates a method 400 similar to the method 200 illustrated in FIG. 2, with the difference that in method 400, the vulnerability criterion is met when the potential corruption meets a similarity criterion with an error pattern corresponding to an uncorrectable error.

[0048] Method 400 begins with operations similar to those used by method 200. The system identifies memory cells in a memory region associated with at least one error (operation 404). The system may use ECC to identify erroneous memory cells to determine whether a bit value associated with a particular memory cell in the memory region (e.g., a low or high charge state of a capacitor in a DRAM device) matches an expected value. If the stored bit value differs from the expected bit value for the particular memory cell, the system identifies the particular memory cell as storing an erroneous bit value (i.e., associating the cell with an error). The system may identify erroneous cells in a particular region of memory, thereby identifying a pattern of memory cells in the region storing bit values, some of which store correct bit values ​​and some of which store erroneous bit values.

[0049] Similar to method 200, method 400 may further accumulate erroneous memory cells over time in an error vector (operation 408) and / or filter errors using a threshold error count and / or decrement rate (operation 412). These techniques are described above in the context of operations 408 and 412.

[0050] Regardless of the error accounting technique used, once the system identifies memory cells in the memory region as erroneous, it generates multiple subsets of cells associated with the errors (operation 416) to identify potential corruption patterns. In some embodiments, each subset is a different combination of erroneous memory cells (or their corresponding cell identifiers). As described above, the system generates these potential corruption patterns based on the assumption that any cell associated with an error during the measurement period is more likely to be associated with another error in the future. Thus, each potential corruption pattern represents a combination of cells that may produce a future error, assuming that a current erroneous cell may be associated with a future error. In some embodiments, each different combination of erroneous memory cells may be represented as an error vector to facilitate performing a similarity analysis.

[0051] The system then identifies patterns of erroneous memory cells that are known to be uncorrectable via the ECC algorithm used by the system (operation 420). The technique for operation 420 is similar to the technique described above in the context of operation 220.

[0052] The system then compares the various potential corruption patterns to the patterns of uncorrectable memory cells generated via the ECC algorithm (operation 424). The system may perform the comparison of operation 424 by performing a similarity comparison (e.g., cosine similarity) between the vector representation of each potential corruption pattern (i.e., the error vector of each potential corruption pattern) and the vector representation of each correctable error pattern.

[0053] If at least one potential corruption pattern meets a similarity threshold with any of the uncorrectable error patterns (operation 424), the memory region is determined to be capable of generating uncorrectable errors (operation 428). Based on operation 428, the system determines that vulnerability criteria are met (operation 430). The system may optionally identify uncorrectable errors and / or recommend remedial action. The system may optionally correct any errors that are capable of being corrected (operation 438).

[0054] Alternatively, if the potential corruption pattern does not resemble an uncorrectable error pattern, the system determines that the memory region does not meet the vulnerability criteria (operation 434). The error may optionally be corrected using ECC (operation 438), and the system may resume monitoring (operation 404). 5 is a Venn diagram 500 that graphically illustrates an example relationship between a set of uncorrectable corruption patterns 504 and a set of potential corruption patterns 508. As shown, an uncorrectable corruption pattern 504 may be tangent to the set of potential corruption patterns 508. The tangent point 512 indicates that only a single potential corruption pattern 508 needs to meet the similarity criteria with the set of uncorrectable corruption patterns 504 to meet the vulnerability criterion. The single tangent point 512 between a pattern 504 and a pattern 508 represents a minimum condition for meeting the vulnerability criterion.

[0055] 5. Exemplary Embodiments Detailed examples are described below for clarity. The components and / or operations described below should be understood as examples that may not be applicable to certain embodiments. Therefore, the components and / or operations described below should not be construed as limiting the scope of any of the claims.

[0056] 6, 7, 8A and 8B illustrate various stages of the techniques described above in the context of a particular memory region.

[0057] 6 shows a memory region 604 including memory cells 612A, 612B, 612C, and 612D in a first column 610 and memory cells 616A, 616B, 616C, and 616D in a second column 614. Memory region 604 may be part of a larger memory array. The limited size of memory region 604 is presented in FIG. 6 for convenience and clarity of illustration.

[0058] Each of memory cells 612A-612D, 616A-616D is labeled with a corresponding error status 628. Memory cells 612A, 612D, 616A, 616B, and 616C each store a bit that matches a corresponding bit value that is checked using an ECC algorithm executed by a computing device (e.g., a processor) in communication with memory region 604.

[0059] Memory cells 612B, 612C, and 616D are labeled with an error status 628 indicating that the bit values ​​stored in these cells deviate from the expected bit value. The error status 628 for these memory cells is a "threshold number of errors" that reflects the optional use of filters and / or thresholds described above. That is, in some embodiments, memory cells 612B, 612C, and 616D are not associated with an error until a minimum number of deviations from the expected bit value are detected within a measurement period. Once identified as associated with an erroneous bit value, the collection of memory cells 612B, 612C, and 616D constitutes a first corruption pattern.

[0060] Figure 7 illustrates several different combinations of the erroneous cells shown in Figure 6. That is, Figure 7 illustrates potential corruption patterns 704, 708, 712, 716, 720, 724, and 728, each of which is a subset of the erroneous cells shown in Figure 6. Potential corruption patterns 704, 708, and 712 each illustrate potential corruption patterns having only one of erroneous cells 612B, 612C, and 612D. Potential corruption patterns 716, 720, and 724 include potential corruption patterns that are subsets of two of the erroneous cells, respectively. Potential corruption pattern 728 is a subset of all three erroneous cells.

[0061] As explained above, each of the potential corruption patterns 704, 708, 712, 716, 720, 724, and 728 is generated based on the assumption that any memory cell currently storing an erroneous bit value may generate an error in the future.

[0062] 8A illustrates an uncorrectable corruption pattern 804 as determined according to an analysis of an error correction code associated with memory region 604. Uncorrectable corruption pattern 804 includes memory cells 612B and 612C. 616 D.

[0063] 8B shows one potential corruption pattern associated with a different combination of erroneous cells in FIG. 6 that matches uncorrectable error pattern 804. That is, potential corruption pattern 716 includes the same cells 612B and 616D that are present in uncorrectable corruption pattern 804. Because potential corruption pattern 716 matches uncorrectable error pattern 804 (or more generally, meets a similarity criterion with uncorrectable error pattern 804), memory region 604 meets the vulnerability criterion. The system may then take or generate a notification recommending remedial action.

[0064] 6. Computer Networks and Cloud Networks In one or more embodiments, a computer network provides connectivity among a set of nodes. The nodes may be local and / or remote with respect to one another. The nodes are connected by a set of links. Examples of links include coaxial cable, unshielded twisted cable, copper cable, optical fiber, and virtual links.

[0065] A subset of nodes implements computer networks. Examples of such nodes include switches, routers, firewalls, and network address translators (NATs). Another subset of nodes uses computer networks. Such nodes (also referred to as "hosts") may run client processes and / or server processes. A client process makes a request for a computing service (e.g., running a particular application and / or storing a particular amount of data). A server process responds by performing the requested service and / or returning corresponding data.

[0066] A computer network may be a physical network that includes physical nodes connected by physical links. A physical node is any digital device. A physical node may be a function-specific hardware device such as a hardware switch, a hardware router, a hardware firewall, and a hardware NAT. Additionally or alternatively, a physical node may be a general-purpose machine configured to run various virtual machines and / or applications that perform respective functions. A physical link is a physical medium that connects two or more physical nodes. Examples of links include coaxial cable, unshielded twisted cable, copper cable, and optical fiber.

[0067] A computer network may be an overlay network. An overlay network is a logical network implemented on top of another network (e.g., a physical network). Each node in the overlay network corresponds to a respective node in the underlying network. Thus, each node in the overlay network is associated with both an overlay address (which addresses the overlay node) and an underlay address (which addresses the underlay node that implements the overlay node). An overlay node may be a digital device and / or a software process (e.g., a virtual machine, an application instance, or a thread). Links connecting overlay nodes are implemented as tunnels through the underlying network. The overlay nodes at either end of the tunnel treat the underlying multi-hop path between them as a single logical link. Tunneling is achieved through encapsulation and decapsulation.

[0068] In some embodiments, a client may be local to and / or remote from a computer network. A client may access a computer network through a private network or another computer network, such as the Internet. A client may communicate a request to the computer network using a communication protocol, such as the Hypertext Transfer Protocol (HTTP). The request is communicated through an interface, such as a client interface (e.g., a web browser), a program interface, or an application programming interface (API).

[0069] In one embodiment, a computer network provides connectivity between clients and network resources. The network resources include hardware and / or software configured to run server processes. Examples of network resources include processors, data storage, virtual machines, containers, and / or software applications. The network resources are shared among multiple clients. The clients request computing services from the computer network independently of one another. The network resources are dynamically allocated to requests and / or clients on an on-demand basis. The network resources allocated to each request and / or client may be scaled up or down based on, for example, (a) the computing services requested by a particular client, (b) the aggregated computing services requested by a particular tenant, and / or (c) the aggregated computing services requested of the computer network. Such a computer network may be referred to as a "cloud network."

[0070] In one embodiment, a service provider offers a cloud network to one or more end users. Various service models can be enabled by the cloud network, including, but not limited to, Software-as-a-Service (SaaS), Platform-as-a-Service (PaaS), and Infrastructure-as-a-Service (IaaS). In SaaS, the service provider offers end users the ability to use the service provider's applications running on the network resources. In PaaS, the service provider offers end users the ability to deploy custom applications on the network resources. The custom applications can be created using programming languages, libraries, services, and tools supported by the service provider. In IaaS, the service provider offers end users the ability to provide processing, storage, network, and other basic computing resources provided by the network resources. Any arbitrary application, including an operating system, can be deployed on the network resources.

[0071] In an embodiment, various deployment models may be realized by a computer network, including, but not limited to, a private cloud, a public cloud, and a hybrid cloud. In a private cloud, network resources are provided for exclusive use by a specific group of one or more entities (as used herein, the term "entity" refers to a business, organization, person, or other entity). The network resources may be local and / or remote to the premises of the specific group of entities. In a public cloud, cloud resources are provided to multiple entities (also referred to as "tenants" or "customers") that are independent of one another. The computer network and its network resources are accessed by clients corresponding to different tenants. Such a computer network may be referred to as a "multi-tenant computer network." Several tenants may use the same specific network resources at different times and / or simultaneously. The network resources may be local and / or remote to the tenant's premises. In a hybrid cloud, the computer network includes a private cloud and a public cloud. An interface between the private cloud and the public cloud enables data and application portability. Data stored in the private cloud and the public cloud may be exchanged through the interface. Applications implemented in the private cloud and applications implemented in the public cloud may have dependencies on each other. Calls from applications in the private cloud to applications in the public cloud (and vice versa) may be made through interfaces.

[0072] In some embodiments, tenants of a multi-tenant computer network are independent of one another. For example, the business or operations of one tenant may be separate from the business or operations of another tenant. Different tenants may require different network requirements from the computer network. Examples of network requirements include processing speed, amount of data storage, security requirements, performance requirements, throughput requirements, latency requirements, resiliency requirements, Quality of Service (QoS) requirements, tenant isolation, and / or consistency. The same computer network may need to fulfill different network requirements required by different tenants.

[0073] In one or more embodiments, in a multi-tenant computer network, tenant isolation is implemented to ensure that applications and / or data of different tenants are not shared with each other. Various tenant isolation approaches may be used.

[0074] In one embodiment, each tenant is associated with a tenant ID. Each network resource in a multi-tenant computer network is tagged with a tenant ID. A tenant is granted access to a particular network resource only if the tenant and the particular network resource are associated with the same tenant ID.

[0075] In one embodiment, each tenant is associated with a tenant ID. Each application implemented by the computer network is tagged with a tenant ID. Additionally or alternatively, each data structure and / or dataset stored by the computer network is tagged with a tenant ID. A tenant is granted access to a particular application, data structure and / or dataset only if the tenant and the particular application, data structure and / or dataset are associated with the same tenant ID.

[0076] As an example, each database implemented by a multi-tenant computer network may be tagged with a tenant ID. Only the tenant associated with the corresponding tenant ID may access the data in a particular database. As another example, each entry in a database implemented by a multi-tenant computer network may be tagged with a tenant ID. Only the tenant associated with the corresponding tenant ID may access the data in a particular entry. However, a database may be shared by multiple tenants.

[0077] In one embodiment, the subscription list indicates which tenants have permission to access which applications. For each application, a list of tenant IDs of tenants authorized to access the application is stored. A tenant is granted access to a particular application only if the tenant's tenant ID is included in the subscription list corresponding to the particular application.

[0078] In one embodiment, network resources (e.g., digital devices, virtual machines, application instances, and threads) corresponding to different tenants are isolated in tenant-specific overlay networks maintained by a multi-tenant computer network. As an example, packets from any source device in a tenant overlay network can be sent only to other devices in the same tenant overlay network. An encapsulation tunnel is used to prohibit any transmission from a source device on a tenant overlay network to a device in another tenant overlay network. Specifically, a packet received from a source device is encapsulated in an outer packet. The outer packet is sent from a first encapsulation tunnel endpoint (communicating with a source device in the tenant overlay network) to a second encapsulation tunnel endpoint (communicating with a destination device in the tenant overlay network). The second encapsulation tunnel endpoint decapsulates the outer packet to obtain the original packet sent by the source device. The original packet is sent from the second encapsulation tunnel endpoint to a destination device in the same specific overlay network.

[0079] 7. Other; Extensions Embodiments are directed to systems having one or more devices that include a hardware processor and are configured to perform any of the operations described herein and / or recited in any of the appended claims.

[0080] In one embodiment, a non-transitory computer-readable storage medium includes instructions that, when executed by one or more hardware processors, cause performance of any of the operations described herein and / or recited in any of the appended claims.

[0081] Any combination of the features and functions described herein may be used in accordance with one or more embodiments. In the foregoing specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Therefore, the specification and drawings should be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the invention, and what is intended by the applicant to be the scope of the invention, is the literal and equivalent scope of the set of claims issuing from this application in the specific form from which such claims issue, including any subsequent amendments.

[0082] 8. Hardware Overview According to one embodiment, the techniques described herein are implemented by one or more special-purpose computing devices. The special-purpose computing devices may be hardwired to execute the techniques, or may include digital electronic devices such as one or more application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or network processing units (NPUs) that are permanently programmed to execute the techniques, or may include one or more general-purpose hardware processors that are programmed to execute the techniques according to program instructions in firmware, memory, other storage, or a combination. Such special-purpose computing devices may also combine custom hardwired logic, ASICs, FPGAs, or NPUs with custom programming to achieve the techniques. The special-purpose computing devices may be desktop computer systems, portable computer systems, handheld devices, networking devices, or any other devices incorporating hardwired and / or program logic that implement the techniques.

[0083] 9 is a block diagram illustrating a computer system 900 upon which embodiments of the present invention may be implemented. Computer system 900 includes a bus 902 or other communication mechanism for communicating information, and a hardware processor 904 coupled to bus 902 for processing information. Hardware processor 904 may be, for example, a general-purpose microprocessor.

[0084] Computer system 900 further includes main memory 906, such as a random access memory (RAM) or other dynamic storage device coupled to bus 902, for storing information and instructions to be executed by processor 904. Main memory 906 may also be used to store temporary variables or other intermediate information during execution of instructions to be executed by processor 904. Such instructions, when stored on a non-transitory storage medium accessible to processor 904, render computer system 900 into a special-purpose machine that is customized to perform the operations specified in the instructions.

[0085] Computer system 900 further includes a read-only memory (ROM) 908 or other static storage device coupled to bus 902 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic disk or optical disk, is provided and coupled to bus 902 for storing information and instructions.

[0086] Computer system 900 may be coupled via bus 902 to a display 912, such as a cathode ray tube (CRT), for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is coupled to bus 902 for communicating information and command selections to processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, or cursor direction keys, for communicating directional information and command selections to processor 904 and for controlling cursor movement on display 912. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), which allows the device to locate a position on a surface.

[0087] Computer system 900 may implement the techniques described herein using customized hardwired logic, one or more ASICs or FPGAs, firmware and / or program logic that, in combination with the computer system, causes or programs computer system 900 to be a special-purpose machine. According to one embodiment, the techniques herein are performed by computer system 900 in response to processor 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another storage medium, such as storage device 910. Execution of the sequences of instructions contained in main memory 906 causes processor 904 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0088] The term "storage medium" as used herein refers to any non-transitory medium that stores data and / or instructions that cause a machine to operate in a specific manner. Such storage media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device(s) 910. Volatile media include dynamic memory, such as main memory 906. Common forms of storage media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cartridges, content-addressable memory (CAM), and ternary content-addressable memory (TCAM).

[0089] Storage media is distinct from, but may be used in conjunction with, transmission media. Transmission media participates in transferring information between storage media. For example, transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 902. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0090] Various forms of media may be involved in carrying one or more sequences of one or more instructions to processor 904 for execution. For example, the instructions may initially be carried on a magnetic disk or solid state drive of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 900 may receive the data on the telephone line and convert the data to an infrared signal using an infrared transmitter. An infrared detector may receive the data carried in the infrared signal and appropriate circuitry may place the data on bus 902. Bus 902 carries the data to main memory 906, from which processor 904 retrieves and executes the instructions. The instructions received by main memory 906 may optionally be stored on storage device 910 either before or after execution by processor 904.

[0091] Computer system 900 also includes a communication interface 918 coupled to bus 902. The communication interface 918 provides a two-way data communication coupling to a network link 920 that is connected to a local network 922. For example, communication interface 918 may be an Integrated Services Digital Network (ISDN) card, cable modem, satellite modem, or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 918 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface 918 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

[0092] Network link 920 typically provides data communication through one or more networks to other data devices. For example, network link 920 may provide a connection through local network 922 to a host computer 924 or to data equipment operated by an Internet Service Provider (ISP) 926. ISP 926, in turn, provides data communication services through the world-wide packet data communication network commonly referred to as the "Internet" 928. Local network 922 and Internet 928 both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 920 and through communication interface 918, which carry the digital data to and from computer system 900, are exemplary forms of transmission media.

[0093] Computer system 900 can send messages and receive data, including program code, through the network(s), network link 920 and communication interface 918. In the Internet example, a server 930 might transmit a requested code for an application program through Internet 928, ISP 926, local network 922 and communication interface 918.

[0094] The received code may be executed by processor 904 as it is received, and / or stored in storage device 910, or other non-volatile storage for later execution.

[0095] In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indication of the scope of the invention, and what is intended by the applicant to be the scope of the invention, is the literal and equivalent scope of the set of claims issuing from this application in the specific form in which such claims issue, including any subsequent amendments.

Claims

1. A program comprising instructions that, when executed by one or more hardware processors, cause the performance of operations, the operations including: identifying a first plurality of one or more memory cells in a region of the memory each associated with at least one error by reading values ​​stored in the memory; generating a plurality of combinations corresponding to a subset of the first plurality of one or more memory cells as a first plurality of potential corruption patterns; identifying a plurality of correctable corruption patterns corresponding to correctable errors associated with the memory cells of the region of the memory; determining that at least one potential corruption pattern of the first plurality of potential corruption patterns does not meet a similarity criterion with any of the plurality of correctable corruption patterns; In response to the act of determining: determining that the region of the memory meets a vulnerability criterion for data corruption associated with an uncorrectable error pattern.

2. The operation further comprises: identifying a second plurality of one or more memory cells stored in the region of the memory, each associated with at least one error; generating a plurality of combinations corresponding to a subset of the second plurality of one or more memory cells as a second plurality of potential corruption patterns; combining the first plurality of potential failure patterns with the second plurality of potential failure patterns to form a superset of potential failure patterns; determining that at least one potential corruption pattern of the superset of potential corruption patterns does not satisfy the similarity criterion with any of the plurality of correctable corruption patterns; In response to the act of determining: and determining that the region of the memory meets the vulnerability criteria for data corruption associated with the uncorrectable corruption pattern.

3. 3. The program of claim 1, wherein the operations further include establishing a minimum threshold for errors corresponding to a memory cell of the first plurality of one or more memory cells, wherein a cell is identified as a member of the first plurality of one or more memory cells associated with at least one error when the minimum threshold is exceeded.

4. The first plurality of one or more memory cells identifying one or more memory cells of the first plurality in the region of the memory associated with respective errors during a period of time; collecting each of the memory cells of the first plurality of one or more memory cells identified during the period of time; generating an error vector corresponding to one or more memory cells of the first plurality and an indication of the error; storing the error vector in an error vector table in the region of the memory, the error vector being indexed by an address corresponding to a cell associated with the memory cell; The program of claim 1 , wherein the program is identified by:

5. The operation further comprises: identifying a second plurality of one or more memory cells stored in the region of the memory, each associated with at least one error; generating an additional error vector corresponding to one or more memory cells of the second plurality and an indication of the error; combining the error vector corresponding to one or more memory cells of the first plurality with the additional error vector corresponding to one or more memory cells of the second plurality to form a combined error vector; generating a superset of potential corruption patterns using the combined error vector; determining that at least one potential corruption pattern of the superset of potential corruption patterns does not satisfy the similarity criterion with any of the plurality of correctable corruption patterns; In response to the act of determining: and determining that the region of the memory meets the vulnerability criteria for data corruption associated with the uncorrectable corruption pattern.

6. The act of determining that at least one potential corruption pattern does not satisfy the similarity criterion includes: generating a vector corresponding to said pattern of said plurality of correctable corruption patterns; and performing a vector comparison to compare the error vector corresponding to the memory cell of the first plurality of one or more memory cells with the vectors corresponding to the plurality of correctable corruption patterns.

7. The operation is applying a minimum error threshold to the memory cells of the first plurality of one or more memory cells; measuring a number of errors for each memory cell of the first plurality of one or more memory cells; 7. The program of claim 1, wherein associating the memory cell of the first plurality of one or more memory cells with at least one error comprises associating the error with a particular memory cell when the number of errors for the particular memory cell exceeds the minimum error threshold.

8. The operation is defining a measurement period during which a number of errors for each memory cell of the first plurality of one or more memory cells is measured; identifying an error time associated with the identification of the error associated with one or more memory cells of the first plurality; 8. The program of claim 7, further comprising: defining a threshold period in the measurement period, after which errors associated with one or more memory cells of the first plurality are removed.

9. A program comprising instructions that, when executed by one or more hardware processors, cause the performance of operations, the operations including: identifying a first plurality of one or more memory cells in a region of the memory each associated with at least one error by reading values ​​stored in the memory; generating a plurality of combinations corresponding to a subset of the first plurality of one or more memory cells as a first plurality of potential corruption patterns; identifying a plurality of uncorrectable corruption patterns corresponding to uncorrectable errors associated with the memory cells of the region of the memory; determining that at least one potential corruption pattern of the first plurality of potential corruption patterns satisfies a similarity criterion with any of the plurality of uncorrectable corruption patterns; In response to the act of determining: determining that the region of the memory meets a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

10. The operation further comprises: identifying a second plurality of one or more memory cells stored in the region of the memory, each associated with at least one error; generating a plurality of combinations corresponding to a subset of the second plurality of one or more memory cells as a second plurality of potential corruption patterns; combining the first plurality of potential failure patterns with the second plurality of potential failure patterns to form a superset of potential failure patterns; determining that at least one potential corruption pattern of the superset of potential corruption patterns satisfies the similarity criterion with any of the plurality of uncorrectable corruption patterns; In response to the act of determining: and determining that the region of the memory meets the vulnerability criteria for data corruption associated with an uncorrectable error pattern.

11. 11. The program of claim 9 or 10, wherein the operations further include establishing a minimum threshold of errors corresponding to a memory cell of the first plurality of one or more memory cells, wherein a cell is identified as a member of the first plurality of one or more memory cells associated with at least one error when the minimum threshold is exceeded.

12. The first plurality of one or more memory cells identifying one or more memory cells of the first plurality in the region of the memory associated with respective errors during a period of time; collecting each of the memory cells of the first plurality of one or more memory cells identified during the period of time; generating an error vector corresponding to one or more memory cells of the first plurality and an indication of the error; storing the error vector in an error vector table indexed by an address corresponding to a cell associated with the memory cell in the region of the memory; 10. The program of claim 9, wherein the program is identified by:

13. The operation further comprises: identifying a second plurality of one or more memory cells stored in the region of the memory, each associated with at least one error; generating an additional error vector corresponding to one or more memory cells of the second plurality and an indication of the error; combining the error vector corresponding to one or more memory cells of the first plurality with the additional error vector corresponding to one or more memory cells of the second plurality to form a combined error vector; generating a superset of potential corruption patterns using the combined error vector; determining that at least one potential corruption pattern of the superset of potential corruption patterns satisfies the similarity criterion with any of the plurality of correctable corruption patterns; In response to the act of determining: and determining that the region of the memory meets the vulnerability criteria for data corruption associated with the uncorrectable corruption pattern.

14. The act of determining that at least one potential corruption pattern satisfies the similarity criterion includes: generating a vector corresponding to said pattern of said plurality of uncorrectable corruption patterns; and performing a vector comparison to compare the error vector corresponding to the memory cell of the first plurality of one or more memory cells with the vectors corresponding to the plurality of uncorrectable corruption patterns.

15. The operation is applying a minimum error threshold to the memory cells of the first plurality of one or more memory cells; measuring a number of errors for each memory cell of the first plurality of one or more memory cells; 15. The program of claim 9, wherein associating the memory cell of the first plurality of one or more memory cells with at least one error comprises associating the error with a particular memory cell when a number of errors for the particular memory cell exceeds the minimum error threshold.

16. The operation is defining a measurement period during which a number of errors for each memory cell of the first plurality of one or more memory cells is measured; identifying an error time associated with the identification of the error associated with one or more memory cells of the first plurality; 16. The program of claim 15, further comprising: defining a threshold period in the measurement period, after which errors associated with one or more memory cells of the first plurality are removed.

17. 1. A system comprising: at least one device including a hardware processor; The system is configured to perform the operations of any one of claims 1 to 16.

18. A system comprising means for performing the operations of any one of claims 1 to 16.

19. A method comprising the operations of any one of claims 1 to 16.

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