Communication device and communication system

Abstract

A communication device (100) comprises: first and second partial arrays (101, 102); a distribution means (103) for dividing an input signal into a plurality of distribution signals; first selection means (104A, 104B) for inputting the input signal to the first and second partial arrays (101, 102) in a first mode and inputting the distribution signals to the first and second partial arrays (101, 102) in a second mode; a second selection means (105) for inputting an output signal of the first partial array (101) to the second partial array (102) in the first mode and inputting a zero signal to the second partial array (102) in the second mode; a combination means (106) for combining output signals of the first partial array (101) and the second partial array (102); and a third selection means (107) for outputting the output signal of the second partial array (102) in the first mode and outputting a combination signal output by the combination means (106) in the second mode.

Description

[Technical Field]

[0001] The present disclosure relates to a communication device and a communication system. [Background technology]

[0002] In recent years, MIMO (multiple-input and multiple-output) has been developed as a technology to increase communication speeds. In wireless communications, MIMO aims to increase communication speeds and improve communication quality by using multiple antennas at both the transmitter and receiver. In optical communications, MIMO aims to increase communication speeds by using multicore fiber (MCF) or multimode fiber (MMF).

[0003] In a multicore fiber, multiple cores are arranged in one cladding. The more cores arranged in one cladding, the more the transmission capacity improves, and the faster the communication speed can be achieved. On the other hand, in the case of a multicore fiber, particularly a coupled multicore fiber, the more cores there are, the shorter the distance between cores becomes, making crosstalk more likely to occur. Therefore, it is necessary to compensate for crosstalk between cores. Patent Document 1 describes a technology in which multiple cores in a multicore fiber are divided into several core groups by cutoff sections, and crosstalk removal processing is performed for each core group. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-090227 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 can only accommodate multi-core fibers having cutoff units for dividing multiple cores into several core groups. Furthermore, a compensation circuit for compensating for crosstalk in a multi-core fiber has a configuration in which computing units are arranged in an array. Furthermore, the number of computing units is proportional to the square of the number of cores (the number of input signals). In other words, the number of computing units required for a compensation circuit differs depending on the number of cores included in the multi-core fiber. Therefore, in order to accommodate each multi-core fiber with a different number of cores, a dedicated compensation circuit for each multi-core fiber is required, which increases the manufacturing cost of the communication device. Furthermore, it is conceivable to compensate for crosstalk in a multi-core fiber with a small number of cores by using part of a compensation circuit for a multi-core fiber with a large number of cores. However, in this case, there is a problem that the baud rate decreases, i.e., the communication speed decreases.

[0006] The present disclosure has been made to solve such problems, and aims to provide a communication device and a communication system that are highly versatile and capable of compensating signals without reducing communication speed. [Means for solving the problem]

[0007] A communication device according to a first aspect of the present disclosure comprises a first partial array comprising a portion of an arithmetic unit array in which a plurality of arithmetic units are arranged in an array; a second partial array comprising another portion of the arithmetic unit array; a distribution means for dividing an input signal into a plurality of distribution signals; a first selection means for inputting the input signal to the first partial array or the second partial array in a first mode, and inputting the distribution signal to the first partial array and the second partial array in a second mode different from the first mode; a second selection means for inputting an output signal of the first partial array to the second partial array in the first mode, and inputting a 0 signal to the second partial array in the second mode; a combining means for combining the output signal of the first partial array and the output signal of the second partial array; and a third selection means for outputting the output signal of the second partial array in the first mode, and outputting the combined signal output by the combining means in the second mode.

[0008] A communication system according to a second aspect of the present disclosure comprises a transmitting device that generates and outputs a multiplexed signal, a transmission path that transmits each of the output multiplexed signals, and a communication device according to any one of claims 1 to 3 that receives a multiplexed signal input from the transmission path and outputs a received signal, wherein the communication device compensates for crosstalk imparted to the multiplexed signal transmitted by the transmission path. [Effects of the Invention]

[0009] It is possible to provide a communication device and a communication system that are highly versatile and capable of compensating signals without reducing communication speed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of a communication device according to a first embodiment. [Figure 2] FIG. 10 is a diagram illustrating a configuration of a communication device according to a second embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing an example of a multicore fiber. [Figure 4]FIG. 10 is a diagram illustrating an example of a signal compensation circuit. [Figure 5] FIG. 1 is a diagram illustrating an example of a signal compensation circuit compatible with a single mode fiber. [Figure 6] FIG. 1 is a diagram illustrating the relationship between the configuration of a communication device and a baud rate. [Figure 7] FIG. 1 is a diagram illustrating the relationship between the configuration of a communication device and a baud rate. [Figure 8] FIG. 10 is a diagram illustrating a configuration of a communication device according to a third embodiment. [Figure 9] FIG. 10 is a block diagram showing the configuration of a communication system according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or corresponding elements are designated by the same reference numerals, and for clarity of explanation, duplicate explanations will be omitted as necessary. <Embodiment 1> FIG. 1 is a block diagram showing the configuration of a communication device 100 according to a first embodiment. The communication device 100 includes a computing unit array (not shown) in which a plurality of computing units are arranged in an array. In MIMO, the computing unit array performs predetermined arithmetic processing on a multiplexed signal transmitted through a transmission path. In the first embodiment, a computing unit array that compensates for crosstalk imparted to a multiplexed signal will be described as an example of the computing unit array. Furthermore, the communication device according to the present invention has a configuration in which the computing unit array is divided into a plurality of partial arrays to accommodate a plurality of multiplexed signals each having a different number of multiplexed signals. That is, the communication device according to the present invention uses a single computing unit array to perform arithmetic processing on each of a plurality of multiplexed signals each having a different number of multiplexed signals. For example, as shown in FIG. 1, the communication device 100 includes a first partial array 101, a second partial array 102, a distribution means 103, first selection means 104A and 104B, a second selection means 105, a combination means 106, a third selection means 107, and a control unit 108.

[0012] The first partial array 101 comprises a part of the arithmetic unit array, and the second partial array 102 comprises another part of the arithmetic unit array. The first partial array 101 is a circuit part for processing an input signal S1 included in a multiplexed signal input to the communication device 100, and comprises some of the arithmetic units of the arithmetic unit array. The second partial array 102 is a circuit part for processing an input signal S2 included in a multiplexed signal input to the communication device 100, and comprises another part of the arithmetic units of the arithmetic unit array.

[0013] The distribution means 103 divides the input signal S1 into a plurality of distribution signals S11 and S12. The distribution signal S11 is input to a first selection means 104A, and the distribution signal S12 is input to a first selection means 104B. The distribution means 103 can be realized by, for example, an interleaved ADC (interleaved analog-to-digital converter).

[0014] The first selection means 104A inputs the input signal S1 to the first partial array 101 in the first mode, and inputs the distribution signal S11 to the first partial array 101 in the second mode. Similarly, the first selection means 104B inputs the input signal S2 to the second partial array 102 in the first mode, and inputs the distribution signal S12 to the second partial array 102 in the second mode. Here, the first mode is a mode in which the maximum number of input signals that the communication device 100 can process are input to the communication device 100. In the first embodiment, the number of input signals that the communication device 100 can process is two. In the second mode, a number of input signals that is less than the maximum number of input signals that the communication device 100 can process is one. In the first embodiment, the number that is less than the number of input signals that the communication device 100 can process is one. That is, the communication device 100 according to the first embodiment can compensate for crosstalk of a multiplexed signal in which two input signals S1 and S2 are multiplexed, or of an unmultiplexed input signal S1, using a single arithmetic unit array. A switching signal for switching between the first mode and the second mode is input to the first selection means 104A and 104B from a control unit 108 (described later). The first selection means 104A and 104B then switch between the first mode and the second mode in accordance with the switching signal. The first selection means 104A and 104B can be realized by, for example, a selector.

[0015] The second selection means 105 inputs the output signal of the first partial array 101 to the second partial array 102 in the first mode, and inputs a 0 signal to the second partial array 102 in the second mode. In other words, the second selection means 105 does not input a signal to the second partial array 102 in the second mode. In addition, a switching signal for switching between the first mode and the second mode is input to the second selection means 105 from the control unit 108. Then, the second selection means 105 switches between the first mode and the second mode in accordance with the switching signal. The second selection means 105 can be realized by, for example, a selector.

[0016] The combining means 106 generates a combined signal by combining the output signal of the first sub-array 101 and the output signal of the second sub-array 102. The combined signal generated by the combining means 106 is input to the third selecting means 107. The combining means 106 can be realized by, for example, a multiplexer.

[0017] The third selection means 107 outputs the output signal of the second partial array 102 in the first mode, and outputs the combined signal output by the combining means 106 in the second mode. A switching signal for switching between the first mode and the second mode is input to the third selection means 107 from the control unit 108. The third selection means 107 then switches between the first mode and the second mode in accordance with the switching signal. The third selection means 107 can be realized by, for example, a selector.

[0018] The control unit 108 inputs a switching signal for switching between the first mode and the second mode to the first selection means 104A and 104B, the second selection means 105, and the third selection means 107.

[0019] In the communication device 100 according to the first embodiment described above, when input signals S1 and S2 equal to the maximum number of input signals that the communication device 100 can process are input (first mode), the input signal S1 is input to the first partial array 101, and the input signal S2 is input to the second partial array 102. Next, the input signal S1 that has been compensated for in the first partial array 101 is output from the first partial array 101, and the input signal S2 that has been compensated for in the second partial array 102 is output from the third selection means 107. In this way, the communication device 100 can perform compensation processing on the input signals S1 and S2 included in the multiplexed signal in the first mode.

[0020] Furthermore, in the communication device 100, when input signals S1 fewer than the maximum number of input signals that the communication device 100 can process are input (second mode), the input signal S1 is divided into distribution signals S11 and S12 by the distribution means 103, the distribution signal S11 is input to the first partial array 101, and the distribution signal S12 is input to the second partial array 102. Next, the distribution signal S11 compensated for in the first partial array 101 and the distribution signal S12 compensated for in the second partial array 102 are combined by the combining means 106. Then, the combined signal generated by the combining means 106 is output from the third selecting means 107. In this way, the communication device 100 can perform compensation processing on the non-multiplexed signal S1 in the second mode.

[0021] This allows the communication device 100 to compensate for crosstalk in a multiplexed signal in which two input signals S1 and S2 are multiplexed, or in an input signal S1 that is not multiplexed, using a single arithmetic unit array, thereby providing a highly versatile communication device 100.

[0022] Furthermore, in the second mode, the compensation process is performed using both the first partial array 101 and the second partial array 102, so that the throughput does not decrease. Therefore, it is possible to provide the communication device 100 that can compensate for signals without reducing the communication speed.

[0023] The communication device 100 includes a processor, a memory, and a storage device (not shown). The storage device stores a computer program that implements the processing of the communication method according to this embodiment. The processor then loads the computer program from the storage device into the memory and executes the computer program. This allows the processor to function as a control unit 108.

[0024] Each control unit 108 may be realized by dedicated hardware. Some or all of the components of each device may be realized by general-purpose or dedicated circuits, processors, etc., or a combination of these. These may be configured by a single chip, or by multiple chips connected via a bus. Some or all of the components of each device may be realized by a combination of the above-mentioned circuits, etc., and a program. A CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array), etc., may be used as the processor.

[0025] Furthermore, when some or all of the components of communication device 100 are realized by multiple information processing devices, circuits, etc., the multiple information processing devices, circuits, etc. may be centrally or distributed. For example, the information processing devices, circuits, etc. may be realized as a client-server system, a cloud computing system, or the like, in a form in which each is connected via a communication network. Furthermore, the functions of communication device 100 may be provided in a SaaS (Software as a Service) format.

[0026] <Embodiment 2> FIG. 2 is a diagram showing the configuration of a communication device 200 according to a second embodiment. In the second embodiment, a multiplexed optical signal will be described as an example of a multiplexed signal. Furthermore, a multicore fiber transmission line will be described as an example of a transmission line through which the multiplexed optical signal is transmitted. A multicore fiber transmission line is a transmission line constructed using a multicore fiber. FIG. 3 shows a cross-sectional view of a multicore fiber 300 as an example of a multicore fiber. As shown in FIG. 3, the multicore fiber 300 includes a cladding 301 and a plurality of cores 302 embedded in the cladding 301. In the example shown in FIG. 3, four cores 302 are embedded in the cladding 301. The greater the number of cores 302 included in the multicore fiber 300, the greater the transmission amount and the higher the communication speed. On the other hand, the greater the number of cores in the multicore fiber 300, the shorter the distance between the cores 302, making crosstalk (indicated by arrows in FIG. 3) more likely to occur.

[0027] FIG. 4 shows an example of a compensation circuit 400 that compensates for crosstalk between cores 302 of a multicore fiber 300. FIG. 4 illustrates a case where optical signals in which x-polarization and y-polarization are polarization-multiplexed are input from four cores 1, 2, 3, and 4, respectively. As shown in FIG. 4, the compensation circuit 400 includes a multiplier 401 and an adder 402 as computing units. The compensation circuit 400 also includes an ADC (Analog-Digital Converter) 403 for converting the input x-polarization and y-polarization into digital signals. The multiplier 401 multiplies the input signals X1, X2, X3, and X4 derived from the x-polarization and the input signals Y1, Y2, Y3, and Y4 derived from the y-polarization by a filter coefficient. The adder 402 adds the multiplied input signals X1, X2, X3, and X4 derived from the x-polarization and the multiplied input signals Y1, Y2, Y3, and Y4 derived from the y-polarization, respectively. In this way, in order to compensate for the crosstalk that occurs between each of the four cores 1, 2, 3, and 4, the compensation circuit 400 has a configuration in which arithmetic units 401 and 402 are arranged in an array in a first direction and a second direction that intersects with the first direction. In the example shown in Fig. 4, 64 multipliers 401 and 56 adders are arranged in an array.

[0028] Fig. 5 shows an example of a compensation circuit 500 for an optical signal transmitted through a transmission path constructed using a single-mode fiber (hereinafter also referred to as a "single-mode fiber transmission path"). As shown in Fig. 5, compensation circuit 500 includes, as computing units, four multipliers 501 and two adders 502. Compensation circuit 500 also includes an ADC 503 for converting input x-polarized wave and y-polarized wave into digital signals.

[0029] 4 and 5, the compensation circuit 400 and the compensation circuit 500 have significantly different configurations. Specifically, the number of computing units included in the compensation circuit 400 for an optical signal transmitted through a multicore fiber transmission line is proportional to the square of the number of cores (number of input signals) of the multicore fiber. In other words, the number of computing units required for the compensation circuit differs depending on the number of cores included in the multicore fiber. Therefore, in order to support multicore fibers with different numbers of cores, compensation circuits dedicated to each multicore fiber are required.

[0030] Fig. 6 shows a compensation circuit 600 for an optical signal transmitted through a multicore fiber transmission line having two cores 1 and 2. Similar to compensation circuit 400, compensation circuit 600 includes a multiplier 601, an adder 602, and an ADC 603. Fig. 7 shows a compensation circuit 700 for an optical signal transmitted through a single-mode fiber transmission line having one core. Similar to compensation circuit 500, compensation circuit 700 includes a multiplier 701, an adder 702, and an ADC 703. In compensation circuit 700, multiplier 701 and adder 702 are arranged in parallel. When the baud rate of the optical signal input to compensation circuit 600 and the baud rate of the optical signal input to compensation circuit 700 are the same (e.g., 64 Gsps), the baud rate of the signal input to multipliers 601 arranged in the first direction of compensation circuit 600 (e.g., 16 Gsps) is slower than the baud rate of the signal input to multipliers 701 arranged in the first direction of compensation circuit 700 (e.g., 32 Gsps). Therefore, one computing unit array cannot support both single-mode fiber transmission lines and multi-core fiber transmission lines with the same baud rate. Therefore, a compensation circuit dedicated to the single-mode fiber transmission line and a compensation circuit dedicated to the multi-core fiber transmission line are required. Similarly, to support multi-core fibers with different numbers of cores, a compensation circuit dedicated to each multi-core fiber is required.

[0031] Commercializing an optical communication system typically requires a digital signal processor (DSP) built with an application specific integrated circuit (ASIC). Therefore, incorporating a dedicated compensation circuit for single-mode fiber and a dedicated compensation circuit for each multicore fiber with a different number of cores increases the manufacturing cost of the communication device.

[0032] Therefore, the communication device 200 according to the second embodiment has a configuration in which a computing unit array, in which a plurality of computing units are arranged in an array, is divided into a plurality of partial arrays in order to accommodate a plurality of multiplexed optical signals having different numbers of optical signals. Specifically, as shown in FIG. 2 , the communication device 200 according to the second embodiment includes a first partial array 201, a second partial array 202, a third partial array 203, a fourth partial array 204, distribution means 205A and 205B, first selection means 206A, 206B, 206C, and 206D, second selection means 207A and 207B, combining means 208A and 208B, third selection means 209A and 209B, a control unit 210, an ADC 211, and a multiplier 212 and an adder 213 as computing units. Note that descriptions overlapping with those of the first embodiment will be omitted as appropriate.

[0033] In the second embodiment, a case will be described as an example in which a multiplexed optical signal in which x polarization and y polarization are polarization-multiplexed is input to the communication device 200. Also, a case will be described as an example in which the communication device 200 includes a computing unit array capable of processing a maximum of two optical signals. That is, the maximum number of input signals that the communication device 200 can process is two, and the maximum number of cores of a multicore fiber that the communication device 200 can support is two.

[0034] The first partial array 201, the second partial array 202, the third partial array 203, and the fourth partial array 204 each comprise a different part of a computing unit array. The first partial array 201 and the third partial array 203 are circuit parts for processing an input signal X1 derived from x polarization and an input signal Y1 derived from y polarization, which are included in an optical signal input to the communication device 200. The second partial array 202 and the fourth partial array 204 are circuit parts for processing an input signal X2 derived from x polarization and an input signal Y2 derived from y polarization, which are included in an optical signal input to the communication device 200. The optical signal input to the communication device 200 is converted into a digital signal by an ADC 211.

[0035] Specifically, the first partial array 201 and the third partial array 203 are connected in a first direction, and input signals X1 and Y1 multiplied by the multiplier 212 of the first partial array 201 are input to the third partial array 203. The second partial array 202 and the fourth partial array 204 are connected in a first direction, and input signals X2 and Y2 multiplied by the multiplier 212 of the second partial array 202 are input to the fourth partial array 204. The first partial array 201 and the second partial array 202 are connected in a second direction via second selection means 207A and 207B. The input signals X1 and Y1 multiplied by the multiplier 212 of the first partial array 201 and added by the adder 213 are input to the second partial array 202 via the second selection means 207A and 207B. The third partial array 203 and the fourth partial array 204 are connected in the second direction. The input signals X1 and Y1 are multiplied by the multiplier 212 of the third partial array 203 and added by the adder 213, and are input to the fourth partial array 204.

[0036] The distribution means 205A divides the input signal X1 into a plurality of distribution signals X10 and X11. The distribution signal X10 is input to the first selection means 206A, and the distribution signal X11 is input to the first selection means 206C. The distribution means 205B divides the input signal Y1 into a plurality of distribution signals Y10 and Y11. The distribution signal Y10 is input to the first selection means 206B, and the distribution signal Y11 is input to the first selection means 206D. The distribution means 205A and 205B can be realized, for example, by interleaved ADCs.

[0037] The first selection means 206A inputs the input signal X1 to the first sub-array 201 in the first mode and inputs the distribution signal X10 to the first sub-array 201 in the second mode. Similarly, the first selection means 206B inputs the input signal Y1 to the first sub-array 201 in the first mode and inputs the distribution signal Y10 to the first sub-array 201 in the second mode. Similarly, the first selection means 206C inputs the input signal X2 to the second sub-array 202 in the first mode and inputs the distribution signal X11 to the second sub-array 202 in the second mode. Similarly, the first selection means 206D inputs the input signal Y2 to the second sub-array 202 in the first mode and inputs the distribution signal Y11 to the second sub-array 202 in the second mode.

[0038] Here, the first mode is a mode in which optical signals of the maximum number of input signals that the communication device 200 can process are input to the communication device 200. As described above, in the second embodiment, the number of input signals that the communication device 200 can process is two. Moreover, the second mode is a mode in which optical signals of a number less than the maximum number of input signals that the communication device 200 can process are input to the communication device 200. As described above, in the second embodiment, the number less than the number of input signals that the communication device 200 can process is one. That is, the communication device 200 according to the second embodiment can compensate for crosstalk of a multiplexed optical signal in which two optical signals are multiplexed or of an unmultiplexed optical signal using a single arithmetic unit array. Moreover, a switching signal for switching between the first mode and the second mode is input to the first selection means 206A, 206B, 206C, and 206D from a control unit 210, which will be described later. The first selection means 206A, 206B, 206C, and 206D then switch between the first mode and the second mode in accordance with the switching signal. The first selection means 206A, 206B, 206C, and 206D can be realized by, for example, selectors.

[0039] The second selection means 207A, 207B input the output signal of the first partial array 201 to the second partial array 202 in the first mode, and input a 0 signal to the second partial array 202 in the second mode. In other words, the second selection means 207A, 207B do not input a signal to the second partial array 202 in the second mode. In addition, a switching signal for switching between the first mode and the second mode is input to the second selection means 207A, 207B from the control unit 210. Then, the second selection means 207A, 207B switch between the first mode and the second mode in accordance with the switching signal. The second selection means 207A, 207B can be realized by, for example, a selector.

[0040] The combining means 208A and 208B generate a combined signal by combining the output signal of the first sub-array 201 and the output signal of the second sub-array 202. The combined signals generated by the combining means 208A and 208B are input to the third selecting means 209A and 209B. The combining means 208A and 208B can be realized by, for example, a multiplexer.

[0041] The third selection means 209A outputs the output signal of the second partial array 202 in the first mode, and outputs the combined signal output by the combining means 208A in the second mode. Similarly, the third selection means 209B outputs the output signal of the second partial array 202 in the first mode, and outputs the combined signal output by the combining means 208B in the second mode. In addition, a switching signal for switching between the first mode and the second mode is input from the control unit 210 to the third selection means 209A, 209B. Then, the third selection means 209A, 209B switch between the first mode and the second mode in accordance with the switching signal. The third selection means 209A, 209B can be realized by, for example, a selector.

[0042] The control unit 210 inputs a switching signal for switching between the first mode and the second mode to the first selection means 206A, 206B, 206C, and 206D, the second selection means 207A and 207B, and the third selection means 209A and 209B.

[0043] In the communication device 200 according to the second embodiment described above, when optical signals of the maximum number of input signals that the communication device 200 can process are input (first mode), the input signals X1 and Y1 are input to the first partial array 201, and the input signals X2 and Y2 are input to the second partial array 202. Next, the input signals X1 and Y1 compensated in the first partial array 201 are further compensated in the second partial array 202. Furthermore, the input signals X2 and Y2 compensated in the second partial array 202 are further compensated in the fourth partial array 204. Next, the input signals X1 and Y1 compensated in the second partial array 202 are output from the third selection means 209A and 209B. Furthermore, the input signals X2 and Y2 compensated in the fourth partial array 204 are output from the fourth partial array 204. In this way, the communication device 200 can compensate optical signals included in a multiplexed optical signal in the first mode.

[0044] Furthermore, in the communication device 200, when optical signals fewer than the maximum number of input signals that the communication device 200 can process are input (second mode), the optical signal X1 is divided into distribution signals X10 and X11 by the distribution means 205A, the distribution signal X10 is input to the first partial array 201, and the distribution signal X11 is input to the second partial array 202. Furthermore, in the second mode, the optical signal Y1 is divided into distribution signals Y10 and Y11 by the distribution means 205B, the distribution signal Y10 is input to the first partial array 201, and the distribution signal Y11 is input to the second partial array 202. Next, the distribution signal X10 compensated in the first partial array 201 and the distribution signal X11 compensated in the second partial array 202 are combined by the combining means 208A. Furthermore, the distribution signal Y10 compensated for in the first partial array 201 and the distribution signal Y11 compensated for in the second partial array 202 are combined by the combining means 208B. The combined signals generated by the combining means 208A and 208B are then output from the third selecting means 209A and 209B. In this way, the communication device 200 can perform compensation processing on non-multiplexed optical signals in the second mode. Note that in the second mode, the third partial array 203 and the fourth partial array 204 are not used in the arithmetic processing.

[0045] This allows the communication device 200 to compensate for crosstalk in a multiplexed optical signal in which two optical signals are multiplexed or in an unmultiplexed optical signal using a single computing unit array, thereby providing a highly versatile communication device 200.

[0046] Furthermore, in the second mode, the throughput does not decrease because compensation processing is performed using both the first partial array 201 and the second partial array 202. Therefore, it is possible to provide the communication device 200 that can compensate for signals without reducing the communication speed.

[0047] <Embodiment 3> 8 is a diagram showing the configuration of a communication device 800 according to the third embodiment. The communication device 800 according to the third embodiment differs from the communication device 200 according to the second embodiment in that it includes distribution units 801A and 801B instead of the distribution units 205A and 205B, and further includes first selection units 206E, 206F, 206G, and 206H, second selection units 207C and 207D, combining units 208C and 208D, third selection units 209C and 209D, and combining units 802A and 802B, and includes a control unit 803 instead of the control unit 210. Therefore, in the description of the third embodiment, elements that are the same as or correspond to those in the second embodiment are denoted by the same reference numerals, and descriptions that overlap with those in the second embodiment will be omitted as appropriate.

[0048] The distribution means 801A divides the input signal X1 into distribution signals X10, X11, X12, and X13. The distribution signal X10 is input to the first selection means 206A, the distribution signal X11 is input to the first selection means 206C, the distribution signal X12 is input to the first selection means 206E, and the distribution signal X13 is input to the first selection means 206G. The distribution means 801B divides the input signal Y1 into a plurality of distribution signals Y10, Y11, Y12, and Y13. The distribution signal Y10 is input to the first selection means 206B, the distribution signal Y11 is input to the first selection means 206D, the distribution signal Y12 is input to the first selection means 206F, and the distribution signal Y13 is input to the first selection means 206H. The distribution means 801A and 801B can be realized, for example, by interleaved ADCs.

[0049] The first selection means 206E inputs the input signal X1 multiplied in the first sub-array 201 to the third sub-array 203 in the first mode, and inputs the distribution signal X12 to the third sub-array 203 in the second mode. Similarly, the first selection means 206F inputs the input signal Y1 multiplied in the first sub-array 201 to the third sub-array 203 in the first mode, and inputs the distribution signal Y12 to the third sub-array 203 in the second mode. Similarly, the first selection means 206G inputs the input signal X2 multiplied in the second sub-array 202 to the fourth sub-array 204 in the first mode, and inputs the distribution signal X13 to the fourth sub-array 204 in the second mode. Similarly, in the first mode, the first selection means 206H inputs the input signal Y2 multiplied in the second partial array 202 to the fourth partial array 204, and in the second mode, inputs the distribution signal Y13 to the fourth partial array 204. Also, a switching signal for switching between the first mode and the second mode is input to the first selection means 206A, 206B, 206C, 206D, 206E, 206F, 206G, and 206H from a control unit 803 (described later). Then, the first selection means 206A, 206B, 206C, 206D, 206E, 206F, 206G, and 206H switch between the first mode and the second mode in accordance with the switching signal. The first selection means 206A, 206B, 206C, 206D, 206E, 206F, 206G, and 206H can be realized by, for example, selectors.

[0050] The second selection means 207C and 207D input the output signal of the third partial array 203 to the fourth partial array 204 in the first mode, and input a 0 signal to the fourth partial array 204 in the second mode. In other words, the second selection means 207C and 207D do not input a signal to the fourth partial array 204 in the second mode. Furthermore, a switching signal for switching between the first mode and the second mode is input from the control unit 803 to the second selection means 207A, 207B, 207C, and 207D. The second selection means 207A, 207B, 207C, and 207D then switch between the first mode and the second mode in accordance with the switching signal. The second selection means 207A, 207B, 207C, and 207D can be realized, for example, by a selector.

[0051] The combining means 208C and 208D generate a combined signal by combining the output signal of the third sub-array 203 and the output signal of the fourth sub-array 204. The combined signals generated by the combining means 208C and 208D are input to the third selecting means 209C and 209D. The combining means 208A, 208B, 208C, and 208D can be realized by, for example, multiplexers.

[0052] The third selection means 209C outputs the output signal of the fourth partial array 204 in the first mode, and outputs the combined signal output by the combining means 208C in the second mode. Similarly, the third selection means 209D outputs the output signal of the fourth partial array 204 in the first mode, and outputs the combined signal output by the combining means 208D in the second mode. Furthermore, a switching signal for switching between the first mode and the second mode is input from the control unit 803 to the third selection means 209A, 209B, 209C, and 209D. The third selection means 209A, 209B, 209B, 209C, and 209D then switch between the first mode and the second mode in accordance with the switching signal. The third selection means 209A, 209B, 209B, 209C, and 209D can be realized by, for example, selectors.

[0053] The combining means 802A combines the output signal of the third selecting means 209A and the output signal of the third selecting means 209C to generate a combined signal and outputs the combined signal. Similarly, the combining means 802B combines the output signal of the third selecting means 209B and the output signal of the third selecting means 209D to generate a combined signal and outputs the combined signal. The combining means 802A and 802B can be realized by, for example, a multiplexer.

[0054] The control unit 803 inputs a switching signal for switching between the first mode and the second mode to the first selection means 206A, 206B, 206C, 206D, 206E, 206F, 206G, and 206H, the second selection means 207A, 207B, 207C, and 207D, and the third selection means 209A, 209B, 209C, and 209D.

[0055] The communication device 800 according to the third embodiment described above can compensate for crosstalk of a multiplexed optical signal in which two optical signals are multiplexed or a non-multiplexed optical signal using a single arithmetic unit array, similar to the communication device 200 according to the second embodiment. Therefore, a highly versatile communication device 200 can be provided.

[0056] Furthermore, in the second mode, the compensation process is performed using not only the first partial array 201 and the second partial array 202 but also the third partial array 203 and the fourth partial array 204, thereby improving throughput. Therefore, it is possible to provide a communication device 800 that can be applied to communications with high communication speeds (high baud rates).

[0057] The number of multipliers 212 included in the computing unit array, the number of divisions of the computing unit array, and the number of computing units (multipliers 212, adders 213) included in each partial array are not limited to those in the above-described embodiment. In other words, by designing a communication device by adjusting the number of multipliers 212 included in the computing unit array, the number of divisions of the computing unit array, and the number of computing units included in each partial array, the communication device can perform compensation processing for multiplexed optical signals transmitted through multicore fiber transmission lines with different numbers of cores.

[0058] For example, when the arithmetic unit array has 2N multipliers 212 (N is an integer equal to or greater than 2) arranged in an array in the first direction and 2N multipliers 212 in the second direction, each partial array may have 2M multipliers (M is a number satisfying 1≦M≦(N / 2)) arranged in an array in the first direction and 2M multipliers in the second direction. Here, N corresponds to the number of input signals multiplexed in a multiplexed signal input to a communication device. In other words, when a multiplexed signal is transmitted through a multicore fiber transmission line, N corresponds to the number of cores included in the multicore fiber. It is assumed that the number of multipliers 212 included in each partial array is the same.

[0059] As a result, for example, when N=2, M=1, and the arithmetic unit array has a configuration in which 4×4 multipliers 212 are arranged in an array, and each partial array has a configuration in which 2×2 multipliers 212 are arranged in an array, and the arithmetic unit array is divided into four partial arrays. This is the configuration described in the above-mentioned embodiments 2 and 3, and can perform compensation processing for both a multiplexed optical signal transmitted by a multicore fiber transmission line having two cores and a multiplexed optical signal transmitted by a single-mode fiber transmission line, for example.

[0060] Furthermore, for example, when N=3, 1≦M≦1.5 holds, and the arithmetic unit array has a configuration in which 6×6 multipliers 212 are arranged in an array. When each partial array has a configuration in which 2×2 multipliers 212 are arranged in an array (M=1), the arithmetic unit array is divided into nine partial arrays. When each partial array has a configuration in which 3×3 multipliers 212 are arranged in an array (M=1.5), the arithmetic unit array is divided into four partial arrays. This makes it possible to perform compensation processing for each of multiplexed optical signals transmitted through a multicore fiber transmission line having three cores, a multicore fiber transmission line having two cores, or a single-mode fiber transmission line.

[0061] Furthermore, for example, when N=4, 1≦M≦2 holds, and the arithmetic unit array has a configuration in which 8×8 multipliers 212 are arranged in an array. When each partial array has a configuration in which 2×2 multipliers 212 are arranged in an array (M=1), the arithmetic unit array is divided into 16 partial arrays. When each partial array has a configuration in which 4×4 multipliers 212 are arranged in an array (M=2), the arithmetic unit array is divided into four partial arrays. This makes it possible to perform compensation processing for each of multiplexed optical signals transmitted through a multicore fiber transmission line having four cores, a multicore fiber transmission line having two cores, or a single-mode fiber transmission line.

[0062] Furthermore, for example, when N=5, 1≦M≦2.5 holds, and the arithmetic unit array has a configuration in which 10×10 multipliers 212 are arranged in an array. When each partial array has a configuration in which 2×2 multipliers 212 are arranged in an array (M=1), the arithmetic unit array is divided into 25 partial arrays. When each partial array has a configuration in which 5×5 multipliers 212 are arranged in an array (M=2.5), the arithmetic unit array is divided into four partial arrays. This makes it possible to perform compensation processing for each of multiplexed optical signals transmitted through a multicore fiber transmission line having five cores, a multicore fiber transmission line having two cores, or a single-mode fiber transmission line. Note that when M=2, the number of multipliers 212 included in each partial array is not equal.

[0063] <Embodiment 4> 9 shows the configuration of a communication system 900 according to a fourth embodiment. The communication system 900 includes an optical transmitting device 901, a multicore fiber transmission line 902, and an optical receiving device 903. The optical transmitting device 901 generates and outputs a multiplexed optical signal including various types of information. The multiplexed optical signal output from the optical transmitting device 901 is input to the optical receiving device 903 via the multicore fiber transmission line 902 or the like. The optical receiving device 903 receives the multiplexed optical signal transmitted by the multicore fiber transmission line 902 and outputs a received signal. Specifically, the optical receiving device 903 has a configuration equivalent to any one of the communication devices 100, 200, and 800 according to the first to third embodiments described above, and compensates for crosstalk imparted to the demultiplexed optical signal transmitted by the multicore fiber transmission line 902.

[0064] In the communication system 900 according to the fourth embodiment described above, similarly to the first to third embodiments, a single computing unit array can be used to compensate for crosstalk in a multiplexed optical signal in which a plurality of optical signals are multiplexed, or in an optical signal that is not multiplexed. Furthermore, in the communication system 900, similarly to the first to third embodiments, in the second mode, the compensation process is performed using each partial array, so that throughput does not decrease. Therefore, signals can be compensated without reducing the communication speed. Therefore, it is possible to provide a communication system 900 that is highly versatile and can compensate signals without reducing the communication speed.

[0065] Although the above-described embodiment has been described as a hardware configuration, the present disclosure is not limited to this. The above-described processes of the present disclosure can also be realized by causing a CPU to execute a computer program.

[0066] In the above example, the program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, DVDs (Digital Versatile Discs), and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program may also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can be supplied to a computer via wired communication paths such as electrical wires and optical fibers, or via wireless communication paths.

[0067] The present disclosure is not limited to the above-described embodiments, and may be modified as appropriate without departing from the spirit and scope of the present disclosure. In addition, the present disclosure may be implemented by appropriately combining the respective embodiments.

[0068] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. For example, in the above-described embodiments 2 to 4, compensation processing for a polarization-multiplexed multiplexed optical signal has been described as an example, but the present invention is also applicable to optical communication MIMO that is not polarization-multiplexed, and is also applicable to wireless communication MIMO. Furthermore, in the above-described embodiments, a computing unit array that compensates for crosstalk has been described as an example, but the computing unit array may be any array of computing units, and may perform other processing. [Explanation of symbols]

[0069] 100,200,800 communication equipment 101,201 First subarray 102,202 Second subarray 203 Third Subarray 204 Fourth Subarray 103,205A,205B,801A,801B Distribution means 104A, 104B, 206A to 206H First selection means 105, 207A to 207D Second selection means 106,208A~208D Coupling means 107, 209A to 209D Third selection means 802A,802B coupling means 108,210,803 Control Unit 211 ADC 212 Multiplier 213 Adder 900 Communication Systems 901 Optical transmitter (transmitter) 902 Multicore fiber transmission line 903 Optical receiving device (communication device)

Claims

1. a first partial array including a part of the array of computing units in which a plurality of computing units are arranged in an array and which performs processing to compensate for crosstalk imparted to a multiplexed signal transmitted through a transmission path in a MIMO system; a second partial array including another part of the arithmetic unit array; a dividing means for dividing an input signal into a plurality of divided signals; a first selection means for inputting the input signal to the first partial array or the second partial array in a first mode, and for inputting the distribution signal to the first partial array and the second partial array in a second mode different from the first mode; second selection means for inputting an output signal of the first partial array to the second partial array in the first mode, and for inputting a 0 signal to the second partial array in the second mode; a combining means for combining the output signals of the first subarray and the second subarray; a third selection means for outputting an output signal of the second sub-array in the first mode and outputting a combined signal output by the combining means in the second mode; Equipped with Communication equipment.

2. When the arithmetic unit array has a configuration in which 2N (N is an integer of 2 or more) arithmetic units are arranged in an array in a first direction and 2N (N is an integer of 2 or more) arithmetic units are arranged in an array in a second direction intersecting the first direction, the first partial array and the second partial array have a configuration in which 2M (M is a number satisfying 1≦M≦(N / 2)) arithmetic units are arranged in an array in the first direction and 2M (M is a number satisfying 1≦M≦(N / 2)) arithmetic units are arranged in an array in the second direction. The communication device according to claim 1 .

3. the first mode is a mode in which the maximum number of input signals that the communication device can process is input, and the second mode is a mode in which the number of input signals that is less than the maximum number of input signals is input. The communication device according to claim 1 .

4. a transmitting device that generates and outputs a multiplexed signal; a transmission path for transmitting each of the output multiplexed signals; a communication device according to any one of claims 1 to 3, which receives a multiplexed signal input from the transmission path and outputs a received signal; Equipped with the communication device compensates for crosstalk imparted to the multiplexed signal transmitted through the transmission path; Communication system.

5. The communication system according to claim 4 , wherein the transmission line is a multi-core fiber transmission line.

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