Liquid crystal display device

Abstract

To provide a thin touch panel, a touch panel with high visibility, a lightweight touch panel, or a touch panel consuming less power.SOLUTION: A pair of conductive layers composing a capacitive touch sensor has a plurality of openings, and are formed in a mesh-like shape. The conductive layers are arranged overlapped with a region between two display elements in a plan view. The pair of conductive layers composing the touch sensor are arranged inside a pair of substrates included in a touch panel. A conductive layer that can supply constant potential is provided between the pair of conductive layer and a circuit driving the display elements.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention The present invention relates to an input device. 2. Field of the Invention The present invention relates to a display device. TECHNICAL FIELD One embodiment of the present invention relates to an input / output device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention disclosed herein relates to an article, a method, or a manufacturing method. The technical fields include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, For example, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. It can be mentioned as follows.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one embodiment of a semiconductor device. power devices, input / output devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.) BACKGROUND ART Some electronic devices and devices include semiconductor devices. [Background technology]

[0004] In recent years, display devices equipped with touch sensors as position input means have come into practical use. A display device equipped with a touch sensor is called a touch panel or touch screen. (Hereinafter, this will be simply referred to as a "touch panel"). For example, Mobile information terminals include smartphones and tablet terminals.

[0005] One type of display device is a liquid crystal display device that includes a liquid crystal element. The transistors are arranged in a trix shape and used as switching elements connected to each pixel electrode. Active matrix liquid crystal display devices using such devices have been attracting attention.

[0006] For example, a metal oxide channel-type switching element is used as a switching element connected to each pixel electrode. Active matrix liquid crystal display devices using transistors as a composition region are known. (Patent Documents 1 and 2).

[0007] Active matrix LCD devices are broadly divided into two types: transmissive and reflective. It is known that

[0008] Transmissive LCD devices use a backlight such as a cold cathode fluorescent lamp to convert the liquid crystal optically. By using the adjustment function, the light from the backlight passes through the liquid crystal and is output to the outside of the liquid crystal display device. Select the output state and the non-output state, and display light and dark, and further combine them. By combining these two, an image is displayed.

[0009] In addition, a reflective liquid crystal display device utilizes the optical modulation effect of liquid crystal to reflect external light, i.e., incident light. A state in which the light is reflected by the pixel electrode and output to the outside of the device, and a state in which the incident light is not output to the outside of the device By selecting the brightness and darkness, and combining them, you can display an image. Reflective liquid crystal display devices have a backlight that is lighter than transmissive liquid crystal display devices. Since it does not use a battery, it has the advantage of consuming less power. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0011] A function that allows input by touching the screen with a finger or stylus as a user interface There is a demand for a touch panel that has a display panel with a touch panel.

[0012] In addition, there is a demand for thinner and lighter electronic devices that use touch panels. Therefore, there is a demand for thinner and lighter touch panels.

[0013] For example, the touch panel has a structure in which a touch sensor is provided on the visible side (display surface side) of the display panel. It can be concluded that

[0014] Here, a touch panel in which a capacitive touch sensor is provided on the display surface side of the display panel is When the display panel is configured as a panel, the pixels and wiring that make up the display panel and the touch sensor If the distance between the electrodes and wiring becomes small, the noise generated when the touch sensor drives the display panel decreases. This makes the touch panel more susceptible to noise, resulting in a decrease in detection sensitivity. There are cases where this happens.

[0015] An object of one embodiment of the present invention is to provide a thin touch panel. One of the objectives is to provide a touch panel with high visibility. One of the objectives is to provide a touch panel with reduced power consumption. One of our goals is to provide

[0016] Another object is to provide a novel input / output device. One of our goals is to provide the following.

[0017] The description of these problems does not preclude the existence of other problems. One embodiment does not necessarily solve all of these problems. It is possible to extract other issues from the claims and other descriptions. [Means for solving the problem]

[0018] One aspect of the present invention is a semiconductor device comprising a first substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The touch panel has a third conductive layer, a fourth conductive layer, and a liquid crystal layer. The fourth conductive layer is located on the same plane as the third conductive layer but spaced apart from the third conductive layer. The second conductive layer is located above the liquid crystal layer. The first conductive layer is located above the second conductive layer. The first conductive layer has a plurality of openings. The second conductive layer has a mesh shape having a function of transmitting visible light, and The third conductive layer and the fourth conductive layer overlap each other. The fourth conductive layer has a function of transmitting visible light. The third conductive layer has a portion overlapping one of the openings. The fourth conductive layer has a portion overlapping the other end of the opening. The first conductive layer has a portion located between the third conductive layer and the fourth conductive layer.

[0019] In the above, the second conductive layer functions as a common electrode, and the third and fourth conductive layers Each of the conductive layers preferably functions as a pixel electrode.

[0020] Another aspect of the present invention is a semiconductor device including a first substrate, a first conductive layer, a second conductive layer, and a third conductive layer. a touch panel having the first conductive layer, a fourth conductive layer, a fifth conductive layer, and a liquid crystal layer. The fifth conductive layer is located on the first substrate. The fifth conductive layer has a portion overlapping the third conductive layer. The fourth conductive layer has a portion overlapping the third conductive layer and a portion overlapping the fourth conductive layer. The liquid crystal layer is located above the third conductive layer and the fifth conductive layer. The second conductive layer is located above the liquid crystal layer. The first conductive layer is located above the second conductive layer. The first conductive layer is located on the upper side. The first conductive layer has a mesh-like shape with a plurality of openings. The conductive layer has a function of transmitting visible light, and the portion overlapping with the third conductive layer and the fourth conductive layer The third conductive layer has a portion overlapping with one of the openings. The fourth conductive layer has a portion overlapping with one of the openings. The conductive layer has a portion overlapping the other one of the openings. The third conductive layer, the fourth conductive layer, and the fifth conductive layer At least one of the conductive layers has a function of transmitting visible light. The conductive layer has a portion located between the third conductive layer and the fourth conductive layer. The fifth conductive layer has a comb-like shape or a shape with slits. The third conductive layer and the fifth conductive layer overlap each other, one of the openings, and the third conductive layer or and one of the fifth conductive layers overlap each other, and the other of the third conductive layer or the fifth conductive layer and a portion that does not overlap with the

[0021] In the above, the third conductive layer and the fourth conductive layer each function as a pixel electrode. In addition, the fifth conductive layer preferably functions as a common electrode.

[0022] In the above, the fifth conductive layer is located below the third conductive layer and the fourth conductive layer. It is preferable to place

[0023] In the above, the second conductive layer is electrically connected to a terminal to which a constant potential is supplied. It is preferable that

[0024] In the above, a second substrate is provided above the first conductive layer, and the first conductive layer and The second conductive layer is preferably formed on a second substrate.

[0025] In the above, a light-shielding layer is provided above the first conductive layer, and the light-shielding layer and the first conductive layer Preferably, the conductive layer and the conductive layer have overlapping portions.

[0026] In the above, it is preferable that a circular polarizer be provided above the first conductive layer.

[0027] In the above, a first colored layer and a second colored layer are provided above the third conductive layer. The first colored layer has an area overlapping one of the openings, and the second colored layer has an area overlapping the other of the openings. In this case, the first conductive layer preferably has a region including the first colored layer and the second colored layer. It is preferable that the color layer has a portion overlapping at least one of the color layers.

[0028] In the above, above the third conductive layer and below the second conductive layer, It is preferable that the spacer has a portion overlapping with the first conductive layer.

[0029] In the above, a transistor is provided between the liquid crystal layer and the first substrate, and the transistor One of the source and drain of the transistor is electrically connected to the third conductive layer. The transistor preferably includes a semiconductor layer containing an oxide semiconductor. The semiconductor device has a first gate electrode and a second gate electrode, and the first gate electrode is located below the semiconductor layer. the second gate electrode is located above the semiconductor layer; It is preferable that the semiconductor layer and the third conductive layer have an overlapping region. The gate electrode and the semiconductor layer preferably contain the same metal element.

[0030] Alternatively, in the above, a transistor is provided between the liquid crystal layer and the first substrate, and the transistor The source or drain of the transistor is electrically connected to the third conductive layer. The capacitor is made of a semiconductor layer containing amorphous silicon, polycrystalline silicon, or single crystal silicon. In this case, the transistor preferably has a first gate electrode and a second gate electrode. The first gate electrode is located below the semiconductor layer, and the second gate electrode is The second gate electrode, the semiconductor layer, and the third conductive layer are located above the semiconductor layer. It is preferable to have overlapping regions. [Effects of the Invention]

[0031] According to one aspect of the present invention, a thin touch panel can be provided. It is possible to provide a touch panel that is easy to use. It is also possible to provide a lightweight touch panel. A touch panel with reduced power consumption can be provided.

[0032] Note that one embodiment of the present invention does not necessarily have all of these effects. Other effects can be extracted from the description, drawings, claims, etc. [Brief explanation of the drawings]

[0033] [Figure 1] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 2] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 3] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 4] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 5] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 6] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 7] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 8] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 9] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 10] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 11] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 12] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 13] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 14] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 15] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 16] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 17] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 18] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 19] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 20] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 21] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 22] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 23] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 24] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 25] 1 shows a configuration example of a touch sensor according to an embodiment. [Figure 26] 1 shows a configuration example of a touch sensor according to an embodiment. [Figure 27] 1 shows a configuration example of a touch sensor according to an embodiment. [Figure 28] 1 shows an example of the configuration of a touch panel according to an embodiment. [Figure 29] 1 shows an example of the configuration of a touch panel according to an embodiment. [Figure 30] 1A and 1B are a circuit diagram and a timing chart of a touch sensor according to an embodiment. [Figure 31] 1A to 1C are diagrams illustrating a pixel including a touch sensor according to an embodiment. [Figure 32] 1A to 1C are diagrams illustrating operations of a touch sensor and a pixel according to an embodiment. [Figure 33] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 34] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 35] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 36] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 37] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 38] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 39] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 40]1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 41] FIG. 2 is a diagram illustrating an energy band structure. [Figure 42] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 43] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 44] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 45] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 46] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 47] 1A and 1B are cross-sectional views illustrating one embodiment of a transistor. [Figure 48] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 49] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 50] FIG. 1 is a block diagram of a touch panel module according to an embodiment. [Figure 51] 1 shows a configuration example of a touch panel module according to an embodiment. [Figure 52] 1A to 1C are diagrams illustrating a display module according to an embodiment. [Figure 53] 1A to 1C illustrate electronic devices according to an embodiment. [Figure 54] 1A to 1C illustrate electronic devices according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0034] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0035] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0036] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0037] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0038] The words "film" and "layer" can be used interchangeably. For example, the term "conductive layer" may be changed to the term "conductive film." In some cases, the term "insulating film" can be changed to the term "insulating layer." .

[0039] (Embodiment 1) In this embodiment, a configuration example of an input device (touch sensor) of one embodiment of the present invention and a The structure of an input / output device (touch panel) including an input device according to one embodiment and a display device (display panel) An example will be described with reference to the drawings.

[0040] In the following, a capacitive touch sensor is applied as a touch sensor according to one embodiment of the present invention. This section explains what happens when:

[0041] In this specification, the touch panel has a function of displaying (outputting) images on a display surface. Touch sensors detect when a finger, stylus, or other object touches or approaches the display surface. Therefore, the touch panel is one type of input / output device. do.

[0042] In this specification, the substrate of the touch panel may be provided with, for example, an FPC (Flexible Printed Circuit). Printed Circuit) or TCP (Tape Carrier P Those with connectors such as package or COG (Chip On Gauge) on the board The touch panel module is a device that has an IC (integrated circuit) mounted on it using the On Glass method. It is sometimes called a touch panel or simply a touch panel.

[0043] A capacitive touch sensor applicable to one aspect of the present invention includes a pair of conductive layers. Capacitive coupling occurs between the pair of conductive layers. When the object to be detected touches the pair of conductive layers, or The capacitance between a pair of conductive layers changes when they come close to each other, and this is used for detection. It is possible to do so.

[0044] The capacitance type includes the surface capacitance type and the projected capacitance type. There are two types of capacitance methods, self-capacitance and mutual capacitance, which differ mainly in their driving methods. The mutual capacitance method is preferable because it allows simultaneous multi-point detection.

[0045] Preferably, each of the pair of conductive layers constituting the touch sensor has an opening. More preferably, the mesh-like shape has a plurality of openings. It is preferable that the opening and the display element are arranged so as to overlap each other. By doing so, light from the display element is emitted to the outside through the opening, The pair of conductive layers constituting the touch sensor do not need to be light-transmitting. The material of the pair of conductive layers is a metal or alloy having a lower resistance than the transparent conductive material. Therefore, the influence of delay in the detection signal is reduced, and the timing Furthermore, this configuration can improve the detection sensitivity of the touch panel. The present invention can also be suitably applied to large display devices such as televisions.

[0046] In addition, the pair of conductive layers constituting the touch sensor are disposed between the two display elements in a plan view. In this case, it is preferable that the pair of conductive layers are arranged to overlap with the region of the pair of conductive layers that blocks visible light. It is more preferable to use a material that can provide a conductive layer between adjacent pixels. It can also function as a light-shielding layer to suppress color mixing. There is no need to separately form a black matrix or the like, which simplifies the manufacturing process and reduces the number of steps. This can be expected to improve the accuracy and reduce production costs. By using this technology, a touch panel with excellent visibility can be realized.

[0047] In addition, a light-shielding layer or a circularly polarized light It is preferable to have a configuration including a plate. By doing so, reflection of external light by the conductive layer can be prevented. It is possible to suppress or prevent the conductive layer from being visible to the user. It is possible.

[0048] At this time, a pair of conductive layers constituting the touch sensor avoids the optical path of light from the display element. Since the lenses are arranged in a circular pattern, moire does not occur in principle. This refers to the interference fringes that occur when two or more periodic patterns are superimposed. This makes it possible to realize a touch panel with extremely high display quality.

[0049] Examples of display elements included in the touch panel of one embodiment of the present invention include a liquid crystal element, a MEMS element, and a display element. (Micro Electro Mechanical Systems) Chemical elements, organic EL (Electro Luminescence) elements and light-emitting diodes Light-emitting devices such as LEDs (Light Emitting Diodes), electrophoretic devices, etc. Various display elements can be used.

[0050] Here, the touch panel is a transmissive liquid crystal display device that uses liquid crystal elements as display elements. It is preferable to apply

[0051] Furthermore, a pair of conductive layers constituting the touch sensor are connected to a pair of substrates of the touch panel. In this case, it is preferable to place the conductive layer constituting the touch sensor on the inside. It is preferable that the conductive layer has a shape having an opening. Therefore, for example, a conductive layer constituting the touch sensor may have no opening and be transparent. In comparison with the case where a conductive film having a conductive property is used, the electrical noise generated when driving the display element is reduced by the conductive film. In other words, the display element and the touch panel can be placed between the pair of substrates. High detection sensitivity can be achieved even when both conductive films constituting the sensor are sandwiched. As a result, a touch panel that is both thin and highly sensitive can be realized. .

[0052] Between the pair of conductive layers constituting the touch sensor and the circuit that drives the display element, It is more preferable to provide a conductive layer capable of supplying a constant potential. Specifically, the conductive layer can function as a layer for driving a display element. This prevents noise from the circuit from being transmitted to the touch sensor. This prevents noise generated when the touch sensor is driven from reaching the display element, the circuit that drives the display element, or It is also possible to prevent the current from being transmitted to the wiring that constitutes the circuit. The timing for driving the display element and the timing for driving the touch sensor are shifted. The display element and touch sensor are connected without taking measures such as suppressing the influence of noise by It is also possible to drive both sensors simultaneously or to drive them without synchronizing the timing of these drives. Therefore, for example, the drive frequency of the display element (frame rate) can be By increasing the resolution, smooth video display can be achieved. By increasing the driving frequency of the display element, it is possible to further improve the detection accuracy. The drive frequency and the touch sensor drive frequency can be set independently and freely. For example, depending on the situation, it is possible to set a period during which one or both drive frequencies are set low. By doing so, it is also possible to reduce power consumption.

[0053] In particular, of the pair of conductive layers that function as a common electrode and a pixel electrode of a liquid crystal element, the pixel electrode A vertical electric field type liquid crystal element in which a common electrode is provided on one substrate side and a vertical electric field type liquid crystal element in which a common electrode is provided on the other substrate side In other words, it is preferable to use a transistor and wiring that constitute the pixel and a touch sensor. It is preferable that the common electrode is located between a pair of conductive layers constituting the capacitor. By adopting such a configuration, the common electrode can function as a shield layer. .

[0054] A more specific configuration example of one embodiment of the present invention will be described below with reference to the drawings.

[0055] [Configuration example] FIG. 1(A) is a perspective schematic view of a touch panel module 10 according to one embodiment of the present invention. FIG. 1B is a perspective schematic view of the touch panel module 10 with a pair of substrates separated. The touch panel module 10 has a structure in which a substrate 31 and a substrate 21 are bonded together. The touch sensor 22 is provided on the substrate 21 side.

[0056] The substrate 21 is provided with an FPC 41. A touch panel is attached to the surface of the substrate 21 facing the display panel. The touch sensor 22 includes a conductive layer 23, a conductive layer 24, a conductive layer 25, etc. Also, wiring 29 is provided to electrically connect these conductive layers to the FPC 41. 41 has a function of supplying a signal from the outside to the touch sensor 22. 1 has a function of outputting a signal from the touch sensor 22 to the outside. A form that does not have this feature is sometimes simply called a touch panel.

[0057] The substrate 21 on which the touch sensor 22 is formed is a touch sensor substrate or a touch panel. For example, such a substrate can be used as a touch sensor module. By attaching it to the display surface of a device, a touch panel can be formed.

[0058] The touch sensor 22 includes a plurality of conductive layers 23, a plurality of conductive layers 24, and a plurality of conductive layers 25. The conductive layer 23 has a shape that extends in one direction. The plurality of conductive layers 24 are arranged side by side in the direction of the arrow. The conductive layer 25 is disposed so as to be located between the conductive layers 23 and 25. The conductive layer 25 is disposed so as to be located between the conductive layers 23 and 25. In other words, the extension of the conductive layer 23 electrically connects two adjacent conductive layers 24. The plurality of conductive layers 24 arranged in a direction intersecting the stretching direction are connected by the plurality of conductive layers 25. are electrically connected.

[0059] Here, the conductive layer 23 and the conductive layer 25 have an overlapping region. An insulating layer is provided between the conductive layer 25 and the insulating layer.

[0060] Capacitive coupling occurs between the adjacent conductive layers 23 and 24. The capacitor element 11 is formed by the conductive layer 23 and the conductive layer 24. For example, in the case of a projected capacitance type When using the driving method, one of the conductive layers 23 and 24 is used as a transmitting electrode, The other can be used as a receiving electrode.

[0061] In this example, the plurality of conductive layers 24 are electrically connected by the conductive layer 25. The conductive layer 24 is formed in a shape that is extended in one direction in the same manner as the conductive layer 23, and the conductive layer 23 and the conductive layer 24 By providing an insulating layer between the conductive layer 25 and the conductive film 26, the conductive layer 25 may be omitted. At this time, the conductive layer 23 and the conductive layer 24 partially overlap each other.

[0062] The conductive layers 23, 24, 25, and other conductive films, that is, the conductive layers that constitute the touch panel, As a material that can be used for the wiring and electrodes that form the semiconductor device, for example, a material with a low resistance value is desirable. For example, metals such as silver, copper, and aluminum may be used. Such a structure is made up of many conductors with a diameter or width of a few nanometers. Metal nanowires may also be used. Examples include Ag nanowires, Cu nanowires, and Al nanowires. Nanowires may also be used. In the case of Ag nanowires, the light transmittance is, for example, 89% or more. The sheet resistance value can be realized to be 40Ω / □ or more and 100Ω / □ or less. Such metal nanowires have high transmittance, and are therefore suitable for use as electrodes in display devices, such as pixel electrodes and common electrodes. The metal nanowire may be used as a conducting electrode.

[0063] Alternatively, at least one of the conductive layers 23, 24, and 25 may have a conductive layer. Oxides can also be used, such as conductive materials including indium oxide, tin oxide, or zinc oxide. In addition, a material that transmits visible light may be used for the conductive layer 23, the conductive layer 24, or the conductive layer 25. When a transparent material is used, the conductive layer and the display element are arranged to overlap with each other, and the conductive layer is In other words, a material that transmits visible light may be used. When a material is used, the conductive layer does not need to have a mesh-like upper surface.

[0064] A display unit 32 is provided on the substrate 31. The display unit 32 is arranged in a matrix. The pixel 33 preferably includes a plurality of sub-pixel circuits. The sub-pixel circuits are electrically connected to the display elements. Preferably, the pixel 32 includes a circuit 34 electrically connected to the pixel 33. The circuit 34 is, for example, For example, a circuit that functions as a gate drive circuit can be applied. The circuit 32 or the circuit 34 has a function of supplying a signal from the outside. It is preferable to mount an IC that functions as a source driver circuit on the substrate 31 or the FPC 42. The IC may be mounted on the substrate 31 by the COG method, or the FP on which the IC is mounted may be mounted. C42, TAB, TCP, etc. can also be installed.

[0065] In the touch panel module according to one aspect of the present invention, a touch operation is performed by the touch sensor 22. The position information can be output based on the change in capacitance when the sensor is pressed. This allows images to be displayed.

[0066] [Cross-section example] An example of a cross-sectional configuration of the touch panel module 10 will be described below with reference to the drawings. The touch panel module 10 exemplified below uses VA (Vertical Array) as a display element. It uses a transmissive liquid crystal element in which the (Single Alignment) mode is applied. do.

[0067] [Cross-sectional configuration example 1] FIG. 2 is a schematic cross-sectional view of the touch panel module 10. In FIG. 2, an area including the FPC 42, an area including the circuit 34, an area including the display unit 32, and an FPC 41; 1 shows an example of a cross section of a region including the above.

[0068] The substrate 21 and the substrate 31 are bonded together by an adhesive layer 141. The liquid crystal 112 is sealed in the area surrounded by the substrate 31 and the adhesive layer 141. The substrate 21 has a polarizing plate 130a on the outer surface thereof. The substrate 31 has a polarizing plate 130b on the outer surface thereof. 30b.

[0069] Although not shown, on the outside of the polarizing plate 130a or the polarizing plate 130b, A backlight can be provided. The backlight is a direct type. It may be an LED (Light E) type backlight or an edge-light type backlight. By using a direct backlight equipped with a local This is preferable because it makes edge lapping easier and increases contrast. When a light-type backlight is used, the thickness of the touch panel module including the backlight is This is preferable because it can reduce

[0070] Between the substrate 31 and the substrate 21, there is a touch sensor 22 including a conductive layer 23 and a conductive layer 24; Connection portion 101, wiring 29, display element 60, transistor 201, transistor 202, capacitor A capacitor 203, a connection portion 204, wiring 35, etc. are provided.

[0071] On the substrate 31, insulating layers such as an insulating layer 211, an insulating layer 212, an insulating layer 213, and an insulating layer 214 are formed. A part of the insulating layer 211 serves as a gate insulating layer for each transistor. The insulating layer 212 functions as a dielectric of the capacitor element 203. The insulating layer 213 and the insulating layer 214 are provided to cover the transistors, the capacitor element 203, etc. The insulating layer 214 functions as a planarization layer. In the case where the insulating layer covering the capacitor etc. has three layers, namely, insulating layer 212, insulating layer 213, and insulating layer 214, However, the present invention is not limited to this and may have four or more layers, or may have a single layer or two layers. The insulating layer 214, which functions as a planarizing layer, may not be provided if it is not necessary. .

[0072] Moreover, on the substrate 31, a conductive layer 221, a conductive layer 222, a conductive layer 223, a semiconductor layer 231, and a conductive layer 232 are formed. , a conductive layer 111, etc. are provided. In this example, a plurality of conductive layers obtained by processing the same conductive film are provided. In some cases, layers will be described with the same reference numerals.

[0073] The conductive layer 221 is used as one of the gate electrodes of each transistor and one of the electrodes of the capacitor 203. The conductive layer 222 can be used as a source electrode of each transistor. Alternatively, it can be used for a drain electrode, the other electrode of the capacitor 203, a wiring, or the like. The conductive layer 223 can be used as the other gate electrode of each transistor, wiring, etc. The semiconductor layer 231 can be used as a semiconductor layer for each transistor.

[0074] In FIG. 2, as an example of the display section 32, a sub-pixel 33R, a sub-pixel 33G adjacent thereto, and 1 shows a cross section of a portion of the subpixel 33B. For example, the subpixel 33R is a red subpixel. The subpixel 33G is a subpixel that exhibits green, and the subpixel 33B is a subpixel that exhibits blue, For example, the subpixel 33R includes a transistor 202 and The display device includes a capacitance element 203, a display element 60, and a colored layer 131R. The capacitor 202, the capacitance element 203, wiring, and the like constitute a sub-pixel circuit.

[0075] FIG. 2 shows an example in which a transistor 201 is provided as the circuit 34 .

[0076] In FIG. 2, as an example of a transistor 201 and a transistor 202, a channel is formed. The semiconductor layer 231 is sandwiched between two gate electrodes (conductive layer 221 and conductive layer 223). This shows an example in which the threshold voltage of the transistor is In addition, the conductive layer 221 and the conductive layer 223 are connected to each other, and two gate electrodes are connected to each other. Such a transistor may be driven by a polarity. It is possible to increase the effective mobility and increase the on-current. It is possible to manufacture a circuit capable of high-speed operation. Furthermore, it is possible to reduce the area occupied by the circuit portion. By using a transistor with a large on-state current, it is possible to Even if the number of wires increases when the touch panel is made larger or more precise, This makes it possible to reduce signal delays and suppress display unevenness.

[0077] 3, a structure without the conductive layer 223 may be used. By not providing the touch panel, the manufacturing process can be simplified and manufacturing costs can be reduced. can be done.

[0078] The transistors included in the circuit 34 and the transistors included in the display unit 32 have the same structure. The plurality of transistors in the circuit 34 may all have the same structure. Alternatively, transistors of different structures may be used in combination. The plurality of transistors may all have the same structure, or may have different structures. A combination of these may also be used.

[0079] At least one of the insulating layers 212 and 213 covering each transistor is resistant to water and hydrogen. It is preferable to use a material in which impurities are not easily diffused, such as the insulating layer 212. In this case, the insulating layer 213 can function as a barrier film. It is possible to effectively suppress the diffusion of impurities into the transistor from the outside. This makes it possible to realize a highly reliable touch panel.

[0080] The conductive layer 111 is provided on the insulating layer 214. The conductive layer 111 is The source or drain of the transistor 202 is connected through an opening formed in the insulating layer 212, the edge layer 213, etc. The conductive layer 111 is electrically connected to one of the drains of the capacitor 203. The electrode is electrically connected to the other electrode.

[0081] On the surface of the substrate 21 facing the substrate 31, a conductive layer 23, a conductive layer 24, a conductive layer 25, wiring 29, an insulating layer An edge layer 121, an overcoat 123, a spacer 124, a colored layer 131G (not shown), A colored layer 131R, a colored layer 131B, a light-shielding layer 132, a conductive layer 113, and the like are provided.

[0082] 2 shows a cross section of the intersection of the conductive layer 23 and the conductive layer 24. The conductive layer 25 is provided on the same plane as the conductive layer 23 and the conductive layer 24. The conductive layer 23 is sandwiched between two insulating layers 121 and 122. The conductive layer 24 is electrically connected to the conductive layer 25 through an opening provided in the insulating layer 121. There are.

[0083] The light-shielding layer 132, the colored layer 131R, etc. are provided on the insulating layer 121. An overcoat 123 is provided to cover the layer 132, the colored layer 131R, etc. On the coating 123, a conductive layer 113 is provided.

[0084] In FIG. 2, the display element 60 is sandwiched between the conductive layer 111 and a part of the conductive layer 113. The display is made up of a liquid crystal 112.

[0085] In the conductive layer 111, the conductive layer 113, the insulating layer 214, etc., the surface in contact with the liquid crystal 112 An alignment film for controlling the alignment of the liquid crystal 112 may be provided on the liquid crystal layer 112 .

[0086] In the configuration shown in FIG. 2, the conductive layer 23 and the like are arranged so as not to overlap the display element 60. In other words, the opening of the conductive layer 23 and the display element 60 are overlapped with each other. Alternatively, the conductive layer 23 may be formed on the substrate 21 so that the conductive layer 23 is formed on the substrate 21 between two adjacent sub-pixels. The conductive layer 111 is disposed so as to overlap the area between the two conductive layers 111. Although the example of the layer 23 is shown, the conductive layer 24 and the conductive layer 25 are also similarly not overlapped with the display element 60. It is preferable that the electrodes are arranged in such a manner that the electrodes are not overlapped.

[0087] In the display element 60, the conductive layer 111 and the conductive layer 113 have a function of transmitting visible light. With this configuration, the display element 60 can be a transmissive liquid crystal element. For example, when the backlight is disposed on the substrate 31 side, the backlight polarized by the polarizing plate 130b The light from the light passes through the substrate 31, the conductive layer 111, the liquid crystal 112, the conductive layer 113, and the substrate 21. At this time, the light passing through the conductive layer 111 and the conductive layer 113 reaches the polarizing plate 130a. The orientation of the liquid crystal 112 can be controlled by applying a voltage, thereby controlling the optical modulation of light. That is, the intensity of the light emitted through the polarizing plate 130a can be controlled. The light outside the specific wavelength range is absorbed by the colored layer 131R, and the light is extracted. The emitted light is, for example, red light.

[0088] Here, a linear polarizer may be used as the polarizer 130a, but a circular polarizer may also be used. For example, a linear polarizer and a quarter-wave retardation plate are laminated together to form a circular polarizer. In particular, as shown in FIG. 2, the touch sensor 132 can be positioned closer to the substrate 21 than the light-shielding layer 132. When the conductive layers 23 and 24 (and the conductive layer 25) that constitute the capacitor are arranged, the conductive layers In this case, the polarizing plate 130a reflects external light and the reflected light may be visible. By using a circular polarizer, reflection can be suppressed.

[0089] When a circular polarizing plate is used as the polarizing plate 130a, a circular polarizing plate is also used as the polarizing plate 130b. Alternatively, a normal linear polarizing plate can be used. Depending on the type of polarizing plate applied to b, the cell gap and arrangement of the liquid crystal element used in the display element 60 may be adjusted. The desired contrast can be achieved by adjusting the direction, drive voltage, etc.

[0090] Here, the display element 60 is a pair of electrodes in the thickness direction of the touch panel module 10. The electrode arrangement applies an electric field to the liquid crystal 112 in the thickness direction. The placement method is not limited to this, and a method of applying an electric field in a direction perpendicular to the thickness direction may also be used. good.

[0091] In particular, the touch panel module 10 is a normally black type liquid crystal display device, for example, It is preferable to use a transmissive liquid crystal display device that employs a vertical alignment (VA) mode. The alignment mode is MVA (Multi-Domain Vertical Alignment). nment) mode, PVA(Patterned Vertical Alignme) nt) mode, ASV (Advanced Super View) mode, etc. It is possible.

[0092] In addition, liquid crystal elements applicable to the display element 60 include liquid crystal elements to which various modes are applied. For example, in addition to the VA mode, TN (Twisted Nematic) tic) mode, IPS (In-Plane-Switching) mode, FFS (F Ringe Field Switching) mode, ASM (Axially Sy mmetric aligned Micro-cell) mode, OCB (Optic FLC (F erroelectric Liquid Crystal) mode, AFLC (Ant iFerroelectric Liquid Crystal mode etc. A liquid crystal element can be used.

[0093] The liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of the liquid crystal is due to the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal used in the liquid crystal element is controlled by a bias current (including an electric field or an oblique electric field). Thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC) Polymer Dispersed Liquid Crystal, Ferroelectric Liquid Crystal These liquid crystal materials can be used as cholesteric liquid crystals depending on the conditions. The phases include nematic, smectic, cubic, chiral nematic, and isotropic phases.

[0094] The liquid crystal material may be either a positive type liquid crystal or a negative type liquid crystal. The optimum liquid crystal material may be selected depending on the mode and design to be applied.

[0095] Here, the conductive layer 113 can be used as, for example, a common electrode, and the conductive layer 111 can be used as, for example, a common electrode. For example, it can be used as a pixel electrode.

[0096] In FIG. 2, the conductive layer 113 is disposed on top of the conductive layer 23, the conductive layer 24, the conductive layer 25, etc. Therefore, a common potential, a ground potential, or any other constant potential can be applied to the conductive layer 113. By this, when the conductive layer 23, the conductive layer 24, and the conductive layer 25 are driven, the substrate 31 At the same time, the electrical noise generated on the side of the substrate 31 can be blocked. When the sub-pixel circuit connected to the substrate 21 is driven, the electrical noise generated on the substrate 21 side is blocked. It is possible.

[0097] A connecting portion 204 is provided in an area near the end of the substrate 31. The connecting portion 204 is In the configuration shown in FIG. 5 and a conductive layer 223 are laminated to form a connecting portion 204. In addition, a connecting portion 101 is provided in an area near the end of the substrate 21. The connecting portion 101 is 2, the wiring is electrically connected to the FPC 41 via the connection layer 241. A part of the wire 29, a conductive layer obtained by processing the same conductive film as the conductive layer 25, and a conductive layer 113 and a conductive layer obtained by processing the same conductive film as the conductive film. This shows:

[0098] 2, as an example, a conductive layer 221 functioning as a wiring and a conductive layer 222 functioning as a wiring are shown. For example, the conductive layer 221 may function as a scanning line. The conductive layer 22 is used as one or both of a wiring functioning as a capacitance line and a wiring functioning as a capacitance line. 2 can be used as a wiring that functions as a signal line.

[0099] Here, when a detection object such as a finger or a stylus directly touches the area above the polarizing plate 130a, In that case, a protective layer (ceramic coating, etc.) may be provided on the substrate. The protective layer is preferably made of, for example, silicon oxide, aluminum oxide, or yttrium oxide. Alternatively, inorganic insulating materials such as yttria-stabilized zirconia (YSZ) can be used. Further, the substrate may be made of tempered glass. The tempered glass may be made by an ion exchange method, an air cooling method, or the like. The material is subjected to physical or chemical treatment and compressive stress is applied to the surface. It is possible.

[0100] The overcoat 123 prevents impurities such as pigments contained in the colored layer 131R from being absorbed by the liquid crystal 112. It has the function of preventing the spread of

[0101] The spacer 124 is provided on the conductive layer 113 and is arranged to keep the distance between the substrate 21 and the substrate 31 constant or more. In FIG. 2, the spacer 124 and the structure on the substrate 31 side (for example, For example, the conductive layer 111 and the insulating layer 214 are not in contact with each other. In this example, the spacer 124 is provided on the substrate 21 side. For example, the conductive layers 111 of two adjacent sub-pixels may be provided on the conductive layer 31 side. Alternatively, a granular spacer may be used as the spacer 124. Although materials such as silica can be used for the spacer, organic resins and rubber are also suitable. In this case, the granular spacers are preferably made of a material having elasticity of 0.05 to 0.05 mm. The shape may be irregular.

[0102] Here, as shown in FIG. 2, the spacer 124 and the conductive layer 23 (or the conductive layer 24, the conductive layer 2 5) is preferably arranged so as to overlap the spacer 124 and the light-shielding layer 132. By doing so, the display element 60 is preferably arranged in a space. Since the spacers 124 are not disposed, the light is absorbed, refracted, scattered, etc. by the spacers 124. Since the light is not scattered, the light extraction efficiency can be improved.

[0103] In the touch panel module 10 according to one embodiment of the present invention, the conductive layer 23, the conductive layer 24, and The conductive layer 25 can also function as a light-shielding layer to suppress color mixing between adjacent sub-pixels. In FIG. 3, the conductive layer 23, the conductive layer 24, and the conductive layer 25 also function as a light-shielding layer, and the light-shielding layer 132 is provided. In this case, the conductive layers 23, 24, and 25 are not formed. It is preferable to use a material that blocks visible light. Alternatively, it is preferable to use a material that reflects visible light. Alternatively, a layer containing a material that reflects visible light and a layer that reflects less visible light on the substrate 31 side may be provided. When a layer that absorbs at least a portion of the light transmitted through the conductive layer 111 is laminated, This is preferable because it can prevent light that reaches the conductive layer 23 etc. from being reflected back to the substrate 31 side.

[0104] As shown in FIG. 4, the ends of two adjacent colored layers are overlapped with the conductive layer 23, etc. In FIG. 4, the sub-pixel 33G and the sub-pixel 33R are arranged in the vicinity of the boundary. In this case, the conductive layer 23, the end of the colored layer 131G, and the end of the colored layer 131R are provided so as to overlap each other. In addition, the conductive layer 23 and the colored layer 24 are formed near the boundary between the sub-pixel 33R and the sub-pixel 33B. The end of the layer 131R and the end of the colored layer 131B are provided so as to overlap each other. Since there is no need to provide a new layer that absorbs visible light, manufacturing costs can be reduced. The colored layer disposed on the conductive layer 23 may be only one layer, but colored layers of two or more colors may be disposed on top of each other. This can enhance the effect of absorbing visible light more effectively.

[0105] 5, the conductive layers 23, 24, and The light-shielding layer 132, the colored layer 131R, etc. may be arranged closer to the substrate 21 than the conductive layer 25. By doing so, the conductive layer 23, the conductive layer 24, and the conductive layer 25 can be Since external light does not reach the conductive layer 23, the conductive layer 24, and the conductive layer 25 are not visible. In addition, in FIG. 5, the light-shielding layer 132, the colored layer 131R, etc. are covered. The insulating layer 126 is formed by using a material that functions as a planarizing layer. It is preferable that

[0106] As shown in FIG. 6, the conductive layers 23, 24, and The light-shielding layer 132 is disposed closer to the substrate 21 than the conductive layer 25, and the light-shielding layer 132 is disposed closer to the substrate 31 than the conductive layer 25. A color layer 131R or the like may be disposed.

[0107] 7, the colored layer 131R and the like may be disposed on the substrate 31 side. In this case, the light-shielding layer 132 may be provided on the substrate 21 side as shown in FIG. 7, or on the substrate 31 side. Alternatively, the light-shielding layer 132 may not be provided.

[0108] Also, as shown in FIG. 8, a configuration may be adopted in which the connecting portion 101 is not provided on the substrate 21 side. In the example shown in FIG. 8, the conductive layer disposed on the substrate 31 side and the conductive layer disposed on the substrate 21 side are connected by the connector 243. This shows a configuration in which the conductive layer disposed on the substrate 21 side is electrically connected to the conductive layer. The wiring 29 can be electrically connected to the wiring arranged on the substrate 31 side. A signal is sent from an FPC (not shown) or an IC (not shown) arranged on the side 31 to the conductive layer 24. A signal can be supplied or transmitted from the conductive layer 24 to the FPC or IC.

[0109] At this time, the conductive layer 23 and the conductive layer 24 constituting the touch sensor 22 are electrically connected. Not only the wiring 29 but also the conductive layer 113 are arranged on the substrate 31 side by the connector 243. In this case, the FP arranged on the substrate 31 side can be electrically connected to the wiring. A potential or a signal can be supplied to the conductive layer 113 from C or IC.

[0110] The connectors 243 may be, for example, conductive particles. For this purpose, particles of organic resin or silica coated with a metal material may be used. It is preferable to use nickel or gold as the metal material, as this reduces the contact resistance. Particles coated with layers of two or more metal materials, such as nickel coated with gold, are used. It is preferable to use a material that can be elastically or plastically deformed as the connector 243. At this time, the conductive particles are preferably crushed in the vertical direction as shown in FIG. This may result in a connection between the connector 243 and the conductive layer electrically connected thereto. The increased contact area reduces contact resistance and prevents problems such as poor connections. .

[0111] The connector 243 is preferably disposed so as to be covered with the adhesive layer 141. For example, After applying the paste or the like that will become 141, the connector 243 can be placed. A structure in which the adhesive layer 141 is used around the periphery, such as a display device with a sealing structure or a display device with a hollow sealing structure. In addition, a configuration in which a connector 243 is disposed in the portion where the adhesive layer 141 is provided can be applied. do.

[0112] 9, the capacitor element 203 is formed by the conductive layer 111 and the conductive layer 114. 9, a conductive layer 214 may be formed on the insulating layer 214. An insulating layer 215 is provided to cover the conductive layer 114, and a conductive layer 114 is provided on the insulating layer 215. Here, when the display element 60 is a transmissive liquid crystal element, a conductive layer 111 is provided. The conductive layer 114 can be formed using a light-transmitting material similar to the conductive layer 111 .

[0113] The above is the description of the first cross-sectional configuration example.

[0114] [Cross-sectional configuration example 2] In the following, a touch panel model using a liquid crystal element of a mode different from that of the above-mentioned cross-sectional configuration example 1 will be described. An example of the cross-sectional structure of the module 10 will be described. Note that the following will be about parts that overlap with those described above. The explanation of the above will be omitted and only the differences will be explained.

[0115] FIG. 10 shows an example in which a liquid crystal element in the FFS mode is used as the display element 60. The display element 60 includes a conductive layer 151, a liquid crystal layer 152, and a conductive layer 153.

[0116] The conductive layer 153 is disposed on the insulating layer 214. The insulating layer An insulating layer 215 is provided, and a conductive layer 151 is provided on the insulating layer 215. The conductive layer 151 is The insulating layer 215, the insulating layer 214, the insulating layer 213, and the insulating layer 212 are provided with openings. It is electrically connected to either the source or the drain of the transistor 202 .

[0117] The conductive layer 151 has a comb-like top surface or a top surface with slits. The conductive layer 153 is disposed overlapping the conductive layer 151. The conductive layer 153 is also disposed overlapping the colored layer 131R and the like. In this region, there is a portion where the conductive layer 151 is not disposed on the conductive layer 153.

[0118] In FIG. 10, the conductive layer 151 functions as a pixel electrode, and the conductive layer 153 functions as a common electrode. In addition, the conductive layer 15 provided on the upper layer and having a comb-like or slit-like upper surface shape 1 can be used as a common electrode, and the conductive layer 153 provided below can be used as a pixel electrode. In that case, the conductive layer 153 is electrically connected to one of the source and drain of the transistor 202. Simply connect it to the network.

[0119] The conductive layer 151 and the conductive layer 153 are laminated with an insulating layer 215 interposed therebetween, and a capacitive element is formed therebetween. Therefore, it is not necessary to form a separate capacitance element, and the aperture ratio of the pixel is can be increased.

[0120] Here, even in the case of a mode that uses a horizontal electric field such as FFS mode or IPS mode, By providing the conductive layer 113, it functions as a shield layer for suppressing the influence of noise. At this time, the conductive layer 113 has a thickness that does not affect the switching of the liquid crystal 152. A constant potential can be applied, for example, ground potential, common potential, or any other constant potential. Alternatively, for example, the conductive layer 153 and the conductive layer 113 may be set to the same potential.

[0121] Here, by using a conductive material that transmits visible light as the conductive layer 153, a transparent liquid crystal display can be obtained. In addition, both the conductive layer 151 and the conductive layer 153 can be made of a material that transmits visible light. It is preferable to use a conductive material that has a high conductivity, since it is possible to further increase the aperture ratio.

[0122] In the case of a reflective liquid crystal element, either the conductive layer 151 or the conductive layer 153 Alternatively, a material that reflects visible light may be used for both of these. The aperture ratio can be increased by using a material that reflects visible light. Alternatively, a material that transmits visible light may be used for the conductive layer 151 .

[0123] Alternatively, the conductive layer 151 may be made of a material that reflects visible light, and the conductive layer 153 may be made of a material that transmits visible light. By using a material having a conductive layer 151, a semi-transmissive liquid crystal element may be realized. a reflection mode using light reflected by the conductive layer 151, and a reflection mode using light transmitted through a slit provided in the conductive layer 151. The LCD panel can be switched between a transmissive mode, which uses light from a backlight, and a transparent mode, which uses light from a backlight.

[0124] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. The blue phase is a characteristic of the liquid crystal composition containing a liquid crystal and a chiral agent. The composition does not require alignment treatment and has little viewing angle dependency. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This can prevent defects and damage to the liquid crystal display device during the manufacturing process.

[0125] 10 shows a case where the light-shielding layer 132 is provided in contact with the upper surface of the conductive layer 25. However, an insulating layer may be provided between them so that they do not come into contact with each other.

[0126] 11 shows a case where the conductive layer 223 is not provided, as compared with FIG. When used as a common electrode, as shown in FIG. It is preferable to dispose a conductive layer 153 between the conductive layer 31 and the conductive layer 151. Therefore, the influence of the electric field of the electric layer 151 on the semiconductor layer 231 can be suppressed.

[0127] The connection portion 204 is formed by laminating a part of the wiring 35 and a conductive layer 224. The conductive layer 224 is formed by sputtering in an atmosphere containing oxygen gas. In this way, oxygen is preferably introduced into the insulating layer 212, which is the surface on which the conductive layer 224 is to be formed. Alternatively, excess oxygen can be added. When an oxide semiconductor is used for the semiconductor layer, the excess oxygen compensates for oxygen vacancies in the semiconductor layer. In addition, the insulating layer 212, the oxide semiconductor In the case where excess oxygen is supplied to the conductive layer, or both, the insulating layer 213 is It is preferable to use a material that can suppress the transmission of oxygen.

[0128] In FIG. 11, the conductive layer 224 is removed by etching in the area other than the connection portion 204. 10 and the like, other than the transistor. The gate electrode or other electrodes or wiring may also be used.

[0129] Here, a pair of conductive layers (conductive layer 151 and conductive layer 153) constituting the display element 60 The upper conductive layer 153 serves as a pixel electrode, and the lower conductive layer 151 serves as a pixel electrode. Although an example of using it as a common electrode has been shown, it is not limited to this. For example, 51 can be used as a pixel electrode and the conductive layer 153 located on the upper side can be used as a common electrode. At this time, the conductive layer 151 has an island-like top surface, and the transistor 202 The conductive layer 153 may be electrically connected to a source electrode or a drain electrode. The upper surface has a lit or comb-like shape, and the gap between two or more adjacent pixels is It is sufficient to arrange it over the entire area.

[0130] The above is the description of the cross-sectional configuration example 2.

[0131] [Cross-sectional configuration example 3] In the following, touch sensors having configurations different from the above-described cross-sectional configuration examples 1 and 2 are applied. An example of the cross-sectional configuration of the touch panel module 10 will be described. The explanation of the same parts will be omitted and only the differences will be explained.

[0132] The touch panel module shown in FIG. 12 has a conductive layer 25 The main difference is that it has a conductive layer 125 instead of the insulating layer 122 .

[0133] The conductive layer 125 shown in FIG. 12 is made of a conductive material containing a metal oxide.

[0134] For example, among the transparent conductive materials described later, metal oxides can be used. .

[0135] Alternatively, it is preferable that the insulating layer 100 includes an oxide semiconductor having a low resistance. When an oxide semiconductor is used for the semiconductor layer of the transistor included in the touch panel module 10, In this case, it is preferable to use an oxide semiconductor having a lower resistivity than this.

[0136] For example, the resistance of the conductive layer 125 can be reduced by a method for controlling the resistivity of an oxide semiconductor, which will be described later. It can be done.

[0137] In this case, an insulating layer containing a large amount of hydrogen is used as the insulating layer 122 covering the conductive layer 125. For example, it is preferable that the insulating film contains silicon nitride.

[0138] The conductive layer 125 is made of a conductive metal oxide or a low-resistance oxide semiconductor. This prevents oxidation of the surface, resulting in a highly reliable touch panel module 10. It can be realized.

[0139] In addition, like the conductive layer 113 in the cross-sectional configuration example 2, a part of the conductive layer 125 is The conductive layer 125 is disposed so as to overlap the element 60. That is, another part of the conductive layer 125 serves as a shield layer. With this configuration, the components constituting the touch sensor 22 can function as a The conductive layer that functions as a shield layer and the conductive layer that functions as a shield layer can be formed simultaneously. The process can be simplified.

[0140] The above is the description of Cross-sectional Configuration Example 3.

[0141] [Cross-section example 4] In the following, the structure of the transistor in the touch panel is a top-gate transistor. An example is shown in Figure 13.

[0142] The touch panel module shown in FIG. 13 has a transistor configuration different from that shown in FIG. The main difference is the structure of 301 and 302. Other than the transistor structure, the structure is the same as that shown in FIG. Since they are almost identical, the same reference numerals are used for the same parts, and detailed explanations of the common parts are omitted. It will be decided.

[0143] The transistors 301 and 302 are formed by forming a semiconductor layer 231 on a buffer layer 300 and a gate insulating layer 232 on the buffer layer 300. The insulating layer 211 functions as a gate insulating layer, and the gate insulating layer overlaps the semiconductor layer 231. A conductive layer 221 that functions as an electrode and an insulating layer covering the conductive layer 221 that functions as a gate electrode The insulating layer 212 and the insulating layer 213 are connected to the conductive layer 22 serving as a source electrode or a drain electrode. 2. The region of the semiconductor layer that does not overlap with the gate electrode is the same as the region of the semiconductor layer that overlaps with the gate electrode. It is preferable that the region (low resistance region 232) has a lower resistance than the channel formation region.

[0144] In this configuration example, when an oxide semiconductor layer is used for the semiconductor layer 231, a layer that does not overlap with the gate electrode In order to make the region of the semiconductor layer where the gate electrode overlaps the region of the semiconductor layer lower in resistance than the channel forming region, Impurity elements (rare gases, nitrogen, phosphorus, boron, hydrogen, etc.) are added to the semiconductor layer area where they should not be It is preferable to add rare gas such as helium or argon. In addition, methods for adding impurities include plasma and ion implantation. By using ion implantation, the gate electrode can be used as a mask to form a self-aligned Adding a pure element is preferable because it is possible to reduce the resistance of part of the oxide semiconductor layer.

[0145] The capacitor element 203 includes a conductive layer 221, a semiconductor layer 231 with a reduced resistance, and a layer therebetween. and an insulating layer 211 that functions as a dielectric. The conductive layer 221, the conductive layer 222, and the insulating layers 212 and 213 disposed therebetween are included. The configuration may be such that:

[0146] The connection portion 204 is formed by laminating a part of the wiring 35 and the conductive layer 111. do.

[0147] The buffer layer 300 is made of an insulating material such as silicon oxide or metal oxide. The metal oxides used as 300 include aluminum, indium, gallium, zinc, etc. The buffer layer 300 is made of an oxide containing one or more of the following: water, hydrogen, etc. It is preferable to use a material that is difficult for impurities to diffuse. By using such a structure, the transistor 301 can function as a thin film. , 302, it is possible to effectively suppress the diffusion of impurities from the outside, This allows for a highly reliable touch panel.

[0148] Here, the semiconductor layer 231 of the transistor 301 and the transistor 302 is an oxide semiconductor. For example, the semiconductor film may be amorphous, microcrystalline, polycrystalline, or the like. The semiconductor material of the semiconductor layer 231 can be, for example, Semiconductor materials made of elements from Group 14 (silicon, germanium, etc.) Compound semiconductors (silicon carbide, Examples include silicon, silicon-germanium ...

[0149] For example, an amorphous silicon film is formed, and then the amorphous silicon film is crystallized to form a polycrystalline silicon film, from which the semiconductor layer 2 is formed. The amorphous silicon film can be crystallized using a method using a wavelength of 400 nm or less. laser crystallization method using laser irradiation, lamp annealing crystallization method using infrared light, and crystallization at temperatures above 400℃. There are methods such as solid phase growth using heat treatment at up to 600°C and high-temperature annealing crystallization at around 950°C. In the solid phase growth method, a catalytic element such as nickel is added to the amorphous silicon film, and then the film is heated. In addition, there are methods for crystallizing amorphous silicon films. For example, a catalytic element such as nickel may be added to the silicon film to solidify it by heat treatment. The polycrystalline silicon film is then grown by phase growth. To do this, laser light is irradiated onto the polycrystalline silicon film.

[0150] To obtain a single-crystal silicon film, a single-crystal (or polycrystalline) silicon wafer is subjected to hydrogen immobilization. The film may be formed by injecting ions or the like and peeling off the surface layer. It is possible.

[0151] The semiconductor layer 231 of the transistor 301 and the transistor 302 has a channel formation region and Low resistance regions 232 are formed on both sides of the channel forming region. The anti-doped region 232 is a lightly doped drain region (LDD). region) and a heavily doped region that functions as a source region or a drain region. Here, the low concentration impurity region may have a lower impurity concentration than the high concentration impurity region. The impurity concentration is higher than that of the channel formation region.

[0152] When transistors 301 and 302 are n-type transistors, In this case, the low resistance region 232 may be a p-type region. For example, phosphorus (P), arsenic (As), etc. may be added. On the other hand, the transistors 301 and 302 may be formed as p In the case of a n-type transistor, the low resistance region 232 may be an n-type region. It is preferable to use a region doped with boron (B), aluminum (Al), gallium (Ga), etc. In addition, in order to control the threshold voltage of the transistor, the channel shape of the semiconductor layer 231 is The above-mentioned impurities may be added to the low-resistance region 232 at a lower concentration than the low-resistance region 232 .

[0153] The region of the semiconductor layer 231 that does not overlap with the gate electrode is made a region with lower resistance than the channel forming region. In order to make the semiconductor layer 231 have a low conductivity, it is preferable to add an impurity element to the semiconductor layer 231 that does not overlap with the gate electrode. Furthermore, typical methods for adding impurities include a method using plasma and ion implantation. When the ion implantation method is used, the gate electrode is used as a mask. By adding an impurity element in a self-aligned manner, the resistance of a part of the semiconductor layer 231 can be reduced. I wish.

[0154] In addition, as the transistor 301 and the transistor 302, a plurality of channels are formed in the semiconductor layer 231. A transistor with a structure having a channel formation region (also called a multi-channel structure or a multi-gate structure) For example, two or more gate electrodes may be arranged on the semiconductor layer 231 at intervals. In addition, the region between two adjacent channel formation regions may have the above-described structure. The low-resistance region (either low-concentration impurity region or high-concentration impurity region, or both) By forming the transistor into a multi-channel structure, This can reduce the leakage current in the off state.

[0155] The capacitor element 203 is formed by a part of the low resistance region 232 of the semiconductor layer 231 and the insulating layer 21 2 and a conductive layer 221 are stacked. The impurity concentration of resistor region 232 is higher than the impurity concentration of the source and drain regions of transistor 302. The concentration may be higher than the concentration of the substance. For example, the conductive layer 221 and the insulating layer may be formed by combining the conductive layer 221 and the insulating layer. The insulating layer 212 and the insulating layer 213 may be stacked between the insulating layer 222 and the insulating layer 213. .

[0156] Here, the transistor 301, the transistor 302, etc. are the transistors shown in FIGS. 14 can be replaced with transistor 201 and transistor 202. 15 is a cross-sectional view of the transistor of FIG. 16 is a schematic cross-sectional view of the transistor in FIG. 17 is a schematic cross-sectional view of the transistor of FIG. 6 when replaced. FIG. 18 is a cross-sectional schematic diagram of the transistors in FIG. 7 when they are replaced. 20 is a schematic cross-sectional view of the transistor of FIG. 21 is a schematic cross-sectional view of the case where the transistor in FIG. FIG.

[0157] In FIG. 21 etc., a pair of conductive layers (conductive layer 151 and conductive layer 153) constituting the display element 60 The upper conductive layer 151 serves as a pixel electrode, and the lower conductive layer 153 serves as a pixel electrode. Although an example of using it as a common electrode has been shown, it is not limited to this. When the layer 151 is used as a pixel electrode and the conductive layer 153 located above is used as a common electrode, In FIG. 22, the conductive layer 151 has an island-like top surface, and the transistor The conductive layer 153 is electrically connected to the source electrode or drain electrode of the transistor 202. has a top surface shape with slits or a comb-like top surface shape, and has two or more adjacent They are arranged between the pixels.

[0158] The above is the description of Cross-sectional Configuration Example 4.

[0159] [Cross-section example 5] In the following, the structure of the transistor in the touch panel is a bottom-gate transistor. Another example where

[0160] The touch panel module shown in FIG. 23 has a transistor configuration different from that shown in FIG. The main difference is the structure of the transistors 401 and 402. Since the configuration is almost the same as that of the previous example, the same symbols are used for the same parts, and a detailed description of the common parts is This will be omitted.

[0161] The transistors 401 and 402 are formed on a substrate 31 by a conductive layer 221 which functions as a gate electrode. an insulating layer 211 that covers the conductive layer 221 and functions as a gate insulating layer; A semiconductor layer 231 overlapping the conductive layer 221 on the substrate 1, and a source electrode or The semiconductor layer 231 has a conductive layer 222 that functions as a drain electrode. The channel formation region has a low resistance region 232 having a lower electrical resistivity than the channel formation region.

[0162] The capacitance element 203 is made up of a conductive layer 221, a conductive layer 222, and a dielectric layer disposed therebetween. The capacitor 203 has an insulating layer 211 which functions as a gate insulating layer. Note that the structure of the capacitor 203 is not limited to this. Alternatively, the insulating layer may be formed by combining other conductive layers with insulating layers. A low resistance region 232 of the semiconductor layer 231 and an insulating layer 233 disposed therebetween that functions as a dielectric and an edge layer 211.

[0163] In FIG. 23, as an example of a transistor 401 and a transistor 402, a channel is formed. The semiconductor layer 231 is sandwiched between two gate electrodes (conductive layer 221 and conductive layer 223). This shows an example of applying the composition.

[0164] 23, the connection portion 204 is formed by connecting a part of the wiring 35 and the same conductive film as the conductive layer 223. 1 shows an example in which the conductive layer is formed by laminating conductive layers obtained by processing the conductive layer.

[0165] 24, a structure without the conductive layer 223 may be used. By not providing the touch panel, the manufacturing process can be simplified and the manufacturing cost can be reduced. This can be done.

[0166] The above-described configuration examples can be implemented by appropriately combining at least some of them. do.

[0167] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0168] [About each component] Each of the above components will be described below.

[0169] {substrate} The substrate of the touch panel can be made of a material having a flat surface. The substrate on the side from which light is extracted is made of a material that transmits the light. For example, glass or quartz is used. Materials such as ceramic, sapphire, and organic resin can be used.

[0170] By using a thin substrate, the touch panel can be made lighter and thinner. Furthermore, by using a substrate having a thickness sufficient to provide flexibility, a flexible touch panel can be obtained. This can be achieved.

[0171] Examples of glass include alkali-free glass, barium borosilicate glass, and aluminophobic glass. Usable materials include silicate glass.

[0172] Examples of materials that are flexible and transparent to visible light include: Thickness of glass, polyethylene terephthalate (PET), polyethylene naphthalate Polyester resins such as (PEN), polyacrylonitrile resins, polyimide resins, polymers methyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PE S) Resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamide imide resin, polyvinyl chloride resin, polytetrafluoroethylene (PTFE) resin, etc. In particular, it is preferable to use a material with a low thermal expansion coefficient, such as polyamideimide. Resin, polyimide resin, PET, etc. can be suitably used. Uses substrates impregnated with resin or substrates with a lower thermal expansion coefficient by mixing inorganic fillers into organic resin Since the substrate using such a material is light in weight, the substrate can be easily used. The touch panel can also be made lighter.

[0173] In addition, the substrate on the side from which light is not extracted does not need to be light-transmitting. In addition to the substrate, a metal substrate, a ceramic substrate, a semiconductor substrate, etc. can also be used. Metallic and alloy materials have high thermal conductivity and easily conduct heat to the entire encapsulation substrate. This is preferable because it can suppress local temperature rises in the touch panel. For this purpose, the thickness of the metal substrate is preferably 10 μm or more and 200 μm or less, and more preferably 20 μm or more and 50 μm or less. It is more preferable that the thickness is 0 μm or less.

[0174] The material for the metal substrate is not particularly limited, but examples thereof include aluminum, copper, and nickel. Metals such as nickel, or alloys such as aluminum alloys or stainless steel are preferably used. It is possible.

[0175] In addition, insulating treatment is performed by oxidizing the surface of the metal substrate or forming an insulating film on the surface. For example, a substrate that has been subjected to a coating process such as spin coating or dipping, or an electrodeposition process may be used. The insulating film may be formed by deposition, evaporation, sputtering, or the like. In addition to leaving it in the air or heating it, an oxide film is formed on the surface of the substrate by anodizing or other methods. That's fine.

[0176] The flexible substrate is a layer made of the above material and a substrate that protects the surface of the touch panel from scratches. Hard coating layers (such as silicon nitride layers) that protect the surface from the pressure, and layers made of materials that can disperse pressure The material may be laminated with a layer (for example, an aramid resin layer). To prevent the device from reducing its lifespan, a low-permeability insulating film is laminated on a flexible substrate. For example, silicon nitride, silicon oxynitride, aluminum oxide, nitride An inorganic insulating material such as aluminum can be used.

[0177] The substrate may be formed by laminating a plurality of layers. In particular, a substrate having a glass layer may be used. This improves the barrier properties against water and oxygen, making it possible to create a highly reliable touch panel. do.

[0178] For example, a substrate having a glass layer, an adhesive layer, and an organic resin layer stacked from the side closest to the display element is used. The thickness of the glass layer is preferably 20 μm or more and 200 μm or less. The thickness of the glass layer is 25 μm or more and 100 μm or less. A glass layer with such a thickness is highly resistant to water and oxygen. It can simultaneously achieve high barrier properties and flexibility. The thickness of the organic resin layer is 10 μm. The thickness of such organic resin is set to be 200 μm or more, and preferably 20 μm or more and 50 μm or less. By providing this layer, it is possible to suppress breakage and cracks in the glass layer and improve mechanical strength. By applying such a composite material of glass material and organic resin to a substrate, This makes it possible to provide a highly reliable flexible touch panel.

[0179] {Transistor} The transistor has a conductive layer that functions as a gate electrode, a semiconductor layer, and a a conductive layer that functions as a drain electrode; a conductive layer that functions as a gate insulating layer; and an insulating layer. In the above, a transistor having a bottom gate or top gate structure is The case where it is applied is shown.

[0180] Note that there is no particular limitation on the structure of a transistor included in a touch panel of one embodiment of the present invention. For example, a staggered transistor or an inverted staggered transistor may be used. In addition, the transistor structure may be either a top gate type or a bottom gate type. The semiconductor material used for the transistor is not particularly limited, and examples thereof include oxide semiconductors, silicon Examples of suitable materials include silicon and germanium.

[0181] The crystallinity of the semiconductor material used in the transistor is not particularly limited. A semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single-crystal semiconductor, or a semiconductor having a partially crystalline region) If a semiconductor having crystallinity is used, This is preferable because it can suppress deterioration of the resistor characteristics.

[0182] Semiconductor materials used in transistors include, for example, elements of Group 14, compound semiconductors, and the like. A conductor or an oxide semiconductor can be used for the semiconductor layer. A conductor, a semiconductor containing gallium arsenide, an oxide semiconductor containing indium, or the like can be used.

[0183] In particular, the semiconductor in which the transistor channel is formed has a band gap larger than that of silicon. It is preferable to use an oxide semiconductor with a wide band gap. Furthermore, when a semiconductor material with a low carrier density is used, the current in the off state of the transistor is This is preferable because it can reduce the flow.

[0184] For example, the oxide semiconductor may contain at least indium (In) or zinc (Zn It is preferable that the oxide contains In-M-Zn (wherein M is Al, Ti, Metals such as Ga, Ge, Y, Zr, Sn, La, Ce or Hf) nothing.

[0185] In particular, the semiconductor layer has a plurality of crystal portions, and the c-axes of the crystal portions are aligned with the surface on which the semiconductor layer is formed. Or, the crystals are oriented approximately perpendicular to the upper surface of the semiconductor layer, and grain boundaries are observed between adjacent crystal portions. It is preferable to use an oxide semiconductor film that cannot be formed by the above-mentioned method.

[0186] Such oxide semiconductors have no crystal grain boundaries, so when the display panel is bent, The occurrence of cracks in the oxide semiconductor film due to stress is suppressed. Such oxide semiconductors are suitable for use in touch panels that are flexible and can be curved. It can be used.

[0187] In addition, by using such a crystalline oxide semiconductor for the semiconductor layer, This suppresses fluctuations in the resistance, thereby achieving a highly reliable transistor.

[0188] In addition, a transistor using an oxide semiconductor with a wider band gap than silicon is The low off-state current allows the charge stored in the capacitor connected in series with the transistor to be maintained for a long time. By applying such a transistor to a pixel, it is possible to hold the voltage for a long period of time. This makes it possible to stop the drive circuit while maintaining the gradation of the image displayed in each display area. As a result, a display device with extremely reduced power consumption can be realized.

[0189] The semiconductor layer may be, for example, at least indium (In), zinc (Zn), and M (Al, Ti). In-M-Zn oxide containing metals such as Ga, Y, Zr, La, Ce, Sn or Hf In addition, the electric field of a transistor using the oxide semiconductor is preferably It is preferable to include a stabilizer therewith to reduce variations in air properties.

[0190] The stabilizer includes the metals described above under M, for example, gallium (Ga), silicon (Si), and the like. Sn, hafnium (Hf), aluminum (Al), or zirconium (Zr) Other stabilizers include lanthanum (La), a lanthanide. , Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Samarium (Sm), Europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium ( Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0191] Examples of oxide semiconductors that form the semiconductor layer include In-Ga-Zn oxides, In- Al-Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd- Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z n-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn In-based oxides, In-Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides, In-Hf- Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides can be used. can.

[0192] Here, the In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than n may be included.

[0193] The semiconductor layer and the conductive layer may contain the same metal element from the oxides. By using the same metal element for the semiconductor layer and the conductive layer, it is possible to reduce manufacturing costs. For example, by using metal oxide targets with the same metal composition, manufacturing costs can be reduced. In addition, the etching gas or etching gas used in processing the semiconductor layer and the conductive layer can be However, the semiconductor layer and the conductive layer may be made of the same metal element. Even if they have the same structure, the composition may be different. For example, During this process, metal elements in the film may be released, resulting in a different metal composition.

[0194] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In to M is When the sum of In and M is 100 atomic %, it is preferable that In is 25 atomic % or more. M is less than 75 atomic %, and more preferably In is more than 34 atomic %. High, and M must be less than 66 atomic%.

[0195] The semiconductor layer has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably The energy gap is 3 eV or more. This allows the off-state current of the transistor to be reduced.

[0196] The thickness of the semiconductor layer is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less. More preferably, the thickness is 3 nm or more and 50 nm or less.

[0197] The semiconductor layer is In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or N In the case of d), the sputtering target used to form the In-M-Zn oxide film The atomic ratio of the metal elements preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the targeting target was In:M:Zn=1:1:1, In: Preferably, M:Zn=1:1:1.2, In:M:Zn=3:1:2. The atomic ratio of the semiconductor layer is included in the sputtering target as an error. This includes a variation of plus or minus 40% in the atomic ratio of metal elements.

[0198] For example, an oxide semiconductor film having a low carrier density is used as the semiconductor layer. , the carrier density is 1×10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 below , and more preferably 1 × 10 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following oxide semiconductor film is used.

[0199] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0200] When silicon or carbon, which is one of the group 14 elements, is contained in the semiconductor layer, As a result, oxygen vacancies increase in the semiconductor layer, causing it to become n-type. Carbon concentration (Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by spectrometry is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0201] In addition, in the semiconductor layer, alkali metal or alkali metals obtained by secondary ion mass spectrometry The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Alkali metals and alkaline earth metals are oxide semiconductors. When the electrons combine with the electrons, carriers may be generated, increasing the off-state current of the transistor. Therefore, it is necessary to reduce the concentration of alkali metals or alkaline earth metals in the semiconductor layer. It is preferable that

[0202] In addition, when nitrogen is contained in the semiconductor layer, electrons are generated as carriers, and the carrier density As a result, transistors using oxide semiconductors containing nitrogen are easily made n-type. Therefore, in the oxide semiconductor film, nitrogen is It is preferable that the amount of the ions is reduced as much as possible. For example, the amount of the ions obtained by secondary ion mass spectrometry is The nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0203] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor be.

[0204] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0205] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0206] Looking at it from the other way around, a stable oxide semiconductor can be considered completely amorphous. In addition, it is not isotropic (for example, in a small area) and cannot be called an oxide semiconductor. An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has unstable voids. In terms of instability, a-like OS is physically amorphous oxide. It is similar to a semiconductor.

[0207] First, the CAAC-OS film will be described.

[0208] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0209] Transmission Electron Microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of the CAAC-OS film was obtained using a microscope. (also called high-resolution TEM images) On the other hand, high-resolution TEM images also clearly show the boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur.

[0210] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. The CAAC-OS film is formed on a surface (also called a surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface thereof.

[0211] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction almost perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0212] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0213] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0214] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0215] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0216] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. The film has a small number of carrier generation sources, so the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative. (also called normally-on) is rare. An oxide semiconductor film with intrinsic purity has few carrier traps. Transistors using conductor films have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time it takes for the impurity concentration to reach the target is long, and it may behave as if it were a fixed charge. A transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0217] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0218] Next, a microcrystalline oxide semiconductor film will be described.

[0219] The microcrystalline oxide semiconductor film has crystalline parts that can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal parts contained in the film are large, with sizes of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are microcrystals is called n c-OS(nanocrystalline oxide semiconductor ) film. In addition, the nc-OS film clearly shows the grain boundaries in high-resolution TEM images, for example. It may not be possible to confirm.

[0220] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, in the case of nc-OS films, X-rays with a diameter larger than that of the crystals are used. When structural analysis is performed using an RD device, the crystal In addition, the peaks indicating the crystal planes were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter of 50 nm or more. When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal. When nanobeam electron diffraction is performed on the nc-OS film, spots are observed. When you do this, you may see a circular (ring-shaped) area of ​​high brightness. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. may be observed.

[0221] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0222] Next, the amorphous oxide semiconductor film will be described.

[0223] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0224] In amorphous oxide semiconductor films, no crystalline parts can be identified in high-resolution TEM images. .

[0225] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the analysis by the plane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0226] Note that the oxide semiconductor film has a structure that exhibits physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly as a pseudo-amorphous oxide film. This is called a semiconductor film.

[0227] In a-like OS films, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where the crystalline part can be clearly seen and areas where the crystalline part is not clearly seen. The a-like OS film has regions where it cannot be seen by TEM observation. A small amount of electron irradiation can cause crystallization, and the growth of crystalline portions can be observed. On the other hand, if the nc-OS film is of high quality, crystallization can be observed by TEM observation using a small amount of electron irradiation. is rarely seen.

[0228] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution This can be done using TEM images. For example, InGaZnO4 crystals have a layered structure. There are two Ga-Zn-O layers between the In-O layers. The device has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned along the c-axis. It has a layered structure. Therefore, the distance between adjacent layers is (009) The lattice spacing (also called the d value) is approximately the same as that of the Therefore, focusing on the lattice fringes in the high-resolution TEM image, In the area where the spacing is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In It corresponds to the ab plane of the GaZnO4 crystal.

[0229] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the conductive film is known, the density can be determined by comparing it with the density of a single crystal with the same composition. For example, the structure of the oxide semiconductor film can be estimated by using the following formula: The density of the -like OS film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film is 92.3% or more of the density of the crystal. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is However, it is difficult to form the film.

[0230] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atom In the oxide semiconductor film that satisfies the [atomic ratio], single-crystal InGaZnO with a rhombohedral crystal structure The density of 4 is 6.357 g / cm 3 Therefore, for example, In:Ga:Zn=1:1: In an oxide semiconductor film that satisfies the atomic ratio of 1, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1 In the oxide semiconductor film satisfying the atomic ratio of 0.1 to 1, the density and CAAC of the nc-OS film were The density of the -OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0231] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density corresponding to the single crystal of the desired composition can be calculated. The density of a single crystal of a desired composition varies depending on the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate it by combining the above.

[0232] The semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA region, or a crystalline structure region. The film may be a mixed film having two or more of the C—OS region and the single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC region, or the like. In some cases, the compound may have two or more regions of either an -OS region or a single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC region, or the like. -OS region, single crystal structure region, or a laminated structure of two or more regions. do.

[0233] Alternatively, silicon is preferably used as the semiconductor in which the channel of the transistor is formed. Although amorphous silicon may be used as silicon, silicon having crystallinity is particularly preferred. It is preferable to use silicon. For example, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. In particular, polycrystalline silicon has a lower temperature than single-crystal silicon. It can be formed without any additional process and has higher field effect mobility and higher reliability than amorphous silicon. By applying such a polycrystalline semiconductor to the pixel, the aperture ratio of the pixel can be improved. Even if the display panel has extremely high resolution, the gate drive circuit and source drive circuit This makes it possible to form the circuit and the pixel on the same substrate, reducing the number of parts that make up electronic devices. It is possible.

[0234] The bottom-gate transistor described in this embodiment can reduce the manufacturing steps. In this case, the use of amorphous silicon or oxide semiconductor makes it possible to form a polycrystalline Since it can be formed at a lower temperature than silicon, it can be used for wiring and electrode materials below the semiconductor layer, as well as for the substrate. It is possible to use materials with low heat resistance, which broadens the range of material choices. For example, a glass substrate having an extremely large area can be suitably used. Top-gate transistors have good characteristics because they can easily form impurity regions in a self-aligned manner. This is preferable because it can reduce variations. This is suitable for use with crystalline silicon, single crystal silicon, etc.

[0235] {Conductive layer} In addition to the gate, source, and drain of the transistor, various wiring that makes up the touch panel Materials that can be used for conductive layers such as wires and electrodes include aluminum, titanium, Chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or The material is a metal such as tungsten, or an alloy containing this as its main component, in a single layer structure or a multilayer structure. For example, a single layer structure of aluminum film containing silicon, aluminum film on titanium film, Two-layer structure with tungsten film on top of aluminum film, two-layer structure with tungsten film on top of aluminum film, copper - Two-layer structure with copper film laminated on magnesium-aluminum alloy film, copper film laminated on titanium film Two-layer structure with copper film laminated on tungsten film, two-layer structure with titanium film or titanium nitride film A titanium film and an aluminum film or copper film are laminated on the titanium film or titanium nitride film. A three-layer structure in which a titanium film or titanium nitride film is formed on top of the titanium film, a molybdenum film or The molybdenum nitride film is a layer of aluminum overlaid on the molybdenum film or the molybdenum nitride film. A molybdenum film or a copper film is laminated on the substrate, and a molybdenum film or a molybdenum nitride film is then formed on the laminate. There are three-layer structures, etc. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide Furthermore, when copper containing manganese is used, the shape can be easily controlled by etching. This is preferable because it increases

[0236] Examples of the conductive material having light-transmitting properties include indium oxide, indium tin oxide, and indium tin oxide. Conductive oxides such as indium zinc oxide, zinc oxide, and gallium-doped zinc oxide, or Graphene can be used. Alternatively, gold, silver, platinum, magnesium, nickel, tantalum, etc. such as tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium Metallic materials and alloy materials containing such metallic materials can be used. Alternatively, a metal material, an alloy material (or a combination thereof) may be used. When using these nitrides, it is sufficient to make them thin enough to have light transmission properties. A laminated film of a material can be used as the conductive layer. For example, a silver-magnesium alloy and an insulator can be used. It is preferable to use a laminated film of tin oxide or the like, since the conductivity can be increased.

[0237] Alternatively, the conductive layer is preferably made of an oxide semiconductor similar to that of the semiconductor layer. When the conductive layer is formed, the conductive layer exhibits a lower electrical resistance than the region in which the channel of the semiconductor layer is formed. , is preferably formed.

[0238] For example, such a conductive layer may be used as a conductive layer 2 which functions as a second gate electrode of a transistor. 23. Alternatively, it can be applied to other conductive layers having light-transmitting properties. Cut.

[0239] {Method for controlling the resistivity of oxide semiconductors} The oxide semiconductor film that can be used for the semiconductor layer and the conductive layer has oxygen vacancies and / or is a semiconductor material whose resistivity can be controlled by the concentration of impurities such as hydrogen and water in the film. Therefore, a process that increases oxygen deficiency and / or impurity concentration in the semiconductor layer and the conductive layer, or by selecting a treatment that reduces oxygen vacancies and / or impurity concentrations, respectively. The resistivity of the oxide semiconductor film can be controlled.

[0240] Specifically, a plasma treatment is performed on an oxide semiconductor film used for a conductive layer, and the oxide semiconductor Increase of oxygen vacancies in the film and / or impurities such as hydrogen and water in the oxide semiconductor film By increasing the amount of the oxide semiconductor film, the carrier density can be increased and the resistivity can be reduced. Alternatively, an insulating film containing hydrogen may be formed in contact with the oxide semiconductor film, and the insulating film containing hydrogen may be formed in contact with the oxide semiconductor film. By diffusing hydrogen from the insulating film into the oxide semiconductor film, the carrier density is increased and the resistivity is reduced. The oxide semiconductor film can have low conductivity.

[0241] On the other hand, the semiconductor layer that functions as the channel region of the transistor is in contact with the insulating film that contains hydrogen. At least one of the insulating films in contact with the semiconductor layer contains oxygen. Then, by applying an insulating film capable of releasing oxygen, it is possible to supply oxygen to the semiconductor layer. The semiconductor layer to which oxygen is supplied becomes resistant because oxygen vacancies in the film or at the interface are filled. The insulating film capable of releasing oxygen can be an oxide semiconductor film with high resistivity. For example, a silicon oxide film or a silicon oxynitride film can be used.

[0242] In order to obtain an oxide semiconductor film with low resistivity, an ion implantation method, an ion doping method, etc. , plasma immersion ion implantation method, etc. Nitrogen or nitrogen may be implanted into the oxide semiconductor film.

[0243] In order to obtain an oxide semiconductor film with low resistivity, the oxide semiconductor film is subjected to plasma treatment. For example, the plasma treatment may be carried out using a rare gas (He, Ne, A Plasma using gas containing one or more selected from the group consisting of r, Kr, Xe), hydrogen, and nitrogen. More specifically, plasma treatment under an Ar atmosphere, a mixture of Ar and hydrogen, Plasma treatment under a mixed gas atmosphere, plasma treatment under an ammonia atmosphere, and plasma treatment under Ar and ammonia Plasma treatment in a mixed gas atmosphere of nia or plasma treatment in a nitrogen atmosphere Examples include:

[0244] By the plasma treatment, the oxide semiconductor film is formed into a lattice from which oxygen is desorbed (or Oxygen vacancies are formed in the separated portions. These oxygen vacancies may become a cause of carrier generation. In addition, in the vicinity of the oxide semiconductor film, more specifically, in the lower side or the upper side of the oxide semiconductor film, When hydrogen is supplied from the insulating film adjacent to the side, the oxygen vacancies and hydrogen combine to form the capacitor. In some cases, electrons are generated.

[0245] On the other hand, an oxide semiconductor film in which oxygen vacancies are filled and the hydrogen concentration is reduced can be made highly purified and intrinsic. Alternatively, it can be said that the oxide semiconductor film is substantially highly purified and made intrinsic. The carrier density of the oxide semiconductor film is 8×1011 pieces / cm 3 Less than 1 x 10 1 1 pieces / cm 3 less than 1×10 10 pieces / cm 3 High An oxide semiconductor film that is pure intrinsic or substantially highly pure intrinsic has a small number of carrier generation sources. Therefore, the carrier density can be reduced. Since the oxide semiconductor film has a low density of defect states, the density of trap states can be reduced. can.

[0246] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. Very small, with a channel width of 1×10 6 Even if the device has a channel length of 10 μm, When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 A and below Therefore, the above-mentioned high purity pure or substantially high purity pure can be obtained. A transistor using a semiconductor layer including an oxide semiconductor film, which is electrically conductive, for a channel region is This results in a highly reliable transistor with little fluctuation in characteristics.

[0247] As an insulating film in contact with the oxide semiconductor film used as a conductive layer, for example, an insulating film containing hydrogen In other words, an insulating film capable of releasing hydrogen, typically a silicon nitride film, is used. As an insulating film capable of releasing hydrogen, indicates that the hydrogen concentration in the film is 1×10 22 atoms / cm 3 It is preferable that this is equal to or greater than this. By forming such an insulating film in contact with the conductive layer, hydrogen can be effectively contained in the conductive layer. In this way, by changing the structure of the insulating film in contact with the semiconductor layer and the conductive layer, In this case, the resistivity of the oxide semiconductor film can be controlled.

[0248] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. The oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portions from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. By bonding with oxygen, which bonds with metal atoms, electrons, which act as carriers, may be generated. Therefore, the conductive layer provided in contact with the insulating film containing hydrogen has a higher hydrogen content than the semiconductor layer. An oxide semiconductor film with high carrier density is obtained.

[0249] The semiconductor layer in which the channel region of the transistor is formed has as little hydrogen as possible. Specifically, it is preferable that the semiconductor layer is The hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atom s / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 a toms / cm 3 Less than 1 x 10 18 atoms / cm 3 The following is more preferable: is 5 x 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / c m 3 The following applies.

[0250] On the other hand, the conductive layer has a higher hydrogen concentration and / or oxygen vacancy than the semiconductor layer, and has a lower resistivity. The hydrogen concentration in the conductive layer is 8×10 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 More preferably, 5 × 10 20 a toms / cm 3 In addition, the hydrogen concentration in the conductive layer is higher than that in the semiconductor layer. The resistivity of the conductive layer is at least 2 times, preferably at least 10 times, that of the semiconductor layer. 1×10 -8 1×10 times more -1 It is preferably less than 1×10 -3 Ωcm or more 1×10 4 Ωcm, and more preferably a resistivity of 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0251] {insulating layer} Examples of insulating materials that can be used for the insulating layers, overcoats, spacers, etc. include: Examples include resins such as acrylic and epoxy, resins with siloxane bonds, silicon oxide, Inorganic insulation such as silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide Materials can also be used.

[0252] {adhesive layer} The adhesive layer is made of a hardening resin such as a thermosetting resin, a photo-hardening resin, or a two-component mixed hardening resin. For example, acrylic resin, urethane resin, epoxy resin, or silicone resin can be used. A resin having a hydroxyl bond can be used.

[0253] {Connection Layer} Anisotropic Conductive Film (ACF) is used as the connection layer. conductive film) and anisotropic conductive paste (ACP) Conductive Paste) can be used.

[0254] {Colored layer} Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples include resin materials.

[0255] {Light blocking layer} The light-shielding layer can be made of a material that blocks light emitted from the light-emitting element, such as a metal material. Resin materials containing pigments, dyes, etc. can be used. Alternatively, two or more colored layers may be stacked to form a light-shielding layer. It may also function as such.

[0256] This concludes the explanation of each component.

[0257] [Touch sensor configuration example] Next, a touch panel that can be applied to the touch panel module 10 according to one embodiment of the present invention will be described. An example of the configuration of the sensor 22 will be described with reference to the drawings.

[0258] FIG. 25(A) is a schematic top view (schematic plan view) showing a part of the touch sensor 22. FIG. 25(B) is an enlarged schematic top view of the area surrounded by the dashed line in FIG. 25(A). .

[0259] The conductive layer 23 and the conductive layer 24 are each formed in a lattice (also called a mesh) or a plurality of In FIG. 25(A) and the like, the conductive layer 2 In order to explain the outline shapes of the conductive layer 24 and the conductive layer 3, the grid and openings are omitted.

[0260] As shown in FIGS. 25(A) and 25(B), the width of the conductive layer 23 at the intersection with the conductive layer 25 is small. It is preferable that the conductive layer 23 has a narrowed shape so that the conductive layer 23 is small. This makes it possible to reduce the size of the capacitance formed in the portion where the conductive layer 25 overlaps. For example, in the case of a self-capacitance or mutual capacitance touch sensor, the smaller the capacitance, the easier it is to detect. The output sensitivity can be improved.

[0261] In addition, a conductive layer electrically insulated from the adjacent conductive layer 23 and conductive layer 24 is provided between them. The conductive layer 26 may be included. By including the conductive layer 26, the thickness of the touch sensor 22 can be reduced. For example, the conductive layer 23 and the conductive layer 24 may be formed on the same surface. When formed on a flat surface, a similarly formed conductive layer 26 is provided to allow these conductive layers to be formed. This improves the coverage of the thin film formed after the process of forming the conductive layer, and makes the surface flat. Furthermore, the thickness of the touch sensor 22 is made uniform, so that the light from the pixels passing through the touch sensor 22 It is possible to realize a touch panel with reduced luminance unevenness and improved display quality.

[0262] In addition, in FIG. 25(C), the conductive layer 23 and the conductive layer 24 are formed on different planes, and the conductive layer In this case, the conductive layer 26 is not provided with the conductive layer 23 or the conductive layer 25. It may be formed on the same plane as either of the layers 24 or on a different plane. If the conductive layer 26 is not required, it may not be provided.

[0263] FIG. 26(A) shows a circuit diagram of a touch sensor 22 having a plurality of conductive layers 23 and a plurality of conductive layers 24. 26(A) shows an example of a circuit diagram. For simplicity, six conductive layers 23 and six Although the configuration having the conductive layer 24 is shown, the number is not limited to this.

[0264] One conductive layer 23 and one conductive layer 24 form one capacitance element 11. Therefore, the capacitive elements 11 are arranged in a matrix.

[0265] The capacitance element 11 is formed by laminating a conductive layer 23 and a conductive layer 24, or by laminating a conductive layer 23 and a conductive layer 24. The capacitance is formed by arranging the conductive layer 24 in close proximity to each other.

[0266] In the case of the projected self-capacitance method, a pulse voltage is scanned on each of the conductive layers 23 and 24. The value of the current flowing through the sensor is detected at that time. In this case, capacitive coupling occurs between the object to be detected and the conductive layer 23 or the conductive layer 24. Therefore, the magnitude of the capacitance connected to the conductive layer 23 or the conductive layer 24 changes. When a pulse voltage is applied, the magnitude of the current that flows changes. By detecting the position of the object, it is possible to obtain the position information of the object.

[0267] In the case of the projected mutual capacitance method, a pad is provided on either the conductive layer 23 or the conductive layer 24. A pulse voltage is applied to the other side, and the current flowing through the other side is detected. When the object to be detected approaches, an electric field is generated between the conductive layer 23 and the conductive layer 24. The electric field generated between the conductive layer 23 and the conductive layer 24 changes due to the shielding by the object to be detected. This causes a change in the current flowing through the other side. It is possible to obtain location information.

[0268] The current may be detected by detecting the total amount of current. In this case, an integrating circuit or the like may be used. Alternatively, the peak value of the current may be detected. It is also possible to convert it into a voltage and detect the peak value of the voltage.

[0269] The conductive layer 23 and the conductive layer 24 each have a lattice or mesh shape (mesh) having a plurality of openings. 26(B) shows a top view of a part of the conductive layer 23. An example of this state is shown.

[0270] The conductive layer 23 shown in FIG. 26(B) is a lattice having a horizontal spacing P1 and a vertical spacing P2. FIG. 26(B) shows a case where the interval P1 and the interval P2 are approximately the same. However, they may be spaced at different intervals. For example, as shown in Figure 26(C), In this way, the vertical spacing P2 may be made larger than the horizontal spacing P1, or vice versa. The same applies to the conductive layer 24.

[0271] The conductive layer 23 or the conductive layer 24 has an aperture ratio (the number of holes in the conductive layer 23 or the conductive layer 24 per unit area). The ratio of the open area of ​​the layer 24 is, for example, 20% or more and less than 100%, preferably 30% or more and less than 100%. It is preferable to have a region where the ratio is less than 0.00%, more preferably 50% or more but less than 100%. .

[0272] The aperture ratio can be easily calculated from, for example, the interval P1, the interval P2, and the width of the conductive layer. Alternatively, in the periodic region R shown in FIG. 26(B), the area of ​​the region R and the The aperture ratio can be calculated from the ratio of the area of ​​the conductive layer 23 included in the region R is a region that is a periodic unit of the pattern of the periodic conductive layer 23, and this is divided into vertical and horizontal By arranging them periodically in the lateral direction, a pattern of the conductive layer 23 can be formed.

[0273] In the conductive layers 23 and 24, the width of the pattern constituting the lattice is set to, for example, 50 nm. or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, more preferably 1 μm or more and 2 μm or less It is preferable to make the width of the pattern constituting the grating smaller. This makes it possible to narrow the pixel spacing when the aperture and pixel overlap, as will be described later. Therefore, a touch panel with higher definition and a higher aperture ratio can be realized.

[0274] FIG. 27(A) is a further enlarged schematic top view of the boundary between the conductive layer 23 and the conductive layer 24. do.

[0275] The conductive layer 23 and the conductive layer 24 each have a lattice or mesh shape. That is, the conductive layer 23 and the conductive layer 24 each preferably have a plurality of openings. It is preferable that the openings 23a and 24a are formed in the shape of the openings 23a and 24a. By providing the opening and the pixel so that they overlap, light from the display element of the pixel is guided to the conductive layer. The light is blocked by the conductive layer 23 and the conductive layer 24, or is transmitted through the conductive layer 23 and the conductive layer 24. As a result, the pixel aperture ratio and light extraction efficiency are not sacrificed. The touch sensor 22 can be applied to a touch panel without using a conductive material. The layer 25 is also preferably shaped so as not to overlap with the pixels.

[0276] As shown in FIG. 27(A), at these boundaries, a part of the conductive layer 23 and the conductive layer 2 4. In this configuration, the opening 22a is formed by being surrounded by a part of the opening 22a. By doing so, it is possible to make the distance between the conductive layer 23 and the conductive layer 24 as small as possible. In particular, when using the mutual capacitance method, the capacitance between the two The distance between the conductive layers is reduced, and the electric field strength generated between the conductive layers 23 and 24 is increased. It is preferable that:

[0277] FIG. 27(B) is an enlarged schematic top view of the intersection of the conductive layer 23 and the conductive layer 24. 2 shows an example in which two adjacent conductive layers 24 are electrically connected by a conductive layer 25. An insulating layer 121 (not shown) is provided between the conductive layer 23 and the conductive layer 24 and the conductive layer 25. The conductive layer 24 and the conductive layer 25 are connected to each other through an opening provided in the insulating layer 121. The conductive layer 23 and the conductive layer 25 are electrically connected to each other via the insulating layer 121. They have overlapping areas.

[0278] [Example of conductive layer openings and pixel arrangement] Each diagram in FIG. 28 shows a pixel and a sub-pixel included in the pixel when viewed from the display surface side, and a conductive layer 2 3. Here, the conductive layer 23 will be used as an example for explanation. The conductive layer 24 and the conductive layer 25 may have the same structure.

[0279] In FIG. 28(A), the pixel 33 is made up of three sub-pixels: a sub-pixel 33R, a sub-pixel 33G, and a sub-pixel 33B. For example, the sub-pixel 33R displays red, and the sub-pixel The sub-pixel 33G may have a function of displaying green, and the sub-pixel 33B may have a function of displaying blue. The number of sub-pixels included in the pixel 33 and the types of colors of the sub-pixels are not limited to these.

[0280] Each of the sub-pixels included in the pixel 33 includes a display element. The above-mentioned transmissive liquid crystal element can be used. In addition, other elements such as organic EL elements can also be used. Any light-emitting element, reflective or semi-transmissive liquid crystal element, electrophoretic method or electronic liquid powder (registered trademark ) display element (also called electronic ink) that displays images using a shutter-type MEMs Examples of such display elements include the S display element and the optical interference type MEMS display element. In addition to the elements, the device has transistors, capacitors, and wiring that electrically connects them. It's fine.

[0281] In the configuration shown in FIG. 28(A), each of the plurality of openings in the conductive layer 23 corresponds to a sub-pixel 33R, The subpixels 33G and 33B are arranged so as to overlap with one of the three subpixels. In this way, the opening of the conductive layer 23 is arranged so as to overlap one sub-pixel. It is preferable.

[0282] In FIG. 28(B), a conductive layer 23 is disposed between two adjacent sub-pixels exhibiting different colors. As shown in FIG. 28(B), two adjacent sub-pixels that exhibit the same color are Since there is no problem of color mixing between the elements, there are portions where the conductive layer 23 is not provided. It may also be configured as follows.

[0283] In FIGS. 28(C) and (D), the pixel 33 is further increased compared to the configuration shown in FIGS. 28(A) and (B). The sub-pixel 33Y displays, for example, yellow. It should be noted that a pixel that can display white can be applied instead of the sub-pixel 33Y. In this way, it is possible to apply a pixel that can display more than three colors. By providing the pixel 33 with this, power consumption can be reduced.

[0284] In FIGS. 28(A) to 28(D), an example in which the sub-pixels are arranged in stripes is shown. For example, as shown in FIG. 28(E), a configuration in which two color sub-pixels are alternately arranged in one direction is used. Good too.

[0285] The size of the sub-pixels of the pixel 33 (for example, the area of ​​the area that contributes to display) is For example, the subpixels that show blue, which has a relatively low visibility, may be made larger, or It is also possible to make the sub-pixels showing green or red, which have a relatively high luminosity, smaller.

[0286] In FIGS. 28(F) and 28(G), among the subpixels 33R, 33G, and 33B, This shows an example in which the size of pixel 33B is made larger than the other sub-pixels. 28A and 28B, the pixel 33R and the sub-pixel 33G are alternately arranged. The three sub-pixels are arranged in stripes, each with a different size. It can also be done as follows.

[0287] As described above, the positional relationship between the conductive layer 23 and the sub-pixels has been explained. The same applies to the conductive layer 24 and the conductive layer 25. The opening 23a of the conductive layer 23 and one or more sub-pixels overlap each other, and The opening 24a of the conductive layer 24 and one or more other sub-pixels overlap each other. As described above, each sub-pixel has a display element, and therefore the openings 23a and 24a are It can also be said that the display element has an overlapping area with one or more display elements.

[0288] As shown in FIGS. 29A to 29G, in plan view, the conductive layer 23 and each sub-pixel When the conductive layer 23 or the like is made to function as a light-shielding layer, Such an arrangement is preferable because it is possible to suppress light leakage from the sub-pixels. For example, the conductive layer 23 may be provided so as to overlap the end of the colored layer of the sub-pixel or the end of the pixel electrode. Therefore, the conductive layer 23 can be arranged so that such gaps do not occur. By adopting such a configuration, the surface area of ​​the conductive layer 23 can be increased, and therefore the wiring resistance of the conductive layer 23 can be reduced. This reduces the amount of radiation emitted by the target object, thereby increasing the detection sensitivity.

[0289] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0290] (Embodiment 2) In this embodiment, an example of a method for driving an input device or an input / output device according to one embodiment of the present invention will be described. This will be explained with reference to the drawings.

[0291] [Example of sensor detection method] FIG. 30(A) is a block diagram showing the configuration of a mutual capacitance type touch sensor. In (A), a pulse voltage output circuit 601 and a current detection circuit 602 are shown. In (A), an electrode 621 to which a pulse voltage is applied and an electrode 622 to which a change in current is detected are arranged. The electrodes are shown as six wires, X1-X6 and Y1-Y6. The number is not limited to this. Also, in FIG. 30(A), the electrode 621 and the electrode 622 overlap each other. Alternatively, the electrodes 621 and 622 may be arranged close to each other to form a space. The electrode 621 and the electrode 622 have functions interchangeably. That's fine.

[0292] The pulse voltage output circuit 601 applies a pulse voltage to the wirings X1 to X6 in order, for example. When a pulse voltage is applied to the wiring of X1-X6, a capacitance 603 is formed. An electric field is generated between the electrodes 621 and 622, and a current flows through the capacitor 603. The electric field generated between the electrodes changes due to shielding caused by touching with a finger or stylus. The capacitance value of the capacitor 603 changes when touched by a finger or a stylus. This can be used to detect the proximity or contact of an object to be sensed.

[0293] The current detection circuit 602 detects the current in the wiring Y1-Y6 due to a change in the capacitance value of the capacitor 603. The Y1-Y6 wiring is used to detect changes in the proximity or connection of the object to be detected. If there is no contact, the detected current value will not change, but if the object to be detected approaches or touches the object, When the capacitance value decreases, the change in the current value is detected. The total amount may be detected. In this case, an integrating circuit or the like may be used for detection. Alternatively, the peak value of the current may be detected. In this case, the current is converted into a voltage and the voltage value is The peak value may be detected.

[0294] Next, FIG. 30(B) shows the input of the mutual capacitance type touch sensor shown in FIG. 30(A). The timing chart of the output waveform is shown in Figure 30(B). In FIG. 30(B), when the object to be detected is not detected ( Two cases are shown: when the object is detected (touched) and when the object is not detected (touched). For the wiring of Y1-Y6, the waveform is shown as a voltage value corresponding to the detected current value. The display panel is also performing a display operation. It is desirable that the timing of the detection operation of the touch sensor be synchronized with the timing of the detection operation of the touch sensor. Note that FIG. 30(B) shows an example in which the display operation is not synchronized.

[0295] A pulse voltage is applied to the wires X1-X6 in order, and the The waveform in the Y6 wiring changes. When there is no proximity or contact of the object to be detected, X1-X6 The waveforms of Y1-Y6 change uniformly according to the change in the voltage of the wiring. Or, at the contact point, the current value decreases, and the corresponding voltage waveform also changes. do.

[0296] In this way, by detecting the change in capacitance, the proximity or contact of the object to be detected can be detected. The detected object such as a finger or a stylus can be detected by a touch sensor or a touch panel. A signal may be detected even when the device is in close proximity to the sensor without touching it.

[0297] The pulse voltage output circuit 601 and the current detection circuit 602 are, for example, integrated circuits (ICs) on a single chip. It is preferable that the IC is formed in the touch panel. It is preferable that the terminal is mounted on a substrate inside the housing of an electronic device. When using a touch panel, the parasitic capacitance increases at the bent part, increasing the effect of noise. Therefore, it is recommended to use an IC that uses a driving method that is less susceptible to noise. For example, it is preferable to apply a driving method that increases the signal-to-noise ratio (S / N ratio). It is preferable to use an IC that has a

[0298] [Configuration example of an in-cell touch panel] In the above, the electrodes constituting the touch sensor are provided on a substrate different from the substrate on which the display element and the like are provided. Although the case where the touch sensor is formed on a plate is shown, it is also possible to form the touch sensor on a substrate on which a display element or the like is provided. Alternatively, one or both of a pair of electrodes may be provided.

[0299] Below, we will discuss a touch panel (so-called Here, we will explain the configuration example of a touch panel (a fully in-cell type touch panel). However, one embodiment of the present invention is not limited to this. The present invention is not limited to this, and various display elements can be applied.

[0300] FIG. 31(A) shows one of the pixel circuits provided in the display unit of the touch panel exemplified in this configuration example. FIG. 1 is an equivalent circuit diagram of a portion.

[0301] One pixel has at least a transistor 3503 and a liquid crystal element 3504. The element may further have a storage capacitor. 3501 is electrically connected to either the source or drain, and wiring 3502 is electrically connected to either the source or drain. It is being done.

[0302] The pixel circuit includes a plurality of wirings (for example, wiring 3510_1, wiring 3510_2, wiring 3510_3, wiring 3510_4, wiring 3510_5, wiring 3510_6, wiring 3510_7, wiring 3510_8, wiring 3510_9, wiring 3510_10, wiring 3510_11, wiring 3510_12, wiring 3 _2) and a plurality of wirings (for example, wiring 3511) extending in the Y direction, which are mutually are provided across each other and are capacitively coupled.

[0303] In addition, among the pixels provided in the pixel circuit, some adjacent pixels are The electrodes of the liquid crystal elements are electrically connected to each other to form one block. The lock is divided into island blocks (e.g., block 3515_1, block 3515_2) and , linear blocks extending in the Y direction (for example, block 3516) Although FIG. 31 shows only a part of the pixel circuit, these two types of The blocks are repeatedly arranged in the X and Y directions. For example, a common electrode or a counter electrode can be used. The electrode may be, for example, a pixel electrode.

[0304] The wiring 3510_1 (or wiring 3510_2) extending in the X direction is connected to the island-shaped block 3 515_1 (or block 3515_2). The wiring 3510_1 extending in the X direction is connected in an inconsistent manner along the X direction via a linear block. A plurality of island-shaped blocks 3515_1 arranged in succession are electrically connected. The wiring 3511 extending in the direction perpendicular to the plane of the arrows is electrically connected to the linear block 3516 .

[0305] FIG. 31(B) shows a plurality of wirings 3510 extending in the X direction and a plurality of wirings 3510 extending in the Y direction. This is an equivalent circuit diagram showing the connection configuration of the line 3511. Each of the wirings 3510 extending in the X direction is connected to an input voltage or a common A ground potential can be input to each of the wirings 3511 extending in the Y direction. (or reference potential) or electrically connect the wiring 3511 to the detection circuit. The wiring 3510 and the wiring 3511 can be interchanged.

[0306] An example of the operation method of the above-mentioned touch panel will be described below with reference to FIGS. 32(A) and 32(B). explain.

[0307] Here, one frame period is divided into a writing period and a detection period. This is the period when image data is written to the wiring 3501 (gate line or scanning line). On the other hand, the detection period is the period during which sensing is performed by the touch sensor. The wirings 3510 extending in the X direction are sequentially selected and an input voltage is input.

[0308] 32A is an equivalent circuit diagram during the writing period. A common potential is input to both the wiring 3510 extending in the Y direction and the wiring 3511 extending in the Y direction. can be.

[0309] FIG. 32(B) is an equivalent circuit diagram at a certain point in the detection period. Each of the wirings 3511 extending in the X direction is electrically connected to a detection circuit. Of the wirings 3510, the input voltage is input to the selected one, and the other A common potential is input.

[0310] The driving method exemplified here is applicable not only to the in-cell method but also to the touch panel exemplified above. This can also be applied to

[0311] In this way, the image writing period and the period for sensing by the touch sensor can be separated. This prevents touch noise caused by pixel writing noise. The decrease in sensitivity of the sensor can be suppressed.

[0312] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0313] (Embodiment 3) In this embodiment, the transistor 201 and the transistor 202 ( and transistor 301, transistor 302, transistor 401, transistor 40 2) An example of a transistor that can be used in place of the transistor shown in FIG. do.

[0314] The touch panel module 10 according to one embodiment of the present invention includes a bottom-gate transistor and a The transistors can be fabricated using various types of transistors, such as top-gate transistors. Therefore, the semiconductor layer material and transistor structure to be used can be adjusted to suit the existing production line. can be easily replaced.

[0315] [Bottom-gate transistor] FIG. 33(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 33A1 is a cross-sectional view of a transistor 810. In FIG. 33A1, the transistor 810 is The transistor 810 is formed on a substrate 771 with an insulating layer 772 interposed therebetween. An electrode 746 is provided on the semiconductor layer 742. The semiconductor layer 742 is provided on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer. It can function.

[0316] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0317] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0318] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0319] The electrodes, semiconductor layers, insulating layers, and the like constituting the transistor disclosed in this embodiment may be the same as those in other embodiments. It can be formed using the materials and methods disclosed in the embodiments.

[0320] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The carrier concentration in the resulting region increases, and the region becomes n-type.+ layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0321] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0322] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0323] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0324] Note that when an oxide semiconductor is used for the semiconductor layer 742, the insulating layer 729 is formed using an oxide semiconductor. Alternatively, heat treatment may be performed before or after the formation of the insulating layer 729. Oxygen contained in the insulating layer 729 and other insulating layers is diffused into the semiconductor layer 742, and the semiconductor layer 7 Alternatively, the insulating layer 729 can be formed by heating. By this, oxygen vacancies in the semiconductor layer 742 can be compensated for.

[0325] Generally, the CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD), Thermal CVD (TCVD) CVD) method, and metal CVD (MCVD) method depending on the source gas used. :Metal CVD) method, metal organic CVD (MOCVD) method These methods can be classified into methods such as CVD.

[0326] Generally, the evaporation method includes resistance heating evaporation, electron beam evaporation, MBE (Molecular Beam Evaporation), Beam Epitaxy) method, PLD (Pulsed Laser Deposit) ion) method, IBAD(Ion Beam Assisted Deposition) These methods can be classified into the ALD (Atomic Layer Deposition) method and the ALD (Atomic Layer Deposition) method.

[0327] The plasma CVD method can produce high-quality films at relatively low temperatures. When using a deposition method that does not use plasma during deposition, damage to the surface to be deposited may occur. Moreover, a film with few defects can be obtained.

[0328] Generally, the sputtering method is classified into DC sputtering method, magnetron sputtering method, sputtering, RF sputtering, ion beam sputtering, ECR (Electro Cyclotron Resonance (Cyclotron Resonance) sputtering method, facing target sputtering They can be classified into methods such as the tarring method.

[0329] In the facing target sputtering method, the plasma is confined between the targets. It is possible to reduce plasma damage to the substrate. Also, depending on the tilt of the target, This allows the incident angle of sputtering particles onto the substrate to be shallow, improving step coverage. It can be done.

[0330] The transistor 811 shown in FIG. 33A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0331] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0332] Both the electrode 746 and the electrode 723 can function as gate electrodes. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate electrode. That's fine.

[0333] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0334] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0335] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0336] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0337] In addition, the electrode 746 and the electrode 723 each have the function of shielding an external electric field. Therefore, charges such as charged particles generated on the insulating layer 772 side or above the electrode 723 are transferred to the semiconductor layer 7 This does not affect the channel formation region of 42. As a result, stress tests (e.g., negative voltage applied to the gate) Applying a charge - GBT (Gate Bias-Temperature) stress test ) degradation is suppressed. Also, depending on the magnitude of the drain voltage, the on-current begins to flow. This can reduce the phenomenon of gate voltage (rising voltage) changing. occurs when electrode 746 and electrode 723 are at the same potential or at different potentials.

[0338] The BT stress test is a type of accelerated test that measures the transients that occur during long-term use. It is possible to evaluate the characteristic changes (aging) of the stator in a short time. The amount of change in the threshold voltage of a transistor before and after the test is an important indicator for examining reliability. The smaller the fluctuation in threshold voltage, the more reliable the transistor is. .

[0339] In addition, the electrode 746 and the electrode 723 are provided, and the electrode 746 and the electrode 723 are set to the same potential. This reduces the amount of variation in threshold voltage. At the same time, the variations in electrical characteristics are reduced.

[0340] A transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0341] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0342] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0343] Figure 33(B1) shows a channel protection transistor, which is a type of bottom gate transistor. 8 shows a cross-sectional view of transistor 820. Transistor 820 has a similar structure to transistor 810. The difference is that an insulating layer 741 covers a semiconductor layer 742. In an opening formed by selectively removing a portion of the insulating layer 741 that overlaps the conductor layer 742, The semiconductor layer 742 and the electrode 744a are electrically connected to each other. In another opening formed by selectively removing a part of the insulating layer 741, the semiconductor layer 742 and The electrode 744b is electrically connected to the insulating layer 741. can function as a channel protection layer.

[0344] The transistor 821 shown in FIG. 33B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0345] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0346] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the distance between the electrodes 744a and 746 is increased. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0347] The transistor 825 shown in FIG. 33C1 is a bottom-gate transistor. The transistor 825 is a channel-etched transistor having an insulating layer 729. Electrodes 744a and 744b are formed without using the When forming the electrode 744b, a part of the semiconductor layer 742 that is exposed may be etched. On the other hand, since the insulating layer 729 is not provided, productivity of the transistor can be increased.

[0348] The transistor 826 shown in FIG. 33C2 has a back gate electrode over the insulating layer 729. It differs from transistor 825 in that it has a functioning electrode 723 .

[0349] [Top-gate transistor] FIG. 34(A1) shows a cross section of a transistor 830, which is a type of top-gate transistor. The transistor 830 includes a semiconductor layer 742 over an insulating layer 772. an electrode 744a on the layer 742 and the insulating layer 772, the electrode 744a being in contact with a part of the semiconductor layer 742; The semiconductor layer 742 has an electrode 744b in contact with a part of the semiconductor layer 742. An insulating layer 726 is provided on the electrode 744b, and an electrode 746 is provided on the insulating layer 726.

[0350] Transistor 830 is connected between electrode 746 and electrode 744a, and between electrode 746 and electrode Since the electrodes 746 and 744b do not overlap, the parasitic capacitance generated between the electrodes 746 and 744a and Furthermore, the parasitic capacitance occurring between the electrode 746 and the electrode 744b can be reduced. After forming the electrode 746, the impurity 755 is introduced into the semiconductor using the electrode 746 as a mask. By introducing the impurities into the semiconductor layer 742, the impurities are self-aligned in the semiconductor layer 742. A pure region can be formed (see FIG. 34(A3)). A transistor with good electrical characteristics can be realized.

[0351] The impurity 755 is introduced by an ion implantation device, an ion doping device, or a plasma treatment device. This can be done using a processing device.

[0352] The impurity 755 may be, for example, at least one of group 13 elements or group 15 elements. When an oxide semiconductor is used for the semiconductor layer 742, At least one element selected from the group consisting of rare gases, hydrogen, and nitrogen is used as impurities 755. It is also possible that

[0353] The transistor 831 shown in FIG. 34A2 has an electrode 723 and an insulating layer 727. The transistor 831 is formed on the insulating layer 772. The electrode 723 has an insulating layer 727 formed on the electrode 723. The electrode 723 has a Therefore, the insulating layer 727 can function as a gate insulating layer. The insulating layer 727 can function as a dielectric layer. It can be formed as follows.

[0354] Like the transistor 811, the transistor 831 has a large on-current relative to its area. That is, for the required on-current, the transistor 8 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. A body device can be realized.

[0355] The transistor 840 illustrated in FIG. 34B1 is a top-gate transistor. The transistor 840 is formed by forming the electrodes 744a and 744b on a semiconductor substrate. The transistor 830 differs from the transistor 830 in that the layer 742 is formed. The transistor 841 has an electrode 723 and an insulating layer 727. 40. In the transistor 840 and the transistor 841, the semiconductor layer 742 A part of the semiconductor layer 742 is formed on the electrode 744a, and another part of the semiconductor layer 742 is formed on the electrode 744b. will be done.

[0356] Like the transistor 811, the transistor 841 has a large on-current relative to its area. That is, for the required on-current, the transistor 8 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. A body device can be realized.

[0357] The transistor 842 illustrated in FIG. 35A1 is a top-gate transistor. The transistor 842 is formed by forming the insulating layer 729 and then forming the electrode 744a and the electrode 744b. The transistor 830 and the transistor 840 differ from each other in that the electrode 744a is formed. The electrode 744b is formed by a semiconductor layer in an opening formed in the insulating layer 728 and the insulating layer 729. The conductive layer 742 is electrically connected to the conductive layer 742.

[0358] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 as a mask, an impurity 755 is introduced into the semiconductor layer 742, The impurity region can be formed in a self-aligned manner in 742 (Fig. 35(A3)). The transistor 842 is formed by insulating layer 726 extending beyond the edge of electrode 746. When the impurity 755 is introduced into the semiconductor layer 742, the semiconductor layer 742 The impurity concentration in the region where the impurity 755 is introduced through the insulating layer 726 is Therefore, the area in the semiconductor layer 742 is smaller than the area into which the impurity 755 is introduced without any intervening layer. In the region adjacent to the portion overlapping with the electrode 746, an LDD (Lightly Doped Dron) is formed. ain) region is formed.

[0359] The transistor 843 shown in FIG. 35A2 has an electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771 and an insulating The electrode 723 overlaps the semiconductor layer 742 via the edge layer 772. The electrode 723 functions as a back gate electrode. It can be done.

[0360] In addition, the transistor 844 shown in FIG. 35(B1) and the transistor shown in FIG. 35(B2) As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 35(C1) and the transistor shown in FIG. 35(C2) The insulating layer 726 may remain, as may the insulating layer 847.

[0361] The transistors 842 to 847 are also formed with the electrode 746. As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. Furthermore, according to one aspect of the present invention, a transistor with good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0362] [S-channel transistor] FIG. 36 illustrates an example of a transistor structure in which an oxide semiconductor is used as the semiconductor layer 742. In FIG. The transistor 850 illustrated in FIG. 36 includes a semiconductor layer 742b formed on a semiconductor layer 742a. The upper surface of the semiconductor layer 742b and the side surfaces of the semiconductor layer 742b and the semiconductor layer 742a are The transistor 850 has a structure covered with the semiconductor layer 742c. FIG. 36(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 36(A). FIG. 36(C) is a cross-sectional view in the channel length direction. FIG. 1 is a cross-sectional view (cross-sectional view in the channel width direction) of a portion indicated by a dotted chain line.

[0363] The transistor 850 also includes an electrode 743 that functions as a gate electrode. The electrode 3 can be formed using the same material and method as the electrode 746. The electrode 743 is a stack of two conductive layers.

[0364] The semiconductor layer 742a, the semiconductor layer 742b, and the semiconductor layer 742c are made of In or Ga. It is made of a material containing one or both of these. Typically, it is made of In-Ga oxide (In and Ga). oxides containing In and Zn), In-Zn oxides (oxides containing In and Zn), In-Zn-Zn oxides ( Oxides containing In, element M, and Zn. Element M is Al, Ti, Ga, Y, Zr, La, One or more elements selected from Ce, Nd, or Hf, which have a stronger bond with oxygen than In. It is a rare metal element.

[0365] The semiconductor layer 742a and the semiconductor layer 742c are formed by the same metal element as that of the semiconductor layer 742b. In other words, it is preferable that the material contains one or more kinds of the same metal element. When the material is used, the interface between the semiconductor layer 742a and the semiconductor layer 742b and the semiconductor layer This can make it difficult for an interface state to be generated at the interface between the semiconductor layer 742c and the semiconductor layer 742b. This makes it difficult for carriers to be scattered or captured at the interface, and improves the field-effect mobility of the transistor. It is also possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device with good electrical characteristics. This becomes:

[0366] The thickness of the semiconductor layer 742a and the semiconductor layer 742c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 742b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0367] The semiconductor layer 742b is an In-M-Zn oxide, and the semiconductor layer 742a and the semiconductor When layer 742c is also an In-M-Zn oxide, semiconductor layer 742a and semiconductor layer 742 c is In:M:Zn=x1:y1:z1 [atomic ratio], and the semiconductor layer 742b is In:M:Z If n=x2:y2:z2 [atomic ratio], then y1 / x1 is greater than y2 / x2 The semiconductor layer 742a, the semiconductor layer 742c, and the semiconductor layer 742b can be selected so that Preferably, the semiconductor is arranged so that y1 / x1 is 1.5 times or more larger than y2 / x2. Preferably, the semiconductor layer 742a, the semiconductor layer 742c, and the semiconductor layer 742b are selected. The semiconductor layer 742a and the semiconductor layer 742b are formed such that y1 / x1 is at least twice as large as y2 / x2. More preferably, y1 / x1 is selected to be greater than y2 / The semiconductor layer 742a, the semiconductor layer 742c, and the semiconductor layer 742d are set to be three times or more larger than x2. Select layer 742b. When y1 is equal to or greater than x1, the transistor has stable electrical characteristics. However, if y1 is three times or more than x1, the field effect of the transistor Since the mobility is reduced, it is preferable that y1 is less than three times x1. By configuring the semiconductor layer 742a and the semiconductor layer 742c as described above, The layer 742c can be a layer in which oxygen vacancies are less likely to occur than in the semiconductor layer 742b.

[0368] When the semiconductor layer 742a and the semiconductor layer 742c are made of In-M-Zn oxide, I The content of In and element M when the sum of n and M is 100 atomic % is preferably is less than 50 atomic % of In and 50 atomic % or more of element M, and more preferably In is less than 25 atomic % and element M is 75 atomic % or more. When the layer 742b is an In-M-Zn oxide, the sum of In and M is 100 atomic %, the content of In and element M is preferably 25 atomic % or more of In and 25 atomic % or more of element M. M is less than 75 atomic %, more preferably In is 34 atomic % or more, and element M is less than 66 atomic %.

[0369] For example, a semiconductor layer 742a containing In or Ga and a semiconductor layer 742b containing In or Ga 742c: In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, Or In-Ga-Zn oxide formed using a target with an atomic ratio of 1:9:6, etc. In-Ga oxide formed using a target with an atomic ratio of In:Ga=1:9 The semiconductor layer 742b may be made of In:Ga Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 atomic ratio The In-Ga-Zn oxide formed using a target can be used. The atomic ratios of the semiconductor layer 742a, the semiconductor layer 742b, and the semiconductor layer 742c are each The atomic ratios listed above may vary by ±20%.

[0370] In order to provide stable electrical characteristics to a transistor using the semiconductor layer 742b, The impurities and oxygen vacancies in the layer 742b are reduced to make the semiconductor layer 742b highly intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. The channel formation region in the semiconductor layer 742b is an oxide semiconductor that can be regarded as intrinsic or substantially intrinsic. It is preferable to use a conductive layer.

[0371] Note that an oxide semiconductor layer that can be considered substantially intrinsic is an oxide semiconductor layer having a carrier density of , 8×10 11 pieces / cm 3 Less than 1 x 10 11 pieces / cm 3 Less than, even more preferred 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 oxide semiconductor This refers to the body layer.

[0372] FIG. 37 illustrates an example of a transistor structure in which an oxide semiconductor is used as the semiconductor layer 742. In FIG. The transistor 822 illustrated in FIG. 37 includes a semiconductor layer 742b formed on a semiconductor layer 742a. The transistor 822 is a bottom-gate transistor having a back gate electrode. FIG. 37(A) is a top view of the transistor 822. FIG. 37(B) ) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 37(A) (in the channel length direction). FIG. 37(C) shows the area indicated by the dashed line Y1-Y2 in FIG. 37(A). 1 is a cross-sectional view (cross-sectional view in the channel width direction).

[0373] The electrode 723 provided on the insulating layer 729 is connected to the insulating layer 726, the insulating layer 728, and the insulating layer 729. The openings 747a and 747b in the electrode 729 are electrically connected to the electrode 746. Therefore, the same potential is supplied to the electrode 723 and the electrode 746. It is not necessary to provide either the opening 747a or the opening 747b. It is not necessary to provide both the opening 747a and the opening 747b. When no electrode is provided, different potentials can be applied to the electrode 723 and the electrode 746 .

[0374] [Energy band structure of oxide semiconductors] Here, the semiconductor layer 742a, the semiconductor layer 742b, and the semiconductor layer 742c are stacked. The function and effect of the semiconductor layer 742 formed will be described with reference to FIGS. 41(A) and 41(B). ) will be explained using the energy band structure diagram shown in Figure 41(A). 41(A) is an energy band diagram of the region indicated by the dashed line in 1-D2. 8 shows the energy band structure of the channel forming region of the transistor 850.

[0375] In Figure 41(A), Ec882, Ec883a, Ec883b, Ec883c, Ec886 are the insulating layer 772, the semiconductor layer 742a, the semiconductor layer 742b, and the semiconductor layer 742c, respectively. , indicates the energy of the conduction band minimum of the insulating layer 726.

[0376] Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also called "electron affinity") is The energy difference between the empty level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap. For example, the measurement can be performed using HORIBA JOBIN YVON UT-300. The energy difference between the vacuum level and the top of the valence band was also measured by ultraviolet photoelectron spectroscopy (UPS). Traviolet Photoelectron Spectroscopy ( For example, it can be measured using VersaProbe (PHI).

[0377] The In-Ga was formed using a target with an atomic ratio of In:Ga:Zn=1:3:2. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- Ga -Zn target with an atomic ratio of In:Ga:Zn=1:3:4 was used. The energy gap of Ga-Zn oxide is approximately 3.4 eV and the electron affinity is approximately 4.5 eV. In addition, the In film was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I layer was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is approximately 3.9 eV, and the electron affinity is approximately 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is approximately 3.5 eV, and the electron affinity is approximately 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used for formation. The energy gap of the In-Ga-Zn oxide is approximately 3.5 eV and the electron affinity is approximately 4. 5 eV. In addition, a target with an atomic ratio of In:Ga:Zn=1:1:1 was used. The energy gap of the synthesized In-Ga-Zn oxide is approximately 3.2 eV, and the electron affinity is approximately 4 0.7 eV. In addition, using a target with an atomic ratio of In:Ga:Zn=3:1:2, The energy gap of the formed In-Ga-Zn oxide is approximately 2.8 eV, and the electron affinity is approximately It is 5.0 eV.

[0378] Since the insulating layer 772 and the insulating layer 726 are insulators, Ec882 and Ec886 are Closer to the vacuum level (lower electron affinity) than 3a, Ec883b, and Ec883c .

[0379] Also, Ec883a is closer to the vacuum level than Ec883b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0 0.15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0380] Also, Ec883c is closer to the vacuum level than Ec883b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0 0.15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0381] In addition, the vicinity of the interface between the semiconductor layer 742a and the semiconductor layer 742b and the semiconductor layer 742b A mixed region is formed near the interface with the semiconductor layer 742c, so that the energy of the conduction band minimum That is, at these interfaces, there are no or almost no levels. stomach.

[0382] Therefore, in the stacked structure having this energy band structure, electrons flow through the semiconductor layer 742b Therefore, the interface between the semiconductor layer 742a and the insulating layer 772, Alternatively, even if a level exists at the interface between the semiconductor layer 742c and the insulating layer 726, the level The boundary between the semiconductor layer 742a and the semiconductor layer 742b has almost no effect on the movement of electrons. There are almost no levels at the interface between the semiconductor layer 742c and the semiconductor layer 742b. Therefore, the movement of electrons in the region is not hindered. A transistor having a stacked structure of conductors can achieve high field-effect mobility.

[0383] As shown in FIG. 41(A), the interface between the semiconductor layer 742a and the insulating layer 772 and the semiconductor layer 742b are In the vicinity of the interface between the dielectric layer 742c and the insulating layer 726, there are trap levels 89 due to impurities and defects. 0 can be formed, but due to the presence of the semiconductor layer 742a and the semiconductor layer 742c, This can distance the semiconductor layer 742b from the trap states.

[0384] In particular, in the transistor exemplified in this embodiment, the top surface and side surface of the semiconductor layer 742b are semiconductor The lower surface of the semiconductor layer 742b is in contact with the semiconductor layer 742a. In this way, the semiconductor layer 742b is covered with the semiconductor layer 742a and the semiconductor layer 742c. By doing so, the influence of the trap levels can be further reduced.

[0385] However, if the energy difference between Ec883a or Ec883c and Ec883b is small, In this case, electrons in the semiconductor layer 742b may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer, The threshold voltage of the transistor is shifted in the positive direction.

[0386] Therefore, the energy difference between Ec883a and Ec883c and Ec883b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is This reduces voltage fluctuations and improves the electrical characteristics of the transistor. I wish.

[0387] The band gaps of the semiconductor layer 742a and the semiconductor layer 742c are It is preferable that the band gap is wider than that of b.

[0388] FIG. 41(B) shows the energy band structure of the portion indicated by the dashed line D3-D4 in FIG. 37(B). FIG. 41B shows the energy band of the channel formation region of the transistor 822. The structure is shown.

[0389] In FIG. 41B, Ec887 indicates the energy of the bottom of the conduction band of the insulating layer 728. By forming the semiconductor layer 742 into two layers, the semiconductor layer 742a and the semiconductor layer 742b, a transistor Since the semiconductor layer 742c is not provided, the trap level 890, but the semiconductor layer 742 has a higher electric field than when it has a single layer structure. Effective mobility can be achieved.

[0390] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment, a highly reliable transistor can be realized. Therefore, a semiconductor device with good performance can be realized.

[0391] In addition, oxide semiconductors have a large energy gap of 3.0 eV or more, and are highly sensitive to visible light. In addition, in transistors obtained by processing oxide semiconductors under appropriate conditions, In this case, the off-state current is 100zA (1×) under the temperature conditions in use (for example, 25°C). 10 -19 A) or less, or 10zA (1 x 10 -20 A) and below, and even 1zA(1 x10 -21 A) or less. Therefore, a semiconductor device with low power consumption can be provided. It can be provided.

[0392] According to one embodiment of the present invention, a transistor with low power consumption can be provided. As a result, a semiconductor device such as a display element or a display device with low power consumption can be realized. Furthermore, it is possible to realize a semiconductor device such as a display element or a display device with high reliability.

[0393] Returning to the description of the transistor 850 shown in FIG. By providing the layer 742b, the side surface of the semiconductor layer 742b can also be covered with the electrode 743. That is, the transistor 850 can be turned on by the electric field of the electrode 743. In this way, the electric field of the conductive film The structure of a transistor that electrically surrounds the semiconductor layer in which the channel is formed is called a surro This is called an unded channel (S-channel) structure. A transistor with an EL structure is called an "S-channel transistor" or "S -channel transistor.

[0394] In the S-channel structure, a channel is formed in the entire (bulk) semiconductor layer 742b. In the S-channel structure, the drain current of the transistor can be increased. Furthermore, the electric field of the electrode 743 can As a result, the entire channel formation region formed in the semiconductor layer 742b can be depleted. Therefore, in the S-channel structure, the off-state current of the transistor can be further reduced. It is possible.

[0395] In addition, by increasing the height of the protrusion of the insulating layer 772 and reducing the channel width, the S-channel The effect of increasing the on-current and reducing the off-current due to the n-type structure can be further enhanced. Furthermore, when forming the semiconductor layer 742b, the exposed semiconductor layer 742a may be removed. In this case, the side surfaces of the semiconductor layer 742a and the semiconductor layer 742b may be aligned.

[0396] 38, a transistor 851 is provided below the semiconductor layer 742 with an insulating layer interposed therebetween. An electrode 723 may be provided as an electrode. FIG. 38A is a top view of the transistor 851. 38(B) is a cross-sectional view of the area indicated by the dashed line X1-X2 in FIG. 38(C) is a cross-sectional view of the area indicated by the dashed line Y1-Y2 in FIG. 38(A).

[0397] Also, as in the transistor 852 shown in FIG. 39, an insulating layer 775 is provided above the electrode 743. 39A, the layer 725 may be provided over the insulating layer 775. Figure 39(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in Figure 39(A). FIG. 39(C) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 39(A). FIG.

[0398] In FIG. 39, the layer 725 is provided on the insulating layer 775, but it may be provided on the insulating layer 728 or The layer 725 may be provided over the insulating layer 729. When the layer 725 is formed using a light-blocking material, the light This can prevent the transistor characteristics from changing due to irradiation and the reliability from decreasing. The layer 725 is formed to be at least larger than the semiconductor layer 742b, and the layer 725 is formed to cover the semiconductor layer 742b. The layer 725 can be made of an organic material, an inorganic material, or the like. Alternatively, the layer 725 may be made of a conductive material. In this case, the layer 725 may be supplied with a voltage or may be left in an electrically floating state. You may do so.

[0399] FIG. 40 shows an example of a transistor having an S-channel structure. The transistor 848 has almost the same configuration as the transistor 847 described above. The transistor 848 has a semiconductor layer 742 formed on a protrusion provided in an insulating layer 772. The transistor 848 is a type of top-gate transistor with a back gate electrode. FIG. 40A is a top view of the transistor 848. FIG. 40B is a top view of the transistor 848. 40(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 1 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG.

[0400] The electrode 744a provided on the insulating layer 729 is connected to the insulating layer 726, the insulating layer 728, and the insulating layer 729. The layer 729 is electrically connected to the semiconductor layer 742 through an opening 747c. The electrode 744b provided on the insulating layer 729 is connected to the insulating layers 726, 728, and and an opening 747d formed in the insulating layer 729, which is electrically connected to the semiconductor layer 742. It is being done.

[0401] The electrode 743 provided on the insulating layer 726 is connected to the insulating layer 726 and the insulating layer 772. The electrode 723 is electrically connected to the opening 747a and the opening 747b. Therefore, the same potential is supplied to the electrode 743 and the electrode 723. It is not necessary to provide either the opening 747a or the opening 747b. In the case where both openings 747a and 747b are not provided, In this case, different potentials can be applied to the electrodes 723 and 743 .

[0402] Note that the semiconductor layer used in the transistor having the S-channel structure is an oxide semiconductor. However, it is not limited to the above.

[0403] [Other configuration examples] In the following, referring to Figures 42 to 47, a thin polycrystalline silicon (polysilicon) film is used. 1 shows an example of the structure of an n-channel transistor.

[0404] FIG. 42(A) is a top view of the transistor 70A. FIG. 42(B) is a top view of the L 42(C) is a cross-sectional view taken along the line W1-W2 in FIG. 42(A). 42B is a cross-sectional view of the transistor 70A in the channel length L direction. 42C is a cross-sectional view of the transistor 70A in the channel width W direction.

[0405] The transistor 70A has a conductive layer 710 serving as a gate on a substrate 72 having an insulating surface. 73, an insulating layer 74 on the conductive layer 73, and a semiconductor layer overlapping the conductive layer 73 with the insulating layer 74 interposed therebetween. A conductor layer 75, an insulating layer 76 on the semiconductor layer 75, and a semiconductor layer 75 with the insulating layer 76 interposed therebetween. A conductive layer 77 overlapping the conductive layer 77 and functioning as a gate, an insulating layer 78 on the conductive layer 77, and an insulating layer An insulating layer 79 on the edge layer 78 and openings provided in the insulating layers 76, 78 and 79. 10, which is electrically connected to the semiconductor layer 75 and functions as a source or drain. The conductive layer 80 and the conductive layer 81 are connected to each other.

[0406] The semiconductor layer 75 has a channel forming region 82 at a position overlapping the conductive layer 77 and a channel A pair of LDD regions 83 and a channel forming region 8 2, a pair of impurity regions 84 positioned to sandwich an LDD region 83 therebetween. The impurity region 84 functions as a source region or a drain region. , and the impurity region 84 is formed by imparting an n-type conductivity to the semiconductor layer 75 with an impurity element, e.g. , phosphorus (P), arsenic (As), etc. are added.

[0407] The transistor 70A has a first insulating layer (insulating layer 74) on a first conductive layer (conductive layer 73). and a semiconductor layer 75 having a channel forming region 82 on a first insulating layer (insulating layer 74). a second insulating layer (insulating layer 76) on the semiconductor layer 75; ) and a second conductive layer (conductive layer 77) on the second insulating layer. The semiconductor layer 75 is covered with a layer (insulating layer 76) in the channel width direction. In the cross section, the first conductive layer (conductive layer 73) and the second conductive layer (conductive layer 77) are surrounded by It has a structure in which the junction is closed, i.e., an S-channel structure.

[0408] By using the structure shown in FIG. 42(C), the current flows through the entire semiconductor layer 75 (bulk). Since the current flows inside the semiconductor layer 75, it is less susceptible to the influence of interface scattering, and therefore a high It should be noted that if the semiconductor layer 75 is made thicker, the on-current can be improved. This can be done.

[0409] In the transistor 70A, a gate electric field is applied to the semiconductor layer 75 in a direction perpendicular to the gate. In addition, a gate electric field is applied from the side. A strong electric field is applied, and current flows through the bulk of the semiconductor layer 75. This makes it possible to improve the field effect mobility of the transistor 70A.

[0410] In addition, by using an S-channel structure for the transistor, the semiconductor layer 75 It also has the effect of eliminating the influence of impurities mixed into the first conductive layer (conductive The second conductive layer (conductive layer 73) and the second conductive layer (conductive layer 77) prevent light from being irradiated onto the semiconductor film from above and below. Since light can be blocked and photoexcitation can be suppressed, an increase in off-current can be prevented.

[0411] Here, an example of an n-channel transistor is shown, but the n-type conductivity is Instead of the impurity element given to 5, an impurity element that gives p-type conductivity, such as boron ( B), aluminum (Al), gallium (Ga), etc., can be added to form p-channel transistors. The channel shape of the n-channel transistor 70A can be A small amount of impurity element that imparts p-type conductivity to the growth region 82 may be added.

[0412] The semiconductor layer 75 may be crystallized by various techniques. There are a laser crystallization method using laser light and a crystallization method using a catalytic element. The crystallization method using silicon and the laser crystallization method can also be used in combination. When using a substrate with excellent heat resistance such as quartz as 72, thermal crystallization using an electric furnace is crystallization method, lamp annealing crystallization method using infrared light, crystallization method using catalytic elements, 950℃ A crystallization method in which high-temperature annealing is combined may also be used.

[0413] The amorphous silicon film is irradiated with laser light to form a polycrystalline silicon film, and the polycrystalline silicon film is then subjected to a to-beam irradiation. When used as the channel forming region 82 of the transistor 70A, it is formed by irradiating with laser light. The grain boundaries reach below the polycrystalline silicon film, so the current flows through the interface of the semiconductor film. It flows through the bulk of the semiconductor film, so the influence of variations in the laser beam irradiation energy is low. It can be reduced.

[0414] Conventionally, threshold voltage control was performed by adding a low concentration of impurity elements to the channel region. In the case of a structure in which a semiconductor layer is sandwiched between a pair of gate electrodes, carriers are generated at the interface between the semiconductor layer and the insulating film. There is a high probability that carriers will be injected into the insulating film or the interface between the insulating film and the semiconductor layer, causing the threshold voltage to rise. In addition, the energy band structure of this channel region According to the study, the only path for carriers is near the interface between the semiconductor layer and the insulating film. Hot carriers accelerated by the voltage applied to the drain flow into the interface between the insulating film and the semiconductor layer. The decrease in mobility and drain current due to implantation into the surface or insulating film is a major problem. Ta.

[0415] In the transistor 70A, in addition to the gate electric field from the direction perpendicular to the semiconductor film, That is, the gate electric field is applied to the entire semiconductor film. This results in a current flowing through the bulk of the semiconductor film. It is possible to improve the mobility.

[0416] In FIG. 42A, the conductive layer 77 functions as a gate and the conductive layer 78 functions as a back gate electrode. Although the structure shown has a conductive layer 73 that functions as a Depending on the circuit, a transistor in which the conductive layer 73 functioning as a back gate electrode is omitted may be used. It may also be provided partially.

[0417] In FIG. 42A, the conductive layer 77 functioning as a gate has a tapered portion. A gate electrode having a tapered portion is used, and an impurity element is doped into the semiconductor layer. By forming impurity regions in a self-aligned manner using this technique, a semiconductor device with little hot carrier degradation can be produced. It can be achieved.

[0418] In the transistor 70A, a conductive layer 77 functioning as a gate and a back gate electrode The conductive layer 73 functions as an electrode and is electrically connected to the conductive layer 74, but different potentials are applied to each of them. An example of this is shown in Figure 43. Figure 43(A) shows a transistor. 43(B) is a cross-sectional view taken along line L1-L2 in FIG. 43(A). FIG. 43(C) is a cross-sectional view taken along line W1-W2 in FIG. 43(A).

[0419] The transistor 70B shown in FIG. 43 differs from the transistor 70A in the type of insulating layer 74. In the transistor 70B, the insulating layer 74 is formed by a method such as plasma CVD. The insulating film is used. The insulating film is formed by the presence of the conductive layer 73 that functions as a back gate electrode. Convex portions are formed on the film surface, and the semiconductor film is then formed on top of them. The surface shape is reflected.

[0420] The transistor 70B also has a channel forming region that is backed by a conductive layer 77 that functions as a gate. The S-channel structure is surrounded by a conductive layer 73 that functions as a gate electrode. .

[0421] FIG. 44A shows a top view of a transistor 70C. 44(C) is a cross-sectional view taken along line L1-L2, which represents the channel length direction of transistor 70C. 1 is a cross-sectional view taken along line W1-W2, which represents the channel width direction of a transistor 70C.

[0422] FIG. 44A shows a conductive layer 77, a conductive layer 73, a semiconductor layer 75, a conductive layer 80, and a conductive layer 81. , opening 93, opening 94, opening 95 and opening 96. Conductive layer 77 is a gate and The conductive layer 73 functions as a back gate. The openings 93 and 94 are formed in the semiconductor layer The openings 95 and 96 are openings for connecting the conductive layer 75 to the conductive layer 80 and the conductive layer 81. The openings are for electrically connecting the conductive layer 77 to the conductive layer 73 .

[0423] In FIG. 44(B), a conductive layer 73, an insulating layer 74, and a semiconductor device with the insulating layer 74 interposed therebetween are provided on a substrate 72. a semiconductor layer 75 overlapping the conductive layer 73; an insulating layer 76 on the semiconductor layer 75; a conductive layer 77a which overlaps with the semiconductor layer 75 with a gate electrode therebetween, and A conductive layer 77b, an insulating layer 78 on the conductive layers 77a and 77b, and an insulating layer 78 on the insulating layer 78. The insulating layer 76, the insulating layer 78 and the insulating layer 79 are provided with openings 93 and 94. The conductive layer 74 is electrically connected to the semiconductor layer 75 and functions as a source or a drain. The conductive layer 80 and the conductive layer 81 are provided.

[0424] In FIG. 44(C), a conductive layer 73, an insulating layer 74, a semiconductor layer 75, and an insulating layer 76 are formed on a substrate 72. The edge layer 76 and the conductive layer 77a and conductive layer 77b are electrically connected to the conductive layer 73 at the openings 95 and 96. and conductive layer 77b, an insulating layer 78 on conductive layer 77a and conductive layer 77b, and The semiconductor layer 75 includes a channel forming region 82, an LDD region 83, and an insulating layer 79. , and impurity region 84. The conductive layer 77a and the conductive layer 77b are configured to form the conductive layer 77. The doping is performed through the areas of the conductive layer 77a that do not overlap with the conductive layer 77b. The length of the LDD region overlapping the conductive layer 77a can be determined by the following formula: The thickness of the conductive layer 77b is controlled by the conductive layer 77b, which serves as a mask during the ion doping. The conductive layer 77a and the conductive layer 77b are used as a mask during ion doping. The LDD region is formed in a self-aligned manner, and the length (Lov) is required. The length of the LDD region overlapping the conductive layer 77a can be adjusted. This allows for precise control of the length, and improves the lifetime against hot carrier degradation. This allows highly reliable semiconductor devices to be manufactured with a high yield.

[0425] In the transistor 70C, the conductive layer 77 is a gate, and the conductive layer 77 is electrically connected to the conductive layer 77. The conductive layer 73, which is the back gate, forms a channel in the channel forming region 82 of the semiconductor layer 75. In other words, this structure is such that the upper surface of the channel forming region is electrically surrounded by the It is possible to form a structure that encloses the channel forming region from the top, bottom and side surfaces. This allows the on-current to be increased and the size in the channel width direction to be reduced. Since the channel forming region is surrounded by a conductive film, the channel forming region can be easily shielded from light. This can be done easily, and photoexcitation caused by unintended light irradiation on the channel formation region can be suppressed. It can be controlled.

[0426] In the transistor 70C, the semiconductor layer 75 has a side edge in the W1-W2 direction. In addition, the conduction state due to the unintended increase in conductivity caused by the LDD region 83 can be suppressed. In addition, the influence of the distribution variation of the impurity element added to the impurity region 84 can be reduced. Cut.

[0427] In the configuration shown in FIGS. 44(A) to 44(C), the W1-W2 direction in the semiconductor layer 75 This can prevent a conductive state due to an unintended increase in conductivity at the side end portion in the direction of the electrode. Furthermore, the influence of variations in the distribution of the impurity elements added to the semiconductor layer 75 can be reduced. do.

[0428] In the configurations shown in Figures 44(A) to 44(C), the gate and back gate are electrically connected. However, as shown in the example in Figure 43, a configuration in which they are at separate potentials is also effective. This configuration is particularly effective when configuring a circuit that is composed only of n-channel types. The threshold voltage of the transistor can be controlled by applying a voltage to the back gate. ED-MOS is composed of transistors with different voltages, and is used for logic circuits such as inverter circuits. Such a logic circuit can be used as a driving circuit for driving pixels. By applying this technology to the circuit, the area occupied by the driver circuit can be reduced, which contributes to the narrow frame of the display device. In addition, the back gate voltage can be adjusted to turn the transistor off. By setting the voltage at this level, the off-state current of the transistor can be reduced. Therefore, even if the refresh rate of the display device is increased, the written voltage Therefore, the display by reducing the number of times of writing can be This is expected to reduce the power consumption of the device.

[0429] The top view and cross-sectional view shown in Figures 44(A) to 44(C) are examples and may be of other configurations. For example, Figure 45(A)-Figure 45(C) can be combined with Figure 44(A)-Figure 44(C). 1 shows different top and cross-sectional views.

[0430] The transistor 70D shown in FIGS. 45(A) to 45(C) is ) in that the conductive layer 77 serving as the gate is formed as a single layer. In addition, the positions of the openings 95 and 96 are closer to the channel forming region 82. By doing so, the upper surface, the lower surface, and the channel formation region of the transistor 70D are It is possible to easily apply an electric field from the side toward the channel forming region. Even if the structure is the same as that of Figs. 44(A) to (C), the S-channel structure is It can be effective.

[0431] As another configuration, Figs. 46(A) to 46(C) are shown in Figs. 44(A) to 44(C), and 45(A) to 45(C) show different top views and cross-sectional views.

[0432] The configuration shown in Figs. 46(A) to 46(C) is similar to that shown in Figs. 44(A) to 44(C) and 45 (A)-(C) is different from the configuration shown in FIG. 45(C) in that the back gate of the transistor 70E is The conductive layer 73 is made up of a conductive layer 73a and a conductive layer 73b, and the conductive layer 73b is made up of the conductive layer 73a. The point is that the structure is surrounded by the same as in Figures 44(A) to 44(C). Since the S-channel structure is used, this effect can be fully achieved.

[0433] In addition, in the configurations of FIGS. 46(A) to 46(C), the conductive layer 73b has a mobile element. Even when metals (e.g., copper (Cu)) are used, mobile elements do not penetrate into the semiconductor film. This can prevent the semiconductor film from deteriorating.

[0434] The conductive layer 73a, which functions as a barrier film on the surface where the wiring is to be formed, is made of a material such as a high-temperature silicon dioxide. The melting point materials tungsten (W), molybdenum (Mo), chromium (Cr), and titanium (T i), tantalum (Ta), or its alloys (e.g., W-Mo, Mo-Cr , Ta-Mo), or their nitrides (e.g., tungsten nitride, titanium nitride, titanium The material used for the insulating layer is a nitride containing titanium and silicon. The conductive layer 73b may be made of copper (C However, there is no particular limitation as long as the material is low resistance. For example, silver (Ag), aluminum Aluminum (Al), gold (Au), and alloys thereof may also be used. The preferred method for forming the resist mask is sputtering, but conditions that do not damage the resist mask are also acceptable. By selecting the conditions, the CVD method can also be used.

[0435] In FIG. 47(A) and FIG. 47(B), an n-channel transistor 70 and a p-channel 2 and transistor 71.

[0436] Here, an n-channel transistor 70 and a p-channel transistor 71 are formed on the same substrate. An example of a transistor configured with an n-channel transistor 70 and a p-channel transistor 71 is shown. By combining transistors 71, a CMOS circuit or the like can be fabricated.

[0437] The transistor 70 is formed on a substrate 72 having an insulating surface, and a conductive layer 70 serving as a gate. 3, an insulating layer 74 on the conductive layer 73, and a semiconductor layer overlapping the conductive layer 73 with the insulating layer 74 interposed therebetween. A semiconductor layer 75, an insulating layer 76 on the semiconductor layer 75, and an insulating layer 76 overlapping the semiconductor layer 75. The conductive layer 77a and the conductive layer 77b are folded and function as gates. and an insulating layer 78 on the conductive layer 77b, an insulating layer 79 on the insulating layer 78, an insulating layer 76, an insulating The semiconductor layer 75 is electrically connected to the insulating layer 78 through an opening in the insulating layer 79. The semiconductor device also includes a conductive layer 80 and a conductive layer 81 which function as a source or a drain.

[0438] The width of the conductive layer 77b in the channel length direction is shorter than that of the conductive layer 77a. The conductive layer 77b is laminated in this order from the insulating layer 76 side. A channel formation region 82 is formed at a position overlapping with the conductive layer 77b. A pair of LDD regions 83 are positioned so as to surround the channel forming region 82 and the LDD region 83. The pair of impurity regions 84 are positioned so as to sandwich the source. It functions as a drain region.

[0439] The transistor 71 has a conductive layer functioning as a gate on a substrate 72 having an insulating surface. The conductive layer 85, the insulating layer 74 on the conductive layer 85, and the insulating layer 74 overlapping the conductive layer 85 with the insulating layer 74 interposed therebetween. The semiconductor layer 86 is formed on the insulating layer 76, and the semiconductor layer 86 is formed on the insulating layer 76. 6 and function as gates, and a conductive layer 87a and a conductive layer 87b 87a and the insulating layer 78 on the conductive layer 87b, the insulating layer 79 on the insulating layer 78, and the insulating layer 76 , which are electrically connected to the semiconductor layer 86 through openings provided in the insulating layers 78 and 79. and a conductive layer 88 and a conductive layer 89 which function as a source or a drain. do.

[0440] The width of the conductive layer 87b in the channel length direction is shorter than that of the conductive layer 87a. The conductive layer 87b is laminated in this order from the insulating layer 76 side. A channel forming region 90 is formed at a position overlapping with the conductive layer 87b. The pair of impurity regions 91 are arranged to surround the source region. Or it functions as a drain region.

[0441] In FIG. 47A, conductive layers 77a and 77b functioning as gates and a back gate electrode However, other configurations may be used. As shown in FIG. 47(B), the conductive layer 73 functioning as a back gate electrode may be omitted. In FIG. 47A, the conductive layers 87a and 87b functioning as gates and the back Although a structure having a conductive layer 85 functioning as a gate electrode is shown, other structures may be used. For example, as shown in FIG. 47(B), a conductive layer 85 functioning as a back gate electrode is It may be omitted.

[0442] The n-channel transistor 70 shown in FIG. 47(A) is a Sc This is a channel structure, which corresponds to the transistor 70C in FIG. The top view of the n-channel transistor 70 shown in (A) is the same as that of the transistor 70 shown in FIG. 47(A) corresponds to a top view of the n-channel transistor 70 The cross-sectional view in the channel width direction corresponds to the cross-sectional view of the transistor 70C in FIG.

[0443] Figures 48(A)-(C) and 49(A)-(C) show a transistor with a slightly different configuration from the above. 1A and 1B show a top view and a cross-sectional view of a transistor.

[0444] The transistor 70F shown in FIGS. 48(A) to 48(C) has a so-called staggered structure.

[0445] The transistor 70F includes an insulating layer 74 on a substrate 72, a semiconductor layer 75 on the insulating layer 74, and An insulating layer 76 on the insulating layer 74 and the semiconductor layer 75, a conductive layer 77 on the insulating layer 76, and 6 and an insulating layer 78 on the conductive layer 77, an insulating layer 79 on the insulating layer 78, and a conductive layer on the insulating layer 79. The semiconductor layer 75 includes a channel forming region 82 and an impurity region 83. The semiconductor layer 75 may have an LDD region.

[0446] The conductive layer 80 is formed by passing through the openings 93 provided in the insulating layers 76, 78, and 79. The conductive layer 81 is electrically connected to the semiconductor layer 75 through the insulating layer 76 and the insulating layer 78 and an opening 94 formed in the insulating layer 79. .

[0447] The insulating layer 74 functions as a base insulating layer. A portion of the conductive layer 77 functions as a gate insulating layer, and a portion of the conductive layer 77 functions as a gate electrode. The insulating layer 78 and the insulating layer 79 also function as interlayer insulating layers. In addition, a part of the conductive layer 80 functions as a source electrode, and a part of the conductive layer 81 functions as a source electrode. The portion of the semiconductor layer 75 functions as a drain electrode. The impurity region 84 is formed in a region that does not overlap with the conductive layer 77, which is a so-called self-aligned type. The transistor 70F is a transistor with a single gate structure. is.

[0448] Next, a transistor 70G shown in FIGS. 49(A)-(C) has a so-called staggered structure. This is a structure in which a back gate electrode is provided in the transistor 70F described above.

[0449] The conductive layer 73, a part of which functions as a back gate electrode, is located below the insulating layer 74. The transistor 70G has a channel forming region 82 sandwiched between the conductive layer 73 and the conductive layer 77. Here, the conductive layer 73 and the conductive layer 77 are electrically connected in a region not shown. It is preferable that

[0450] As shown in FIGS. 49B and 49C, the region of the insulating layer 74 that does not overlap with the semiconductor layer 75 is The thickness is smaller than the area overlapping with the semiconductor layer 75. The side surfaces of the channel forming region 82 can be covered with the conductive layer 77. The gate electric field can be applied effectively from the side of the formation region 82 .

[0451] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0452] (Fourth embodiment) In this embodiment, a touch panel including a touch panel according to one embodiment of the present invention and an IC will be described. An example of the module configuration will be described with reference to the drawings.

[0453] FIG. 50 shows a block diagram of the touch panel module 6500. The controller 6500 includes a touch panel 6510 and an IC 6520.

[0454] The touch panel 6510 includes a display unit 6511, an input unit 6512, and a scanning line driver circuit 65 The display portion 6511 has a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines. The input unit 6512 has a function of displaying an image. It has multiple sensor elements that detect contact or proximity and functions as a touch sensor. The scanning line driver circuit 6513 has a function of outputting a scanning signal to the scanning lines of the display portion 6511. Possess the ability.

[0455] For ease of explanation, the touch panel 6510 is configured as follows: The input unit 6512 is shown separately, but it has a function to display an image and a function as a touch sensor. It is preferable to use a so-called in-cell type touch panel that has both of the above functions. .

[0456] As a touch sensor type that can be used as the input unit 6512, for example, a capacitive touch sensor is used. Capacitive touch panels can be used. Surface capacitive touch panels and projected capacitive touch panels can be used. Projected capacitive touch panels include the self-capacitance type and the mutual capacitance type. The mutual capacitance method is preferable because it allows simultaneous multipoint detection.

[0457] However, the present invention is not limited to this, and it is also possible to detect the proximity or contact of a detection object such as a finger or a stylus. Various types of sensors that can be used for the input unit 6512 can also be applied. For example, In addition to the capacitance type, there are also resistive film type, surface acoustic wave type, infrared type, and optical type. Various methods can be used, including the academic method.

[0458] Representative in-cell touch panels are the semi-in-cell type and the full-in-cell type. The semi-in-cell type has both a substrate that supports the display element and an opposing substrate, or On the other hand, the full-in-cell type refers to a configuration in which electrodes and the like that constitute the touch sensor are provided on the surface. This refers to a configuration in which electrodes that constitute a touch sensor are provided on a substrate that supports a display element. A cell-type touch panel is preferable because it can simplify the configuration of the opposing substrate. As a full-in-cell type, the electrodes that make up the display element also serve as the electrodes that make up the touch sensor. This structure is preferable because it simplifies the manufacturing process and reduces manufacturing costs.

[0459] The display unit 6511 supports HD (1280 x 720 pixels), FHD (1920 x 10 80), WQHD (pixel count 2560 x 1440), WQXGA (pixel count 2560 x 160 0), 4K (pixel count 3840 x 2160), 8K (pixel count 7680 x 4320) It is preferable to have a very high resolution, especially 4K, 8K or higher. In addition, it is preferable that the pixel density (resolution) of the pixels provided in the display portion 6511 is However, it is 300 ppi or more, preferably 500 ppi or more, and more preferably 800 ppi or more. , more preferably 1000 ppi or more, and more preferably 1200 ppi or more. The display portion 6511 having such high resolution and high definition allows For personal use such as home use, it is important to enhance the sense of realism and depth. This makes it possible to:

[0460] The IC 6520 includes a circuit unit 6501, a signal line driver circuit 6502, and a sensor driver circuit 6503. 503 and a detection circuit 6504. The circuit unit 6501 includes a timing controller It has a controller 6505, an image processing circuit 6506, etc.

[0461] The signal line driver circuit 6502 supplies an analog signal to a signal line of the display portion 6511. For example, the signal line driver circuit 6502 has a function of outputting an image signal (also called a video signal). As an example, the shift register circuit and the buffer circuit may be combined. The touch panel 6510 may also have a demultiplexer circuit connected to the signal lines. good.

[0462] The sensor driving circuit 6503 outputs a signal that drives the sensor element of the input unit 6512. The sensor driver circuit 6503 has a function of, for example, a shift register circuit and a buffer circuit. A configuration combining a first circuit can be used.

[0463] The detection circuit 6504 receives an output signal from the sensor element of the input section 6512 and outputs it to the circuit unit. For example, the detection circuit 6504 may include an amplifier circuit and an analog Log-to-digital conversion circuit (ADC: Analog-to-Digital Converter) In this case, the detection circuit 6504 receives the signal from the input unit 6512. The output analog signal is converted into a digital signal and output to the circuit unit 6501 .

[0464] The image processing circuit 6506 of the circuit unit 6501 controls the display of the touch panel 6510. a function to generate and output a signal to drive the input unit 6511; and a function to analyze the signal output from the input unit 6512 and output the signal. It has the function of outputting 0.

[0465] As a more specific example, the image processing circuit 6506 performs the following in accordance with an instruction from the CPU 6540: The image processing circuit 6506 has a function of generating a video signal. The video signal is then processed according to the user's needs, converted into an analog video signal, and sent to the signal line driver circuit 6. The image processing circuit 6506 also has the function of supplying the image data to the CPU 6540. In accordance with the instruction, it has a function of generating a drive signal to be output to the sensor drive circuit 6503. The image processing circuit 6506 analyzes the signal input from the detection circuit 6504 and outputs it as position information. and outputs it to the CPU 6540.

[0466] The timing controller 6505 also receives the video signal processed by the image processing circuit 6506. The scanning line driver circuit 6513 and the sensor driver circuit 6503 receive the synchronous signal. A function to generate and output signals (clock signals, start pulse signals, etc.) The timing controller 6505 also detects when the detection circuit 6504 outputs a signal. The timing control unit 100 may have a function to generate and output a signal that defines the timing. The scanning controller 6505 controls the signals to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6514. It is preferable to output signals synchronized with the signals output to the line 6502 and the line 6503. The period during which the pixel data of the display unit 6511 is rewritten and the period during which the pixel data of the input unit 6512 is sensed are also included. For example, it is preferable to divide one frame period into two periods for storing pixel data. The touch panel 6510 is driven by dividing it into a rewriting period and a sensing period. In addition, for example, by providing two or more sensing periods in one frame period, The detection sensitivity and detection accuracy can be improved.

[0467] The image processing circuit 6506 can have a configuration including a processor, for example. For example, DSP (Digital Signal Processor), GPU (Gra A microprocessor such as a phics processing unit can be used. These microprocessors can also be implemented as FPGAs (Field Programmable Gate Arrays). Gate Array) and FPAA (Field Programmable A PLDs (Programmable Logic Devices) such as analog arrays The configuration may be realized by various programs depending on the processor. By interpreting and executing these instructions, various data processing and program control are carried out. The program that can be executed by the processor may be stored in a memory area of ​​the processor. Alternatively, it may be stored in a separately provided storage device.

[0468] The touch panel 6510 includes a display unit 6511, a scanning line driver circuit 6513, and an I The circuit unit 6501, the signal line driver circuit 6502, and the sensor driver circuit 6503 included in the C6520 503, a detection circuit 6504, or an externally provided CPU 6540, etc. By using an oxide semiconductor in the region, a transistor with extremely low off-state current can be used. Since the off-state current of the transistor is extremely low, the transistor can be used as a memory. As a switch to hold the charge (data) that has flowed into the capacitive element that functions as an element By using this feature, data retention can be ensured for a long period of time. By using this in the registers and cache memory of the image processing circuit 6506, The image processing circuit 6506 is operated, and in other cases, the information of the immediately preceding processing is saved in the storage element. This enables normally-off computing, and This allows for reduced power consumption of the module 6500 and the electronic device in which it is implemented.

[0469] In this case, the circuit unit 6501 is connected to the timing controller 6505 and the image processing circuit. Although the image processing circuit 6506 is configured to have the image processing circuit 6506 itself, A circuit having some of the functions of IC6520 may be provided outside the IC6520. The CPU 6540 may take on the functions or part of the functions of the logic circuit 6506. The unit 6501 includes a signal line driver circuit 6502, a sensor driver circuit 6503, and a detection circuit 650 4 and a timing controller 6505.

[0470] Although an example in which the IC 6520 includes the circuit unit 6501 has been shown here, The IC6501 can be configured not to be included in the IC6520. The signal line driver circuit 6502, the sensor driver circuit 6503, and the detection circuit 6504 are included. For example, when multiple ICs are mounted on the touch panel module 6500, In this case, a circuit unit 6501 is separately provided, and an IC 652 without a circuit unit 6501 is provided. A plurality of 0 can be arranged, or a circuit having only the IC 6520 and the signal line driver circuit 6502 can be arranged. It is also possible to combine and arrange ICs that are different from each other.

[0471] In this way, the touch panel 6510 has a function of driving the display unit 6511 and a function of driving the input unit 651 The touch panel module is made up of a single IC incorporating the functions to drive the touch panel. This reduces the number of ICs mounted on the 6500, thereby reducing costs. Cut.

[0472] Figure 51 (A), (B), and (C) show touch panel modules 6 equipped with IC6520. 500 is a schematic diagram.

[0473] In FIG. 51(A), the touch panel module 6500 includes a substrate 6531, an opposing substrate 65 32, including a plurality of FPCs 6533, ICs 6520, ICs 6530, etc. Also, a substrate 653 A display section 6511, an input section 6512, and a scanning line driver circuit 6513 are disposed between the substrate 6511 and the opposing substrate 6532. 513. The IC6520 and IC6530 are COG (Chip On Glass) The semiconductor device is mounted on a substrate 6531 by a mounting method such as a mounting method using a mounting board.

[0474] The IC6530 is the same as the IC6520 described above except that only the signal line driver circuit 6502 is is an IC having a signal line driver circuit 6502 and a circuit unit 6501. The IC6530 receives external signals via FPC6533. Signals can be output from IC6520 and IC6530 to the outside via 533.

[0475] In FIG. 51(A), two scanning line driver circuits 6513 are provided so as to sandwich a display portion 6511. The figure also shows an example of a configuration that includes IC6530 in addition to IC6520. Such a configuration is suitable for use when the display unit 6511 has extremely high resolution. can be done.

[0476] Figure 51(B) shows an example where one IC6520 and one FPC6533 are mounted. In this way, by consolidating the functions into one IC6520, the number of parts can be reduced. 51(B), the scanning line driver circuit 6513 is connected to the display portion 651. This shows an example of placement along the side of the two short sides of 1 that is closer to the FPC6533.

[0477] FIG. 51(C) shows a PCB (Printed Circuit) on which an image processing circuit 6506 and other components are mounted. 6 shows an example of a configuration having an I / O board 6534. C6520, IC6530, and PCB6534 are electrically connected by FPC6533. Here, the IC 6520 does not have the image processing circuit 6506 described above. The composition can be applied.

[0478] In each diagram of Figure 51, IC6520 and IC6530 are mounted on F It may be mounted on PC6533. For example, IC6520 or IC6530 may be mounted on COF (C Hip On Film method and TAB (Tape Automated Bonding) g) method or other mounting methods can be used to mount the FPC6533.

[0479] As shown in Figures 51(A) and (B), the FPC 6533 and IC The configuration in which IC6520 (and IC6530) etc. are arranged allows for a narrow frame, so for example, It can be suitably used in electronic devices such as smartphones, mobile phones, and tablet terminals. In addition, the configuration using PCB6534 as shown in Figure 51(C) can be used in televisions, for example. Application devices, monitor devices, tablet terminals, laptop computers, etc. It can be suitably used for the following.

[0480] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0481] (Embodiment 5) In this embodiment, a display module including a display device or a display system according to one embodiment of the present invention will be described. The module and electronic device will be described with reference to FIGS. 52 to 54.

[0482] The display module 8000 shown in FIG. 52 includes an upper cover 8001 and a lower cover 8002. Between them, the touch panel 8004 connected to the FPC 8003, the frame 8009, and the printer It has a power board 8010 and a battery 8011.

[0483] A display panel, a touch panel, or a touch panel module according to an embodiment of the present invention may include, for example, For example, it can be used for the touch panel 8004.

[0484] The upper cover 8001 and the lower cover 8002 are designed to fit the size of the touch panel 8004. The shape and dimensions can be changed as needed.

[0485] The touch panel 8004 is a resistive or capacitive touch panel. In addition, the opposing substrate (sealing substrate) of the touch panel 8004 can be used by overlapping it with the It is also possible to provide a touch panel function. It is also possible to provide an optical sensor in each pixel of the display 4 to create an optical touch panel.

[0486] In addition, when a transmissive or semi-transmissive liquid crystal element is used, the backlight is turned on as shown in Figure 52. A backlight 8007 may be provided. The backlight 8007 has a light source 8008. In FIG. 52, an example of a configuration in which a light source 8008 is arranged above a backlight 8007 is shown. For example, the light source 8008 may be disposed at the end of the backlight 8007. In addition, a light diffusing plate may be used. When using an optical element or a reflective panel, the backlight 8007 It may not be provided.

[0487] The frame 8009 not only protects the touch panel 8004 but also secures the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by operation. The frame 8009 may also function as a heat sink.

[0488] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0489] In addition, the Touch Panel 8004 adds components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as follows.

[0490] 53(A) to 53(H) and 54(A) and (B) are diagrams showing electronic devices. These electronic devices are made up of a housing 5000, a display unit 5001, a speaker 5003, an LED light pump 5004, operation keys 5005 (including a power switch or an operation switch), connection terminal 5006, Sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light , liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow (including functions to measure volume, humidity, gradient, vibration, odor or infrared), microphone 5008, etc.

[0491] FIG. 53(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc.

[0492] FIG. 53(B) shows a portable image reproducing device (for example, a DVD reproducing device) equipped with a recording medium. In addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, etc. It is possible.

[0493] FIG. 53(C) shows a television set, which includes a stand 5012 and other components in addition to those described above. The television device can be operated using an operation switch provided in the housing 5000. This can be done by a separate remote control device 5013. The channel and volume can be controlled by the operation keys provided on the display unit 5001. In addition, the remote control operation device 5013 can be used to operate the image displayed on the remote control device. A display unit for displaying information output from the controller 5013 may be provided.

[0494] FIG. 53(D) shows a portable gaming machine, which includes, in addition to the above, a recording medium reading unit 5011, etc.

[0495] Figure 53(E) is a digital camera with a TV receiving function, and in addition to the above, It may have a lens 5014, a shutter button 5015, an image receiving unit 5016, etc.

[0496] FIG. 53(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 5002, a recording unit, It may have a medium reading unit 5011, etc.

[0497] Figure 53(G) shows a portable television receiver, which, in addition to the above, has a function for transmitting and receiving signals. 5017, etc.

[0498] FIG. 53(H) shows a wristwatch type information terminal, which includes, in addition to the above, a band 5018, a clasp, and the like. The housing 5000 also serves as a bezel. The display unit 5001 has a non-rectangular display area. icon 5020, other icons 5021, etc. can be displayed.

[0499] Figure 54(A) is a digital signage. Figure 54(B) shows a digital signage attached to a cylindrical pillar.

[0500] The electronic devices shown in FIGS. 53(A) to 53(H) and 54(A) and (B) are used in various For example, various information (still images, videos, text images, etc.) can be displayed. Functions that display information on the display unit, touch panel function, calendar, date or time display function, etc. function, the function to control processing by various software (programs), wireless communication function, The ability to connect to various computer networks using wired communication functions, and the ability to connect to various computer networks using wireless communication functions the function of transmitting or receiving various data, the program recorded on the recording medium, or It can have a function to read out data and display it on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another The function of displaying text information mainly on one display unit, or displaying images that take parallax into account on multiple displays By displaying a stereoscopic image, the device can have the function of displaying a stereoscopic image. In electronic devices with an image unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or internal to the camera). The image capturing device may have functions such as storing the captured image in a memory (storage), displaying the captured image on a display unit, etc. Note that the electronic devices shown in FIGS. 53(A) to 53(H) and 54(A) and (B) have The functions that can be implemented are not limited to these, and various other functions can be implemented.

[0501] The electronic device described in this embodiment has a display unit for displaying some information. The display unit is characterized in that the display panel, touch panel, or A touch panel module or the like can be applied.

[0502] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0503] 10 Touch Panel Module 11 Capacitor element 21 PCB 22 Touch Sensor 22a opening 23a opening 24a opening 23 Conductive layer 24 Conductive layer 25 Conductive layer 26 Conductive layer 29 Wiring 31 PCB 32 Display section 33 pixels 33B subpixel 33G subpixel 33R subpixel 33Y subpixel 34 circuits 35 Wiring 41 FPC 42 FPC 60 Display element 70 transistors 70A transistor 70B transistor 70C transistor 70D transistor 70E transistor 70F transistor 70G transistor 71 Transistor 72 PCB 73 Conductive Layer 73a Conductive layer 73b Conductive layer 74 Insulating layer 75 Semiconductor layer 76 Insulating Layer 77 Conductive Layer 77a Conductive layer 77b Conductive layer 78 Insulating Layer 79 Insulating Layer 80 Conductive layer 81 Conductive layer 82 Channel formation region 83 LDD area 84 Impurity region 85 Conductive Layer 86 Semiconductor layer 87a Conductive layer 87b Conductive layer 88 Conductive Layer 89 Conductive Layer 90 Channel formation region 91 Impurity region 93 Aperture 94 Aperture 95 Aperture 96 Aperture 101 Connection 111 Conductive layer 112 LCD 113 Conductive Layer 114 Conductive layer 121 Insulating layer 122 Insulating layer 123 Overcoat 124 Spacer 125 Conductive Layer 126 Insulating Layer 130a Polarizing plate 130b Polarizing plate 131B Colored layer 131G colored layer 131R colored layer 132 Light blocking layer 141 Adhesive layer 151 Conductive layer 152 LCD 153 Conductive Layer 201 Transistor 202 Transistor 203 Capacitor 204 Connection 211 Insulating layer 212 Insulating layer 213 Insulating Layer 214 Insulating layer 215 Insulating Layer 221 Conductive layer 222 Conductive layer 223 Conductive Layer 224 Conductive Layer 231 Semiconductor layer 232 Low resistance region 241 Connection Layer 242 Connection Layer 243 Connectors 300 buffer layer 301 Transistor 302 Transistor 401 Transistor 402 transistor 601 Pulse voltage output circuit 602 Current detection circuit 603 capacity 621 Electrode 622 Electrode 723 Electrode 725 layers 726 Insulation Layer 727 Insulation Layer 728 Insulation Layer 729 Insulation Layer 741 Insulation Layer 742 Semiconductor layer 742a Semiconductor layer 742b Semiconductor layer 742c Semiconductor layer 743 Electrode 744a electrode 744b electrode 746 Electrode 747a aperture 747b aperture 747c aperture 747d aperture 755 Impurities 771 Circuit Board 772 Insulation Layer 775 Insulation Layer 810 Transistor 811 Transistor 820 transistors 821 Transistor 822 transistor 825 transistors 826 Transistor 830 transistors 831 Transistor 840 transistors 841 Transistor 842 transistors 843 Transistor 844 transistors 845 transistors 846 transistors 847 Transistor 848 transistors 850 transistors 851 Transistor 852 transistors 882 Ec 883a Ec 883b Ec 883c Ec 886 Ec 887 Ec 890 trap levels 3501 Wiring 3502 Wiring 3503 Transistor 3504 Liquid crystal elements 3510 Wiring 3510_1 Wiring 3510_2 Wiring 3511 Wiring 3515_1 Block 3515_2 Block 3516 blocks 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Stand 5013 Remote control operation machine 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Band 5019 Clasp 5020 Icon 5021 Icon 6500 Touch Panel Module 6501 Circuit Unit 6502 Signal line driver circuit 6503 Sensor driver circuit 6504 detection circuit 6505 timing controller 6506 Image processing circuit 6510 Touch Panel 6511 Display section 6512 input section 6513 Scanning line driver circuit 6520 IC 6530 IC 6531 Circuit Board 6532 Opposing substrate 6533 FPC 6534 PCB 6540 CPU 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] A liquid crystal display device having a touch sensor function, a first substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a liquid crystal layer, a first colored layer, a second colored layer, and an insulating layer; the third conductive layer is located on the first substrate; the fourth conductive layer is located on the same plane as the third conductive layer but spaced apart from it; the liquid crystal layer is located above the third conductive layer, the first colored layer and the second colored layer are located above the liquid crystal layer, the second conductive layer is located above the first colored layer and the second colored layer, the insulating layer has a region in contact with the first colored layer, a region in contact with the second colored layer, and a region in contact with the liquid crystal layer; the first conductive layer is located above the second conductive layer, the first conductive layer has a plurality of openings; the second conductive layer is an oxide semiconductor containing hydrogen at 8×10 19 atoms / cm 3 or more, has a function of transmitting visible light, and has a portion overlapping with the third conductive layer and a portion overlapping with the fourth conductive layer; the third conductive layer and the fourth conductive layer have a function of transmitting visible light, the third conductive layer has a portion overlapping one of the openings, the fourth conductive layer has a portion overlapping the other one of the openings, A liquid crystal display device, wherein the first conductive layer has a portion located between the third conductive layer and the fourth conductive layer in a plan view.

Images