Apparatus and method for generating or receiving a synchronization header

Abstract

According to one embodiment, an apparatus (100) for generating a data stream is provided. The apparatus (100) is configured to generate a data stream such that the data stream includes header data and payload data. The apparatus (100) is configured to generate header data such that the header data includes a synchronization header. Moreover, the apparatus (100) is configured to generate the synchronization header using binary coding. Furthermore, the apparatus (100) is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits.

Description

[Technical Field]

[0001] The present invention relates to an apparatus and method for generating or receiving a synchronization header. [Background technology]

[0002] In most communication systems, transmission occurs in a bursty manner, meaning that over time there are quiet gaps where no data is transmitted, followed by data bursts where payload is transported. In many communication systems and applications, it is desirable for the receiver to recover timing at the beginning of a data burst. Summary of the Invention [Problem to be solved by the invention]

[0003] The object of the present invention is to provide an improved concept for data communication. The object of the present invention is to provide a device according to claim 1. , request request 38 The system according to claim 39、40 The method according to claim 41 and a data stream according to claim 42. [Means for solving the problem]

[0004] According to one embodiment, an apparatus for generating a data stream is provided. The apparatus is configured to generate a data stream such that the data stream includes header data and payload data. The apparatus is configured to generate header data such that the header data includes a synchronization header. Moreover, the apparatus is configured to generate the synchronization header using binary coding. Furthermore, the apparatus is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. Moreover, according to one embodiment, there is provided an apparatus for receiving a data stream. The data stream includes header data and payload data. The header data includes a synchronization header. The synchronization header is binary encoded, and the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. The apparatus is configured to obtain the payload data of the data stream using the synchronization sequence of the synchronization header of the data stream. Further provided is a system comprising: an apparatus for generating a data stream; and an apparatus for receiving a data stream. The apparatus for generating a data stream is configured to generate the data stream such that the data stream includes header data and payload data. Moreover, the apparatus for generating a data stream is configured to generate header data such that the header data includes a synchronization header. Furthermore, the apparatus for generating a data stream is configured to generate the synchronization header using binary coding, and the apparatus for generating a data stream is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. The apparatus for receiving a data stream is configured to obtain the payload data of the data stream using the synchronization sequence of the synchronization header of the data stream. Moreover, according to one embodiment, a method for generating a data stream is provided. The method includes generating a data stream such that the data stream includes header data and payload data. Generating the header data is performed such that the header data includes a synchronization header. Generating the synchronization header is performed using binary coding. Generating the synchronization header is performed such that the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. Further, according to one embodiment, a method for receiving a data stream is provided. The data stream includes header data and payload data. The header data includes a synchronization header. The synchronization header is binary encoded, and the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. The method includes obtaining payload data of the data stream using the synchronization sequence of the synchronization header of the data stream. Moreover, computer programs are provided, each computer program being configured to perform one of the methods described above when run on a computer or signal processor. Further, a data stream including header data and payload data according to one embodiment is provided, wherein the header data includes a synchronization header, the synchronization header being binary encoded, and the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. In the following, embodiments of the invention will be explained in more detail with reference to the drawings. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an apparatus for generating a data stream according to one embodiment. [Figure 2] FIG. 1 illustrates an apparatus for receiving a data stream according to one embodiment. [Figure 3] FIG. 1 illustrates a system, according to one embodiment. [Figure 4] FIG. 10 illustrates an example of a synchronization sequence in PAM representation, according to one embodiment. [Figure 5] FIG. 5 is a diagram showing a synchronization sequence in 0 / 1 representation for the embodiment shown in FIG. 4. [Figure 6] FIG. 10 illustrates a version of a synchronization header in which the first insertion and the surrounding PRBS have double the bits, according to one embodiment. [Figure 7]FIG. 10 illustrates a version of the synchronization header in which the first insertion has double the bits, according to another embodiment. [Figure 8] FIG. 10 illustrates a version of the synchronization header in accordance with a further embodiment, where every insertion only has a single bit but the entire sequence is repeated. DETAILED DESCRIPTION OF THE INVENTION

[0006] FIG. 1 shows an apparatus 100 for generating a data stream according to one embodiment. The apparatus 100 is configured to generate a data stream such that the data stream includes header data and payload data. The apparatus 100 is configured to generate the header data such that the header data includes a synchronization header. Moreover, the apparatus 100 is configured to generate the synchronization header using binary coding. Furthermore, the apparatus 100 is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. According to one embodiment, the apparatus 100 may be configured to generate a synchronization sequence including a number of bits, for example, such that the total number of transitions in the synchronization sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 35% of the number of bits in the synchronization sequence. In one embodiment, the apparatus 100 may be configured to generate the synchronization sequence such that the total number of transitions in the synchronization sequence is greater than or equal to 50% of the number of bits in the synchronization sequence, for example. According to one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes a pseudo-random binary sequence, for example.

[0007] In one embodiment, the apparatus 100 may generate a synchronization sequence including, for example, a first number of bits, as follows: a first total number of transitions from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value in the synchronization sequence; First number of bits against The first ratio is a second total number of transitions from the first bit value to the second bit value and from the second bit value to the first bit value in a pseudorandom binary sequence including the second number of bits; Second number of bits against Second Ratio The generated signal may be configured to be greater than

[0008] In one embodiment, the apparatus 100 may be configured to generate a pseudo-random binary sequence, for example, by using a linear feedback shift register. According to one embodiment, the apparatus 100 may be configured to generate the pseudo-random binary sequence such that the pseudo-random binary sequence is different from the synchronization sequence, for example. According to one embodiment, the apparatus 100 can be configured to generate a pseudorandom binary sequence (PRBS) only in part, for example, by starting with a defined seed value and running a predefined number of shifts before resetting to the seed value. The seed value and run length can be selected, for example, so that the longest same-symbol run length, close to the PRBS order, is not included in the used fragment of the PRBS. This avoids long CDR dead times while still providing high variability in the bit patterns.

[0009] In one embodiment, the apparatus 100 may be configured to generate a pseudo-random binary sequence including a number of bits such that, for example, the total number of transitions in the pseudo-random binary sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is greater than or equal to 15% of the number of bits in the pseudo-random binary sequence. For example, the sequence 0001110001 contains 10 bits, two transitions from 0 to 1 and one transition from 1 to 0, i.e., a total number of transitions of 3. In this example of the sequence 0001110001, the total number of transitions is less than 30% of the number of bits in the sequence (in fact, it is 30% = 3 / 10).

[0010] In another example, the sequence 0101010101 contains 10 bits, 5 transitions from 0 to 1 and 4 transitions from 1 to 0, i.e., a total number of transitions of 9. In this example of the sequence 0101010101, the total number of transitions is more than 30% of the number of bits in the sequence (in practice, it is 90% = 9 / 10). For example, the synchronization sequence shown by Figure 4 or Figure 5 has 40 bit values ​​and 21 total transitions (10 transitions from -1 to +1 / 0 to 1 and 11 transitions from +1 to -1 / 1 to 0), which results in a total number of transitions vs. bit value ratio of 21 / 40 = 52.5%.

[0011] According to one embodiment, the apparatus 100 may be configured to generate the pseudorandom binary sequence such that, for example, the total number of transitions in the pseudorandom binary sequence is greater than or equal to 30% of the number of bits in the pseudorandom binary sequence. In order to efficiently find the synchronization sequence by correlation, the portion close to the synchronization sequence (here, for example, the PRBS-based sequence) should have a different transition density compared to the synchronization sequence. For example, a high density can occur with a short (sub)sequence of the same symbol, for example, many repetitions can occur so that the portion of the base sequence resembles the synchronization sequence to a higher degree. Furthermore, a high transition density concentrates a lot of energy in a narrow frequency band, resulting in a higher energy emission.

[0012] In one embodiment, the 40-bit synchronization sequence, eg, the 40-bit synchronization sequence of FIGS. 4 and 5, may be dithered, for example, to avoid emitting too much energy. According to one embodiment, for example, PRBS10 to PRBS30 may be used for the pseudo-random binary sequence. PRBS10 is a pseudorandom value of length 2 10 Generates a sequence of -1, after which the sequence generates the same previous value again (repeating the previous value). PRBS30 is a pseudorandom value of length 2 30 Generates a sequence of -1, after which the sequence generates the same previous value again (repeating the previous value). Generally, PRBSx is a sequence of pseudorandom values ​​of length 2 x Generates a sequence of -1, after which the sequence generates the same previous value again (repeating the previous value).

[0013] In one embodiment, the pseudo-random binary sequence may be, for example, a selected pseudo-random binary sequence, and the apparatus 100 may be configured, for example, to generate an initial pseudo-random binary sequence and select a portion of the initial pseudo-random binary sequence that is smaller than the initial pseudo-random binary sequence as the selected pseudo-random binary sequence, which has the advantage that, for example, a PRBSx having a larger x than necessary may be used so that more randomness is generated in the final selected PRBS. For example, in one embodiment, a portion of a PRBS19 sequence may be used, and the PRBS19 sequence may be different from, for example, a sequence containing 19 consecutive 1 values ​​(and different from, for example, a sequence containing 19 consecutive 0 values). Generally, sufficient transitions occur, and at the same time, generally, there is sufficient variability in the sequence. Thus, a compromise between fast-locking CDR and low emissions is achieved.

[0014] In one embodiment, the apparatus 100 may be configured, for example, to assign bits of a pseudo-random binary sequence to bit positions of a synchronization header, and the apparatus 100 may be configured, for example, to insert bits of the synchronization sequence, but may be configured, for example, to not insert said bits of the pseudo-random binary sequence into the synchronization header. According to one embodiment, the apparatus 100 may be configured, for example, to stop using bits of the pseudo-random binary sequence when the apparatus 100 inserts bits of the synchronization sequence into the synchronization header. The apparatus 100 may be configured, for example, to continue inserting the next bit of the pseudo-random binary sequence into the synchronization header after the apparatus 100 inserts bits of the synchronization sequence into the synchronization header.

[0015] In one embodiment, the apparatus 100 may be configured to insert, for example, two or three times each of two or more bits of the pseudorandom binary sequence into the synchronization header. According to one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes the synchronization sequence at least twice, for example such that the synchronization header includes the synchronization sequence at least twice. In one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes the synchronization sequence more than twice, for example. According to one embodiment, the apparatus 100 may be configured to generate a synchronization header, for example, such that the synchronization header may include a synchronization sequence, for example, at the beginning of the synchronization header, and such that the synchronization header may include a synchronization sequence, for example, at the end of the synchronization header. In one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header contains two synchronization sequences concatenated at the beginning of the synchronization header and two synchronization sequences concatenated at the end of the synchronization header, i.e., at the beginning of the synchronization header, the synchronization header contains a concatenation of two synchronization sequences, and at the end of the synchronization header, the synchronization header also contains a concatenation of two synchronization sequences.

[0016] According to one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the second occurrence of the synchronization sequence occurs immediately after the first occurrence of the synchronization sequence in the synchronization header, for example. In one embodiment, the synchronization sequence may be, for example, a first synchronization sequence. Apparatus 100 may be configured to generate the header data such that the header data includes the first synchronization sequence and a second synchronization sequence, where the second synchronization sequence is different from the first synchronization sequence. According to one embodiment, the apparatus 100 may be configured to generate the synchronization header, for example, such that the synchronization header includes a first synchronization sequence and a second synchronization sequence. In one embodiment, the apparatus 100 may be configured to generate a synchronization header including a number of bits, for example, such that the total number of transitions in the synchronization header from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is greater than or equal to 15% of the number of bits in the synchronization header.

[0017] According to one embodiment, the apparatus 100 may be configured to generate the sync header such that the total number of transitions in the sync header is greater than or equal to 30% of the number of bits in the sync header, for example. In one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes a predefined short code, for example. According to one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the predefined short codes are, for example, 8B10B and 4B5B. In one embodiment, the apparatus 100 may be configured to generate a first version of the synchronization sequence, for example, by doubling or tripling each bit of the initial sequence; The apparatus 100 may be configured, for example, to generate the header data such that the synchronization header includes a first version of the synchronization sequence. According to one embodiment, the apparatus 100 may be configured to generate the header data such that the synchronization header further includes a second version of the synchronization sequence, the second version of the synchronization sequence being equal to the initial sequence, for example.

[0018] In one embodiment, the apparatus 100 may be configured to generate the header data such that, for example, a first version of the synchronization sequence precedes a second version of the synchronization sequence within the header data. According to one embodiment, the apparatus 100 may be configured to derive the synchronization sequence from the initial sequence, for example by changing the position of bits in the initial sequence. In one embodiment, the apparatus 100 may be configured to, for example, change the position of the bits of the initial sequence according to a defined waveform. According to an embodiment, the defined waveform may have, for example, a triangular shape, or may be, for example, sinusoidal, or may have, for example, a rectangular shape, or may have, for example, a sawtooth shape. In one embodiment, the apparatus 100 may be configured to use, for example, a clocked digital waveform to change the position of bits in the initial sequence.

[0019] According to one embodiment, the apparatus 100 may be configured to change the position of the bits of the initial sequence in response to, for example, a pseudo-random signal. In one embodiment, the device 100 may be configured to change the position of the bits of the initial sequence, for example, according to a multiplication factor, which depends on how many times the synchronization sequence has already been inserted by the device 100 into the header data. According to one embodiment, for the second insertion of the synchronization sequence into the synchronization header, the second value of the multiplication factor may be, for example, half of the first value of the multiplication factor used for the first insertion of the synchronization sequence into the header data. In one embodiment, the first value of the multiplication factor may be, for example, two, and the second value of the multiplication factor may be, for example, one.

[0020] According to one embodiment, the apparatus 100 may be configured to generate the sync header such that the sync header includes a predefined field therein to indicate, for example, that the sync header has a predefined length. In one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes an information field having a predefined length, the information field including the additional information, for example. According to one embodiment, the apparatus 100 may be configured to generate the data stream such that, for example, a synchronization header of the data stream precedes the payload data of the data stream within the data stream. In one embodiment, the apparatus 100 may be configured to generate the data stream such that, for example, the payload data is binary encoded.

[0021] According to one embodiment, the apparatus 100 may be configured to generate the data stream such that, for example, the payload data is multi-level coded. In one embodiment, the apparatus 100 may be configured to generate the synchronization header, for example, such that the synchronization header has a predefined length. According to one embodiment, the apparatus 100 may be configured to generate the synchronization header such that the synchronization header includes two or more predefined header fields, for example. In one embodiment, the apparatus 100 may be configured to generate the data stream using, for example, pulse amplitude modulation. According to one embodiment, the apparatus 100 may be configured to, for example, transmit a data stream to a receiver. In one embodiment, the apparatus 100 may be configured to transmit a data stream over a shared medium, for example. According to one embodiment, the device 100 may be suitable for use in, for example, an automotive environment or an aerospace environment.

[0022] FIG. 2 illustrates an apparatus 200 for receiving a data stream according to one embodiment. The data stream includes header data and payload data. The header data includes a synchronization header. The synchronization header is binary encoded and includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits. According to one embodiment, the synchronization sequence may include, for example, several bits, and the total number of transitions from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value in the synchronization sequence may be, for example, 35% or more of the number of bits in the synchronization sequence. In one embodiment, the total number of transitions in the synchronization sequence may be, for example, 50% or more of the number of bits in the synchronization sequence. According to one embodiment, the synchronization header may include, for example, a pseudo-random binary sequence.

[0023] In one embodiment, the synchronization sequence may include, for example, a first number of bits. a first total number of transitions from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value in the synchronization sequence; First number of bits against The first ratio is, for example, a second total number of transitions from the first bit value to the second bit value and from the second bit value to the first bit value in a pseudorandom binary sequence including the second number of bits; Second number of bits against Second Ratio It can be larger than

[0024] According to one embodiment, the apparatus 200 may be configured to synchronize clock timing using, for example, a synchronization sequence of a synchronization header of a data stream, and to acquire payload data of the data stream using, for example, the clock timing. In one embodiment, the apparatus 200 may be configured to synchronize the phase of the sampling clock (sampling phase), for example, using a synchronization sequence in a synchronization header of the data stream to synchronize clock timing. According to one embodiment, the synchronization header comprises a pseudo-random binary sequence. In one embodiment, the pseudo-random binary sequence may be different from the synchronization sequence, for example. According to one embodiment, the pseudo-random binary sequence may include, for example, a number of bits, and the total number of transitions in the pseudo-random binary sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is greater than or equal to 15% of the number of bits in the pseudo-random binary sequence.

[0025] In one embodiment, the total number of transitions in the pseudorandom binary sequence may be, for example, 30% or more of the number of bits in the pseudorandom binary sequence. According to one embodiment, the synchronization header may include, for example, two or three times each of two or more bits of a pseudorandom binary sequence. In one embodiment, the synchronization header may include, for example, the synchronization sequence at least twice, eg, the synchronization header may include, for example, the synchronization sequence at least twice. According to one embodiment, the synchronization header may, for example, include the synchronization sequence more than twice. In one embodiment, the synchronization header may include a synchronization sequence, for example, at the beginning of the synchronization header, and the synchronization header may include a synchronization sequence, for example, at the end of the synchronization header. According to one embodiment, the synchronization header may, for example, include the synchronization sequence twice concatenated at the beginning of the synchronization header and twice concatenated at the end of the synchronization header. In one embodiment, for example, the second occurrence of the synchronization sequence may occur immediately after the first occurrence of the synchronization sequence in the synchronization header.

[0026] According to one embodiment, the synchronization sequence may be, for example, a first synchronization sequence. The apparatus 100 may be configured to generate the header data such that the header data includes the first synchronization sequence and a second synchronization sequence, the second synchronization sequence being different from the first synchronization sequence. In one embodiment, the apparatus 100 may be configured to generate the synchronization header, for example, such that the synchronization header includes a first synchronization sequence and a second synchronization sequence. According to one embodiment, the synchronization header may include a number of bits such that, for example, the total number of transitions in the synchronization header from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value may be, for example, 15% or more of the number of bits in the synchronization header.

[0027] In one embodiment, the total number of transitions in the sync header may be, for example, 30% or more of the number of bits in the sync header. According to one embodiment, the synchronization header may include, for example, a predefined short code. In one embodiment, the predefined short codes may be, for example, 8B10B and 4B5B. According to one embodiment, the synchronization header may include, for example, a first version of the synchronization sequence, the first version including two or three times each bit of the initial sequence.

[0028] In one embodiment, the synchronization header may further include, for example, a second version of the synchronization sequence, which may, for example, be equal to the initial sequence. According to one embodiment, for example, a first version of the synchronization sequence may precede a second version of the synchronization sequence in the header data. In one embodiment, the sync header may include a predefined field therein to indicate, for example, that the sync header has a predefined length. According to one embodiment, the synchronization header may include, for example, an information field having a predefined length, the information field including additional information. In one embodiment, a synchronization header for a data stream may, for example, precede the payload data of the data stream within the data stream.

[0029] According to one embodiment, the payload data may be, for example, binary encoded. In one embodiment, the payload data may be, for example, multi-level encoded. According to one embodiment, the synchronization header may, for example, have a predefined length. In one embodiment, the synchronization header may include, for example, two or more predefined header fields. According to one embodiment, the data stream may be, for example, pulse amplitude modulation encoded. In one embodiment, the apparatus 200 may be configured to receive a data stream from, for example, a transmitter. According to one embodiment, the device 200 may be configured to receive a data stream, for example, over a shared medium. In one embodiment, the device 200 may be suitable for use in an automotive environment or an aerospace environment, for example. According to one embodiment, the device 200 may be configured to recover clock timing using a synchronization header, for example, when the device 200 begins receiving a data stream. In one embodiment, the apparatus 200 may be configured to recover clock timing using, for example, a synchronization header.

[0030] According to one embodiment, the device 200 may be configured to track the frequency of the clock timing, for example, during reception of the data stream. In one embodiment, the apparatus 200 may be configured to detect the beginning of payload data in a data stream using, for example, a synchronization sequence. According to one embodiment, the apparatus 200 may be configured to center the sampling clock in the symbol period using, for example, a synchronization header. In one embodiment, the apparatus 200 may be configured to recover clock timing using, for example, a pseudo-random binary sequence. According to one embodiment, the apparatus 200 may be configured to identify synchronization sequences in a data stream, for example, by using correlation.

[0031] FIG. 3 illustrates a system according to one embodiment. The system comprises an apparatus 100 for generating a data stream and an apparatus 200 for receiving a data stream. The apparatus 100 for generating a data stream is configured to generate a data stream such that the data stream includes header data and payload data. Moreover, the apparatus 100 for generating a data stream is configured to generate header data such that the header data includes a synchronization header. Furthermore, the apparatus 100 for generating a data stream is configured to generate the synchronization header using binary coding, and the apparatus 100 for generating a data stream is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence that is a predefined bit sequence including a plurality of bits. The apparatus 200 for receiving a data stream is configured to synchronize clock timing using a synchronization sequence of a synchronization header of the data stream, and further configured to obtain payload data of the data stream using the clock timing.

[0032] In the following, further embodiments of the present invention are provided. Some of the embodiments relate to data communication systems with bursty transmissions, which, as already outlined, means that over time there are quiet gaps during which no data is transmitted, followed by data bursts during which a payload is transported. In this mode, the receiver will recover timing at the beginning of the data burst. This is usually the phase of the sampling clock whose frequency is tracked / recovered during the entire data burst. For this purpose, the data burst is preceded by a synchronization header (also called sync header for short). In one embodiment, the quiet gap is for power conservation purposes, the state of the data communication link, and / or a shared medium, such as, for example, half-duplex data communication (via cable, directional RF link, optical fiber, etc.).

[0033] According to one embodiment, the transition from the quiet gap to the payload in the data burst will occur fast for bandwidth and power efficiency since this transition stage does not carry payload data and does not save power. In one embodiment, each data burst is preceded by a synchronization or resynchronization header (sync header). This synchronization header is used for robust symbol position detection so that the beginning of the payload is known and the data can be correctly decoded. In the following, when referring to a synchronization header, it should be understood that the synchronization header may in particular be, for example, a resynchronization header.

[0034] The synchronization header may also be used by the receiver for clock (phase) recovery, for example, to center the sampling clock when the payload starts to achieve a target signal-to-noise ratio. At the same time, the synchronization header may have properties that limit / avoid emissions due to repeated identical sequences, for example, which is especially important for cycles of data bursts and quiet gaps with fixed period timing. The payload may be implemented, for example, by any kind of coding (binary or multi-level), while the synchronization header may be implemented using binary coding, for example, for more robustness in detection and clear symbol transitions for fast-locking CDR (clock and data recovery). In one embodiment, the sync header may, for example, be of a fixed length in principle, with one optional exception, discussed below: the sync header may be constructed from several fields, for example, at least five or six.

[0035] In an alternative embodiment, an alternative description is that there is a base pattern into which at least two separate patterns (called synchronization sequences, or sync sequences for short) are inserted (replacing portions of the base pattern). The synchronization sequence may be inserted, for example, more than twice, which effectively creates a synchronization header with more than five or six fields.

[0036] According to one embodiment, the base pattern can be used, for example, for phase recovery. Therefore, it should have a sufficiently high transition density to allow the CDR to quickly correct larger offsets. Patterns such as simple 1-0 alternations or code words from short codes such as 8B10B and 4B5B provide this property. However, the regular nature of these patterns also leads to peaks / tones in the spectrum. A class of patterns with edge density (same symbol running length) statistically distributed between 1 and some maximum value are PRBS (pseudo-random binary sequences), which can be generated by a linear feedback shift register (LFSR). The order of the PRBS is preferably one with many symbol transitions (short same-symbol run lengths) to enable faster CDR lock. At the same time, the PRBS must be sufficiently different from the synchronization sequence so that correlation of the synchronization sequence (distorted by the channel) with the synchronization header does not result in false positives. Such a PRBS order is, for example, in the range of 10-19. In one embodiment, the synchronization sequence may be a defined bit sequence that can be conveniently found, for example, by correlation.

[0037] FIG. 4 shows an example of a synchronization sequence represented by −1 and +1 values ​​(PAM representation) according to one embodiment. FIG. 5 shows the synchronization sequence of FIG. 4, where the synchronization sequence is represented by 0 and 1 values ​​(0 / 1 representation). In one embodiment, the values ​​may, for example, already be mapped to PAM2 signal levels (PAM2: Pulse Amplitude Modulation 2). A 0 / 1 sequence may, for example, be obtained by setting all "-1" values ​​to "0". Any circular permutation and any inversion of a circular permutation may, for example, result in a sequence of equivalent properties. Reversing the bit order of any of those permutations / inversions also maintains the equivalent properties. The exact length of the sequence is quadratic. However, this sequence has the important property of being robust in detection in combination with a base PRBS of order 10 or higher. In the concatenation of these sequences, even inversions of the synchronization sequence (inverted receiver input) can be easily found and therefore corrected. To detect PRBS inversions, an approximation of the perfect PRBS sequence is searched for by correlation.

[0038] According to one embodiment, a synchronization sequence may be inserted into the synchronization header, for example, at the beginning and end. This may be done, for example, with a single instance of a synchronization sequence or two or more concatenated synchronization sequences each time. In one embodiment, the synchronization sequence may be inserted multiple times (in time), for example at a defined distance, which may aid in detection robustness, since the distance of the correlation peaks may be evaluated. Alternatively, in another embodiment, for example, a longer synchronization sequence may be used, which has the drawback of increasing the hardware effort in the correlator in the receiver. When the synchronization sequence is inserted, the base pattern PRBS may, for example, be stopped and started again, or may just continue running, for example, throughout the synchronization header, and may, for example, be masked while the synchronization sequence is inserted.

[0039] According to one embodiment, the first insertion of the synchronization sequence can be performed by, for example, doubling or tripling each bit / symbol (or repeating it more frequently). Repeating the symbol improves detection robustness, since the receiver automatically obtains two or more samples from the same repeated symbol, and can also be used for coarse phase correction. This allows for additional filtering and data processing to suppress noise and disturbances from the channel. In one embodiment, the PRBS around the first insertion can be maintained without symbol repetition, or can be inserted with repeated symbols as well. The symbol repetition in the synchronization sequence can exceed the symbol repetition in the PRBS by a small amount, since a significantly extended synchronization sequence would result in false positive correlations with the PRBS.

[0040] In one embodiment, the second (or final) insertion of the synchronization sequence may not involve symbol repetition, for example, so that correlation can provide the correct bit position and enable consistent decoding of the payload data. According to one embodiment, the position of the synchronization sequence within the header may be dithered, for example to reduce / avoid peaks in the transmitter spectrum (power spectral density), which is important for electromagnetic susceptibility applications such as automotive and aerospace. Dithering means shifting the position of the synchronization sequence by an integer number of symbols, for example inserting it in the synchronization header earlier or later with respect to the undithered "0 position," relative to the start of the payload data after the synchronization header. In one embodiment, the dithering source can be, for example, a defined waveform (triangle, sine, rectangular, sawtooth...) or can be, for example, a pseudo-random signal such as a PRBS. According to one embodiment, for example, a clocked digital waveform with a repeatable result can be used. According to one embodiment, at each synchronization header, the dithering source may be evaluated, for example, for a new position, which may then be used, for example, to insert synchronization sequence(s) for those "0 positions."

[0041] In one embodiment, for example, there may be a multiplication factor for the position obtained by the dithering source, which may be different for example for the first insertion of the synchronization sequence and the second (or last) insertion of the synchronization sequence. For example, in one embodiment, the first insertion of a synchronization sequence with twice the bits / symbols may be shifted, e.g., by a factor of 2, and the second (or last) insertion may be shifted, e.g., by a factor of 1 (or more generally, by an integer ratio factor, which may be, e.g., 1 / 2 the value of the first synchronization sequence coefficient). This means that the distance of the correlator peak from the first synchronization sequence to the second / last synchronization sequence is different from the distance from one data burst to the next (and is unique for each different position value obtained from the dithering source). This property may be useful for identifying which synchronization header (or data burst) within the period of the dithering source is currently being evaluated. At the first insertion of the synchronization sequence, it is not important that the synchronization sequence be preceded by a field of PRBS. In one embodiment, this snippet of PRBS may not be transmitted, for example. This results in a synchronization header whose length varies with each evaluation of the dithering source. If the first field is transmitted, the length of the synchronization header may always be the same, for example, regardless of the dithering state. This may be advantageous for CDR lock. According to one embodiment, the synchronization header may be appended with a fixed length information field that may be used, for example, to transport data other than the data burst payload.

[0042] FIG. 6 shows a version of the sync header in which the first insertion and the surrounding PRBS have double the bits, according to one embodiment. FIG. 7 shows a version of the sync header in which the first insertion has double the bits, according to another embodiment. FIG. 8 shows a version of the sync header in accordance with a further embodiment, where every insertion only has a single bit but the entire sequence is repeated.

[0043] While some aspects have been described in the context of an apparatus, it will be apparent that these aspects also represent a description of a corresponding method, with blocks or devices corresponding to method steps or features of method steps. Similarly, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be performed by (or using) a hardware apparatus, such as, for example, a microprocessor, a programmable computer, or electronic circuitry. In some embodiments, one or more of the most important method steps may be performed by such an apparatus. Depending on specific implementation requirements, embodiments of the present invention may be implemented in hardware or software, or at least partially in hardware or at least partially in software. Implementation may be performed using a digital storage medium, such as a floppy disk, DVD, Blu-ray, CD, ROM, PROM, EPROM, EEPROM, or flash memory, that stores electronically readable control signals, which cooperate (or can cooperate) with a programmable computer system to perform the respective methods. Thus, the digital storage medium may be computer-readable.

[0044] Some embodiments according to the present invention include a data carrier having electronically readable control signals that can cooperate with a programmable computer system to perform one of the methods described herein. Generally, embodiments of the present invention may be implemented as a computer program product having program code operable to perform one of the methods when the computer program product runs on a computer. The program code may, for example, be stored on a machine-readable carrier. Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier. In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein when the computer program runs on a computer.

[0045] A further embodiment of the inventive method is therefore a data carrier (or digital storage medium or computer-readable medium) having recorded thereon a computer program for performing one of the methods described herein. The data carrier, digital storage medium or recording medium is typically tangible and / or non-transitory. A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein, The data stream or the sequence of signals can for example be adapted to be transmitted via a data communication connection, for example via the Internet. A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein. A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.

[0046] Further embodiments according to the invention include an apparatus or system configured to transfer (e.g., electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may be, for example, a computer, a mobile device, a memory device, etc. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver. In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functions of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware apparatus.

[0047] The devices described herein may be implemented using a hardware device, or using a computer, or using a combination of a hardware device and a computer. The methods described herein may be performed using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer. The above-described embodiments are merely illustrative of the principles of the present invention. It is to be understood that modifications and variations of the arrangements and details described herein will be apparent to those skilled in the art. It is therefore intended to be limited only by the scope of the claims which immediately follow, and not by the specific details presented by way of description and illustration of the embodiments herein.

Claims

1. An apparatus (100) for generating a data stream, comprising: the apparatus (100) is configured to generate the data stream such that the data stream includes header data and payload data; The apparatus (100) is configured to generate the header data such that the header data includes a synchronization header; The apparatus (100) is configured to generate the synchronization header using binary coding; the apparatus (100) is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, the synchronization sequence being a predefined bit sequence including a plurality of bits; the apparatus (100) is configured to generate the synchronization header such that the synchronization header comprises a pseudo-random binary sequence; the apparatus (100) is configured to insert two or three times each of two or more bits of the pseudo-random binary sequence into the synchronization header; Apparatus (100).

2. The apparatus (100) is configured to generate the synchronization sequence including a number of bits such that a total number of transitions in the synchronization sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 35% of the number of bits in the synchronization sequence or equal to or greater than 50% of the number of bits in the synchronization sequence. The apparatus (100) of claim 1.

3. The apparatus (100) according to claim 2, wherein the synchronization sequence includes a first number of bits. a first total number of transitions from a first bit value to a second bit value different from the first bit value and transitions from the second bit value to the first bit value in the synchronization sequence; said first number of bits against The first ratio is: a second total number of transitions from the first bit value to the second bit value and from the second bit value to the first bit value in the pseudo-random binary sequence comprising a second number of bits; said second number of bits against Second Ratio configured to generate a signal greater than 3. The apparatus (100) of claim 1 or 2.

4. The apparatus (100) configured to generate the pseudo-random binary sequence by using a linear feedback shift register.

4. The apparatus (100) according to any one of claims 1 to 3.

5. The apparatus (100) is configured to generate the pseudo-random binary sequence such that the pseudo-random binary sequence is different from the synchronization sequence, and / or the apparatus (100) is configured to generate the pseudo-random binary sequence only in part by starting with a defined seed value and running through a predefined number of shifts before resetting to the seed value; and / or the device (100) is configured to generate the pseudo-random binary sequence including a number of bits such that the total number of transitions in the pseudo-random binary sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 15% of the number of bits in the pseudo-random binary sequence; and / or The apparatus (100) is configured to generate the pseudorandom binary sequence such that the total number of transitions in the pseudorandom binary sequence is equal to or greater than 30% of the number of bits in the pseudorandom binary sequence. An apparatus (100) according to any one of claims 1 to 4.

6. The pseudo-random binary sequence is a selected pseudo-random binary sequence, and the apparatus (100) is configured to generate an initial pseudo-random binary sequence and select a portion of the initial pseudo-random binary sequence that is smaller than the initial pseudo-random binary sequence as the selected pseudo-random binary sequence; and / or the device (100) is configured to assign bits of the pseudo-random binary sequence to bit positions of the synchronization header, and the device (100) is configured to insert bits of the synchronization sequence into the synchronization header, but not to insert the bits of the pseudo-random binary sequence into the synchronization header. The apparatus (100) according to any one of claims 1 to 5.

7. the device (100) is configured to stop using bits of the pseudo-random binary sequence when the device (100) inserts bits of the synchronization sequence into the synchronization header; the device (100) is configured to continue inserting a next bit of the pseudo-random binary sequence into the synchronization header after the device (100) has inserted the bit of the synchronization sequence into the synchronization header. The apparatus (100) according to any one of claims 1 to 6.

8. The device (100), wherein the synchronization header has the following characteristics: - said synchronization header contains said synchronization sequence at least twice, - said synchronization header contains said synchronization sequence more than twice, the synchronization header includes the synchronization sequence at the beginning of the synchronization header and the synchronization header includes the synchronization sequence at the end of the synchronization header; the synchronization header contains the synchronization sequence twice concatenated at the beginning of the synchronization header and twice concatenated at the end of the synchronization header, the first occurrence of said synchronization sequence in said synchronization header is immediately followed by a second occurrence of said synchronization sequence; the synchronization sequence is a first synchronization sequence, the header data comprises the first synchronization sequence and a second synchronization sequence, and the second synchronization sequence is different from the first synchronization sequence; configured to generate the synchronization header to indicate at least one of: An apparatus (100) according to any one of claims 1 to 7.

9. The device (100), wherein the synchronization header has the following characteristics: the synchronization header comprises a number of bits such that the total number of transitions in the synchronization header from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 15% of the number of bits in the synchronization header, - the sync header is greater than or equal to 30% of the number of bits in the sync header, - the synchronization header includes a predefined short code, - the synchronization header includes predefined short codes, and the predefined short codes are 8B10B and 4B5B; - the synchronization header includes a predefined field in the synchronization header to indicate that the synchronization header has a predefined length, - the synchronization header comprises an information field having a predefined length, the information field comprising additional information; - the synchronization header comprises a predefined length, - the synchronization header comprises two or more predefined header fields, configured to generate the synchronization header to indicate at least one of: An apparatus (100) according to any one of claims 1 to 8.

10. The apparatus (100) configured to generate a first version of the synchronization sequence by doubling or tripling each bit of an initial sequence; the apparatus (100) is configured to generate the header data such that the synchronization header includes the first version of the synchronization sequence. The apparatus (100) according to any one of claims 1 to 9.

11. The apparatus (100) configured to generate the header data such that the synchronization header further includes a second version of the synchronization sequence, the second version of the synchronization sequence being equal to the initial sequence. The apparatus (100) of claim 10.

12. The device (100) is configured to generate the header data such that the synchronization header further includes a second version of the synchronization sequence, the second version of the synchronization sequence is equal to the initial sequence, and the first version of the synchronization sequence precedes the second version of the synchronization sequence in the header data. The apparatus (100) of claim 10.

13. the device (100) is configured to derive the synchronization sequence from the initial sequence by changing the position of bits in the initial sequence; 13. Apparatus (100) according to claim 10 or 12.

14. the device (100) is configured to change the positions of the bits of the initial sequence according to a defined waveform; 14. The apparatus (100) of claim 13.

15. The following conditions: The defined waveform comprises a triangular shape or is a sinusoidal wave, or comprises a rectangular shape or comprises a sawtooth shape, or the apparatus (100) is configured to use a clocked digital waveform to change the positions of the bits of the initial sequence; At least one of the following is satisfied:

15. The apparatus (100) of claim 14.

16. the device (100) is configured to change the positions of the bits of the initial sequence in response to a pseudo-random signal; and / or the device (100) is configured to change the positions of the bits of the initial sequence according to a multiplication factor, the multiplication factor depending on how many times the synchronization sequence has already been inserted by the device into the header data; and / or the device (100) is configured to change the positions of the bits of the initial sequence according to a multiplication factor, the multiplication factor depending on how many times the synchronization sequence has already been inserted by the device into the header data, and wherein for a second insertion of the synchronization sequence into the synchronization header, the second value of the multiplication factor is half of the first value of the multiplication factor used for the first insertion of the synchronization sequence into the header data; and / or the device (100) is configured to change the positions of the bits of the initial sequence according to a multiplication factor, the multiplication factor depending on how many times the synchronization sequence has already been inserted by the device into the header data, and for a second insertion of the synchronization sequence into the synchronization header, the second value of the multiplication factor is half of the first value of the multiplication factor used for the first insertion of the synchronization sequence into the header data, the first value of the multiplication factor being 2 and the second value of the multiplication factor being 1.

14. The apparatus (100) of claim 13.

17. the apparatus (100) is configured to generate the data stream such that the synchronization header of the data stream precedes the payload data of the data stream within the data stream, or the apparatus (100) is configured to generate the data stream such that the payload data is binary encoded, or the apparatus (100) is configured to generate the data stream such that the payload data is multi-level coded; or the apparatus (100) is configured to generate the data stream using pulse amplitude modulation; 17. The apparatus (100) of any one of claims 1 to 16.

18. The device (100) has the following characteristics: - said device (100) is configured to transmit said data stream to a receiver; said device (100) is adapted to transmit said data stream over a shared medium; Indicate at least one of 18. The apparatus (100) of any one of claims 1 to 17.

19. The device (100) is suitable for use in an automotive or aerospace environment.

19. The apparatus (100) of any one of claims 1 to 18.

20. An apparatus (200) for receiving a data stream, comprising: the data stream includes header data and payload data, the header data includes a synchronization header, the synchronization header is binary encoded, and the synchronization header includes a synchronization sequence that is a predefined bit sequence including a plurality of bits; the apparatus (200) is configured to obtain the payload data of the data stream using the synchronization sequence of the synchronization header of the data stream; the synchronization header includes a first version of the synchronization sequence, the first version including two or three times each bit of the initial sequence; Device (200).

21. the synchronization sequence comprises a number of bits, the total number of transitions in the synchronization sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 35% of the number of bits in the synchronization sequence, or equal to or greater than 50% of the number of bits in the synchronization sequence; 21. The apparatus (200) of claim 20.

22. the synchronization header comprises a pseudo-random binary sequence; 22. Apparatus (200) according to claim 20 or 21.

23. the synchronization sequence includes a first number of bits; a first total number of transitions from a first bit value to a second bit value different from the first bit value and transitions from the second bit value to the first bit value in the synchronization sequence; said first number of bits against The first ratio is: a second total number of transitions from the first bit value to the second bit value and from the second bit value to the first bit value in the pseudo-random binary sequence comprising a second number of bits; said second number of bits against Second Ratio greater than 23. The apparatus (200) of claim 22.

24. the pseudo-random binary sequence is different from the synchronization sequence; the pseudo-random binary sequence includes a number of bits, and the total number of transitions in the pseudo-random binary sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 15% of the number of bits in the pseudo-random binary sequence; or the pseudorandom binary sequence includes a number of bits, and the total number of transitions in the pseudorandom binary sequence from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 15% of the number of the bits in the pseudorandom binary sequence, or the total number of transitions in the pseudorandom binary sequence is equal to or greater than 30% of the number of the bits in the pseudorandom binary sequence; 24. Apparatus (200) according to claim 22 or 23.

25. The synchronization header having the following characteristics: - said synchronization header contains said synchronization sequence at least twice, the synchronization header includes the synchronization sequence at the beginning of the synchronization header and the synchronization header includes the synchronization sequence at the end of the synchronization header; the synchronization header contains the synchronization sequence twice concatenated at the beginning of the synchronization header and twice concatenated at the end of the synchronization header, the first occurrence of said synchronization sequence in said synchronization header is immediately followed by a second occurrence of said synchronization sequence; the synchronization sequence is a first synchronization sequence, the header data comprises the first synchronization sequence and a second synchronization sequence, and the second synchronization sequence is different from the first synchronization sequence; the synchronization header comprises a first version of the synchronization sequence, the first version comprising two or three times each bit of an initial sequence, the synchronization header further comprising a second version of the synchronization sequence, the second version of the synchronization sequence being equal to the initial sequence; the synchronization header comprises a first version of the synchronization sequence, the first version comprising two or three times each bit of an initial sequence, the synchronization header further comprising a second version of the synchronization sequence, the second version of the synchronization sequence being equal to the initial sequence, and the first version of the synchronization sequence precedes the second version of the synchronization sequence in the header data; Indicate at least one of 25. Apparatus (200) according to any one of claims 20 to 24.

26. The synchronization header has the following characteristics: the synchronization header comprises a number of bits such that the total number of transitions in the synchronization header from a first bit value to a second bit value different from the first bit value and from the second bit value to the first bit value is equal to or greater than 15% of the number of bits in the synchronization header; the total number of transitions in the sync header is greater than or equal to 30% of the number of bits in the sync header, - the synchronization header includes a predefined short code, - the synchronization header includes predefined short codes, and the predefined short codes are 8B10B and 4B5B; - the synchronization header contains a first version of the synchronization sequence, the first version containing two or three times each bit of the initial sequence, - the sync header includes a predefined field therein to indicate that the sync header includes a predefined length; - the synchronization header includes an information field with a predefined length, the information field including additional information, the synchronization header of the data stream precedes the payload data of the data stream within the data stream; - said synchronization header has a predefined length, - the synchronization header comprises two or more predefined header fields, Indicate at least one of 26. Apparatus (200) according to any one of claims 20 to 25.

27. The payload data has the following characteristics: - the payload data is binary encoded, - said payload data is multi-level coded; Indicate at least one of 27. Apparatus (200) according to any one of claims 20 to 26.

28. The method of claim 27, wherein the data stream is pulse amplitude modulation encoded.

28. Apparatus (200) according to any one of claims 20 to 27.

29. The device (200) according to claim 29, wherein the device (200) has the following characteristics: - said device (200) is adapted to receive said data stream from a transmitter; said device (200) is adapted to receive said data stream via a shared medium; Show at least one of 29. Apparatus (200) according to any one of claims 20 to 28.

30. The apparatus (200) is suitable for use in an automotive or aerospace environment.

30. Apparatus (200) according to any one of claims 20 to 29.

31. The apparatus (200) is configured to synchronize clock timing using the synchronization sequence of the synchronization header of the data stream, and the apparatus is configured to obtain the payload data of the data stream using the clock timing.

31. Apparatus (200) according to any one of claims 20 to 30.

32. The apparatus (200) is configured to synchronize the phase of a sampling clock using the synchronization sequence of the synchronization header of the data stream to synchronize the clock timing; or the device (200) is configured to recover the clock timing using the synchronization header when the device begins receiving the data stream; 32. The apparatus (200) of claim 31.

33. The apparatus (200) is configured to recover the clock timing using the synchronization header; or the device (200) is configured to track the frequency of the clock timing during reception of the data stream; 32. The apparatus (200) of claim 31.

34. The apparatus (200) configured to recover the clock timing using the pseudo-random binary sequence.

34. Apparatus (200) according to claim 32 or 33.

35. The apparatus (200) configured to detect the beginning of the payload data of the data stream using the synchronization sequence.

35. Apparatus (200) according to any one of claims 20 to 34.

36. The apparatus (200) configured to center the sampling clock at a symbol period using the synchronization header.

33. The apparatus (200) of claim 32.

37. the apparatus (200) is configured to identify the synchronization sequence in the data stream by using correlation; 37. Apparatus (200) according to any one of claims 20 to 36.

38. An apparatus (100) according to any one of claims 1 to 19 for generating a data stream; an apparatus (200) according to any one of claims 20 to 37 for receiving said data stream; Equipped with The apparatus (100) of any one of claims 1 to 19 is configured to generate the data stream such that the data stream comprises header data and payload data, The apparatus (100) of any one of claims 1 to 19 is configured to generate the header data such that the header data includes a synchronization header; The device (100) of any one of claims 1 to 19, configured to generate the synchronization header using binary coding, The apparatus (100) of any one of claims 1 to 19 is configured to generate the synchronization header such that the synchronization header includes a synchronization sequence, the synchronization sequence being a predefined bit sequence including a plurality of bits; 38. A system, comprising: an apparatus (200) according to any one of claims 20 to 37, configured to obtain the payload data of the data stream using the synchronization sequence of the synchronization header of the data stream.

39. 1. A method for generating a data stream, comprising: generating the data stream such that the data stream includes header data and payload data; Including, generating the header data such that the header data includes a synchronization header; generating the synchronization header using binary coding; generating the synchronization header is performed such that the synchronization header includes a synchronization sequence, the synchronization sequence being a predefined bit sequence including a plurality of bits; the method includes generating a first version of the synchronization sequence by doubling or tripling each bit of an initial sequence; the method includes generating the header data such that the synchronization header includes the first version of the synchronization sequence; method.

40. 1. A method for receiving a data stream, comprising: the data stream includes header data and payload data, the header data includes a synchronization header, the synchronization header is binary encoded, and the synchronization header includes a synchronization sequence that is a predefined bit sequence including a plurality of bits; The method includes obtaining the payload data of the data stream using the synchronization sequence of the synchronization header of the data stream; the synchronization header includes a pseudo-random binary sequence; the synchronization header includes two or three times each of two or more bits of the pseudo-random binary sequence; A method comprising:

41. 41. A computer program for performing the method according to claim 39 or 40 when the computer program is run on a computer or signal processor.

42. A data stream including header data and payload data, the header data includes a synchronization header; the synchronization header is binary encoded; the synchronization header includes a synchronization sequence, which is a predefined bit sequence including a plurality of bits; the synchronization header includes a pseudo-random binary sequence; the synchronization header includes two or three times each of two or more bits of the pseudo-random binary sequence; Data stream.

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