Gate driver and display device including the same

Abstract

To provide a transparent display device which minimizes visual difference between a display area and a non-display area felt by a user.SOLUTION: A gate driver according to an embodiment of the present invention comprises a plurality of circuit parts spaced apart from each other, each having a circuit element disposed thereon, and a plurality of transparent parts disposed between the circuit parts and configured to allow external light to pass therethrough, where each of the plurality of circuit parts includes at least one circuit block for performing an identical function.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a gate driver and a display device including the same, and more particularly to a gate driver having a transparent portion and a display device including the same. [Background technology]

[0002] An OLED display displays images using organic light-emitting diodes (OLEDs), which generate light by recombining electrons and holes. OLEDs are self-emitting display devices, and are gaining attention as next-generation displays due to their fast response speed and low power consumption.

[0003] An organic light-emitting display device can be formed as a transparent display device by configuring transistors and light-emitting elements inside the device in a transparent form and separating a circuit region from a transmissive region. However, conventional transparent display devices have non-display regions such as bezels, which can reduce the visual perception of a transparent image. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-038964 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a transparent display device that reduces the visual discomfort between a display area and a non-display area. [Means for solving the problem]

[0006] According to one embodiment, the gate driver includes a plurality of circuit sections in which circuit elements are arranged and spaced apart from each other, and a plurality of transparent sections arranged between the circuit sections and transmitting external light, and each of the plurality of circuit sections may include at least one circuit block performing the same function.

[0007] The plurality of circuit sections may include a first extension section extending in a first direction and in which circuit elements are arranged, and a second extension section extending in a second direction perpendicular to the first direction and in which second wiring connecting the circuit sections is arranged.

[0008] The width of the first extension portion in the second direction may be greater than the width of the second extension portion in the first direction.

[0009] The circuit unit may further include a plurality of first wirings for applying global signals to each of the circuit units, and the global signals may include at least one of a scan clock signal, a carry clock signal, a start signal, a reset signal, a sensing selection signal, a first power supply, a second power supply, and a third power supply.

[0010] The plurality of circuit units may include a first circuit unit that controls output of a second gate signal provided to the pixel for pixel sensing; a second circuit unit that sets a voltage of a Q node (or a first node) disposed in the gate driver; a third circuit unit that controls output of a carry signal provided to another stage disposed after the present stage; a fourth circuit unit that resets voltages of the Q node and a QB node (or a second node) disposed in the gate driver in response to the carry signal received from another stage disposed before the present stage; a fifth circuit unit that inverts and outputs signals applied to the Q node and the QB node; a sixth circuit unit that outputs a first gate signal of a gate-off voltage through at least one pull-down transistor that is turned on in response to the voltage of the QB node; and a seventh circuit unit that outputs the first gate signal of a gate-on voltage through at least one pull-up transistor that is turned on in response to the voltage of the Q node.

[0011] The first circuit unit may be disposed adjacent to one side edge of the gate driver.

[0012] The fourth circuit unit may be disposed adjacent to the third circuit unit that outputs the carry signal.

[0013] The sixth circuit unit and the seventh circuit unit may be disposed adjacent to the other side edge of the gate driver.

[0014] The seventh circuit section includes a plurality of sub-circuit sections arranged at a distance from each other, and the transparent section arranged between the sub-circuit sections, and the plurality of sub-circuit sections can include a first sub-circuit section each configured of a portion of the pull-up transistor, and a second sub-circuit section in which the first wiring that applies the scan clock signal to the pull-up transistor is arranged.

[0015] The first, second, third, fourth, fifth, sixth, and seventh circuit sections may be collectively referred to as "the first to seventh circuit sections."

[0016] At least some of the first to seventh circuit units may be configured to directly generate local signals required for the operation of the circuit units, and the local signals may include at least one of a Q node signal for controlling the turn-on and turn-off of the pull-up transistor, a QB node signal for controlling the turn-on and turn-off of the pull-down transistor, the carry signal CR, the first and second gate signals, and an M_o signal for charging and discharging the Q node and the QB node for pixel sensing.

[0017] The circuit unit includes a substrate, a circuit element layer (or first layer) disposed on the substrate and on which the circuit elements are disposed, a planarization layer (or second layer) covering the circuit elements disposed on the circuit element layer, a dummy reflective layer (or third layer) disposed on the planarization layer, and a sealing layer (or fourth layer) covering the dummy reflective layer, and the dummy reflective layer may be composed of a reflective electrode.

[0018] The circuit unit may further include a substrate, a circuit element layer disposed on the substrate and on which the circuit elements are disposed, a planarization layer covering the circuit elements disposed on the circuit element layer, a sealing layer formed on the planarization layer, a cover substrate disposed on top of the sealing layer, and a dummy color filter disposed between the sealing layer and the cover substrate, and the dummy color filter may be made of a photosensitive resin containing a colorant.

[0019] According to one embodiment, a display device includes a display panel including a display area in which pixels are arranged and a non-display area surrounding the display area; and a gate driver disposed in the non-display area and applying gate signals to the pixels via gate lines, wherein each of the display area and the non-display area may include circuit sections in which circuit elements are arranged and spaced apart from each other, and transparent sections disposed between the circuit sections and allowing external light to pass through.

[0020] The circuit portion may include a first extension portion extending in a first direction and in which circuit elements are arranged, and a second extension portion extending in a second direction perpendicular to the first direction and in which second wiring connecting the circuit portions is arranged, and the width of the first extension portion in the second direction may be greater than the width of the second extension portion in the first direction.

[0021] The gate driver may include a first circuit unit that controls output of a second gate signal provided to the pixel for pixel sensing; a second circuit unit that sets a voltage of a Q node disposed in the gate driver; a third circuit unit that controls output of a carry signal provided to another stage disposed after the current stage; a fourth circuit unit that resets voltages of the Q node and a QB node disposed in the gate driver in response to the carry signal received from another stage disposed before the current stage; a fifth circuit unit that inverts and outputs signals applied to the Q node and the QB node; a sixth circuit unit that outputs a first gate signal of a gate-off voltage through at least one pull-down transistor that is turned on in response to the voltage of the QB node; and a seventh circuit unit that outputs the first gate signal of a gate-on voltage through at least one pull-up transistor that is turned on in response to the voltage of the Q node.

[0022] The first circuit unit may be disposed adjacent to an edge of the display panel in the non-display area, and the sixth circuit unit and the seventh circuit unit may be disposed adjacent to the display area.

[0023] The fourth circuit unit may be disposed adjacent to the third circuit unit that outputs the carry signal.

[0024] The seventh circuit section includes a plurality of sub-circuit sections arranged at a distance from each other, and the transparent section arranged between the sub-circuit sections, and the plurality of sub-circuit sections can include a first sub-circuit section each configured of a portion of the pull-up transistor, and a second sub-circuit section in which the first wiring that applies the scan clock signal to the pull-up transistor is arranged.

[0025] The circuit unit in the display area includes a substrate, a circuit element layer disposed on the substrate and having the circuit elements disposed thereon, a planarization layer covering the circuit elements disposed on the circuit element layer, a light-emitting element layer disposed on the planarization layer and having light-emitting elements including an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode electrode and the cathode electrode, a sealing layer covering the light-emitting element layer, a cover substrate disposed on top of the sealing layer, and a color filter disposed between the sealing layer and the cover substrate. The circuit unit in the non-display area includes the substrate, the circuit element layer, the planarization layer, a dummy reflective layer disposed on the planarization layer, and the sealing layer covering the dummy reflective layer, and the dummy reflective layer may be made of the same material as the anode electrode.

[0026] The circuit unit in the display area includes a substrate, a circuit element layer disposed on the substrate and having the circuit elements disposed thereon, a planarization layer covering the circuit elements disposed on the circuit element layer, a light-emitting element layer disposed on the planarization layer and having light-emitting elements including an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode electrode and the cathode electrode, a sealing layer covering the light-emitting element layer, a cover substrate disposed on top of the sealing layer, and a color filter disposed between the sealing layer and the cover substrate. The circuit unit in the non-display area includes the substrate, the circuit element layer, the planarization layer, the sealing layer disposed on the planarization layer, the cover substrate disposed on top of the sealing layer, and a dummy color filter disposed between the sealing layer and the cover substrate, and the dummy color filter may be made of the same material as the color filter.

[0027] The pixels may include R, G, and B pixels, and the circuit unit of the gate driver may have the same size and shape as the R, G, and B pixels.

[0028] The transparent portion disposed in the display area and the transparent portion disposed in the non-display area may have substantially the same shape. [Effects of the Invention]

[0029] In the display device according to the embodiment, the gate driver arranged in the non-display area is configured with a circuit part and a transparent part, similar to the display area, thereby reducing the visual discomfort between the display area and the non-display area. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic perspective view of the display device shown in FIG. [Figure 3] FIG. 2 is a circuit diagram illustrating an embodiment of the pixel shown in FIG. [Figure 4] FIG. 2 is a diagram illustrating a gate driver shown in FIG. 1; [Figure 5] FIG. 5 is a circuit diagram for explaining the operation of the stage shown in FIG. [Figure 6] FIG. 3 is an enlarged view of the area indicated in FIG. 2 according to one embodiment. [Figure 7] 3 is an enlarged view of the area indicated in FIG. 2 according to another embodiment. [Figure 8] FIG. 8 is an enlarged view of the circuit shown in FIG. 7. [Figure 9] FIG. 9 is a block diagram schematically showing a circuit section that constitutes the stage shown in FIG. 8. [Figure 10] FIG. 2 is a diagram illustrating an example of a first pull-up transistor. [Figure 11] FIG. 1 is a cross-sectional view of one embodiment of a display area. [Figure 12] FIG. 10 is a cross-sectional view of one embodiment of a non-display area. [Figure 13] 13 is a plan view showing the arrangement of the dummy reflective patterns and dummy color filters shown in FIG. 12. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, when a component (or a region, layer, portion, etc.) is described as being "on," "connected," or "coupled" to another component, this means that the component may be directly connected / coupled to the other component, or a third component may be disposed between them.

[0032] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, proportions, and dimensions of the components are exaggerated for the effective explanation of the technical contents. "And / or" includes all one or more combinations that the related configurations can define.

[0033] Terms such as "first," "second," etc. may be used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one structural element from another. For example, a first component may be designated as a "second component," and similarly, a second component may be designated as a "first component," without departing from the scope of the present embodiment. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0034] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0035] Terms such as "comprise" or "have" are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof described herein, but should be understood as not precluding the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0036] FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment.

[0037] Referring to FIG. 1, a display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a power supply 40, and a display panel 50.

[0038] The timing controller 10 receives video signals RGB and control signals CS from the outside. The video signals RGB may include a plurality of gray scale data. The timing controller 10 processes the video signals RGB and control signals CS to conform to the operating conditions of the display panel 50, and generates and outputs video data DATA, gate driving control signals CONT1, data driving control signals CONT2, and power supply control signals CONT3.

[0039] The gate driver 20 may be connected to the pixels PX of the display panel 50 via a plurality of first gate lines GL11 to GL1n. The gate driver 20 may generate gate signals based on the gate drive control signal CONT1 output from the timing controller 10, and provide the generated gate signals to the pixels PX via the plurality of first gate lines GL11 to GL1n.

[0040] In various embodiments, the gate driver 20 may be further connected to the pixels PX of the display panel 50 via a plurality of second gate lines GL21 to GL2n. The gate driver 20 may provide sensing signals to the pixels PX via the plurality of second gate lines GL21 to GL2n.

[0041] The data driver 30 may be connected to the pixels PX of the display panel 50 via a plurality of data lines DL1 to DLm. The data driver 30 may generate data signals based on the image data DATA and the data drive control signal CONT2 output from the timing controller 10, and provide the data signals to the pixels PX via the plurality of data lines DL1 to DLm.

[0042] In various embodiments, the data driver 30 may be further connected to the pixels PX of the display panel 50 via a plurality of sensing lines (or reference lines) SL1 to SLm. The data driver 30 may provide a reference voltage (or sensing voltage, initialization voltage) to the pixels PX via the plurality of sensing lines SL1 to SLm, or may sense the state of the pixels PX based on an electrical signal fed back from the pixels PX.

[0043] The power supply unit 40 may be connected to the pixels PX of the display panel 50 via a plurality of power lines PL1 and PL2. The power supply unit 40 may generate driving voltages (e.g., a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS) to be provided to the display panel 50 based on a power supply control signal CONT3, and provide the driving voltages ELVDD and ELVSS to the pixels PX via the corresponding power lines PL1 and PL2.

[0044] A plurality of pixels PX (also called sub-pixels) are arranged on the display panel 50. The pixels PX may be arranged, for example, in a matrix on the display panel 50. The pixels PX may emit light at a brightness corresponding to gate signals and data signals supplied via the first gate lines GL11 to GL1n and the data lines DL1 to DLm. Each pixel PX may display any one of red, green, blue, and white.

[0045] FIG. 2 is a schematic perspective view of the display device shown in FIG.

[0046] The display device 1 can be realized in various forms, for example, in the form of a rectangular plate.

[0047] The display panel 50 includes a display area AA and a non-display area NAA. The display area AA is an area where pixels PX are arranged, and is also called an active area. The non-display area NAA can be arranged around the display area AA.

[0048] The non-display area NAA may be provided with a driver for driving the pixel PX, such as a gate driver 20. The gate driver 20 may be formed in the non-display area NAA of the display panel 50 in a gate-in-panel manner, as shown in FIG.

[0049] A plurality of pads (not shown) may be provided in the non-display area NAA. The pads are not covered by an insulating layer and are exposed to the outside of the display panel 50, and may be electrically connected to the data driver 30, the circuit board 70, etc.

[0050] The flexible film 60 has one end attached to the pad area PA of the display panel 50 and the other end attached to the circuit board 70, thereby electrically connecting the display panel 50 and the circuit board 70. The flexible film 60 may include a plurality of wirings for electrically connecting the pads formed in the pad area PA to the wirings of the circuit board 70.

[0051] The circuit board 70 may be a printed circuit board or a flexible printed circuit board, and may include the timing control unit 10 and the power supply unit 40 implemented in the form of an integrated circuit.

[0052] Fig. 3 is a circuit diagram showing an embodiment of the pixel shown in Fig. 1. Fig. 3 shows, as an example, a pixel PXij connected to the ith gate lines GL1i and GL2i and the jth data line DLj.

[0053] Referring to FIG. 3, the pixel PX includes a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light emitting element LD.

[0054] A first electrode (e.g., drain electrode) of the switching transistor ST is electrically connected to the j-th data line DLj, and a second electrode (e.g., source electrode) is electrically connected to the first node N1. A gate electrode of the switching transistor ST is electrically connected to the i-th first gate line GL1i. When a gate signal of a gate-on level is applied to the i-th first gate line GL1i, the switching transistor ST is turned on and transfers a data signal applied to the j-th data line DLj to the first node N1.

[0055] A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst is connected to the first electrode of the light emitting element LD. The storage capacitor Cst can store a voltage corresponding to the difference between the voltage applied to the first node N1 and the voltage applied to the first electrode of the light emitting element LD.

[0056] A first electrode (e.g., drain electrode) of the driving transistor DT is configured to receive a high-potential driving voltage ELVDD, and a second electrode (e.g., source electrode) is electrically connected to a first electrode (e.g., anode electrode) of the light-emitting element LD. A gate electrode of the driving transistor DT is electrically connected to a first node N1. The driving transistor DT is turned on when a gate-on level voltage is applied via the first node N1, and can control the amount of driving current flowing through the light-emitting element LD in response to the voltage provided to the gate electrode.

[0057] A first electrode (e.g., drain electrode) of the sensing transistor SST is electrically connected to the j-th sensing line SLj, and a second electrode (e.g., source electrode) is electrically connected to a first electrode (e.g., anode electrode) of the light emitting element LD. A gate electrode of the sensing transistor SST is electrically connected to the i-th second gate line GL2i. The sensing transistor SST is turned on when a sensing signal of a gate-on level is applied to the i-th second gate line GL2i, and transmits a reference voltage applied to the j-th sensing line SLj to the first electrode of the light emitting element LD.

[0058] The light emitting element LD outputs light corresponding to a driving current. The light emitting element LD can output light corresponding to any one of red, green, blue, and white. The light emitting element LD can be an organic light emitting diode (OLED).

[0059] FIG. 4 is a diagram illustrating a gate driver shown in FIG. 1, and FIG. 5 is a circuit diagram illustrating the operation of the stage shown in FIG.

[0060] 4, the gate driver 20 includes a plurality of stages ST1 to STn. The stages ST1 to STn include a plurality of input terminals for respectively receiving a scan clock signal SCLK, a carry clock signal CCLK, a start signal Vst / previous stage carry signal CR, a reset signal Rst, a sensing selection signal LSP, a first power supply Vdd, a second power supply Vdd_even / Vdd_odd, and a third power supply Vss, which are applied as global signals to the gate driver 20. The stages ST1 to STn also include a plurality of output terminals connected to one of the first gate lines GL11 to GL1n and one of the second gate lines GL21 to GL2n. The stages ST1 to STn can supply first gate signals GS11 to GS1n to the first gate lines GL11 to GL1n and second gate signals GS21 to GS2n to the second gate lines GL21 to GL2n in response to the input global signals and local signals generated within the stages ST1 to STn.

[0061] Stages ST1 to STn are supplied with a scan clock signal SCLK and a carry clock signal CCLK. Although the scan clock signal SCLK and the carry clock signal CCLK are shown as a single signal, each may be composed of multiple clock signals. For example, the scan clock signal SCLK may be composed of the first to ith scan clock signals, and the carry clock signal CCLK may be composed of the first to ith carry clock signals.

[0062] The scan clock signal SCLK and the carry clock signal CCLK may be square wave signals that alternate between high and low voltages. The high voltage may be higher than the low voltage. The high voltage period corresponds to the width of the gate signal and may be variously set depending on the circuit structure and driving method of the pixel PX.

[0063] In various embodiments, the scan clock signal SCLK may be set to a signal having the same period but with a phase shifted. For example, the first through i-th scan clock signals may be signals whose phase is shifted by 1 / i period from the previous scan clock signal. Similarly, the carry clock signal CCLK may be set to a signal having the same period but with a phase shifted. For example, the first through i-th carry clock signals may be signals whose phase is shifted by 1 / i period from the previous carry clock signal. In various embodiments, the carry clock signals CCLK may be signals synchronized with the corresponding carry clock signals SCLK. However, this embodiment is not limited thereto.

[0064] 5, each stage ST includes pull-up transistors Tup1, Tup2, and Tup3 and a control circuit CC for controlling the operating states of the pull-up transistors Tup1, Tup2, and Tup3. The gate of the first pull-up transistor Tup1 is connected to a Q node Q and is turned on when the Q node Q is set to a gate-on voltage, thereby outputting a scan clock signal SCLK of a gate-on level to the first gate line G11 to G1n as a first gate signal GS1. The gate of the second pull-up transistor Tup2 is connected to the Q node Q and is turned on when the Q node Q is set to a gate-on voltage, thereby outputting a scan clock signal SCLK of a gate-on level to the second gate line G21 to G2n as a second gate signal GS2. The third pull-up transistor Tup3 is turned on in response to a voltage applied to its gate and is capable of outputting a carry clock signal CCLK of a gate-on level as a carry signal CR.

[0065] Stages ST1 to STn can receive a start signal Vst or a carry signal CR output from a previous stage. The start signal Vst is input to the input terminal of the first stage ST1, and the carry signal CR from the previous stage can be input to stages other than the first stage ST1. Here, the carry signal CR can be a carry signal CR output from any one of the stages arranged before the stage. By supplying the start signal Vst or the carry signal CR from the previous stage at a gate-on level to stages ST1 to STn, the generation and output timing of first gate signals GS11 to GS1n and GS21 to GS2n can be controlled.

[0066] The stages ST1 to STn may be supplied with a reset signal Rst. The reset signal Rst is supplied to the stages ST1 to STn during a reset period within one frame to initialize the voltages of the Q node Q and the QB node QB shown in FIG. 5. In one embodiment, the Q node Q may be charged and the QB node QB may be discharged by the reset signal Rst. In one embodiment, the reset period may be included in a vertical blanking period within one frame, and in particular, may be arranged after the sensing period.

[0067] The stages ST1 to STn may receive a sensing selection signal LSP. The sensing selection signal LSP is a signal for controlling the output of the second gate signals GS21 to GS2n during a sensing period within one frame. Only the stage that receives the sensing selection signal LSP at a gate-on level may be controlled to output the second gate signals GS21 to GS2n during the sensing period. During the sensing period, the mobility and threshold voltage of the driving transistor DT and the current characteristics of the light emitting element LD may be sensed for the pixels PX to which the second gate signals GS21 to GS2n are applied. In one embodiment, the sensing period may be included in a vertical blanking period within one frame.

[0068] The first power supply Vdd is a voltage applied to charge the Q node Q and may be electrically connected to the Q node Q. The first power supply Vdd may be set to a gate-on level sufficient to turn on the pull-up transistors Tup1, Tup2, and Tup3 connected to the Q node Q.

[0069] The second power supply Vdd_even / Vdd_odd is a voltage applied to charge the QB node QB and may be electrically connected to the QB node QB. The second power supply Vdd_even / Vdd_odd may be set to a gate-on level sufficient to turn on the pull-down transistors Tdown1, Tdown2, and Tdown3 connected to the QB node QB.

[0070] The third power supply Vss may be a voltage for grounding the stages ST1 to STn and generating gate signals GS11 to GS1n, GS21 to GS2n of gate-off level and a carry signal CR.

[0071] 5, stages ST1 to STn include pull-down transistors Tdown1, Tdown2, and Tdown3 and a control circuit CC for controlling the operating states of the pull-down transistors Tdown1, Tdown2, and Tdown3. The gate of the first pull-down transistor Tdown1 is connected to a QB node QB and is turned on when the QB node QB is set to a gate-on voltage, thereby outputting a third power supply Vss at a gate-off level as a first gate signal to the first gate lines G11 to G1n. The gate of the second pull-down transistor Tdown2 is connected to a QB node QB and is turned on when the QB node QB is set to a gate-on voltage, thereby outputting a third power supply Vss at a gate-off level as a second gate signal to the second gate lines G21 to G2n. The third pull-down transistor Tdown3 is turned on in response to a voltage applied to its gate and is capable of outputting a third power supply Vss at a gate-off level as a carry signal CR.

[0072] 4 and 5, the stages ST1 to ST1n are all shown connected to a single third power supply Vss. However, this embodiment is not limited thereto, and the stages ST1 to ST1n may be connected to multiple low-potential power supplies. For example, in consideration of the characteristics of the circuit elements constituting the gate driver 20 and the circuit elements constituting the pixels PX, and the power consumption of the display device 1, the first and second pull-down transistors Tdown1 and Tdown2 and the third pull-down transistor Tdown3 may be connected to different low-potential power supplies.

[0073] Meanwhile, in various embodiments, the stages ST1 to STn shown in Figure 5 may be configured with a plurality of circuit units spaced apart from one another. Specific embodiments of the stages will be described below.

[0074] Figure 6 is an enlarged view of an embodiment of area A1 shown in Figure 2. Figure 7 is an enlarged view of another embodiment of area A1 shown in Figure 2.

[0075] 6 and 7, a display panel 50 according to an embodiment includes a display area AA and a non-display area NAA. The display area AA and the non-display area NAA each include a circuit portion CA and a transparent portion TA. The transparent portion TA and the circuit portion CA are adjacent to each other and can be disposed continuously without any physical separation. The region in which the circuit portion CA is located is also referred to as the circuit area CA, which is the area in which the circuit is located. The circuit itself can be disposed on a different layer and therefore can be disposed in the X, Y, and / or Z planes. This will be explained in more detail using FIGS. 11 and 12. The extension of the circuit area in the X and Y planes is the circuit area, which can be considered the area occupied by the circuit portion CA. Similarly, the region in which the transparent portion TA is located is the area occupied by the transparent portion.

[0076] The circuit portion CA and the transparent portion TA in the display area AA and the non-display area NAA can have approximately the same size and shape and can be arranged in the same manner, so that the display area AA and the non-display area NAA have the same visual impression, and the display device 1 can effectively function as a transparent display device.

[0077] Here, "same" includes deviations that take into account process margins. For example, in the display area AA and non-display area NAA, the circuit portion CA and the transparent portion TA may have size variations (process margins) of up to several μm on one side. For example, one side of the transparent portion TA in the non-display area NAA may be arranged to be larger or smaller to the left / right, above / below than one side of the transparent portion TA in the display area AA within a range of 5 μm. Furthermore, one side of the circuit portion CA in the non-display area NAA may be arranged to be larger or smaller to the left / right, above / below than one side of the circuit portion CA in the display area AA within a range of 5 μm. The same applies to the following embodiments.

[0078] The circuit section CA in the display area AA may include at least one circuit element constituting a pixel PX, a light-emitting element connected to the circuit element, and wiring connecting these elements. In one embodiment, one unit pixel PXU may be arranged in one circuit section CA. The unit pixel PXU may be composed of all or some of pixels PX that respectively emit red, green, blue, and white light. In one embodiment, unit pixels PXU with different color combinations may be arranged in the circuit section CA.

[0079] The circuit unit CA in the non-display area NAA may include circuit elements for driving the pixels PX. For example, the circuit unit CA in the non-display area NAA may include circuit elements constituting the gate driver 20. As described above, the circuit units CA in the display area AA and the non-display area NAA have generally similar sizes and shapes. In general, the gate driver constituting the gate driver 20 includes more circuit elements than the unit pixels PXU and has a larger area. Therefore, to form the circuit units CA in the display area AA and the non-display area NAA with generally the same size and shape, one stage ST may be implemented across multiple circuit units CA. In this case, the circuit units CA may be spaced apart from each other with a transparent portion TA sandwiched between them.

[0080] In the embodiment of FIG. 6, the circuit portion CA has a rectangular shape. That is, the circuit area is rectangular. The shape of the circuit portion here refers to the shape of the circuit area, also referred to as the circuit region area. Similarly, the shape of the transparent portion described herein refers to the shape of the transparent area. In FIG. 6 and other plan views, the X dimension refers to the horizontal, i.e., left-to-right direction, and the Y dimension refers to the vertical, i.e., top-to-bottom direction. These are the two dimensions that make up the area and can also be thought of as the footprint of the circuit portion CA. As shown in FIGS. 11 and 12, the Z dimension exists within the page. In the embodiment of FIG. 7, the area covered by the circuit portion CA has a cross or pinwheel shape. In these embodiments, the red, green, blue, and white pixels R, G, B, and W can be sequentially arranged from top to bottom, as exemplarily shown in one unit pixel PXU of FIG. 6. Alternatively, the red, green, blue, and white pixels R, G, B, and W can be arranged as exemplarily shown in one unit pixel PXU of FIG. 7, but this embodiment is not limited thereto.

[0081] In addition, in this embodiment, the shape of the circuit portion CA and the arrangement of the pixels PX arranged in the circuit portion CA may be modified in various ways. Hereinafter, the embodiment will be described using a display panel 50 in which the circuit portion CA has a cross or pinwheel shape as an example.

[0082] The transparent portion TA is the remaining area other than the circuit portion CA, where the circuit elements and light-emitting elements described above are not arranged. The transparent portion TA has light-transmitting properties and may be formed transparent or translucent to transmit incident light. Therefore, a transparent or translucent material may be used for the layer laminated on the transparent portion TA. Since the display area AA includes the circuit portion CA and the transparent portion TA, the display panel 50 is realized as a transparent display device that not only displays images but also allows a background image on the opposite side of the display panel 50 to be seen.

[0083] Fig. 8 is an enlarged view of the circuit portion shown in Fig. 7. The circuit portion CA shown in Fig. 8 may be the circuit portion CA arranged in the display area AA or the non-display area NAA.

[0084] 8, the circuit portion CA according to one embodiment may have a cross shape. Specifically, the circuit portion CA may include a first extension portion A extending in a first direction DR1 and a second extension portion B extending in a second direction DR2 substantially perpendicular to the first direction DR1 and overlapping the first extension portion A. An overlapping portion C is formed in the area where the first extension portion A and the second extension portion B overlap. The first direction DR1 may be considered the Y direction, and the second direction DR2 may be considered the X direction.

[0085] Circuit elements constituting at least one pixel PX may be arranged in the first extension portion A in the display area AA. The circuit elements may include transistors and capacitors. Wiring for connecting the circuit elements to each other and applying signals to the circuit elements may be arranged in the second extension portion B in the display area AA. Generally, wiring occupies a smaller area than the circuit elements, so the width W1 of the first extension portion A is greater than the width W2 of the second extension portion B. By arranging circuit elements with a larger area in the first extension portion A and wiring with a smaller area in the second extension portion B, the area of ​​the transparent portion TA around the circuit portion CA is further increased, thereby improving the transparency of the display panel 50.

[0086] Circuit elements constituting a part of the stage ST may be arranged in the first extension portion A in the non-display area NAA. In this case, circuit elements that perform the same function among the circuit elements constituting the stage ST may be arranged in one first extension portion A to form a circuit block. A plurality of circuit blocks may be arranged in one first extension portion A.

[0087] In the first extension portion A in the non-display area NAA, first wiring for applying global signals to the stage ST may be further arranged. The global signals have more types and number than the local signals described below, and it is advantageous for the global signals to be applied independently to each of the circuit units CA arranged in the non-display area NAA. Therefore, since the first wiring for applying the global signals is numerous, it is arranged in the first extension portion A, which has a relatively large area.

[0088] Second wiring for transmitting and receiving local signals between the circuit units CA may be disposed in the second extension unit B in the non-display area NAA. The local signals are signals generated in each circuit block and may include a Q node signal for controlling the turn-on / turn-off of the pull-up transistors Tup1, Tup2, and Tup3, a QB node signal for controlling the turn-on / turn-off of the pull-down transistors Tdown1, Tdown2, and Tdown3, first and second gate signals, a carry signal CR, and an M_o signal for charging / discharging the Q node Q and the QB node QB for pixel sensing, as shown in FIG. 5. The local signals may be transmitted to another distant circuit block via the second wiring disposed in the second extension unit B or output to the outside of the stage ST.

[0089] Local signals generally have fewer numbers and types than global signals. Therefore, by arranging the first wiring for global signals in the first extension portion A and the second wiring for local signals in the second extension portion B, the width W2 of the second extension portion B can be configured to be narrower than the width W1 of the first extension portion A.

[0090] In this way, the area ratio between the first extension A and the second extension B in the display area AA is configured to be approximately the same as the area ratio between the first extension A and the second extension B in the non-display area NAA, thereby allowing the display area AA and the non-display area NAA to have substantially the same visual appearance.

[0091] In the overlapping portion C, a first wiring extending from the first extension portion A in the first direction DR1 and a second wiring extending from the second extension portion B in the second direction DR2 can overlap each other. At this time, by disposing at least one insulating layer between the first wiring and the second wiring, the first wiring and the second wiring can be insulated from each other. Alternatively, the first wiring and the second wiring can be electrically connected via a contact hole formed in the overlapping portion C.

[0092] Figure 9 is a block diagram showing a circuit portion constituting the stage shown in Figure 8. Figure 10 is a diagram showing an example of a first pull-up transistor.

[0093] 9 and 10, in one embodiment, one stage ST can be realized across multiple circuit units CA1 to CA7. Each circuit unit CA can include first to fourteenth circuit blocks, which are a collection of circuit elements performing the same or similar functions. By arranging circuit blocks performing similar functions within one circuit unit CA, the number of second wirings connecting distant circuit units CA can be reduced. To reduce the number of second wirings, each circuit unit CA can be configured to directly generate a local signal useful for the operation of the circuit unit CA. In various embodiments, the number of second wirings connecting distant circuit units CA can be three or four, but this embodiment is not limited thereto.

[0094] The first circuit unit CA1 can control the output of second gate signals GS21 to GS2n for pixel sensing. For example, the first circuit unit CA1 can output the second gate signals GS21 to GS2n to the second gate lines GL21 to GL2n during a sensing period within one frame.

[0095] In one embodiment, the first circuit unit CA1 may include a first circuit block that generates an M_o signal for charging / discharging the Q node Q during pixel sensing, a second circuit block that resets the QB node QB during pixel sensing, and a third circuit block that charges the Q node Q during pixel sensing. The first circuit block may output the M_o signal in response to a sensing selection signal LSP and a carry signal CR from a previous stage. The second circuit block may set the QB node QB to a gate-off voltage in response to the M_o signal output from the first circuit block, the carry signal CR from the previous stage, and a reset signal Rst. The third circuit block may set the Q node Q to a gate-on voltage in response to the reset signal Rst.

[0096] In one embodiment, the first circuit unit CA1 may be disposed at one side edge of the stage ST, for example, at the outermost periphery of the non-display area NAA, in order to reduce electrical influences from voltage fluctuations that occur during operation of the gate driver 20. By being disposed at the outermost periphery, it may be easier to form a capacitor within the first circuit unit CA1.

[0097] The second circuit unit CA2 sets the voltage of the Q node Q. The output of the gate signals GS21 to GS2n can be controlled by the voltage setting of the Q node Q by the second circuit unit CA2. The second circuit unit CA2 can include a fourth circuit block that charges the Q node Q of the stage ST to which the gate signals GS21 to GS2n are output. The fourth circuit block can set the Q node Q to a gate-on voltage or a gate-off voltage in response to a carry signal CR of the previous stage.

[0098] The third circuit unit CA3 may control the output of the carry signal CR. In one embodiment, the third circuit unit CA3 may include a fifth circuit block that controls the turn-on / turn-off of the third pull-up transistor Tup3 and a sixth circuit block that controls the turn-on / turn-off of the third pull-down transistor Tdown3.

[0099] The fifth circuit block controls the turning on / off of the third pull-up transistor Tup3 in response to the carry clock signal CCLK, and when the third pull-up transistor Tup3 is turned on, a carry signal of the gate-on voltage is output.

[0100] The sixth circuit block controls the turn-on / turn-off of the third pull-down transistor Tdown3 based on the second power supply Vdd_even / Vdd_odd, and when the third pull-down transistor Tdown3 is turned on, a carry signal of the gate-off voltage can be output.

[0101] The fourth circuit unit CA4 can reset the voltages of the Q node Q and the QB node QB. During the vertical blanking period of one frame, the fourth circuit unit CA4 can reset the Q node Q to a gate-off voltage and the QB node QB to a gate-on voltage.

[0102] In one embodiment, the fourth circuit unit CA4 may include seventh and eighth circuit blocks that reset the voltage of the Q node Q, and ninth and tenth circuit blocks that reset the voltage of the QB node QB.

[0103] The seventh and eighth circuit blocks can reset the Q node Q to the gate-off voltage using the second power supply Vdd_even / Vdd_odd and the third power supply Vss based on the carry signal of the previous stage, and the ninth and tenth circuit blocks can reset the QB node QB to the gate-on voltage using the second power supply Vdd_even / Vdd_odd and the third power supply Vss.

[0104] In one embodiment, the fourth circuit unit CA4 receives the carry signal from the previous stage and may be disposed adjacent to the third circuit unit CA3 that outputs the carry signal CR. While the fourth circuit unit CA4 is shown disposed to the right of the third circuit unit CA3 in FIG. 9, the fourth circuit unit CA4 may also be disposed to the left of the third circuit unit CA3. By arranging the third circuit unit CA3 that outputs the carry signal CR and the fourth circuit unit CA4 that operates in response to the carry signal CR output from the third circuit unit CA3 adjacent to each other in this manner, the number and length of the second wiring can be reduced.

[0105] The fifth circuit unit CA5 can perform an inverter operation. The fifth circuit unit CA5 can include an eleventh circuit block that outputs signals that invert the voltages of the Q node Q and the QB node QB. The fifth circuit unit CA5 can be disposed adjacent to any other circuit unit that sets / resets the voltages of the Q node Q and the QB node QB, except for the first circuit unit CA1. That is, the fifth circuit unit CA5 can be disposed at any position between the first circuit unit CA1 and the sixth circuit unit CA6. Although FIG. 9 illustrates the fifth circuit unit CA5 as being disposed between the fourth circuit unit CA4 and the sixth circuit unit CA6, this embodiment is not limited thereto, and the fifth circuit unit CA5 can be disposed relatively freely.

[0106] The sixth circuit unit CA6 may include twelfth and thirteenth circuit blocks, each including at least one first pull-down transistor Tdown1, which may output first gate signals GS11 to GS1n and GS21 to GS2n of gate-off voltage to the first gate lines GL11 to GL1n in response to the voltage of the QB node QB.

[0107] The seventh circuit unit CA7 may include a fourteenth circuit block, which may include at least one first pull-up transistor Tup1 and output first gate signals GS11 to GS1n, GS21 to GS2n of gate-on voltage to the first gate lines GL11 to GL1n in response to the voltage of the Q node Q.

[0108] Generally, the first pull-up transistor Tup1 has the largest area among the transistors constituting the gate driver 20 and may therefore be configured with multiple sub-circuits. For example, as shown in FIG. 10, the first pull-up transistor Tup1 may be configured with multiple seventh sub-circuits CA7-1 and CA7-2. Each of the multiple seventh sub-circuits CA7-1 and CA7-2 may be configured with a portion of the first pull-up transistor Tup1. Because the first pull-up transistor Tup1 is connected to the scan clock signal SCLK, when the first pull-up transistor Tup1 is configured with multiple seventh sub-circuits CA7-1 and CA7-2, the length of the wiring that applies the scan clock signal SCLK to the first pull-up transistor Tup1 may be increased. As the wiring length increases, the area of ​​the second extension B shown in FIG. 8 increases, which may reduce the transparency of the display panel 50 and increase the visual difference between the display area AA and the non-display area NAA. To prevent this problem, eighth sub-circuit units CA8-1 and CA8-2, each consisting only of a scan clock signal line, may be disposed adjacent to the seventh sub-circuit units CA7-1 and CA7-2 constituting the first pull-up transistor Tup1. The seventh sub-circuit units CA7-1 and CA7-2 constituting the first pull-up transistor Tup1 and the eighth sub-circuit units CA8-1 and CA8-2, each consisting only of a scan clock signal line SCLK, may be disposed alternately along the second direction DR2. This structure ensures a sufficient circuit area for the first pull-up transistor Tup1, reduces the impedance of the scan clock signal line SCLK, and prevents an increase in the area of ​​the second extension portion B, thereby ensuring the transparency of the display panel 50.

[0109] To shorten the length of the first gate lines GL11-GL1n extending inside the gate driver 20, the other side edges of the gate driver, for example, the sixth circuit unit CA6 and the seventh circuit unit CA7, may be arranged closest to the display area AA. For example, the sixth circuit unit CA6 and the seventh circuit unit CA7 may both be arranged closer to the display area AA than the first, second, third, fourth, and fifth circuit units CA1-CA5. The seventh circuit unit CA7 may be arranged directly adjacent to the display area AA, or the sixth circuit unit CA6 may be arranged adjacent to the display area AA (for example, across the seventh circuit unit CA7).

[0110] 9 shows an example in which the gate driver 20 is configured with seven circuit units CA1 to CA7. However, this embodiment is not limited to this, and the gate driver 20 may be configured with more or less than seven circuit units. Furthermore, each of the circuit units CA1 to CA7 may be configured with more or less circuit blocks than shown.

[0111] 11 is a cross-sectional view showing a circuit portion CA and a transparent portion TA in a display area according to one embodiment. Referring to FIG. 11, in the display area AA, the display panel 50 includes a circuit portion CA and a transparent portion TA. Pixels PX are arranged in the circuit portion CA, and the transparent portion TA is made up of only a transparent insulating layer, allowing incident light to pass through.

[0112] The portions constituting the circuit unit itself can be arranged on any layer, and therefore can be three-dimensional. FIG. 11 extends the Z dimension vertically and the X dimension horizontally. The circuit unit CA can include, for example, a substrate 100, a circuit element layer CEL arranged on the substrate 100, and a light-emitting element layer LDL. The top view of FIG. 11 can be as shown in FIGS. 6, 7, and 8.

[0113] At least one transistor, capacitor, and wiring may be arranged on the circuit element layer CEL as circuit elements that constitute the pixel PX. These various circuit elements together constitute the circuit section CA. A transparent insulating layer may be arranged between the electrodes that constitute the circuit elements, thereby electrically insulating the electrodes from each other. The circuit elements may be covered with a passivation layer and / or an overcoat layer to protect them from foreign matter. Furthermore, the unevenness on the top surface of the circuit elements may be covered with an overcoat layer (planarization layer), thereby preventing diffuse reflection of external light due to the unevenness.

[0114] Light-emitting elements are arranged in the light-emitting element layer LDL. The light-emitting elements include an anode electrode, a light-emitting layer, and a cathode electrode. These various circuit elements together constitute a circuit section CA. If the display panel 50 is a front-emitting type, the anode electrode can be a reflective electrode and the cathode electrode can be a transmissive electrode. However, if the display panel 50 is a rear-emitting type, the anode electrode can be a transmissive electrode and the cathode electrode can be a reflective electrode. In the following, an embodiment will be described taking the case where the display panel 50 is a front-emitting type as an example.

[0115] The circuit elements and the light emitting elements may be covered with an encapsulation layer PAC. The encapsulation layer PAC serves to prevent external moisture from penetrating into the circuit elements and the light emitting elements. The encapsulation layer PAC may be made of an inorganic insulator or may have a structure in which inorganic and organic insulators are alternately stacked, but is not limited thereto.

[0116] A cover substrate 200 may be formed on the encapsulation layer PAC. The cover substrate 200 may be attached onto the encapsulation layer PAC using an adhesive or the like.

[0117] A color filter CF may be further formed between the encapsulation layer PAC and the cover substrate 200. The color filter CF may be disposed overlapping the light emitting element. The CF and MB together constitute a circuit unit CA. The color filter CF is a wavelength-selective optical filter that transmits light of a specific wavelength band, blocks light of other specific wavelength bands, and selectively transmits a portion of the wavelength band of incident light. The color filter CF may be made of a photosensitive resin containing a colorant such as a pigment or dye. Light generated from the light emitting element and passing through the color filter CF may have any one of red, green, and blue. The color filter CF may be omitted for the pixel PX that displays white. A black matrix BM may be formed between the color filters CF to prevent light leakage between the light emitting regions.

[0118] FIG. 12 is a cross-sectional view of an embodiment of the non-display area, and FIG. 13 is a plan view showing the arrangement of the dummy reflective patterns and dummy color filters of FIG.

[0119] 12, in the non-display area NAA, the display panel 50 includes a circuit section CA and a transparent section TA. The circuit section CA includes the circuit blocks of the gate driver 20, while the transparent section TA includes only a transparent insulating layer and transmits incident light. In FIG. 12, elements that are part of the circuit section include CEL and ANO' as well as CF' and BM'.

[0120] In various embodiments, the non-display area NAA has a stacked structure generally similar to that of the display area AA. That is, circuit blocks disposed in the non-display area NAA may be formed with a stacked structure similar to that of the pixels PX. For example, the gate driver 20 does not emit light and therefore does not benefit from including a color filter CF and an anode electrode. However, to provide a visual similarity to the display area AA, it may include a dummy color filter CF' and a dummy reflective pattern ANO'. The dummy reflective pattern ANO' may be a dummy reflective layer or may include a dummy reflective layer ANO'. The dummy reflective pattern ANO' is also called a dummy anode electrode ANO'. The dummy anode electrode ANO' is similar to an anode electrode, but does not provide the electrical function of an anode electrode, and may instead provide the optical function (e.g., reflectivity) of an anode electrode. A specific structure will be described below with reference to a cross-sectional view of the gate driver 20.

[0121] The circuit section CA may include, for example, a substrate 100 and a circuit element layer CEL disposed on the substrate 100. At least one transistor, a capacitor, and wiring may be disposed in the circuit element layer CEL as circuit elements constituting a circuit block. The area where the circuit section is located may be considered a circuit area. A transparent insulating layer may be disposed between electrodes constituting the circuit elements to electrically insulate the electrodes. The circuit elements may be covered with a passivation layer and / or an overcoat layer to protect them from foreign matter. The overcoat layer is a planarizing layer that flattens the unevenness formed on the upper surface of the circuit elements, thereby preventing external light from being diffused by the unevenness of the circuit elements and changing the visual characteristics of the display area AA.

[0122] Dummy reflective patterns ANO' may be formed on the circuit element layer CEL. The dummy reflective patterns ANO' may be made of the same material as the anode electrodes disposed in the display area AA. For example, the dummy reflective patterns ANO' may be made of a reflective electrode. In one embodiment, the dummy reflective patterns ANO' may be made of a reflective layer, which may be made of a metal material such as aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof.

[0123] The planar arrangement of the dummy reflective pattern ANO' in the circuit section CA may correspond to the arrangement of the anode electrode in the pixel PX. The dummy reflective pattern ANO' may have the same or similar shape as the anode electrode, but is not limited to this. The dummy reflective pattern ANO' may be formed in the same process as the anode electrode, but is not limited to this.

[0124] In one embodiment, a specific DC power supply may be applied to the dummy reflective pattern ANO' to prevent interference due to coupling with surrounding elements. For example, the DC power supply may be, but is not limited to, a third power supply Vss. In another embodiment, no power supply may be applied to the dummy reflective pattern ANO', and the dummy reflective pattern ANO' may be left floating.

[0125] The dummy reflective pattern ANO' can reflect external light. The dummy reflective pattern ANO' allows the display area AA where the pixels PX are arranged and the non-display area NAA where the gate driver 20 are arranged to have approximately the same reflectance, thereby improving the visual similarity between them.

[0126] The dummy reflective pattern ANO' may be covered by a sealing layer PAC.

[0127] A cover substrate 200 may be formed on the encapsulation layer PAC. The cover substrate 200 may be attached onto the encapsulation layer PAC using an adhesive or the like.

[0128] Dummy color filters CF' may be further formed between the encapsulation layer PAC and the cover substrate 200. The dummy color filters CF' may be disposed overlapping the dummy reflective patterns ANO'. The dummy color filters CF' may be made of the same material as the color filters CF, for example, a photosensitive resin containing a colorant such as a pigment or dye. A black matrix BM' may be formed between the dummy color filters CF' to prevent light leakage between the light-emitting regions.

[0129] The planar arrangement of the dummy color filters CF' in the circuit section CA can correspond to the arrangement of the color filters CF in the pixels PX. For example, if red, green, blue, and white pixels PX are arranged in a cross shape in the display area AA, red, green, and blue dummy color filters CF' can also be arranged in a cross shape in the non-display area NAA. The dummy color filters CF' can be omitted at positions corresponding to the white pixels PX.

[0130] In addition, the dummy color filters CF′ may have the same or similar shape as the color filters CF, but are not limited thereto. The dummy color filters CF′ may be formed in the same single process as the color filters CF, but are not limited thereto.

[0131] Such a dummy color filter CF' allows the display area AA where the pixels PX are arranged and the non-display area NAA where the gate driver 20 is arranged to have roughly the same visual appearance, thereby improving the visual similarity between them.

[0132] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the technical configuration of the present invention described above can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. The scope of the present invention is defined by the claims set forth below, rather than the above detailed description. Furthermore, all modifications and variations derived from the meaning and scope of the claims and their equivalents should be construed as being within the scope of the present invention. [Explanation of symbols]

[0133] 1 Display panel 10 Timing control section 20 Gate driver 30 Data Drive Unit 40 Power supply section 50 Display Panel

Claims

1. A gate driver provided in a non-display area of ​​a display panel, the gate driver comprising: A plurality of stages are included which output gate signals to a plurality of gate lines, and each stage is a plurality of circuit sections each having a plurality of circuit elements disposed therein and spaced apart from one another; a plurality of transparent portions disposed between the circuit portions and transmitting external light; Including, the plurality of stages includes a first stage and a second stage; the first stage and the second stage include at least a first circuit portion and a second circuit portion, respectively; the first circuitry of the first stage and the first circuitry of the second stage perform the same function, and the second circuitry of the first stage and the second circuitry of the second stage perform the same function; each of the plurality of circuit portions includes at least one circuit block required to perform a predetermined function of each of the plurality of circuit portions; Each of the circuit units comprises: A substrate; a circuit element layer disposed on the substrate and on which the circuit elements are disposed; a planarization layer covering the circuit elements disposed on the circuit element layer; a dummy reflective layer disposed on the planarization layer; a sealing layer that covers the dummy reflective layer; Including, the dummy reflective layer is formed of a reflective electrode, the planarization layer and the sealing layer extend to a display region of the display panel, and a light-emitting element in a pixel of the display panel is configured between the planarization layer and the sealing layer; The dummy reflective layer includes the same material as an anode electrode of the light emitting element.

2. A gate driver provided in a non-display area of ​​a display panel, the gate driver comprising: A plurality of stages are included which output gate signals to a plurality of gate lines, and each stage is a plurality of circuit sections each having a plurality of circuit elements disposed therein and spaced apart from one another; a plurality of transparent portions disposed between the circuit portions and transmitting external light; Including, the plurality of stages includes a first stage and a second stage; the first stage and the second stage include at least a first circuit portion and a second circuit portion, respectively; the first circuitry of the first stage and the first circuitry of the second stage perform the same function, and the second circuitry of the first stage and the second circuitry of the second stage perform the same function; each of the plurality of circuit portions includes at least one circuit block required to perform a predetermined function of each of the plurality of circuit portions; Each of the circuit units comprises: A substrate; a circuit element layer disposed on the substrate and on which the circuit elements are disposed; a planarization layer covering the circuit elements disposed on the circuit element layer; a sealing layer formed on the planarization layer; a cover substrate disposed on the sealing layer; a dummy color filter disposed between the sealing layer and the cover substrate; further comprising the dummy color filter is made of a photosensitive resin containing a coloring agent, the sealing layer and the cover substrate extend to a display area of ​​the display panel, and a color filter for a pixel of the display panel is formed between the sealing layer and the cover substrate; The dummy color filter includes the same material as the color filter.

3. Each of the circuit units comprises: a first extension portion extending in a first direction and on which a circuit element is disposed; a second extension portion extending in a second direction perpendicular to the first direction and on which a second wiring connecting the circuit portions is disposed; 3. The gate driver of claim 1, comprising:

4. The gate driver of claim 3 , wherein the width of the first extension in the second direction is greater than the width of the second extension in the first direction.

5. further comprising a plurality of first wirings for applying a global signal to each of the circuit units; The global signal includes at least one of a scan clock signal, a carry clock signal, a start signal, a reset signal, a sensing selection signal, a first power supply, a second power supply, and a third power supply; The gate driver of claim 4 .

6. The plurality of circuit units include: the first circuit portion performing a function of controlling an output of a second gate signal provided to a pixel for pixel sensing; the second circuit unit performing a function of setting a voltage of a first node disposed in the gate driver; a third circuit portion for controlling the output of a carry signal provided to another stage disposed after the corresponding stage; a fourth circuit unit configured to reset voltages of the first node and a second node disposed in the gate driver in response to the carry signal received from another stage disposed before the corresponding stage; a fifth circuit unit that performs a function of inverting and outputting signals applied to the first node and the second node; a sixth circuit section for outputting a first gate signal of a gate-off voltage through at least one pull-down transistor that is turned on in response to the voltage of the second node; a seventh circuit unit that outputs the first gate signal of a gate-on voltage through at least one pull-up transistor that is turned on in response to the voltage of the first node; Including, The gate driver of claim 5 , wherein each of the plurality of transparent portions is disposed between two adjacent circuit portions among the first to seventh circuit portions.

7. The gate driver of claim 6 , wherein the first circuit unit is disposed adjacent to one side edge of the gate driver.

8. The gate driver of claim 6 , wherein the fourth circuit unit is disposed adjacent to the third circuit unit that outputs the carry signal.

9. The gate driver of claim 6 , wherein the sixth circuit unit and the seventh circuit unit are disposed adjacent to other side edges of the gate driver.

10. The seventh circuit unit is a plurality of sub-circuit portions arranged at a distance from one another; the transparent portion disposed between the sub-circuit portions; Including, The plurality of sub-circuit units include: first sub-circuit portions each comprising a portion of a pull-up transistor; a second sub-circuit section in which the first wiring for applying the scan clock signal to the pull-up transistor is arranged; 7. The gate driver of claim 6, comprising:

11. At least some of the first to seventh circuit units are configured to directly generate local signals necessary for the operation of the circuit units; The local signal is a first signal for controlling the turn-on and turn-off of the pull-up transistor; a second signal for controlling the turn-on and turn-off of the pull-down transistor; and the carry signal, the first and second gate signals, and a third signal for charging and discharging the first node and the second node for pixel sensing. The gate driver of claim 10 , comprising at least one of:

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