Stacked CMOS image sensor and its manufacturing method

Abstract

To provide a stacked complementary metal-oxide semiconductor (CMOS) image sensor having a high full well capacity (FWC).SOLUTION: In a circuit 100, a first integrated circuit (IC) chip 104a including a first semiconductor substrate and a second IC chip 104b including a second semiconductor substrate, are stacked to each other. A pixel sensor 102 spans the first IC chip and the second IC chip, and includes a transfer transistor 114 on the first semiconductor substrate, and a pinned photodiode 106 adjacent to the transfer transistor, and further includes a plurality of additional transistors (a reset transistor 116, a source-follower transistor 118, a select transitory 120) on the second semiconductor substrate. Bulk of the first semiconductor substrate and bulk of the second semiconductor substrate are electrically separated from each other and biased with different voltages (for example, a negative voltage, a ground).SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Integrated circuits (ICs) containing image sensors are used in a wide range of modern electronic devices, such as cameras and mobile phones. Types of image sensors include, for example, complementary metal-oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly preferred due to their low power consumption, small size, high-speed data processing, direct data output, and low manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0002] In CMOS image sensors, pixel sensors typically include a pinned photodiode, and pixel circuits include a transfer transistor, a reset transistor, and a source follower transistor. The semiconductor manufacturing industry continues to pursue miniaturization of CMOS image sensors to achieve low manufacturing costs, relatively high device integration densities, and other requirements. However, it is difficult to continue miniaturizing the transistors in the pixel circuit, and instead, the photodiode shrinks, potentially degrading the performance of the pixel sensor. For example, the full well capacity (FWC), which corresponds to the maximum charge a pixel can hold before saturation and is proportional to the size of the photodiode, decreases, potentially resulting in signal degradation. One approach to increasing the FWC to compensate for smaller pixel sizes is to increase the FD reset voltage and the turn-on voltage of the transfer transistor. The former increases the pinning voltage of the pinned photodiode, thereby increasing its FWC. However, this approach exposes the source follower transistor and reset transistor to relatively high voltages, potentially resulting in reliability issues for these two transistors. [Means for solving the problem]

[0003] In some exemplary embodiments, the present disclosure provides an image sensor including a first IC chip including a first semiconductor substrate, a second IC chip stacked on the first IC chip and including a second semiconductor substrate, and a pixel sensor spanning the first and second IC chips. The pixel sensor includes a first transistor and a light-receiving element in the first semiconductor substrate, and further includes a second transistor in the second semiconductor substrate. The bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other and configured to be biased at different voltages.

[0004] The present disclosure also provides, in some exemplary embodiments, an image sensor including a first substrate, a photodiode and a first transistor adjacent to each other on the first substrate, a second substrate below the first substrate, and a second transistor on the second substrate, wherein the photodiode and the first and second transistors form a pixel sensor, and the body of the first transistor and the anode of the photodiode are electrically coupled together and electrically isolated from the body of the second transistor.

[0005] The present disclosure also provides, in some exemplary embodiments, a method for forming an image sensor, the method including: forming a first IC chip including: forming a photodiode on a first semiconductor substrate; and forming a first transistor on the first semiconductor substrate adjacent to the photodiode, where the photodiode and the first transistor form a first pixel sensor portion; forming a second IC chip including: forming a plurality of second transistors on a second semiconductor substrate, where the second transistors form second pixel sensor portions; and bonding the first IC chip and the second IC chip together such that the first pixel sensor portion and the second pixel sensor portion are stacked and electrically coupled to each other, where the bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other upon completion of bonding. [Effects of the Invention]

[0006] Because the bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other and biased at different voltages, the bulk of the first semiconductor substrate can be biased at a negative voltage and the bulk of the second semiconductor substrate can be grounded (e.g., biased at zero voltage). As a result, the voltages of the photodiode and the first transistor, including the pinning voltage of the photodiode and the turn-on voltage of the first transistor, are relative to a negative voltage rather than ground. This has the effect of increasing these voltages by the magnitude of the negative voltage, which increases the forward current capacitance (FWC) of the photodiode. Also, because the voltage of the second transistor is relative to ground rather than a negative voltage, the second transistor is not subjected to the relatively high voltages experienced by the pinned photodiode and transfer transistor. As a result, the ruggedness and reliability of the second transistor are not affected. [Brief explanation of the drawings]

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features have not been drawn to scale. In fact, the dimensions of the various features shown in the accompanying drawings may be arbitrarily expanded or reduced for clarity of illustration. [Figure 1] FIG. 1 illustrates circuit diagrams of several embodiments of stacked complementary metal-oxide semiconductor (CMOS) image sensors with high full well capacity (FWC). [Figure 2] FIG. 2 depicts electrograms for some embodiments of the image sensor of FIG. [Figure 3] FIG. 3 depicts a schematic cross-sectional view of some embodiments of the image sensor of FIG. [Figure 4] FIG. 4 shows a circuit diagram of some embodiments of the image sensor of FIG. 1 in which the body diode of the reset transistor is shown. [Figure 5] 5A and 5B show circuit diagrams of several alternative embodiments of the image sensor of FIG. 1, with different components of the image sensor. [Figure 6]FIG. 6 shows circuit diagrams of several alternative embodiments of the image sensor of FIG. 1 in which the pixel sensor includes multiple sub-pixels. [Figure 7] FIG. 7 shows circuit diagrams of several alternative embodiments of the image sensor of FIG. 1 in which the pixel sensor includes auxiliary pixel circuitry. [Figure 8] FIG. 8 depicts circuit diagrams of several alternative embodiments of the image sensor of FIG. 1, in which the image sensor further includes a third IC chip. [Figure 9] FIG. 9 depicts a schematic cross-sectional view of some embodiments of the image sensor of FIG. [Figure 10] FIG. 10 shows circuit diagrams of some alternative embodiments of the image sensor of FIG. [Figure 11] FIG. 11 depicts a schematic cross-sectional view of several embodiments of image sensors, each including multiple pixel sensors such as those of FIG. [Figure 12] FIG. 12 depicts a top-down layout view of some embodiments of the image sensor of FIG. [Figure 13] FIG. 13 shows a schematic cross-sectional view of several embodiments of image sensors, each including multiple pixel sensors such as those of FIG. [Figure 14] FIG. 14 illustrates cross-sectional views of some embodiments of the image sensor of FIG. [Figure 15] 15A and 15B show cross-sectional views of several alternative embodiments of the image sensor of FIG. 14, in which the components of the image sensor differ. [Figure 16] 16 depicts cross-sectional views of some alternative embodiments of the image sensor of FIG. 14, in which the image sensor further includes a third IC chip. [Figure 17] FIG. 17 illustrates cross-sectional views of some embodiments of the image sensor of FIG. 14, where the image sensor has conductive pads on the periphery of the substrate. [Figure 18] FIG. 18 depicts cross-sectional views of some alternative embodiments of the image sensor of FIG. 17, in which the substrate has peripheral isolation. [Figure 19]FIG. 19 is a top-down layout view of some alternative embodiments of the image sensor of FIG. [Figure 20] 20A-20C show cross-sectional views of several alternative embodiments of the image sensor of FIG. [Figure 21] FIG. 21 illustrates a cross-sectional view of some embodiments of the image sensor of FIG. 18, where the image sensor includes a plurality of pixel sensors and a third IC chip. [Figure 22] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 23] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 24] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 25] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 26] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 27]22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 28] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 29] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 30] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 31] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 32] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 33] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 represent a series of diagrams of several embodiments of methods for forming stacked CMOS image sensors with high FWC. [Figure 34]FIG. 34 depicts block diagrams of some embodiments of the methods of FIGS. 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33. [Figure 35] 35-37 show cross-sectional views of several alternative embodiments of the operation described with respect to FIG. [Figure 36] 35-37 show cross-sectional views of several alternative embodiments of the operation described with respect to FIG. [Figure 37] 35-37 show cross-sectional views of several alternative embodiments of the operation described with respect to FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] The following embodiments provide many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact with each other, or may include an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact with each other. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for purposes of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations referenced.

[0009] Additionally, spatially relative terms such as "below," "lower," "bottom," "upper," "top," etc. may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] A stacked complementary metal-oxide semiconductor (CMOS) image sensor may include a first integrated circuit (IC) chip and a second IC chip stacked together. The first IC chip contains pixel sensors that are repeated in a grid pattern, and the second IC chip contains an application-specific integrated circuit (ASIC) electrically coupled to the pixel sensors at each repetition of the pixel sensors. The pixel sensors include a pinned photodiode and a pixel circuit localized on the first IC chip. The pinned photodiode is configured to accumulate charge in response to incident radiation. The pixel circuit is configured to enable readout of the accumulated charge and includes a plurality of transistors.

[0011] The plurality of transistors includes a transfer transistor, a reset transistor, and a source follower transistor. The transfer transistor is configured to transfer accumulated charge from the pinned photodiode to a floating diffusion (FD) node. The reset transistor is configured to reset the FD node to a reset voltage and is further configured to reset the pinned photodiode to a pinning voltage. The source follower transistor is configured to non-destructively buffer and amplify the charge at the FD node.

[0012] The semiconductor manufacturing industry continues to pursue miniaturization of CMOS image sensors to achieve low manufacturing costs, relatively high device integration densities, etc. However, it has proven difficult to continue shrinking the transistors in the pixel circuitry, which can result in the photodiode being shrinked instead, potentially degrading the performance of the pixel sensor. For example, this can result in a reduction in full well capacity (FWC), resulting in signal degradation. FWC is proportional to the size of the photosensitive element and corresponds to the maximum charge the pixel can hold before saturation.

[0013] One approach to increasing the FWC to compensate for the relatively small pixel size is to increase the FD reset voltage and the turn-on voltage of the transfer transistor. The former increases the pinning voltage of the pinned photodiode, thereby increasing the FWC of the pinned photodiode. However, this approach may cause reliability issues for the source follower transistor and the reset transistor because they are exposed to relatively high voltages. Furthermore, this approach may rely on a relatively high supply voltage to the source follower transistor, which may increase power consumption during readout.

[0014] Various embodiments of the present disclosure are directed to a stacked CMOS image sensor having a high FWC. A first IC chip and a second IC chip are stacked on top of each other. The first IC chip includes a first semiconductor substrate, and the second IC chip includes a second semiconductor substrate. A pixel sensor is disposed on and spans the first and second semiconductor substrates. The pixel sensor includes a transfer transistor and a pinned photodiode adjacent to the transfer transistor in the first semiconductor substrate, and further includes a plurality of additional transistors (e.g., reset transistor, source follower transistor, etc.) in the second semiconductor substrate. The bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other and configured to be biased at different voltages (e.g., a negative voltage and ground). The bulk of the first semiconductor substrate defines the body of the transfer transistor and the anode of the pinned photodiode, or is electrically coupled (e.g., shorted) to the body of the transfer transistor and the anode of the pinned photodiode. The bulk of the second semiconductor substrate defines the individual bodies of the additional transistors or is electrically coupled (eg, shorted) to the individual bodies of the additional transistors.

[0015] Because the bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other and biased at different voltages, the bulk of the first semiconductor substrate can be biased at a negative voltage and the bulk of the second semiconductor substrate can be grounded (e.g., biased at zero voltage). As a result, the voltages of the pinned photodiode and transfer transistor, including the pinning voltage of the photodiode and the turn-on voltage of the first transistor, are relative to the negative voltage rather than ground. This has the effect of increasing these voltages by the magnitude of the negative voltage, which increases the FWC of the pinned photodiode.

[0016] Because the voltage of the additional transistor is relative to ground rather than a negative voltage, the additional transistor is not subjected to the relatively high voltages that the pinned photodiode and transfer transistor are subjected to. As a result, the ruggedness and reliability of the additional transistor are not affected. Furthermore, because the source follower transistor is not dependent on a relatively high supply voltage, power consumption is not affected.

[0017] Because the pixel sensor spans the first and second IC chips, the pixel sensor has fewer transistors on the first IC chip than it would otherwise. This allows the pixel sensor to be scaled down on the first IC chip without scaling down the pinned photodiode. Because the pinned photodiode is relatively large and located on the first IC chip rather than the second IC chip, the portion of the pixel sensor on the first IC chip may limit the scaling down of the pixel sensor. Therefore, the portion of the pixel sensor on the second IC chip may have unused space. This unused space can be used for additional functions. In addition, scaling down the pixel sensor on the first IC chip can have the effect of scaling down the entire pixel sensor. As described above, because the pixel sensor can be scaled down without scaling down the pinned photodiode, the pixel sensor can have high performance despite its small size.

[0018] Referring to FIG. 1 , a circuit diagram 100 of some embodiments of a stacked CMOS image sensor including a pixel sensor 102 is provided. The pixel sensor 102 spans a first IC chip 104a and a second IC chip 104b that are stacked together. While the first IC chip 104a and the second IC chip 104b are shown stacked horizontally, they may alternatively be stacked vertically. The pixel sensor 102 may be, for example, a four transistor (4T) CMOS active pixel sensor (APS), and / or may be known as, for example, a pixel.

[0019] The pixel sensor 102 includes a pinned photodiode 106 and a pixel circuit 108. In alternative embodiments, the pinned photodiode 106 is another suitable type of light-sensitive element. The pixel circuit 108 further includes a first transistor 110 on the first IC chip 104a and a plurality of second transistors 112 on the second IC chip 104b. The pixel circuit 108 is further configured to enable readout of the pinned photodiode 106.

[0020] The body of the first transistor 110 and the anode of the pinned photodiode 106 are connected to the first substrate terminal T sub1 and the individual body of the second transistor 112 is electrically coupled (e.g., shorted) to the second substrate terminal T sub2 Furthermore, the first substrate terminal T sub1 and the second board terminal T sub2 are electrically isolated from each other. As will be seen later, the first substrate terminal T sub1 may be defined by or electrically connected (e.g., shorted) to the bulk of the semiconductor substrate of the first IC chip 104a, and the second substrate terminal T sub2 may be defined by or electrically coupled to (e.g., shorted to) the bulk of the semiconductor substrate of second IC chip 104b. Note that the bulk of the semiconductor substrate as used throughout this specification is also referred to as the body of the semiconductor substrate.

[0021] The first transistor 110 is more specifically a transfer transistor gated by a transfer signal TX and configured to selectively transfer charge accumulated in the pinned photodiode 106 to a floating diffusion node (FD). The second transistor 112 includes a reset transistor 116, a source follower transistor 118, and a select transistor 120.

[0022] While the image sensor is in use, the first board terminal T sub1 is the negative voltage V NV and the second board terminal T sub2 is biased to ground GND. Negative voltage V NV is negative with respect to ground GND, and in some embodiments is approximately 0 to −5 volts or other suitable value. Thus, the anode of pinned photodiode 106 and the body of transfer transistor 114 are coupled to a negative voltage V NV and the individual body of the second transistor 112 is electrically coupled (eg, shorted) to ground GND.

[0023] The anode of the pinned photodiode 106 and the body of the transfer transistor 114 are connected to a negative voltage V NV , the pinning voltage of the pinned photodiode 106 and the turn-on voltage of the transfer transistor 114 are not ground GND but a negative voltage V NV This is relative to the negative voltage V NV , increasing the FWC of the pinned photodiode 106 and thus improving the performance of the image sensor.

[0024] The voltage of the second transistor 112 is a negative voltage V NVBecause the second transistor 112 is connected to ground GND rather than to the pinned photodiode 106, the second transistor 112 is not subjected to the relatively high voltages experienced by the pinned photodiode 106 and the transfer transistor 114. As a result, the ruggedness and reliability of the second transistor are not affected by the relatively high voltages at the pinned photodiode 106 and the transfer transistor 114. Furthermore, the power consumption in the second transistor 112 is not affected (e.g., is not increased) by the relatively high voltages.

[0025] Because the pixel sensors 102 span the first IC chip 104a and the second IC chip 104b, the pixel sensors 102 have fewer transistors on the first IC chip 104a than they would otherwise. This allows the pixel sensors 102 to be scaled down on the first IC chip 104a without scaling down the pinned photodiode 106. Because the pinned photodiode 106 is relatively large and is present on the first IC chip 104a but not on the second IC chip 104b, the portion of the pixel sensors 102 on the first IC chip 104a can limit the scaling down of the pixel sensors 102. Thus, the portion of the pixel sensors 102 on the second IC chip 104b can have unused space. This unused space can be used for additional functionality. Additionally, scaling down the pixel sensors 102 on the first IC chip 104a can have the effect of scaling down the entire pixel sensor. As described above, the pixel sensor 102 can be miniaturized without miniaturizing the pinned photodiode 106, so the performance of the pixel sensor 102 can be improved even if the size is small.

[0026] Continuing with FIG. 1, reset transistor 116 is gated by a reset signal RST and supplies a reset voltage V RST to the floating diffusion node FD. The reset transistor 116 couples the floating diffusion node FD to a reset voltage V RST To reset the floating diffusion node FD to the reset voltage V RSTFurthermore, the reset transistor 116, in cooperation with the transfer transistor 114, is configured to selectively electrically couple the pinned photodiode 106 to a reset voltage V RST The sensor is configured to selectively electrically couple to the

[0027] The source follower transistor 118 is gated by the charge at the floating diffusion node FD. For example, the gate of the source follower transistor 118 may be electrically coupled (e.g., shorted) to the floating diffusion node FD and / or the source / drain region of the transfer transistor 14. Additionally, the select transistor 120 is gated by a select signal SEL. The source follower transistor 118 and the select transistor 120 are connected to a supply voltage V DD The source follower transistor 118 is electrically coupled in series from the floating diffusion node FD to the output OUT of the pixel sensor 102. The source follower transistor 118 is configured to buffer and amplify the voltage at the floating diffusion node FD for non-destructively reading the voltage. The select transistor 120 is configured to selectively pass the buffered and amplified voltage from the source follower transistor 118 to the output OUT.

[0028] During operation of the pixel sensor, the pinned photodiode 106 is connected to a reset voltage V V via the transfer transistor 114 and reset transistor 116. RST Furthermore, the floating diffusion node FD is reset to the pinning voltage V by electrically coupling the floating diffusion node FD to the reset voltage V by the reset transistor 116. RST By electrically coupling to the reset voltage V RSTThe pinned photodiode 106 is reset to 0. Incident radiation on the pinned photodiode 106 then causes charge to accumulate in the pinned photodiode 106. After the charge has accumulated for an appropriate amount of time, it is transferred to the floating diffusion node FD by the transfer transistor 114. The source follower transistor 118 buffers and amplifies the voltage at the floating diffusion node FD, and the select transistor 120 passes the buffered and amplified voltage from the source follower transistor 118 to the output OUT.

[0029] In some embodiments, a negative voltage V NV is connected to the first substrate terminal T from the reset of the pinned photodiode 106 and the floating diffusion node FD to the buffered and amplified voltage at the output OUT. sub1 In another embodiment, the first substrate terminal T sub1 is biased to ground GND while buffering and amplifying the voltage at floating diffusion node FD and while passing the buffered and amplified voltage from source follower transistor 118 to output OUT. In such other embodiments, the otherwise negative voltage V NV is the first board terminal T sub1 For example, during reset and charge accumulation, the negative voltage V NV is the first board terminal T sub1 The negative voltage V NV A change from GND to ground, for example, increases the signal-to-noise ratio (SNR) at the output OUT.

[0030] In some embodiments, the first and second transistors 110, 112 are metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate-all-around field effect transistors (GAA FETs), nanosheet field effect transistors, etc., or any combination thereof. In at least some embodiments (e.g., where the first and second transistors 110, 112 are MOSFETs, etc.), the first and second transistors 110, 112 have respective body diodes, not shown.

[0031] In some embodiments, the first and second transistors 110, 112 are turned on or conductive in response to a common turn-on voltage at their corresponding gate electrodes. The common turn-on voltage is relative to ground GND for each of the first and second transistors 110, 112 and may be, for example, about 2.8 volts, about 2.5-3.0 volts, or other suitable voltage. The body of the first transistor 110 is connected to a negative voltage V rather than ground GND. NV , the common turn-on voltage is the negative voltage V NV , and is therefore larger for the first transistor 110 than for the second transistor 112.

[0032] In some embodiments, the first and second transistors 110, 112 are turned off or non-conductive in response to separate turn-off voltages at their corresponding gate electrodes. The first transistor 110 has a first turn-off voltage, and the second transistor 112 has a second turn-off voltage. The first and second turn-off voltages are relative to ground GND. Furthermore, the first turn-off voltage is more negative than the second turn-off voltage, V NV The first turn-off voltage is closer to ground GND than the second turn-off voltage, for example, a negative voltage V NV A negative voltage V minus approximately 1.2 volts, which is approximately equal to NV The second turn-off voltage may be, for example, approximately equal to 0 volts, or another suitable voltage.

[0033] 2, a potential diagram 200 is provided for some embodiments of the image sensor of FIG. 1 when the pixel sensor 102 is in a reset state. The pinned photodiode 106 has a first potential well 202 in which negative charge accumulates in response to incident radiation, and the floating diffusion node FD has a second potential well 204 to which the negative charge from the first potential well 202 can be transferred.

[0034] The first potential well 202 is connected to the pinning voltage V pin The pinning voltage V pin is not ground GND but negative voltage V NV is relative to the pinning voltage V pin is larger than it would otherwise be, and is effectively increased by the magnitude of the negative voltage. pin Therefore, the depth of the first potential well 202 is deeper than would otherwise be the case, and the FWC capacitance of the pinned photodiode 106 is larger than would otherwise be the case.

[0035] The second potential well 204 spans the first and second IC chips 104a and 104b, with a portion of the second potential well 204 in the first IC chip 104a and a portion of the second potential well 204 in the second IC chip 104b. RST The reset voltage V RST is the negative voltage V at the first IC chip 104a NV , and the depth is greater in the first IC chip 104a than in the second IC chip 104b. As will be seen hereinafter, this is because the bulk of the semiconductor substrate of the first IC chip 104a is at a negative voltage V NV and the bulk of the semiconductor substrate of the second IC chip 104b is electrically connected (eg, shorted) to ground GND.

[0036] Transfer transistor 114 forms a barrier 206 that separates first potential well 202 and second potential well 204 from each other when transfer transistor 114 is OFF or non-conducting. This prevents negative charge that accumulates in first potential well 202 from migrating from first potential well 202 to second potential well 204. Furthermore, when transfer transistor 114 is ON or conducting, barrier 206 is removed and the potential at transfer transistor 114 is between and offset from the potential at the bottom of first potential well 202 and the potential at the bottom of second potential well 204. Because negative charge moves from a lower potential to a higher potential, this results in negative charge in first potential well 202 migrating to second potential well 204.

[0037] 3, a schematic cross-sectional view 300 is provided of some embodiments of the image sensor of FIG. 1 in which a first IC chip 104a and a second IC chip 104b are vertically stacked. The first IC chip 104a is above the second IC chip 104b, and the image sensor is configured to receive radiation 302 from the top of the image sensor.

[0038] Referring to FIG. 4, a circuit diagram 400 of some embodiments of the image sensor of FIG. 1 is provided in which a body diode 402 of the reset transistor 116 is represented in the source / drain region of the reset transistor 116. Note that the source / drain region may refer to the source or drain individually or collectively depending on the context. The body diode 402 corresponds to a PN junction defined in part by the source / drain region. Furthermore, the body diode 402 is connected to the second substrate terminal T sub2 and a cathode electrically connected (eg, shorted) to the source / drain regions.

[0039] Although not shown, the reset transistor 116 may have an additional body diode at another source / drain region of the reset transistor 116. Additionally, the remainder of the first transistor 110 and second transistor 112 may have individual body diodes similar to the body diode 402 of the reset transistor 116. In contrast to the body diode 402 of the reset transistor 116, the body diode of the first transistor 110 is connected to the second substrate terminal T sub2 Instead, the first board terminal T sub1 The anode may be electrically connected (e.g., shorted) to the cathode.

[0040] 5A and 5B, circuit diagrams 500A, 500B are provided for several alternative embodiments of the image sensor of FIG. 1, where the components of the image sensor differ.

[0041] 5A, the reset transistor 116 is on the first IC chip 104a instead of the second IC chip 104b. Thus, the pixel sensor 102 includes a plurality of first transistors 110, including a transfer transistor 114 and a reset transistor 116. Furthermore, the individual bodies of the first transistors 110, including the body of the reset transistor 116, are connected to the first substrate terminal T sub1 are electrically connected (e.g., shorted) to

[0042] 5B, the first transistor 110 has a first gate dielectric thickness T1, and the plurality of second transistors 112 share a second gate dielectric thickness T2 that is less than the first gate dielectric thickness T1. In an alternative embodiment, the plurality of second transistors 112 have different individual gate dielectric thicknesses, each less than the first gate dielectric thickness T1. The first gate dielectric thickness T1 may be thicker than the second gate dielectric thickness T2, for example, to allow the first transistor 110 to better handle its relatively high turn-on voltage. As described above, the turn-on voltage of the first transistor 110 increases when the body of the first transistor 110 is coupled to a negative voltage V NV is electrically connected (e.g., shorted) to the negative voltage V NVis effectively increased by

[0043] In some embodiments, the first gate dielectric thickness T1 is about 1-1000 angstroms, about 1-500 angstroms, about 500-1000 angstroms, or other suitable value, and / or the second gate dielectric thickness T2 is about 1-500 angstroms, about 1-250 angstroms, about 250-500 angstroms, or other suitable value.

[0044] 6, a circuit diagram 600 of some alternative embodiments of the image sensor of FIG. 1 is provided, in which the pixel sensor 102 includes a plurality of sub-pixels 102s on the first IC chip 104a. More specifically, the pixel sensor 102 includes a plurality of pinned photodiodes 106 and a plurality of first transistors 110 on the first IC chip 104a. The pinned photodiodes 106 are paired with the first transistors 110 in a one-to-one correspondence, with each photodiode-transistor pair forming a sub-pixel 102s. In alternative embodiments, the pinned photodiodes 106 are other suitable types of light-sensitive elements.

[0045] The pinned photodiode 106 is connected to the first substrate terminal T sub1 1 and 2 are electrically coupled (e.g., shorted) to the first transistor 110. For example, the anode of the pinned photodiode 106 is electrically coupled (e.g., shorted) to the first substrate terminal T sub1 The cathodes of the pinned photodiodes 106 are electrically coupled (e.g., shorted) to the subpixels 102s, and the cathodes of the pinned photodiodes 106 are electrically coupled to the first transistors 110, respectively. The first transistors 110 are a plurality of transfer transistors 114 gated by respective transfer signals TX1, TX2, TX3, and TX4, and configured to selectively transfer charge accumulated in the pinned photodiodes 106 to a floating diffusion node FD. The floating diffusion node FD is common to the subpixels 102s. Additionally, the second transistor 112 is as shown in FIG. 1 and is shared by the subpixels 102s.

[0046] 6 depicts the pixel sensor 102 having multiple transfer transistors 114, the pixel sensor 102 may additionally or alternatively include multiple reset transistors 116 and / or multiple source follower transistors 118. The multiple reset transistors 116 may be electrically coupled in parallel. Alternatively, the multiple reset transistors 116 may be separate for each subpixel 102s. In such an alternative embodiment, the pixel sensor 102 may include multiple floating diffusion nodes FD separate for each subpixel 102s and may further include multiple source follower transistors 118 separate for each subpixel 102s.

[0047] Referring to FIG. 7, a circuit diagram 700 of some alternative embodiments of the image sensor of FIG. 1 is provided, in which the pixel sensor 102 includes an auxiliary pixel circuit 702. The auxiliary pixel circuit 702 is electrically coupled between the select transistor 120 and the output OUT of the pixel sensor 102 and is formed by the second transistor 112. Note that the ellipsis in the auxiliary pixel circuit 702 is used to represent zero or more additional second transistors. Furthermore, the auxiliary pixel circuit 702 is configured to perform additional processing on the signal from the select transistor 120 before passing it to the output OUT. For example, noise filtering, etc. may be performed.

[0048] Because the pinned photodiode 106 is relatively large and is present on the first IC chip but not on the second IC chip, the portion of the pixel sensor on the first IC chip may limit the scaling of the pixel sensor. Thus, the portion of the pixel sensor on the second IC chip may have unused space, allowing for integration of auxiliary pixel circuitry 702 into the pixel sensor 102 without enlarging the pixel sensor 102.

[0049] Referring to FIG. 8, a circuit diagram 800 is provided of some alternative embodiments of the image sensor of FIG. 1, in which the image sensor further includes a third IC chip 104c. The third IC chip 104c houses an ASIC 802 electrically coupled to the pixel sensors 102 and any other pixel sensors (not shown) of the image sensor. The ASIC 802 may be configured to perform, for example, analog-to-digital conversion (ADC), buffering, image processing, etc., or any combination thereof. In some embodiments, the ASIC 802 buffers and performs ADC on the outputs OUT of the pixel sensors 102 and any other pixel sensors of the image sensor to generate digital data representing an image, and then performs image processing on the image formed by the digital data.

[0050] The third IC chip 104c includes a plurality of third transistors 804 electrically interconnected to form an ASIC 802, the plurality of third transistors 804 including at least one n-type transistor 804n and at least one p-type transistor 804p. Note that ellipses are used in the ASIC 802 to represent zero or more additional third transistors. The plurality of third transistors 804 may be, for example, MOSFETs, FinFETs, GAA FETs, nanosheet field effect transistors, other suitable types of transistors, or any combination of the foregoing.

[0051] 9, a schematic cross-sectional view 900 is provided of some embodiments of the image sensor of FIG. 8, in which first, second, and third IC chips 104a-104c are vertically stacked. The first IC chip 104a is the top of the image sensor, and the second IC chip 104b is between the first IC chip 104a and the third IC chip 104c. Furthermore, the image sensor is configured to receive radiation 902 from the top of the image sensor.

[0052] Referring to Figure 10, a circuit diagram 1000 is provided of several alternative embodiments of the image sensor of Figure 8, in which the pixel sensor 102 includes the auxiliary pixel circuit 702 described with respect to Figure 7. The auxiliary pixel circuit 702 is electrically coupled between the select transistor 120 and the output OUT of the pixel sensor 102, and is formed by a second transistor 112. Note that ellipses in the auxiliary pixel circuit 702 are used to represent zero or more additional second transistors.

[0053] Referring to FIG. 11 , a schematic cross-sectional view 1100 is provided of some embodiments of an image sensor including multiple pixel sensors 102, each as in FIG. 1 . In other words, the pixel sensor 102 of FIG. 1 is repeated, and multiple instances or repetitions of the pixel sensor of FIG. 1 are present. In alternative embodiments, the pixel sensors 102 are each as in FIGS. 4, 5A, 5B, 6, and 7. Furthermore, the first IC chip 104a and the second IC chip 104b are vertically stacked. The first IC chip 104a is above the second IC chip 104b, and the image sensor is configured to receive radiation 302 from the top of the image sensor.

[0054] 12, a top-down layout view 1200 of some embodiments of the image sensor of FIG. 11 is provided, where the image sensor has rows and columns of pixel sensors 102. The schematic cross-sectional view 1100 of FIG. 11 may be taken, for example, along line A-A' in FIG.

[0055] The multiple rows are rows R1, R2, R3, and R M and the plurality of columns includes columns C1, C2, C3, and C N The subscripts of the row labels correspond to the row number, where M is an integer greater than 3. Similarly, the subscripts of the column labels correspond to the column number, where N is an integer greater than 3. Furthermore, the multiple rows and columns form a two-dimensional array in which the pixel sensors 102 are in a periodic grid pattern. Other suitable patterns are also applicable in alternative embodiments.

[0056] Referring to FIG. 13, a schematic cross-sectional view 1300 is provided of some embodiments of an image sensor including multiple pixel sensors 102, each as in FIG. 10. In other words, the pixel sensor 102 of FIG. 10 is repeated, and multiple instances or repetitions of the pixel sensor of FIG. 10 exist. In an alternative embodiment, the pixel sensors 102 are each as in FIG. 8. Furthermore, an ASIC 802 is shared by the pixel sensors 102. For example, there may be a many-to-one correspondence between the pixel sensors 102 and the ASIC 802. Furthermore, the first, second, and third IC chips 104a-104c are vertically stacked. The second IC chip 104b is between the first IC chip 104a and the third IC chip 104c, and the image sensor is configured to receive radiation 902 from the top of the image sensor.

[0057] Although Figure 12 is described with respect to the image sensor of Figure 11, it should be understood that Figure 12 is also applicable to the image sensor of Figure 13. For example, the schematic cross-sectional view 1300 of Figure 13 may be taken along line A-A' of Figure 12.

[0058] Referring to Figure 14, a cross-sectional view 1400 of some embodiments of the image sensor of Figure 1 is provided. A first IC die 104a and a second IC die 104b are vertically stacked such that the first IC die 104a is above the second IC die 104b. The pinned photodiode 106 and the first transistor 110 are located in and at least partially defined by a first semiconductor substrate 1402 of the first IC die 104a, and the second transistor 112 (only one of which is shown) is located in and partially defined by a second semiconductor substrate 1404 of the second IC die 104b. The first and second semiconductor substrates 1402, 1404 may be, for example, bulk substrates of single crystal silicon, silicon germanium, or the like, or any combination thereof, or may be, for example, other suitable types of semiconductor substrates.

[0059] The bulk 1402b of the first semiconductor substrate 1402 and the bulk 1404b of the second semiconductor substrate 1404 are electrically isolated from each other and are connected to a negative voltage VNV and biased at ground GND. The bulk 1402b of the second semiconductor substrate 1402 defines or is electrically coupled (e.g., shorted) to the body of the first transistor 110 and the anode of the pinned photodiode 106. The bulk 1404b of the second semiconductor substrate 1404 defines or is electrically coupled (e.g., shorted) to the individual bodies of the second transistors 112 (only one of which is shown).

[0060] In at least some embodiments, the bulk 1402b of the first semiconductor substrate 1402 has a single doping type and / or the bulk 1404b of the second semiconductor substrate 1404 has a single doping type. For example, the bulks 1402b, 1404b may be p-type. Furthermore, in at least some embodiments, the bulk 1402b of the first semiconductor substrate 1402 has one or more doping concentrations and / or the bulk 1404b of the second semiconductor substrate 1404 has one or more doping concentrations.

[0061] The bulk 1402b of the first semiconductor substrate 1402 is connected to a negative voltage V NV , the voltages of the pinned photodiode 106 and the first transistor 110, including the pinning voltage of the pinned photodiode 106 and the turn-on voltage of the first transistor 110, can be biased at a negative voltage V instead of ground GND. NV This means that these voltages are compared to the negative voltage V NV , which increases the FWC of the pinned photodiode 106 as described with respect to FIGS.

[0062] The bulk 1404b of the second semiconductor substrate 1404 is connected to a negative voltage V NV Since the second transistor 112 can be biased at ground GND rather than at the negative voltage V NVThe second transistor 112 is connected to ground GND rather than to the pinned photodiode 106. Therefore, the second transistor 112 is not subjected to the relatively high voltage that the pinned photodiode 106 and the first transistor 110 are subjected to. Because the second transistor 112 is not subjected to the relatively high voltage, the durability and reliability of the second transistor 112 are not affected by the relatively high voltage. Furthermore, the power consumption in the second transistor 112 is not affected (e.g., does not increase) by the relatively high voltage.

[0063] 14 , the pinned photodiode 106 includes a collector region 1406 and a pinning region 1408 that overlies the collector region 1406 on the front side of the first semiconductor substrate 1402. Additionally, the pinned photodiode 106 includes a portion of the bulk 1402b of the first semiconductor substrate 1402 that adjacently surrounds the pinning region 1408 and the collector region 1406. During operation, the pinned photodiode 106 receives radiation from above the first semiconductor substrate 1402, which results in the accumulation of charge in the collector region 1406.

[0064] The bulk 1402b of the first semiconductor substrate 1402 and the pinning region 1408 correspond to the doped regions of the first semiconductor substrate 1402 and share a first doping type. Furthermore, the pinning region 1408 has a higher doping concentration than the bulk 1402b of the first semiconductor substrate 1402. The collector region 1406 corresponds to the doped regions of the first semiconductor substrate 1402 and has a second doping type opposite to the first doping type. For example, the first doping type may be p-type and the second doping type may be n-type. Furthermore, the collector region 1406 is adjacent to the pinning region 1408 and the bulk 1402b of the first semiconductor substrate 1402 to form a PN junction.

[0065] The first transistor 110 faces the pinned photodiode 106 on the front side of the first semiconductor substrate 1402. Furthermore, the first transistor 110 includes a first gate electrode 1410, a first gate dielectric layer 1412, first sidewall spacers 1414, and a pair of first source / drain regions 1416. During operation of the image sensor, the first gate electrode 1410 may be biased with a turn-on voltage, causing the first channel region of the first transistor 110 to conduct. This leads to the transfer of charge accumulated in the collector region 1406 of the pinned photodiode 106 to the floating diffusion node FD. Thus, the first transistor 110 is more specifically a transfer transistor 114 in this embodiment.

[0066] A first gate electrode 1410 and a first gate dielectric layer 1412 are stacked on the first semiconductor substrate 1402, with the first gate dielectric layer 1412 separating the first gate electrode 1410 from the first semiconductor substrate 1402. Additionally, the first gate dielectric layer 1412 covers the pinned photodiode 106 on the front side of the first semiconductor substrate 1402. In an alternative embodiment, the first gate dielectric layer 1412 is localized between the first gate electrode 1410 and the first semiconductor substrate 1402.

[0067] The first sidewall spacers 1414 are on the sidewalls of the first gate electrode 1410 and the first gate dielectric layer 1412. Furthermore, the first sidewall spacers 1414 have a pair of segments between which the first gate electrode 1410 and the first gate dielectric layer 1412 are sandwiched. The first sidewall spacers 1414 are a dielectric material and may be or include, for example, silicon nitride, the like, or any combination thereof.

[0068] The first source / drain regions 1416 are in the first semiconductor substrate 1402 and are separated from each other by a first channel region 1418 in the first semiconductor substrate 1402. Furthermore, the first source / drain regions 1416 correspond to doped regions of the first semiconductor substrate 1402 that share a common doping type, which is opposite to the doping type of the bulk 1402b of the first semiconductor substrate 1402. For example, the first source / drain regions 1416 may be n-type and the bulk 1402b of the first semiconductor substrate 1402 may be p-type. One of the first source / drain regions 1416 is formed by the collector region 1406, and the other of the first source / drain regions 1416 partially forms the floating diffusion node FD.

[0069] The second transistors 112 (only one of which is shown) are on the front side of the second semiconductor substrate 1404. Additionally, the second transistor 112 includes a respective second gate electrode 1420, a respective second gate dielectric layer 1422, a respective second sidewall spacer 1424, and a respective pair of second source / drain regions 1426. During operation of the image sensor, the reset transistor 116 of the second transistor 112 enables resetting of the pinned photodiode 106 to a pinning voltage and further enables resetting of the floating diffusion node FD to a reset voltage. Additionally, the source follower transistor (not shown) of the second transistor 112 and the select transistor (not shown) of the second transistor 112 enable non-destructive readout of the charge at the floating diffusion node FD.

[0070] Each second gate electrode 1420 is stacked with a second gate dielectric layer 1422 that separates the second gate electrode 1420 from the second semiconductor substrate 1404. Second sidewall spacers 1424 are on the sidewalls of the second gate electrode 1420 and the second gate dielectric layer 1422, respectively. Thus, each second gate electrode 1420 is sandwiched between segments of a respective second sidewall spacer, and each second gate dielectric layer 1422 is sandwiched between segments of a respective second sidewall spacer. The second sidewall spacers 1424 are a dielectric and may be or include, for example, silicon nitride, the like, or any combination thereof.

[0071] A pair of second source / drain regions 1426 are in the second semiconductor substrate 1404, and one source / drain region of the reset transistor 116 partially forms the floating diffusion node FD. The source / drain regions of each pair of second source / drain regions 1426 correspond to doped regions in the second semiconductor substrate 1404 that share a common doping type, opposite the doping type of the bulk 1404b of the second semiconductor substrate 1404. For example, the pair of second source / drain regions 1426 may be n-type, and the bulk 1404b of the second semiconductor substrate 1404 may be p-type. Furthermore, the source / drain regions of each pair of second source / drain regions 1426 are separated from each other by a corresponding second channel region 1428 in the second semiconductor substrate 1404.

[0072] The first IC chip 104a and the second IC chip 104b include a first interconnect structure 1430 and a second interconnect structure 1432, respectively. The first interconnect structure 1430 and the second interconnect structure 1432 are between the first semiconductor substrate 1402 and the second semiconductor substrate 1404. Furthermore, the first interconnect structure 1430 and the second interconnect structure 1432 include a plurality of conductive wires 1434 and a plurality of conductive vias 1436 stacked in corresponding interconnect dielectric layers 1438. The conductive wires 1434 and the conductive vias 1436 are grouped into multiple wire levels and multiple via levels, respectively, that are stacked alternately to form conductive paths. The via and wire layers in the first interconnect structure 1430 are stacked to define a conductive path leading from the first transistor 110. Similarly, the via and wire layers in the second interconnect structure 1432 are stacked to define a conductive path leading from the second transistor 112.

[0073] Between the first IC chip 104a and the second IC chip 104b are bond structures 1440 that allow the first IC chip 104a and the second IC chip 104b to be bonded together at a bond interface 1442. Such a bond may include, for example, a combination of a metal-to-metal bond and a dielectric-to-dielectric bond at the bond interface 1442.

[0074] Bonding structure 1440 includes bonding dielectric layers 1444 that are separate from first IC chip 104a and second IC chip 104b and bonded in direct contact at bonding interface 1442. Bonding structure 1440 further includes bonding pads 1446 that are separate from first IC chip 104a and second IC chip 104b and bonded in direct contact at bonding interface 1442. Bond pads 1446 are respectively inserted in bonding dielectric layer 1444 and are electrically coupled to first and second interconnect structures 1430 and 1432, respectively, by bonding vias 1448 in bonding dielectric layer 1444.

[0075] 15A and 15B, cross-sectional views 1500A, 1500B are provided of several alternative embodiments of the image sensor of FIG. 14, where the components of the image sensor are different.

[0076] 15A, the first gate dielectric layer 1412 has a thickness T1 that is greater than the individual thickness T2 of the plurality of second gate dielectric layers 1422. Additionally, the first sidewall spacers 1414 have a thickness T3 that is greater than the individual thickness T4 of the plurality of second sidewall spacers 1424. As described above, the turn-on voltage of the first transistor 110 is determined when the body of the first transistor 110 is coupled to a negative voltage V NV is electrically connected (e.g., shorted) to the negative voltage V NV , effectively increasing the drain current. Conversely, the plurality of second transistors 112 have individual bodies electrically coupled (e.g., shorted) to ground GND and therefore do not experience a relatively high turn-on voltage. The relatively large thickness of the first gate dielectric layer 1412 and the first sidewall spacers 1414, for example, enables the first transistor 110 to favorably handle a relatively high turn-on voltage, enhancing the reliability of the first transistor 110. Additionally, the relatively large thickness can reduce gate-induced drain leakage.

[0077] 15B, the image sensor is front-side illuminated rather than back-side illuminated, and is configured to receive incident radiation from the front side of the first semiconductor substrate 1402. This is in contrast to the image sensor of FIG. 14, which is back-side illuminated and thus configured to receive incident radiation from the back side of the first semiconductor substrate 1402. The front side of the first semiconductor substrate 1402 corresponds to the side of the first semiconductor substrate 1402 on which the first interconnect structure 1430 is disposed, and the back side of the first semiconductor substrate 1402 corresponds to the opposite side of the first semiconductor substrate 1402.

[0078] 14, the first semiconductor substrate 1402 and the first interconnect structure 1430 are vertically flipped, with the first interconnect structure 1430 above the first semiconductor substrate 1402. Furthermore, through-substrate vias (TSVs) 1502 extend through the first semiconductor substrate 1402. The TSVs 1502 extend from the first interconnect structure 1430 to the junction structure 1440 to provide electrical coupling between the first interconnect structure 1430 and the junction structure 1440. Furthermore, the TSVs 1502 are separated from the first semiconductor substrate 1402 by a TSV dielectric layer 1502.

[0079] 16, a cross-sectional view 1600 is provided of some alternative embodiments of the image sensor of FIG. 14, where the image sensor further includes a third IC chip 104c. Furthermore, in some embodiments, the image sensor corresponds to circuit diagram 800 of FIG. 8 or circuit diagram 1000 of FIG. 10.

[0080] Third IC chip 104c is vertically stacked with first IC chip 104a and second IC chip 104b and is below second IC chip 104b. Third transistor 804 resides in and is at least partially defined by third semiconductor substrate 1602 of third IC chip 104c. Third semiconductor substrate 1602 may be, for example, a bulk substrate of single crystal silicon, silicon germanium, or the like, or any combination thereof, or may be, for example, any other suitable type of semiconductor substrate.

[0081] The individual bodies of at least some of the third transistors 804 are electrically coupled to (e.g., shorted to) or defined by the bulk 1602b of the third semiconductor substrate 1602. Furthermore, the bulk 1602b of the third semiconductor substrate 1602 is electrically coupled to (e.g., shorted to) the third substrate terminal T sub3 or the third substrate terminal T sub3 Define the third board terminal T sub3 is the first board terminal T sub1 from, and in some embodiments, the second substrate terminal T sub2 In this manner, the bulk 1602b of the third semiconductor substrate 1602 is electrically isolated from the bulk 1402b of the first semiconductor substrate 1402, and in some embodiments, the bulk 1404b of the second semiconductor substrate 1404.

[0082] While the image sensor is in use, the first board terminal T sub1 is the negative voltage V NV and the second substrate terminal T sub2 and the third board terminal T sub3 may be biased to ground GND. As mentioned above, the first substrate terminal T sub1 to a negative voltage V NV Biasing with improves the FWC of the pixel sensor 102.

[0083] Third transistors 804 (only one of which is shown) are on the front side of the third semiconductor substrate 1602. Additionally, the third transistor 804 includes a respective third gate electrode 1604, a respective third gate dielectric layer 1606, a respective third sidewall spacer 1608, and a pair of respective third source / drain regions 1610.

[0084] Each third gate electrode 1604 is stacked with a third gate dielectric layer 1606 that separates the third gate electrode 1604 from the third semiconductor substrate 1602. Third sidewall spacers 1608 are on the sidewalls of the third gate electrode 1604 and the third gate dielectric layer 1606, respectively. Thus, each third gate electrode 1604 is sandwiched between segments of a respective third sidewall spacer, and each third gate dielectric layer 1606 is sandwiched between segments of a respective third sidewall spacer. The third sidewall spacers 1608 are a dielectric and may be or include, for example, silicon nitride, the like, or any combination thereof.

[0085] A pair of third source / drain regions 1610 are in the third semiconductor substrate 1602. The source / drain regions of each pair of third source / drain regions 1610 correspond to doped regions of the third semiconductor substrate 1602 that share a common doping type, opposite that of the bulk 1602b of the third semiconductor substrate 1602. For example, the pair of third source / drain regions 1610 may be n-type, and the bulk 1602b of the third semiconductor substrate 1602 may be p-type. Furthermore, the source / drain regions of each pair of third source / drain regions 1610 are separated from each other by a corresponding third channel region 1612 in the third semiconductor substrate 1602.

[0086] The third IC chip 104c further includes a third interconnect structure 1614 between the second semiconductor substrate 1404 and the third semiconductor substrate 1602. The third interconnect structure 1614 covers the third transistor 804 on the front side of the third interconnect structure 1614. Furthermore, the third interconnect structure 1614 is like the first interconnect structure 1430 and the second interconnect structure 1432 described above. Thus, the third interconnect structure 1614 includes a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in corresponding interconnect dielectric layers 1438. These conductive wires 1434 and conductive vias 1436 define a conductive path leading from the third transistor 804.

[0087] Between the third interconnect structure 1614 and the second semiconductor substrate 1404 is an additional bonding structure 1616. Furthermore, the additional bonding structure 1616 enables bonding of the second IC chip 104b and the third IC chip 104c at an additional bonding interface 1618. Such bonding may include, for example, a combination of a metal-to-metal bond and a dielectric-to-dielectric bond at the additional bonding interface 1618.

[0088] Additional bonding structure 1616 includes an additional bonding dielectric layer 1620 that is separate from second IC die 104b and third IC die 104c and that is bonded in direct contact at additional bonding interface 1618. Additionally, additional bonding structure 1616 includes additional bonding pads 1622 that are separate from second IC die 104b and third IC die 104c and that is bonded in direct contact at additional bonding interface 1618. Additional bonding pads 1622 are respectively inserted in additional bonding dielectric layer 1620 and are electrically coupled to third interconnect structure 1614 and TSV 1626 by additional bonding vias 1624 in additional bonding dielectric layer 1620, respectively.

[0089] The TSVs 1626 extend through the second semiconductor substrate 1404 from the second interconnect structure 1432 to the additional junction structure 1616 to provide electrical coupling therebetween. The TSVs 1626 are further separated from the second semiconductor substrate 1404 by a TSV dielectric layer 1628.

[0090] The third transistor 804 and the third interconnect structure 1614 form an ASIC 802 that is electrically coupled to the pixel sensor 102 via an additional junction structure 1616 and a TSV 1626. The ASIC 802 may be configured to perform, for example, an ADC, buffering, image processing, etc., or any combination thereof, on the output of the pixel sensor 102.

[0091] 17, a cross-sectional view 1700 of some embodiments of the image sensor of FIG. 14 is provided, in which the image sensor includes conductive pads 1702. The conductive pads 1702 are located at the periphery of the image sensor and are exposed from the backside of the first semiconductor substrate 1402 by pad openings 1704. The conductive pads 1702 are electrically coupled (e.g., shorted) to the bulk 1402b of the first semiconductor substrate 1402 by the first interconnect structure 1430, independent of the second interconnect structure 1432. The electrical coupling connects the bulk 1402b of the first semiconductor substrate 1402 from the backside of the first semiconductor substrate 1402 to a negative voltage V NV This allows biasing.

[0092] The second interconnect structure 1432 and the bulk 1404b of the second semiconductor substrate 1404 are electrically isolated from the conductive pad 1702 so as not to be exposed to the relatively high voltage at the first IC chip 104a. As mentioned above, the relatively high voltage is therefore applied to the bulk 1402b of the first semiconductor substrate 1402 by the negative voltage V NV This results in an increase in the FWC of the pinned photodiode 106. By isolating the second interconnect structure 1432 from the relatively high voltage, design constraints can be relaxed and reliability can be improved.

[0093] During the fabrication of the image sensor, the image sensor is formed in bulk, with multiple instances of the image sensor being formed simultaneously on a common wafer. The common wafer is then diced to separate the multiple instances from one another. Such dicing occurs along dicing or scribe lines that correspond to the perimeter or outermost sidewalls of the image sensor as depicted in FIG. 17 . Because the perimeter or outermost sidewalls are exposed during and / or after dicing, it is possible for defects (such as dust particles) to form along the perimeter or outermost sidewalls, which could result in an electrical short from the first semiconductor substrate 1402 to the second semiconductor substrate 1404.

[0094] As described above, the bulk 1402b of the first semiconductor substrate 1402 and the bulk 1404b of the second semiconductor substrate 1404 are electrically isolated from each other and are connected to a negative voltage V NV and biased at ground GND. Electrical shorts caused by dicing may oppose this, for example causing ground faults, and the image sensor may have peripheral isolation in the first semiconductor substrate 1402 as described below.

[0095] 18, a cross-sectional view 1800 of some alternative embodiments of the image sensor of FIG. 17 is provided, in which the first semiconductor substrate 1402 has peripheral isolation. More specifically, isolation trenches 1802 extend completely through the first semiconductor substrate 1402 at the periphery of the first semiconductor substrate 1402 to separate the first semiconductor substrate 1402 into a peripheral portion 1402p and an interior portion 1402i. Furthermore, the conductive pads 1702 are in the isolation trenches 1802 and are exposed from the backside of the first semiconductor substrate 1402.

[0096] The interior 1402i contains the bulk 1402b of the first semiconductor substrate 1402, the pinned photodiode 106, and the first transistor 110, and is further surrounded by a peripheral portion 1402p that is physically and electrically isolated from the interior 1402i. In this manner, the peripheral portion 1402p is electrically floating or electrically connected (e.g., shorted) to ground GND, and the interior 1402i is connected to a negative voltage V NV are electrically connected (e.g., shorted) to

[0097] Since the peripheral portion 1402p is electrically isolated from the inner portion 1402i, an electrical short circuit between the bulk 1402b of the first semiconductor substrate 1402 and the bulk 1404b of the second semiconductor substrate 1404 can be prevented even if a defect (such as a dust particle) occurs along the periphery or outermost sidewall of the image sensor during dicing and / or dicing. NV This can prevent an electrical short circuit between the power supply and ground GND.

[0098] Referring to Figure 19, a top layout diagram 1900 of some embodiments of the image sensor of Figure 18 is provided. The image sensor includes a plurality of pixel sensors 102 in a plurality of rows and a plurality of columns, and further includes a plurality of conductive pads 1702 within isolation trenches 1802 (not shown). Furthermore, the isolation trenches 1802 extend in a closed circuit that completely surrounds the plurality of pixel sensors 102 and the plurality of conductive pads 1702. The cross-sectional view of Figure 18 may be taken, for example, along line B-B' in Figure 19, and the pixel sensors 102 in Figure 18 may correspond, for example, to any one of the pixel sensors 102 along line B-B'.

[0099] 20A-20C, cross-sectional views 200A-2000C of several alternative embodiments of the image sensor of FIG. 18 are provided.

[0100] 20A, isolation trenches 1802 can be partially filled with trench-fill dielectric layer 2002. For example, trench-fill dielectric layer 2002 can fill isolation trenches 1802 around conductive pads 1702, leaving conductive pads 1702 exposed. Filling isolation trenches 1802 eliminates concerns of defective material causing electrical shorts (e.g., between conductive pads) in isolation trenches 1802 during and / or dicing.

[0101] 20B, the isolation trench 1802 has been replaced with an isolation region 2004 and a pad opening 1704 that extends through the isolation region 2004 to expose the conductive pad 1702. The isolation region 2004 is at the periphery or outermost sidewall of the first semiconductor substrate 1402 and extends completely through the first semiconductor substrate 1402. Furthermore, the isolation region 2004 corresponds to a doped region of the first semiconductor substrate 1402 that has an opposite doping type than the bulk 1402b of the first semiconductor substrate 1402. For example, the isolation region 2004 may be n-type and the bulk 1402b of the first semiconductor substrate 1402 may be p-type.

[0102] Due to the opposite doping types, the isolation region 2004 and the bulk 1402b of the first semiconductor substrate 1402 form a PN junction. The PN junction creates a depletion region that completely electrically isolates the bulk 1402b of the first semiconductor substrate 1402 from the periphery or outermost sidewalls of the first semiconductor substrate 1402. That is, such isolation prevents the application of a negative voltage V NV This eliminates concerns about an electrical short between the power supply and ground GND.

[0103] The isolation region 2004 is further electrically coupled (e.g., shorted) to the bulk 1404b of the second semiconductor substrate 1404, and thus electrically coupled (e.g., shorted) to ground GND by the first and second interconnect structures 1430, 1432. Electrically coupling the isolation region 2004 to ground GND increases the size of the depletion formed by the PN junction, thereby improving isolation. In alternative embodiments, the isolation region 2004 is electrically floating and / or electrically coupled to any conductive feature in the first and second interconnect structures 1430, 1432.

[0104] 20C, the isolation trenches 1802 have been replaced with keep-out zones (KOZ) 2006 in which the perimeter or outermost sidewalls of the first semiconductor substrate 1402 are offset from the perimeter or outermost sidewalls of the first interconnect structures 1430 by a distance D. This reduces the likelihood of bad material causing an electrical short from the perimeter or outermost sidewalls of the first semiconductor substrate 1402 to the perimeter or outermost sidewalls of the second semiconductor substrate 1404 during and / or dicing.

[0105] 21 , cross-sectional views 2100 of some alternative embodiments of the image sensor of FIG. 18 are provided, in which the image sensor includes a plurality of pixel sensors 102 and a third IC chip 104c. The pixel sensors 102 are each as described with respect to FIG. 16 and are separated from one another by trench isolation structures 2102 in the first semiconductor substrate 1402. The trench isolation structures 2102 comprise a dielectric material and may be, for example, shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, or the like, or any combination thereof. In some embodiments, the pixel sensors 102 correspond to the circuit diagram 800 of FIG. 8 or the circuit diagram 1000 of FIG. 10.

[0106] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33, a series of illustrations of several embodiments of methods for forming stacked CMOS image sensors with high FWC are provided.

[0107] 22, 23A, 23B, and 24, a first IC chip 104a is formed that includes a first portion 102a of a pixel sensor. The first portion 102a includes a pinned photodiode 106 and a first transistor 110. Furthermore, the anode of the pinned photodiode 106 and the body of the first transistor 110 are connected to a first substrate terminal T of the image sensor to be formed. sub1 are electrically connected (e.g., shorted) to

[0108] 22, the pinned photodiode 106 and the floating diffusion node FD1 are formed in a first semiconductor substrate 1402. A bulk 1402b of the first semiconductor substrate 1402 is connected to a first substrate terminal T sub11406 and defines the anode of the pinned photodiode 106. The pinned photodiode 106 and the floating diffusion node FD1 are laterally separated from one another, and the pinned photodiode 106 includes a collector region 1406 and a pinning region 1408 that covers the collector region 1406.

[0109] The collector region 1406, the pinning region 1408, and the floating diffusion node FD1 correspond to doped regions in the first semiconductor substrate 1402. The collector region 1406 and the floating diffusion node FD1 share a first common doping type, and the pinning region 1408 and the bulk 1402b of the first semiconductor substrate 1402 share a second common doping type that is opposite to the first common doping type. For example, the first common doping type may be n-type and the second common doping type may be p-type. Furthermore, the pinning region 1408 and the bulk 1402b of the first semiconductor substrate 1402 surround the collector region 1406 and the floating diffusion node FD1, and the boundary between the collector region 1406 and the floating diffusion node FD1 is defined by a PN junction.

[0110] 22, a first gate dielectric layer 1412 and a first gate electrode layer 2202 are deposited over the first semiconductor substrate 1402. The first gate dielectric layer 1412 separates the first gate electrode layer 2202 from the first semiconductor substrate 1402. The first gate electrode layer 2202 is conductive and may be or include, for example, doped polysilicon, a metal, other suitable conductive material, or any combination thereof.

[0111] As shown in cross-sectional view 2300A of Figure 23A and circuit diagram 2300B of Figure 23B, the first gate electrode layer 2202 is patterned to form a first gate electrode 1410. The first gate electrode 1410 is laterally between the collector region 1406 and the floating diffusion node FD1. Furthermore, the first gate electrode 1410 is separated from the first semiconductor substrate 1402 by a first gate dielectric layer 1412 that continues to cover the pinned photodiode 106 after patterning.

[0112] The patterning may be performed, for example, by a photolithography / etching process or other suitable patterning process. The photolithography / etching process may include, for example, forming a mask over the first gate electrode layer 2202 and etching the first gate electrode layer 2202 with the mask in place. Although the etch is shown as stopping before etching into the first gate dielectric layer 1412, it may alternatively etch partially or completely through the first gate dielectric layer 1412.

[0113] 23A , first sidewall spacers 1414 are formed on the sidewalls of the first gate electrode 1410, having pairs of segments that sandwich the first gate electrode 1410. The first sidewall spacers 1414 are dielectric and may be formed, for example, by depositing a dielectric layer on the first gate electrode 1410 and etching back the dielectric layer, although other suitable processes are also applicable.

[0114] The first gate electrode 1410, the first gate dielectric layer 1412, and the first sidewall spacers 1414, together with the collector region 1406, the floating diffusion node FD1, and the bulk 1402b of the first semiconductor substrate 1402, form the first transistor 110. The collector region 1406 and the floating diffusion node FD1 serve as a first source / drain region 1416 pair for the first transistor 110. The bulk 1402b of the first semiconductor substrate 1402 serves as the body of the first transistor 110. During use of the first transistor 110, a first channel region 1418 in the first semiconductor substrate 1402 separating the collector region 1406 and the floating diffusion node FD1 changes between a non-conductive state and a conductive state depending on the voltage at the first gate electrode 1410. This allows selective transfer of charge stored in the collector region 1406 to the floating diffusion node FD1, whereby the first transistor 110 is also referred to as the transfer transistor 114.

[0115] 24, a first interconnect structure 1430 is formed above and electrically coupled to the first transistor 110 and the floating diffusion node FD1. The first interconnect structure 1430 includes a plurality of conductive wires 1434 and a plurality of conductive vias 1436 in an interconnect dielectric layer 1438. The conductive wires 1434 and conductive vias 1436 are grouped into multiple wire levels and multiple via levels that are alternately stacked to define a conductive path.

[0116] 24, a first bonding structure 1440a is formed on the first interconnect structure 1430. The first bonding structure 1440a includes a bonding pad 1446 and a bonding via 1448 in a bonding dielectric layer 1444. The bonding pad 1446 and the bonding dielectric layer 1444 form a common bonding surface, and the bonding via 1448 extends from the bonding pad 1446 to the first interconnect structure 1430.

[0117] 25, 26A, and 26B, a second IC chip 104b is formed that includes a second portion 102b of the pixel sensor. The second portion 102b is connected to a second substrate terminal T sub2 The second transistors 112 have respective bodies electrically coupled (eg, shorted) to the first transistor 112.

[0118] 25, the plurality of second transistors 112 are formed on the second semiconductor substrate 1404. Furthermore, the bulk 1404b of the second semiconductor substrate 1404 is connected to the second substrate terminal T sub2 26B , which defines or is electrically coupled (e.g., shorted) to the respective bodies of the second transistors 112. Note that only one second transistor 112, the reset transistor 116, is shown, although additional second transistors (e.g., select transistors and source follower transistors) are shown below in FIG. 26B .

[0119] The second transistor 112 includes a pair of separate second gate electrodes 1420, separate second gate dielectric layers 1422, separate second sidewall spacers 1424, and separate second source / drain regions 1426. The second gate electrodes 1420 are stacked with the second gate dielectric layers 1422 that separate the second gate electrodes 1420 from the second semiconductor substrate 1404. The second sidewall spacers 1424 are respectively on the sidewalls of the second gate electrodes 1420 and on the sidewalls of the second gate dielectric layers 1422.

[0120] The pair of second source / drain regions 1426 are in the second semiconductor substrate 1404 and correspond to doped regions of the second semiconductor substrate 1404 having an opposite doping type to the bulk 1404b of the second semiconductor substrate 1404. The source / drain regions of each pair of second source / drain regions 1426 are separated by a second channel region 1428 in the second semiconductor substrate 1404. The second channel region 1428 changes between a non-conductive state and a conductive state depending on the voltage at a respective one of the second gate electrodes 1420. Furthermore, the source / drain region of one of the pair of second source / drain regions 1426 of the reset transistor 116 defines a floating diffusion node FD2 of the image sensor to be formed.

[0121] As shown in cross-sectional view 2600A of Figure 26A and circuit diagram 2600B of Figure 26B, a second interconnect structure 1432 and a second junction structure 1440b are formed. The second interconnect structure 1432 is overlying and electrically coupled to the second transistor 112. The second junction structure 1440b is overlying and electrically coupled to the second interconnect structure 1432. The second interconnect structure 1432 and the second junction structure 1440b are similar to the first interconnect structure 1430 and the first junction structure 1440a described with respect to Figure 24.

[0122] 26B, the plurality of second transistors 112 includes a reset transistor 116, a source follower transistor 118, and a select transistor 120, which are electrically interconnected by a second interconnect structure 1432 (see, e.g., FIG. 26A). The source follower transistor 118 and the select transistor 120 are electrically coupled in series. Furthermore, the reset transistor 116 has a source / drain region electrically coupled (e.g., shorted) to the gate electrode of the source follower transistor 118.

[0123] As depicted in paragraph 2700A of Figure 27A and circuit diagram 2700B of Figure 27B, second IC chip 104b of Figures 26A and 26B is flipped vertically and bonded to first IC chip 104a of Figure 24 at first bonding interface 1442. The bond includes both a metal-to-metal bond and a dielectric-to-dielectric bond.

[0124] The bonding forms the pixel sensor 102 from the first portion 102a of the pixel sensor 102 in Figure 24 and from the second portion 102b of the pixel sensor 102 in Figures 26A and 26B, and further electrically couples the floating diffusion nodes FD1, FD2 in the first portion 102a and the second portion 102b, respectively, to form a common floating diffusion node FD spanning the first and second IC chips 104a, 104b. sub1 and the second board terminal T sub2 are electrically isolated from each other, and the bulk 1402b of the first semiconductor substrate 1402 and the bulk 1404b of the second semiconductor substrate 1404 are electrically isolated from each other. As will be explained hereinafter, this is the first substrate terminal T sub1 and the second board terminal T sub2 are biased at a negative voltage and ground, respectively, allowing for increased FWC.

[0125] Because the pixel sensor 102 spans the first and second IC chips 104a, 104b, the pixel sensor 102 has fewer transistors on the first IC chip 104a than it would otherwise have. For example, instead of having four transistors on the first IC chip 104a, the pixel sensor 102 may only have one transistor on the first IC chip 104a. This allows the pixel sensor 102 to be scaled on the first IC chip 104a without scaling the pinned photodiode 106.

[0126] Because the pinned photodiode 106 is relatively large and is located on the first IC chip 104a rather than the second IC chip 104b, the portion of the pixel sensor 102 on the first IC chip 104a may limit the miniaturization of the pixel sensor 102. Therefore, miniaturizing the pixel sensor 102 on the first IC chip 104a can have the effect of miniaturizing the entire pixel sensor 102. As described above, because the pixel sensor 102 can be miniaturized without miniaturizing the pinned photodiode 106, the performance of the pixel sensor 102 can be improved even in a small size.

[0127] 28, the second semiconductor substrate 1404 is thinned on a side opposite the second interconnect structure 1432 and the second transistor 112. The thinning may be performed, for example, by chemical mechanical polishing (CMP).

[0128] 28, TSV 1626 is formed to extend through second semiconductor substrate 1404 to second interconnect structure 1432. Further, TSV 1626 is formed to be separated from second semiconductor substrate 1404 and interconnect dielectric layer 1438 of second interconnect structure 1432 by TSV dielectric layer 1628. TSV 1626 is conductive to provide electrical coupling from the backside of second semiconductor substrate 1404 to second interconnect structure 1432.

[0129] 29, a third bonding structure 1616a is formed on the backside of the second semiconductor substrate 1404. The third bonding structure 1616a includes a bonding pad 1622 and a bonding via 1624 in a bonding dielectric layer 1620. The bonding pad 1622 and the bonding dielectric layer 1620 form a common bonding surface, and the bonding via 1624 extends from the bonding pad 1622 to a TSV 1626.

[0130] As shown in Figures 30, 31A and 31B, a third IC chip 104c is formed that includes an ASIC 802. The ASIC 802 is connected to the third substrate terminal T sub3 8. The third transistor 804 includes a plurality of third transistors 804 having respective bodies electrically coupled (eg, shorted) to the

[0131] 30, the plurality of third transistors 804 are formed on the third semiconductor substrate 1602. Furthermore, the bulk 1602b of the third semiconductor substrate 1602 is connected to the third substrate terminal T sub3 31B , and defines or is electrically coupled to (e.g., shorted to) individual bodies of at least some of the third transistors 804. For example, the bulk 1602b of the third semiconductor substrate 1602 may define or be electrically coupled to (e.g., shorted to) an n-type transistor 804n of the plurality of third transistors 804, rather than a p-type transistor of the plurality of third transistors 804. Note that only one third transistor 804 is shown, although additional transistors are shown hereinafter in FIG.

[0132] The third transistor 804 includes a pair of individual third gate electrodes 1604, individual third gate dielectric layers 1606, individual third sidewall spacers 1608, and individual third source / drain regions 1610. The third gate electrodes 1604 are stacked with the third gate dielectric layers 1606, which separate the third gate electrodes 1604 from the second semiconductor substrate 1602. The third sidewall spacers 1608 are on the sidewalls of the third gate electrodes 1604 and the third gate dielectric layers 1606, respectively.

[0133] A pair of third source / drain regions 1610 are in the third semiconductor substrate 1602 and correspond to doped regions of the third semiconductor substrate 1602 having an opposite doping type to immediately adjacent regions of the third semiconductor substrate 1602. Furthermore, the source / drain regions of each pair of third source / drain regions 1610 are separated by a third channel region 1612 in the third semiconductor substrate 1602. The third channel region 1612 changes between a non-conducting state and a conducting state depending on the voltage at a respective one of the third gate electrodes 1604.

[0134] As shown in cross-sectional view 3100A of Figure 31A and circuit diagram 3100B of Figure 31B, a third interconnect structure 1614 and a fourth junction structure 1616b are formed. The third interconnect structure 1614 is overlying and electrically coupled to the third transistor 804. Furthermore, the third interconnect structure 1614 is similar to the first interconnect structure 1430 described with reference to Figure 24. The fourth junction structure 1616b is overlying and electrically coupled to the third interconnect structure 1614. Furthermore, the fourth junction structure 1616b is similar to the third junction structure 1616a described with reference to Figure 29.

[0135] 31B, the plurality of third transistors 804 includes at least one n-type transistor 804n and at least one p-type transistor 804p. Note that ellipses are used in ASIC 802 to represent zero or more additional third transistors.

[0136] As shown in cross-sectional view 3200A of FIG. 32A and circuit diagram 3200B of FIG. 32B, the structure of FIG. 29 is flipped vertically and bonded to the third IC chip 104c of FIGS. 31A and 31B at a second bonding interface 1618. The bonding electrically couples the pixel sensor 102 to the ASIC 802 and includes both a metal-to-metal and a dielectric-to-dielectric bond. Furthermore, the bonding includes a first substrate terminal T sub1 and the third board terminal T sub3 are electrically isolated from each other, and the bulk 1402b of the first semiconductor substrate 1402 and the bulk 1602b of the third semiconductor substrate 1602 are electrically isolated from each other. In some embodiments, the bond electrically couples (e.g., shorts) the bulk 1404b of the second semiconductor substrate 1404 and the bulk 1602b of the third semiconductor substrate 1602 together.

[0137] 33, the first semiconductor substrate 1402 is thinned from the side opposite the first interconnect structure 1430 and the first transistor 110. The thinning may be performed by CMP or the like.

[0138] 33, pad openings 1704 are formed around the periphery of the first semiconductor substrate 1402 and extending through the first semiconductor substrate 1402. Furthermore, conductive pads 1702 are formed in the pad openings 1704 and are electrically coupled to the bulk 1402b of the first semiconductor substrate 1402 by first interconnect structures 1430.

[0139] During use of the image sensor, the bulk 1402b of the first semiconductor substrate 1402 is connected to a negative voltage V NV (e.g., via the first substrate terminal Tsub1 and / or the conductive pad 1702), and the bulk 1404b of the second semiconductor substrate 1404 is biased to ground GND (e.g., via the second substrate terminal T sub2 Furthermore, the bulk 1602b of the third semiconductor substrate 1602 is biased to ground GND (for example, via the third substrate terminal T sub3 As a result of this biasing, the anode of the pinned photodiode 106 and the body of the first transistor 110 are coupled to the negative voltage V NVIn addition, the individual body of the second transistor 112 is electrically coupled (e.g., shorted) to ground GND on the second IC chip 104b.

[0140] The anode of the pinned photodiode 106 and the body of the first transistor 110 are connected to a negative voltage V NV , the pinning voltage of the pinned photodiode 106 and the turn-on voltage of the first transistor 110 are not ground GND but a negative voltage V NV This means that these voltages are compared to the negative voltage V NV , which increases the FWC of the pinned photodiode 106 and thus improves the performance of the pinned photodiode 106.

[0141] The voltage of the second transistor 112 is a negative voltage V NV Because the second transistor 112 is connected to ground GND rather than to the pinned photodiode 106, the second transistor 112 is not subjected to the relatively high voltages experienced by the pinned photodiode 106 and the first transistor 110. Therefore, the ruggedness and reliability of the second transistor 112 are not affected by the relatively high voltages at the pinned photodiode 106 and the first transistor 110. Furthermore, the power consumption of the second transistor 112 is not affected (e.g., is not increased) by the relatively high voltages.

[0142] 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 are described with reference to a method, it should be understood that the structures shown in these figures are not limited to the method and may be separate and independent from the method. 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 are described as a series of operations, it should be understood that in other embodiments, the order of the operations may be changed. 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 are shown and described as a particular set of operations, it should be understood that some of the operations shown and / or described may be omitted in other embodiments. Furthermore, operations not shown and / or described may be included in other embodiments.

[0143] Referring to FIG. 34, a block diagram 3400 of some embodiments of the methods of FIGS. 22, 23A, 23B, 24, 25, 26A, 26B, 27A, 27B, 28-30, 31A, 31B, 32A, 32B, and 33 is provided.

[0144] In 3402, a first IC chip is formed that includes a first portion of a pixel sensor. The first portion includes a pinned photodiode and a first transistor. Further, an anode of the pinned photodiode and a body of the first transistor are electrically coupled together. See, e.g., Figures 22, 23A, 23B, and 24. Such formation includes operations 3402a-3402c. In 3402a, a pinned photodiode is formed in a first semiconductor substrate, and a bulk of the first semiconductor substrate defines or is electrically coupled to the anode of the pinned photodiode. See, e.g., Figure 22. In 3402b, a first transistor is formed on the first semiconductor substrate adjacent to the pinned photodiode, and a bulk of the first semiconductor substrate defines or is electrically coupled to the body of the first transistor. See, e.g., Figures 22, 23A, and 23B. At 3402c, a first interconnect structure is formed overlying and electrically coupled to the first transistor and the pinned photodiode (see, e.g., Figure 24).

[0145] At 3404, a second IC chip is formed that includes a second portion of the pixel sensor. The second portion includes a plurality of second transistors whose individual bodies are electrically coupled together. See, e.g., Figures 25, 26A, and 26B. Such formation includes operations 3404a and 3404b. At 3404a, second transistors are formed on a second semiconductor substrate, the bulk of the second semiconductor substrate defining or electrically coupled to the individual bodies of the second transistors. See, e.g., Figure 25. At 3404b, a second interconnect structure is formed over and electrically coupled to the second transistors. See, e.g., Figures 26A and 26B.

[0146] At 3406, the first IC chip and the second IC chip are bonded together at a first bonding interface. The bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other upon completion of bonding. See, e.g., Figures 27A and 27B.

[0147] At 3408, TSVs are formed that extend through the second semiconductor substrate to the second interconnect structure. See, for example, FIG.

[0148] At 3410, a junction structure is formed on the second semiconductor substrate opposite the second interconnect structure, covering and electrically coupling to the TSV (see, for example, FIG. 29).

[0149] At 3412, a third IC chip is formed that includes an ASIC. The ASIC includes a plurality of third transistors on a third semiconductor substrate, the bulk of the third semiconductor substrate defining or electrically coupling to the individual bodies of at least some of the third transistors. See, e.g., Figures 30, 31A, and 31B.

[0150] At 3414, the second IC chip and the third IC chip are bonded together at a second bonding interface. See, for example, Figures 32A and 32B.

[0151] At 3416, a pad is formed that is electrically coupled to the bulk of the first semiconductor substrate and exposed through the pad opening in the first semiconductor substrate. See, for example, FIG.

[0152] Although block diagram 3400 of Figure 34 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts, separate from those illustrated and / or described herein. Furthermore, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts illustrated herein may occur in one or more separate acts and / or phases.

[0153] During image sensor manufacturing, image sensors are formed in bulk, with multiple instances of the image sensor formed simultaneously on a common wafer. The common wafer is then diced to separate the multiple instances from one another. Such dicing occurs along dicing or scribe lines that correspond to the perimeter or outermost sidewalls of the image sensor, as depicted in FIG. 33 . Because the perimeter or outermost sidewalls are exposed during and / or after dicing, defects (such as dust particles) can form along the perimeter or outermost sidewalls. This can cause electrical shorts from the first semiconductor substrate 1402 to the second semiconductor substrate 1404.

[0154] As described above, the bulk 1402b of the first semiconductor substrate 1402 and the bulk 1404b of the second semiconductor substrate 1404 are electrically isolated from each other and are connected to a negative voltage V NV and biased at ground GND. Electrical shorts caused by dicing may oppose this, for example, causing a ground fault, and the image sensor may have peripheral isolation in the first semiconductor substrate 1402.

[0155] 35-37, cross-sectional views 3500-3700 of several alternative embodiments of the operations described with respect to FIG. 33 are provided in which peripheral isolation eliminates concerns about electrical shorts between the first semiconductor substrate 1402 and the second semiconductor substrate 1404 during and / or after dicing.

[0156] 35, instead of forming pad openings 704, isolation trenches 1802 may be formed, and conductive pads 1702 may be formed in the isolation trenches 1802. Like the pad openings 1704, the isolation trenches 1802 may be formed, for example, by a photolithography / etching process or other suitable patterning process. The isolation trenches 1802 extend completely through the second semiconductor substrate 1402 and further extend in a closed circuit along the periphery of the first semiconductor substrate 1402. In this manner, the isolation trenches 1802 separate the first semiconductor substrate 1402 into a peripheral portion 1402p and an interior portion 1402i both physically and electrically. The top layout of the isolation trenches 1802 may be, for example, as shown in FIG. 19, and / or FIG. 35 may be taken along line B-B' in FIG. 19.

[0157] Due to this isolation, any defective material that occurs on the periphery or outermost sidewalls of the image sensor (corresponding to the sidewalls of the peripheral portion 1402p) during and / or after dicing is electrically isolated from the interior 1402i that contains the bulk 1402b of the first semiconductor substrate 1402.

[0158] 36, an isolation region 2004 is formed that extends completely through the first semiconductor substrate 1402 and further extends in a closed circuit along the periphery of the second semiconductor substrate 1404. The isolation region 2004 corresponds to a doped region in the first semiconductor substrate 1402 and has an opposite doping type to the bulk 1402b of the first semiconductor substrate 1402. In this manner, the isolation region 2004 and the bulk 1402b of the first semiconductor substrate 1402 form a PN junction with a depletion region that electrically isolates the periphery or outermost sidewall of the first semiconductor substrate 1402 from the bulk 1402b of the first semiconductor substrate 1402. The isolation region 2004 may be formed, for example, by ion implantation or other suitable doping process.

[0159] In some embodiments, first and second interconnect structures 1430, 1432 and first and second junction structures 1440a, 1440b are further formed to electrically couple the isolation region 2004 to the bulk 1404b of the second semiconductor substrate 1404. During use of the image sensor, this results in an electrical connection between the isolation region 2004 and ground GND, which can, for example, increase the size of the depletion region at the PN junction.

[0160] 37, instead of forming pad openings 1704, KOZ 2006 is formed, and conductive pads 1702 may be formed in KOZ 2006. KOZ 2006 corresponds to the region where the perimeter or outermost sidewall of first semiconductor substrate 1402 is offset from the perimeter or outermost sidewall of second semiconductor substrate 1404 by a distance D. This reduces the likelihood of defective material electrically shorting first semiconductor substrate 1402 and second semiconductor substrate 1404 during and / or after dicing. KOZ 2006 may be formed by, for example, a photolithography / etching process or other suitable patterning process.

[0161] In some embodiments, the present disclosure provides an image sensor including a first IC chip including a first semiconductor substrate, a second IC chip including a second semiconductor substrate and stacked on the first IC chip, and a pixel sensor spanning the first IC chip and the second IC chip, wherein the pixel sensor includes a first transistor and a light-receiving element in the first semiconductor substrate and further includes a second transistor in the second semiconductor substrate, wherein the bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other and configured to be biased at different voltages. In some embodiments, the body of the first transistor is defined by the bulk of the first semiconductor substrate, and the body of the second transistor is defined by the bulk of the second semiconductor substrate. In some embodiments, the first semiconductor substrate is over the second semiconductor substrate, and the image sensor further includes a pad exposed on the first semiconductor substrate, the pad being electrically coupled to the bulk of the first semiconductor substrate. In some embodiments, the first transistor includes a gate dielectric layer having a first thickness, and the second transistor includes a gate dielectric layer having a second thickness less than the first thickness. In some embodiments, the first transistor includes a first gate stack and a first sidewall spacer on a sidewall of the first gate stack, and the second transistor includes a second gate stack and a first sidewall spacer on a sidewall of the second gate stack, wherein the thickness of the second sidewall spacer is less than the thickness of the first sidewall spacer. In some embodiments, the pixel sensor is a 4T APS. In some embodiments, the pixel sensors are repeated in multiple rows and multiple columns, and the repetition of the pixel sensors is non-overlapping.

[0162] In some embodiments, the present disclosure provides another image sensor including a first substrate, a photodiode and a first transistor adjacent to each other on the first substrate, a second substrate underlying the first substrate, and a second transistor on the second substrate, wherein the photodiode, the first transistor, and the second transistor form a pixel sensor, and the body of the first transistor and the anode of the photodiode are electrically coupled together and electrically isolated from the body of the second transistor. In some embodiments, the body of the second transistor and the body of the first transistor are configured to be simultaneously biased to ground and a negative voltage, respectively. In some embodiments, the image sensor further includes an interconnect structure between the first substrate and the second substrate, and a pad located on the periphery of the first substrate and electrically coupled to the anode of the photodiode by the interconnect structure. In some embodiments, a trench extends laterally along the periphery of the first substrate in a closed circuit surrounding the photodiode and the first transistor, and further extends vertically through the first substrate to separate the first substrate into an interior and a periphery that are electrically isolated from each other. In some embodiments, the first substrate and the second substrate have respective sidewalls extending in separate closed paths around the peripheries of the first substrate and the second substrate, and in a top view, the respective sidewalls of the first substrate are laterally offset from and surrounded by the respective sidewalls of the second substrate. In some embodiments, the first substrate includes a semiconductor material and has a PN junction that extends laterally along the periphery of the first substrate in a closed path surrounding the photodiode and the first transistor and also extends vertically through the first substrate to electrically isolate the interior of the first substrate from the outermost sidewalls of the first substrate. In some embodiments, the image sensor further includes a third substrate stacked with the first and second substrates and a plurality of third transistors on the third substrate, the second substrate being between the first and third substrates, and the third transistors forming an application specific integrated circuit (ASIC) electrically coupled to the pixel sensor.

[0163] In some embodiments, the present disclosure provides a method for forming an image sensor, the method including: forming a first IC chip including: forming a photodiode on a first semiconductor substrate; and forming a first transistor on the first semiconductor substrate adjacent to the photodiode, where the photodiode and the first transistor form a first pixel sensor portion; forming a second IC chip including: forming a plurality of second transistors on a second semiconductor substrate, where the second transistor forms a second pixel sensor portion; and bonding the first IC chip and the second IC chip together such that the first pixel sensor portion and the second pixel sensor portion are stacked and electrically coupled together to form a pixel sensor, where the bulk of the first semiconductor substrate and the bulk of the second semiconductor substrate are electrically isolated from each other upon completion of bonding. In some embodiments, forming the first IC chip further includes forming a first interconnect structure overlying the first transistor, and the method further includes, after the bonding, forming pads on the periphery of the first semiconductor substrate electrically coupled to the first interconnect structure, the first interconnect structure electrically coupling the pads to the first semiconductor substrate. In some embodiments, the method further includes patterning the first semiconductor substrate to form trenches extending laterally along the periphery of the first semiconductor substrate in a closed circuit surrounding the photodiode and the first transistor and extending vertically through the first semiconductor substrate to separate the first semiconductor substrate into electrically isolated interior and peripheral portions, the pads being formed in the trenches. In some embodiments, the anode of the photodiode and the body of the first transistor are electrically isolated from the individual body of the second transistor upon completion of the bonding. In some embodiments, the bonding includes both metal-to-metal and dielectric-to-dielectric junctions.In some embodiments, the method further includes forming a third IC chip, the third IC chip including forming a plurality of third transistors on the third semiconductor substrate and forming a third interconnect structure overlying the third transistors, the third transistors and the third interconnect structure forming an application specific integrated circuit (ASIC), and bonding the second IC chip and the third IC chip together such that the second IC chip is between the first IC chip and the third IC chip, and the ASIC is electrically coupled to the pixel sensor.

[0164] The foregoing outlines features of several embodiments so that those skilled in the art may more easily understand aspects of the present disclosure. Those skilled in the art should appreciate that this disclosure may readily serve as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure. [Industrial Applicability]

[0165] The image sensors of the present disclosure can be used in a wide range of modern electronic devices, such as cameras, cell phones, etc., and the image sensor forming methods of the present disclosure can be used to form such image sensors. [Explanation of symbols]

[0166] 100, 400, 500A, 500B, 600, 700, 800, 1000, 2300B, 2600B, 2700B, 3100B, 3200B: Schematic 102: Pixel sensor 102a:102, first part 102b:2nd part of 102 102s: subpixel 104a: First IC chip 104b: Second IC chip 104c: Third IC chip 106: Pinned photodiode 108: Pixel circuit 110: First transistor 112: Second transistor 114: Transfer transistor 116: Reset transistor 118: Source follower transistor 120: Select transistor 200:Electrogram 202: First potential well 204: Second potential well 206: Barrier 300, 900, 1100, 1300: Schematic cross section 302, 902: Radiation 402: Body diode 702: Auxiliary pixel circuit 802:ASIC 804: Third transistor 804n: n-type transistor 804p: p-type transistor 1200, 1900: Upper layout diagram 1400, 1500A, 1500B, 1600, 1700, 1800, 2000A, 2000B, 2000C, 2100, 2200, 2300A, 2400, 2500, 2600A, 2700A, 2800, 2900, 3000, 3100A, 3200A, 3300, 3500, 3600, 3700: Cross section 1402: First semiconductor substrate 1402b:1402 bulk 1402i: Inside the 1402 1402p: Periphery of 1402 1404: second semiconductor substrate 1404b:Bulk of 1404 1406: Collector area 1408: Pinning area 1410: First gate electrode 1412: First gate dielectric layer 1414: First sidewall spacer 1416: First source / drain region 1418: First channel region 1420: second gate electrode 1422: Second gate dielectric layer 1424: Second sidewall spacer 1426: Second source / drain region 1428: Second channel region 1430: First interconnect structure 1432: Second interconnect structure 1434: Conductive wire 1436: Conductive via 1438: interconnect dielectric layer 1440:Joint structure 1440a: 1st joint structure 1440b:Second joint structure 1442:Joint interface 1444: Bonding dielectric layer 1446: Bonding pad 1448: Junction via 1502, 1526: Through-substrate vias (TSV) 1504, 1628: TSV dielectric layer 1602: Third semiconductor substrate 1602b:1602 bulk 1604: Third gate electrode 1606: Third gate dielectric layer 1608: Third sidewall spacer 1610: Third source / drain region 1612: Third channel region 1614: Third interconnect structure 1616: Additional joint structures 1616a: Third joint structure 1616b: 4th joint structure 1620: Additional bonding dielectric layer 1622: Additional bonding pads 1624: Additional junction vias 1702: Conductive pad 1704: Pad opening 1802: Isolation Trench 2002: Trench-filling dielectric layer 2004: Quarantine area 2006: Keep Out Zone 2102: Trench isolation structure 2202: First gate electrode layer 3400: Block diagram 3402, 3404, 3406, 3408, 3410, 3412, 3414, 3416: Step 3402a, 3402b, 3402c, 3404a, 3404b: Operation A-A', B-B': Section line C1, C2, C3, C N : Pixel sensor row D: Distance FD, FD1, FD2: Floating diffusion nodes GND: Ground OUT output R1, R2, R3, R N : Pixel sensor row RST: Reset signal SEL: Selection signal T1: First gate dielectric thickness T2: Second gate dielectric thickness T3: Thickness of the first sidewall spacer T4: Thickness of the second sidewall spacer TX, TX1, TX2, TX3, TX4: Transmission signal T sub1 : First board terminal T sub2 : Second board terminal T sub3 :Third board terminal V DD : Supply voltage V NV : Negative voltage V pin : pinning voltage V RST :Reset voltage

Claims

1. a first integrated circuit (IC) chip including a first semiconductor substrate; a second IC chip including a second semiconductor substrate and stacked on the first IC chip; a pixel sensor spanning the first IC chip and the second IC chip; Including, the pixel sensor includes a first transistor and a light-receiving element on the first semiconductor substrate, and further includes a second transistor on the second semiconductor substrate; a bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other, the bulk of the first semiconductor substrate is biased at a negative voltage, and the bulk of the second semiconductor substrate is biased at ground; a body of the first transistor and an anode of the light receiving element electrically connected to the bulk of the first semiconductor substrate; the body of the second transistor is electrically coupled to the bulk of the second semiconductor substrate; Image sensor.

2. the first semiconductor substrate overlies the second semiconductor substrate; further comprising a pad exposed on the first semiconductor substrate; the pad is electrically connected to the bulk of the first semiconductor substrate; The image sensor of claim 1 .

3. the first transistor includes a gate dielectric layer having a first thickness; the second transistor includes a gate dielectric layer having a second thickness less than the first thickness. The image sensor of claim 1 .

4. the first transistor includes a first gate stack and a first sidewall spacer on a sidewall of the first gate stack; the second transistor includes a second gate stack and a second sidewall spacer on a sidewall of the second gate stack; the thickness of the second sidewall spacer is less than the thickness of the first sidewall spacer; The image sensor of claim 1 .

5. a first substrate; a photodiode and a first transistor adjacent to each other on the first substrate; a second substrate underlying the first substrate; a second transistor on the second substrate; and Including, the photodiode, the first transistor, and the second transistor form a pixel sensor; a body of the first transistor and an anode of the photodiode are electrically connected to each other and electrically isolated from a body of the second transistor; The body of the second transistor and the body of the first transistor are configured to be simultaneously biased to ground and a negative voltage, respectively. Image sensor.

6. 6. The image sensor of claim 5, wherein a trench extends laterally along the periphery of the first substrate in a closed circuit surrounding the photodiode and the first transistor, and further extends vertically through the first substrate to separate the first substrate into an interior and a periphery that are electrically isolated from each other.

7. the first substrate and the second substrate have respective side walls extending in separate closed paths around the periphery of the first substrate and the second substrate, respectively; In a top view, the individual sidewalls of the first substrate are laterally offset from and surrounded by the individual sidewalls of the second substrate.

6. The image sensor according to claim 5.

8. 1. A method for forming an image sensor, comprising: forming a photodiode on a first semiconductor substrate; forming a first transistor on the first semiconductor substrate adjacent to the photodiode, the photodiode and the first transistor forming a first pixel sensor portion; forming a first interconnect structure overlying the first transistor; forming a first integrated circuit (IC) chip, forming a plurality of second transistors on a second semiconductor substrate, the second transistors forming second pixel sensor portions; forming a second interconnect structure overlying the second transistor; forming a second IC chip, bonding the first IC chip and the second IC chip together such that the first pixel sensor portion and the second pixel sensor portion are stacked and electrically coupled together to form a pixel sensor; Including, a bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other upon completion of the bonding, the bulk of the first semiconductor substrate is biased at a negative voltage during use of the image sensor, and the bulk of the second semiconductor substrate is biased at ground during use of the image sensor; a body of the first transistor and an anode of the photodiode electrically coupled to the bulk of the first semiconductor substrate; a discrete body of the second transistor electrically coupled to the bulk of the second semiconductor substrate; the method further comprising forming pads on the periphery of the first semiconductor substrate after the bonding, the pads being electrically coupled to the bulk of the first semiconductor substrate by the first interconnect structure, independent of the second interconnect structure.

Images