Split Random Number Generator

Abstract

The computing system may implement a split random number generator that may use the random number generator to generate and store in memory a seed value for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.

Description

[Background technology]

[0001] Many modern computing systems utilize random number generators for a variety of applications, including, but not limited to, games, signal and image processing, financial and scientific system modeling, equation solving, and computer security and cryptography. A random number generator operating within a computing system may generate a set of random numbers as a sequence of independent numbers within a predetermined range of values ​​and with a specified distribution within that range. An ideal random number generator provides a stream of uniformly distributed, non-deterministic, independent bits with high entropy.

[0002] In some computing systems, random number generators may be implemented in software. Such software random number generators often produce sequences of numbers that are ultimately deterministic and therefore better characterized as pseudo-random number generators; however, these solutions may utilize various techniques to reduce the predictability of the generated numbers. For example, a random number generator may utilize a dynamic seed value from a high-entropy source, such as data from the system clock, keystroke timing, mouse movements, etc., and incorporate this data to seed the random number generator's calculations to reduce or eliminate correlation and predictability.

[0003] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 illustrates one embodiment of a computing system in which a split random number generator is implemented. [Figure 2] FIG. 1 is a block diagram of computing system components illustrating one embodiment of a split random number generator. [Figure 3] FIG. 1 illustrates one embodiment of a split random number process that may be performed by various components of a computing system. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, numerous specific details are set forth, such as examples of specific systems, components, methods, etc., to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simplified block diagram form to avoid unnecessarily obscuring the embodiments. Thus, the specific details set forth are merely exemplary. Particular embodiments may vary from these example details and still be considered to be within the spirit and scope of the embodiments.

[0006] High-quality random number generation is a critical part of many security applications, including key generation, Elliptic Curve Cryptography (ECC), High-Bandwidth Digital Content Protection (HDCP), encryption, and other applications. Poor-quality random numbers, which have low entropy, high correlation, and are predictable, can lead to security breaches and system compromise.

[0007] Some applications, including but not limited to access control, identification, encryption, control, identification, encryption, audio noise generation, etc., may benefit from a split random number generator that includes at least one single random number generator as an entropy source that provides unique seed values ​​to all CPU cores, rather than each central processing unit (CPU) generating a seed value for its own random number generator. For example, one advantage of one embodiment of a split design is that it achieves the tradeoff of having good performance through firmware implemented in individual random number generators that can be used in parallel, without consuming physical die area to replicate independent hardware random number generators in every processor core.

[0008] 1 illustrates one embodiment of a computing system 100 in which a split random number generator is implemented. Generally, computing system 100 may be embodied as any of a number of different types of devices, including, but not limited to, a laptop or desktop computer, a mobile device, a server, etc. Computing system 100 includes a number of components 102-108 that communicate with each other via a data fabric / bus 101. In computing system 100, each of components 102-108 may be configured to communicate with any of the other components 102-108 either directly via the data fabric / bus 101 or through one or more of the other components 102-108. In various embodiments, some or all of the components 102-108 in computing system 100 may be contained within a single physical enclosure, such as a laptop or desktop chassis or a mobile phone casing, while other devices, such as a display 110 or peripheral devices 108, may be external to the enclosure. In other embodiments, some of the components, such as CPU complexes 104A-104N and platform security complex 105, may reside on the same silicon substrate in the same package within computing system 100 or as separate silicon components.

[0009] In one embodiment, each CPU complex 104A-104N includes processing components on a common integrated circuit substrate, such as one or more processor cores, which may include other dedicated processing and programmable components and logic, for example, to implement a deterministic random bit generator (DRBG). In some embodiments, one or more CPU complexes 104A-104N may include a data-parallel processor having a highly parallel architecture, such as one or more of a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.

[0010] In various embodiments, platform security complex 105 may include various components such as a processor or microcontroller, a cryptographic coprocessor, a random number generator, local memory, a memory management unit, and various interfaces for communicating with other components external to platform security complex 105, such as CPU complexes 104A-104N. Functions of platform security complex 105 include, but are not limited to, creating, monitoring, and maintaining a security environment, managing the boot process, initializing various security-related mechanisms, and monitoring computing system 100 for any suspicious activity or events and responding accordingly. In one embodiment, platform security complex 105 provides entropy or random number generator seed values ​​to random number generators implemented within CPU complexes 104A-104N for secure processes and conforms to international security standards (e.g., the National Institute of Standards and Technology (NIST) security framework).

[0011] Computing system 100 may also include a memory subsystem 106 that includes memory devices used by one or more components of computing system 100, such as random access memory (RAM) modules, dynamic random access memory (DRAM) modules, read-only memory (ROM) modules, bit registers, hard disks, and other non-transitory computer-readable storage media. For convenience, memory devices are grouped herein in memory subsystem 106, but memory devices, such as registers or ROM, may be located throughout computing system 100 or, in some cases, may be located external to computing system 100, such as on an external drive or another computing system.

[0012] Computing system 100 also includes user interface devices for receiving information from or providing information to a user. Specifically, computing system 100 includes input devices 102, such as a keyboard, mouse, touch screen, or other device for receiving information from a user. Computing system 100 may display certain information to the user via a display 110, such as a monitor, light-emitting diode (LED) display, liquid crystal display, or other output device. Computing system 100 further includes a network adapter 107 for transmitting and receiving data over a wired or wireless network, and also includes one or more peripheral devices 108. Peripheral devices 108 may include mass storage devices, position detection devices, sensors, input devices, or other types of devices used by computing system 100.

[0013] Some embodiments of computing system 100 may include fewer or more components than the embodiment shown in Figure 1. For example, certain embodiments are implemented without display 110 or input device(s) 102. Other embodiments may have two or more of certain components. For example, an embodiment of computing system 100 may have additional network adapters or memory components or communication paths other than data fabric / bus 101 to communicatively couple devices to one another.

[0014] One embodiment of a split random number generator includes a master random number generator that generates a seed value for storage in memory accessible by each core random number generator in each CPU core. FIG. 2 illustrates one embodiment of a split random number generator 200 that includes a cryptographic coprocessor 202, a private memory 214, and core processors 220A-220N. In one embodiment, the cryptographic coprocessor 202 resides within a platform security complex (e.g., platform security complex 105 of FIG. 1 ), the private memory resides within a memory subsystem (e.g., memory subsystem 106 of FIG. 1 ), and core processors 220A-220N reside within one or more CPU complexes (e.g., CPU complexes 104A-104N of FIG. 1 ). The partitioning of these components is for illustrative purposes. In other embodiments, these components may be located on the same silicon, the same chip, and / or the same substrate within computing system 100. For example, private memory 214 may reside within platform security complex 105 rather than within memory subsystem 106.

[0015] In one embodiment, cryptographic coprocessor 202 further includes a master random number generator (master RNG) 203 that generates entropy in the form of random numbers to generate seed values ​​for each of core deterministic random bit generators (core DRBGs) 222A-222N of core processors 220A-220N. RNG 203, according to one embodiment, includes a noise source 204, an entropy accumulator 205, controller logic 206, and an encryption block 207. Noise source 204 captures non-deterministic noise samples from naturally occurring or other sources (e.g., ring oscillator, keyboard or mouse input, etc.). Entropy accumulator 205 may then turn the noise samples into high-quality entropy using a National Institute of Standards and Technology (NIST)-approved method. In one embodiment, entropy is fed into encryption block 207 to generate random numbers that comply with industry standards, such as 128-bit Advanced Encryption Standard (AES) encryption 256 to generate 256-bit random numbers. Other embodiments utilize other compliant methods, such as Secure Hash Algorithm (SHA) or other AES lengths.

[0016] In one embodiment, the controller logic 206 controls the output generation of random numbers used as seed values ​​for each processor core, such as seed values ​​216A-216N for each of the DRBGs 222A-222N. The controller logic 206 is coupled to a memory controller 212 to manage the storage of the seed values ​​216A-216N in a private memory 214 that can be accessed by the DRBGs 222A-222N.

[0017] According to one embodiment, each core DRBG 222A-222N includes controller logic 224A-224N, respectively, for controlling the output generation of random numbers. As a result, the output of each core DRBG 222A-222N can be used to implement processor instructions. Additionally, the controller logic 224A-224N may include various other logic, such as one or more counters 225A-225N and decision logic, for generating and detecting trigger events. For example, the counters and logic may be used to determine whether a threshold count-up or count-down time has been reached, or whether a threshold number of generated random numbers has been reached. In various embodiments, the DRBG of a CPU complex may be implemented as dedicated logic or may use existing execution capabilities of the CPU complex, such as the execution capabilities of the core processors 220A-220N.

[0018] For simplicity, Figure 2 shows only one CPU complex, however, cryptographic coprocessor 202, memory controller 212, and private memory 214 may be coupled to and communicate with multiple CPU complexes (e.g., CPU complexes 104A-104N of Figure 1) to implement various embodiments of the split random number generator. Furthermore, although each of the illustrated components is coupled by a separate communication link, some or all of the components of Figure 2 may be coupled to a communication fabric or bus, such as data fabric / bus 101 of Figure 1, and managed by one or more data fabric or bus controllers, such as memory controller 212.

[0019] In one embodiment, master RNG 203, in combination with memory controller 212, generates a new seed value based on the values ​​of flags 217A-217N. In one embodiment, each flag 217A-217N uniquely corresponds to a core processor and a seed value in memory. For example, when core DRBG 222A retrieves seed value 216A, it sets the corresponding flag 217A to indicate that seed value 216A has been retrieved. In one embodiment, memory controller 212 reads the value stored in flag 217A and, if the value indicates that it has been retrieved, signals master RNG 203 to generate and store in memory 214 a new seed value to refresh or replace seed value 217A, and then sets flag 216A to indicate that a new seed value is available. Core DRBG 222A includes controller logic 224A that may periodically check the value of flag 217A, for example, upon detection of a trigger event. If the value indicates that a new value is available, the core DRBG 222A reads and uses the seed value 216A updated by the master RNG 203 for the next random number generation (e.g., running RDRND) and sets the flag 217A again to indicate that the seed value 216A has been retrieved. If the value indicates that a new seed value is not available, the core DRBG 222A continues with its internal reseed to generate the next random number without using an updated seed value from the master.

[0020] In one embodiment, the process for determining when a core DRBG (e.g., DRBGs 222A-222N) retrieves a new seed value does not interfere with certain performance aspects of computing system 100. Each core processor (e.g., core processor 220A) initiates retrieval when it is triggered and needs a seed value, for example, when a counter threshold is met and the core processor is responding to a read random number instruction (RDRAND). Furthermore, when a core processor needs a new seed value, the core processor does not need to internally generate a new seed value, which would interrupt the core processor and create overhead within the system.

[0021] Figure 3 illustrates one embodiment of a split random number process 300 that may be executed by various components of computing system 100, specifically CPU complexes 104A-104N, platform security complex 105, and memory subsystem 106 and their respective components, as shown in Figures 1 and 2. Split random number process 300 begins with boot-time initialization, beginning at block 302, where a random number seed generator (e.g., cryptographic coprocessor 202) generates a seed value and verifies that the seed value is valid.

[0022] At block 304, the random number seed generator communicates or loads each seed value and corresponding flag value into memory (e.g., seed values ​​216A-216N, flags 217A-217N, and private memory 214 of FIG. 2). Thus, each flag uniquely corresponds to a core processor and seed value in memory. At block 306, the memory receives the seed value and sets the value of an associated flag that indicates to each corresponding core processor and DRBG (e.g., core processors 220A-220N and core DRBGs 222A-222N of FIG. 2) that the seed value is available for retrieval. In various embodiments, the flag values ​​may be stored in the same private memory or in separate registers or memories within the memory subsystem, platform security complex, or other components of computing system 100.

[0023] At block 308 in the boot-time sequence, each core processor of a CPU complex (e.g., core processor 220A of FIG. 2) retrieves its respective seed value from memory. Then, at block 310, the core processor sets a respective flag to indicate that the seed value has been retrieved, which is updated in memory at block 312. The boot-time process is complete and transitions to a run-time process, which, according to one embodiment, includes the cryptographic coprocessor and each core processor of each CPU complex executing a respective reseed process.

[0024] Beginning at run time, in block 314, a cryptographic coprocessor (e.g., cryptographic coprocessor 202 of FIG. 2) checks and determines whether it is time to reseed the core processors within each CPU complex. In one embodiment, a cryptographic coprocessor (CCP) reseed event may be triggered by monitoring an internal counter 209 and performing a CCP reseed when the counter 209 reaches a threshold. In various other embodiments, the counter 209 may be external to the cryptographic coprocessor and configured to count an approximate time value, or the trigger may be event-based, such as receiving a signal from a CPU complex or other component within computing system 100 of FIG. 1.

[0025] Returning to block 314, if a CCP reseed event is not triggered, execution returns to the beginning of block 314. If a CCP reseed event is triggered, in block 316, the cryptographic coprocessor reads a flag value associated with each processor core of each CPU complex to check and determine whether the processor core needs a new seed value. If no, the process returns to block 314 to wait for the next CCP reseed event. If yes, the process proceeds to block 318, where the cryptographic coprocessor generates a new seed value, stores it in memory, and sets each corresponding flag to indicate that the seed value is new and available to the associated core processor, which is indicated in memory at block 320. In one embodiment, the cryptographic coprocessor is configured to check, generate, and store new seed values ​​for a selected subset of the core processors for each CCP reseed trigger event. For example, the cryptographic coprocessor may be configured to select and check only a group of eight core processors per trigger event. Servicing the subsets in a staggered approach may prevent race conditions or slowdowns in which too many or all core processors attempt to retrieve a new seed value substantially simultaneously.

[0026] In one embodiment, concurrently with the cryptographic coprocessor processes, each CPU complex, specifically its corresponding core processor, generates random numbers based on the retrieved seed value and periodically checks for new seed values. For simplicity, blocks 322, 324, 326, 328, 329, and 330 are illustrated herein with respect to one core processor, but each core processor of each CPU complex may execute the processes represented by these blocks simultaneously, sequentially, in groups, or any combination thereof.

[0027] Beginning at block 322, a core processor's DRBG (e.g., 222A shown in FIG. 2) waits for an instruction to generate a random number (e.g., RDRAND) and, if not received, waits until it does. Upon receiving an instruction to generate a random number, the process continues with the core processor (e.g., core processor 220A) checking to determine whether a new seed value for its DRBG is needed at block 324. In one embodiment, a core processor reseed event may be triggered by monitoring an internal counter (e.g., counters 225A-225N) and performing a core processor reseed when the counter reaches a threshold. In various other embodiments, the counter may be external to the core processor and configured to count an approximate time value or the number of random numbers generated, or the trigger may be event-based, such as receiving a signal from a cryptographic coprocessor or other component within computing system 100 of FIG. 1.

[0028] Returning to block 324, if a core processor reseed event is not triggered, random number generation execution proceeds to block 326, where a random number is generated based on the internal state of the DRBG, and returns to block 322 to await another instruction. If a core processor reseed event is triggered, in decision block 328, the core processor reads a flag value associated with that processor core to determine whether the cryptographic coprocessor has uploaded a new seed value to memory (e.g., cryptographic coprocessor 202, private memory 214 of FIG. 2). If the flag does not indicate that a new seed value is available, the process updates the internal state with a new internally generated seed value and resets counters in block 329, and returns to block 326 to complete the instruction based on the new internal state of the DRBG. If the flag indicates that a new seed value is available, the process proceeds to block 330, where the core processor retrieves a new seed value from memory and sets a corresponding flag to indicate that a new seed value has been retrieved, which is shown set in memory in block 332. In one embodiment, setting the flag value in block 330 provides an indication to the cryptographic coprocessor that in the next iteration of blocks 314-318, the core processor will retrieve its seed value and be ready for another new seed value.

[0029] Additionally, the process updates the internal state of the DRBG and resets the counters at block 330. In one embodiment, updating the internal state with the new seed value includes mixing the new seed value with the current state value using a logical function such as exclusive OR (XOR).

[0030] In various embodiments, split random number process 300 may be divided among processing elements. For example, the cryptographic coprocessor and each core processor may have shared access to memory but may independently execute their own code within split random number process 300. In other embodiments, each component may be directed by another component or system code, or some combination of independent and shared code within computing system 100, to achieve the same or similar functionality as split random number process 300.

[0031] The computing system includes a master random bit generator that generates a plurality of seed values, each seed value uniquely corresponding to one of a plurality of core processors coupled to the master random bit generator, each core processor including a core random bit generator for deriving one of the plurality of seed values ​​generated by the master random bit generator.

[0032] The computing system also includes a platform security complex coupled to the memory, the platform security complex including a master random bit generator and configured to store in the memory a first value of a plurality of generated seed values ​​and a flag, each flag uniquely corresponding to a seed value and a core processor of the plurality of core processors, the first value indicating a new seed value in the memory.

[0033] In the computing system, each core processor retrieves at least one of a plurality of seed values, checks the value of a flag corresponding to the core processor, and if the value of the flag is a first value, retrieves the flag and the seed value corresponding to the core processor from memory and sets the flag from the first value to a second value to indicate that a new seed value has been retrieved by the core processor.

[0034] Also, in the computing system, the platform security complex checks the values ​​of at least some of the flags corresponding to the multiple core processors, and if the value of the flag is a second value, generates a new seed value, writes it into memory, and sets the value of the flag from the second value to the first value.

[0035] The computing system also includes a counter that generates a trigger event to initiate checking of respective values ​​of at least some of the flags corresponding to the multiple core processors.

[0036] In a computing system, multiple core processors are located within one or more CPU complexes.

[0037] In the computing system, the core random bit generator of each core processor checks a memory for a seed value corresponding to the core processor based on a trigger event.

[0038] In the computing system, each core processor includes a counter configured to generate a trigger event when the value of the counter reaches a threshold value.

[0039] The method includes generating a plurality of seed values, storing the plurality of seed values ​​in a memory, each seed value uniquely corresponding to one of a plurality of core processors, retrieving corresponding seed values ​​from the memory by at least some of the plurality of core processors, and generating a random number based on the retrieved corresponding seed values.

[0040] The method also includes determining which of the multiple core processors retrieved the corresponding seed value, and generating a new seed value for at least a portion of the memory corresponding to the determined retrieved seed value.

[0041] The method also includes generating a new seed value based on detecting the trigger event.

[0042] The method also includes selecting a subset of the plurality of core processors to determine which of the plurality of core processors retrieved the corresponding seed value.

[0043] In the method, determining which of the multiple core processors has retrieved the corresponding seed value includes reading, for each core processor, a flag value that is set to a first value indicating that the corresponding seed value has been retrieved by the core processor, and after generating a new seed value, changing the flag value from the first value to a second value to indicate the new seed value available for retrieval.

[0044] In the method, retrieving the corresponding seed value from the memory is based on detecting a trigger event.

[0045] In the method, detecting a trigger event includes detecting when a counter reaches a threshold time limit.

[0046] In the method, detecting a trigger event includes detecting that a number of random numbers generated based on the retrieved corresponding seed value reaches a threshold.

[0047] The random number generator includes a master random bit generator for generating a seed value and storing the seed value in a memory, and a plurality of core processors, each including a core random bit generator for generating random numbers based on the seed value generated by the master random bit generator.

[0048] The multiple core processor retrieves a corresponding seed value from memory at a memory location that uniquely corresponds to each core processor of the multiple core processors.

[0049] In the random number generator, the master random bit generator determines which seed value to generate based on the corresponding flag value set by each core random bit generator.

[0050] In the random number generator, each core random bit generator is configured to retrieve a corresponding seed value generated by the master random bit generator based on a corresponding flag value set by the master random bit generator.

[0051] The embodiments described herein may include various operations and processes. These operations may be performed by hardware components, software, firmware, or combinations thereof. As used herein, the term "coupled to" may mean directly or indirectly coupled through one or more intervening components. Any of the signals provided via the various signal lines and buses described herein may be time-multiplexed with other signals and provided via one or more common buses. Furthermore, interconnections between circuit components or blocks may be referred to as buses or single signal lines. Each bus may alternatively be one or more single signal lines, and each single signal line may alternatively be a bus.

[0052] Certain embodiments may be implemented as a computer program product, which may include instructions stored on a computer-readable storage medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A computer-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). A computer-readable storage medium may include, but is not limited to, magnetic storage media (e.g., floppy diskettes), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random-access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another type of medium suitable for storing electronic instructions.

[0053] Additionally, some embodiments may be practiced in a distributed computing environment where a computer-readable medium is stored on and / or executed by more than one computer system. Further, information transferred between computer systems may be pulled or pushed through a transmission medium connecting the computer systems.

[0054] Generally, a data structure representing the split random number generator 200 and / or portions thereof embodied in a computer-readable storage medium may be a database or other data structure that can be read by a program and used directly or indirectly to manufacture hardware comprising the split random number generator 200. For example, the data structure may be a behavioral-level description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL, or a register-transfer level (RTL) description. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist comprises a set of gates that also represent the functionality of the hardware comprising the split random number generator 200. The netlist may then be placed and routed to generate a data set that describes the geometric shapes that are applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture semiconductor circuits corresponding to the split random number generator 200. Alternatively, the database on the computer-readable storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, as desired.

[0055] Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be changed such that certain operations may be performed in the reverse order or such that certain operations may be performed at least in part concurrently with other operations. In alternative embodiments, instructions or sub-operations of individual operations may be performed intermittently and / or alternately.

[0056] In the foregoing specification, the embodiments have been described with reference to specific exemplary embodiments thereof. It will be apparent, however, that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A computing system comprising: a multiple core processor; a master random bit generator coupled to the plurality of core processors, the master random bit generator configured to generate a seed value uniquely corresponding to each of the plurality of core processors; At least one core processor of the plurality of core processors is configured to retrieve a seed value generated by a master random bit generator corresponding to the at least one core processor, and generate a random number based on the retrieved seed value. Computing system.

2. further comprising a platform security complex coupled to the memory; the platform security complex comprises the master random bit generator; the platform security complex is configured to store the seed value and a first value of a flag in the memory; the flag uniquely corresponds to the seed value, and the first value indicates a new seed value stored in the memory. The computing system of claim 1.

3. The at least one core processor checking the value of the flag; If the value of the flag is the first value, retrieving the seed value corresponding to the flag from the memory; setting the flag from the first value to a second value to indicate that the new seed value has been retrieved by the at least one core processor; and further configured to: The computing system of claim 2.

4. The platform security complex comprises: checking the value of the flag; If the value of the flag is the second value, generating a new seed value and writing it into the memory; setting the value of the flag from the second value to the first value; and further configured to: The computing system of claim 3.

5. the multiple core processors are arranged in one or more central processing unit (CPU) complexes; The computing system of claim 1.

6. further comprising a plurality of core random bit generators; each core random bit generator is associated with a corresponding core processor of the plurality of core processors; the core random bit generator of a corresponding core processor is configured to check a memory for the seed value of the corresponding core processor based on a trigger event; The computing system of claim 5.

7. each core processor includes a counter configured to generate the trigger event when a value of the counter reaches a threshold value; The computing system of claim 6.

8. 1. A method comprising: a master random bit generator generating a seed value that uniquely corresponds to each of the plurality of core processors; a memory controller storing each seed value in a memory; A core processor among the plurality of core processors retrieves a corresponding seed value from the memory; any one of the core processors generating a random number based on the retrieved corresponding seed value; method.

9. The method further includes the master random bit generator generating one or more new seed values ​​for one or more core processors based on one or more core processors of the plurality of core processors retrieving corresponding sheet values.

9. The method of claim 8.

10. selecting a subset of the core processors from which the corresponding seed value is derived from the plurality of core processors; 10. The method of claim 9.

11. generating the one or more new seed values ​​comprises: For each of the one or more core processors: reading a flag configured to be set to a first value when the corresponding seed value is retrieved by the core processor; after generating the new seed value, changing the flag of the core processor from the first value to a second value to indicate a retrievable new seed value; 10. The method of claim 9.

12. retrieving the corresponding seed value from the memory based on detecting a trigger event in the any one of the core processors; 9. The method of claim 8.

13. detecting the trigger event includes detecting that a counter has reached a threshold time limit; 13. The method of claim 12.

14. detecting the trigger event includes detecting that a number of random numbers generated based on the retrieved corresponding seed value reaches a threshold.

13. The method of claim 12.

15. 1. A system comprising: a master random bit generator configured to generate a seed value and store the seed value in a memory; a plurality of core processors, each of the plurality of core processors including a core random bit generator configured to generate random numbers based on a seed value generated by the master random bit generator and uniquely corresponding to each core processor; system.

16. each said core processor is configured to retrieve a corresponding seed value from said memory at a memory location uniquely corresponding to said core processor; 16. The system of claim 15.

17. further comprising a plurality of core random bit generators associated with the plurality of core processors; the master random bit generator is configured to determine which seed value to generate for each of the plurality of core random bit generators based on a corresponding flag value set by each core random bit generator.

16. The system of claim 15.

18. each core random bit generator configured to retrieve a corresponding seed value generated by the master random bit generator based on a corresponding flag value set by the master random bit generator; 18. The system of claim 17.

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