Indication device

Abstract

To reduce the manufacturing process and manufacturing cost of a display device.SOLUTION: A display device in an example of the present specification includes a first substrate including a plurality of upper pads, a second substrate including a plurality of lower pads, and a plurality of side wires connecting the upper pads and the lower pads. Each of the lower pads includes a first lower pad electrode disposed below the second substrate, a first insulating layer disposed below the first lower pad electrode, a second lower pad electrode disposed below the first insulating layer, a third lower pad electrode disposed below the second lower pad electrode, and a second insulating layer disposed below the third lower pad electrode. The third lower pad electrode is formed of a transparent conductive material.SELECTED DRAWING: Figure 7b

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and are therefore highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device with reduced manufacturing steps and manufacturing costs.

[0006] Another problem to be solved by the present specification is to provide a display device in which the number of disconnection paths is reduced and the problem of defects is reduced.

[0007] Another problem to be solved by the present invention is to provide a display device in which the occurrence of parasitic capacitors is reduced.

[0008] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to one embodiment of the present specification includes a first substrate including a plurality of upper pads, a second substrate including a plurality of lower pads, and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads, and each of the plurality of lower pads includes a first lower pad electrode disposed on a lower portion of a second substrate, a first insulating layer disposed on a lower portion of the first lower pad electrode, a second lower pad electrode disposed on a lower portion of the first insulating layer, a third lower pad electrode disposed on a lower portion of the second lower pad electrode, and a second insulating layer disposed on a lower portion of the third lower pad electrode, and the third lower pad electrode may be made of a transparent conductive material.

[0010] Further details of the embodiments are included in the detailed description and drawings.

[0011] The present specification can reduce the number of mask steps and reduce the manufacturing cost of the display device.

[0012] The present invention can prevent the problem of defects by improving the structure of the pad portion.

[0013] The present invention can prevent corrosion of the pad portion and improve the reliability of the pad portion.

[0014] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0015] [Figure 1]1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 2a] 1 is a partial cross-sectional view of a display device according to an embodiment of the present specification. [Figure 2b] 1 is a perspective view of a tiling display device according to an embodiment of the present specification; [Figure 3] FIG. 2 is an enlarged plan view of a first substrate of a display device according to an embodiment of the present specification. [Figure 4] FIG. 2 is an enlarged plan view of a second substrate of a display device according to an embodiment of the present specification. [Figure 5] 1 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present disclosure. [Figure 6] 1 is a cross-sectional view of a pad area of ​​a display device according to an embodiment of the present disclosure; [Figure 7a] 1 is a cross-sectional view of an upper pad of a display device according to an embodiment of the present disclosure; [Figure 7b] 1 is a cross-sectional view of a lower pad of a display device according to an embodiment of the present disclosure; [Figure 8] FIG. 5 is a cross-sectional view of the second substrate taken along line AA' in FIG. [Figure 9] FIG. 5 is a cross-sectional view of the second substrate taken along line BB' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the present invention to those skilled in the art.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0018] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0019] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0020] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0021] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0022] Like reference numbers refer to like elements throughout the specification.

[0023] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0024] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0025] In the following, the present specification will be described with reference to the drawings.

[0026] 1 is a schematic diagram of a display device according to an embodiment of the present disclosure, in which, for convenience of explanation, only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown among various components of the display device 100.

[0027] Referring to FIG. 1, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0028] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided by the timing controller TC. Although one gate driver GD is shown as being spaced apart from one side of the display panel PN in FIG. 1, the number and arrangement of the gate drivers GD are not limited thereto.

[0029] The data driver DD converts image data input from the timing controller TC into data voltages using a reference gamma voltage in response to a plurality of data control signals provided from the timing controller TC, and supplies the converted data voltages to a plurality of data lines DL.

[0030] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then supply the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0031] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL cross each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, although not shown in the drawing, each of the sub-pixels SP may be connected to a high potential power line, a low potential power line, a reference line, etc.

[0032] A display area AA and a non-display area NA surrounding the display area AA can be defined on the display panel PN.

[0033] The display area AA is an area where an image is displayed on the display device 100. A plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP is the smallest unit constituting the display area AA, and n sub-pixels SP may form one pixel PX. A light-emitting element and a thin film transistor for driving the light-emitting element may be arranged in each of the plurality of sub-pixels SP. The plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0034] A plurality of signal lines are arranged in the display area AA to transmit various signals to the subpixels SP. For example, the signal lines may include a plurality of data lines DL that supply data voltages to the subpixels SP, respectively, and a plurality of scan lines SL that supply gate voltages to the subpixels SP, respectively. The scan lines SL may extend in one direction from the display area AA to be connected to the subpixels SP, and the data lines DL may extend in a direction different from the one direction from the display area AA to be connected to the subpixels SP. In addition, low-potential power supply lines, high-potential power supply lines, etc. may also be arranged in the display area AA, but are not limited thereto.

[0035] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driving ICs such as gate driver ICs and data driver ICs, may be arranged in the non-display area NA. The non-display area NA may be located on the back surface of the display panel PN, i.e., on a surface where the sub-pixels SP are not present, or may be omitted, and is not limited to what is shown in the drawings.

[0036] Meanwhile, drivers such as the gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD may be implemented in the non-display area NA using a GIP (Gate In Panel) method, or may be implemented between multiple sub-pixels SP in the display area AA using a GIA (Gate In Active Area) method. For example, the data driver DD and timing controller TC may be formed on a separate flexible film and printed circuit board and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. If the gate driver GD is implemented using the GIP method and the data driver DD and timing controller TC transmit signals to the display panel PN through pad electrodes in the non-display area NA, it is necessary to secure an area in the non-display area NA for arranging the gate driver GD and the pad electrodes, which may increase the bezel.

[0037] Alternatively, if the gate driver GD is mounted within the display area AA using the GIA method, and side wiring SRL is formed to connect signal wiring on the front side of the display panel PN to pad electrodes on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be minimized. That is, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the above manner, it may be possible to implement a zero-bezel display, in which there is essentially no bezel. For more detailed description, refer to Figures 2a and 2b.

[0038] 2a and 2b are partial cross-sectional and perspective views of a display device according to an embodiment of the present disclosure, respectively;

[0039] A plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are arranged in the non-display area NA of the display panel PN. For example, upper pads TPAD for transmitting signals to the plurality of sub-pixels SP are arranged in the non-display area NA on the front side of the display panel PN, and lower pads BPAD for electrically connecting to driving components such as a flexible film and a printed circuit board are arranged in the non-display area NA on the rear side of the display panel PN.

[0040] In this case, although not shown in the drawing, various signal lines connected to a plurality of sub-pixels SP, such as scan lines SL and data lines DL, may extend from the display area AA to the non-display area NA and be electrically connected to the upper pad TPAD.

[0041] Also, side wirings SRL are arranged along the side surfaces of the display panel PN. The side wirings SRL can electrically connect the upper pads TPAD on the front surface of the display panel PN to the lower pads BPAD on the rear surface of the display panel PN. Thus, signals from driving components on the rear surface of the display panel PN can be transmitted to the sub-pixels SP through the lower pads BPAD, the side wirings SRL, and the upper pads TPAD. Therefore, a signal transmission path is formed from the front surface to the side surfaces and rear surface of the display panel PN, thereby minimizing the area of ​​the non-display region NA of the display panel PN.

[0042] 2b, a tiling display device TD having a large screen can be implemented by connecting a plurality of display devices 100. In this case, when the tiling display device TD is implemented using the display device 100 with a minimized bezel as shown in FIG. 2a, seam areas between the display devices 100 where no image is displayed can be minimized, thereby improving display quality.

[0043] For example, a plurality of sub-pixels SP may form one pixel PX, and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 may be implemented as the same as the distance D1 between pixels PX within one display device 100. Therefore, the distance between pixels PX may be configured to be constant between display devices 100, thereby minimizing seam areas.

[0044] However, FIGS. 2a and 2b are merely examples, and the display device 100 according to an embodiment of the present specification may be a general display device having a bezel, and is not limited thereto.

[0045] Meanwhile, the display panel PN may include a first substrate and a second substrate.

[0046] The first and second substrates will be described in detail below with reference to FIGS.

[0047] FIG. 3 is an enlarged plan view of a first substrate of a display device according to an embodiment of the present specification.

[0048] First, the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components disposed on the upper portion of the display device 100 and may be an insulating substrate. A plurality of pixels PX may be formed on the first substrate 110 to display an image. For example, the first substrate 110 may be made of glass, resin, or the like. Alternatively, the first substrate 110 may be made of a polymer or plastic. In some embodiments, the first substrate 110 may be made of a flexible plastic material.

[0049] 3, a plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of upper pad areas are arranged on the first substrate 110. Among these, the plurality of pixel areas UPA and the plurality of gate driving areas GA may be included in a display area AA of the display panel PN.

[0050] First, the pixel regions UPA are regions in which the pixels PX are arranged. The pixel regions UPA may be arranged in a plurality of rows and a plurality of columns. Each of the pixels PX arranged in the pixel regions UPA includes a plurality of sub-pixels SP. Each of the sub-pixels SP includes a light-emitting element LED and a pixel circuit and can independently emit light.

[0051] The display panel PN includes a plurality of pixels PX, each of which is composed of a plurality of sub-pixels SP. Each of the sub-pixels SP includes a light-emitting element LED and a pixel circuit and can independently emit light. One pixel may include one or more first sub-pixels, one or more second sub-pixels, and one or more third sub-pixels. For example, one pixel may include two first sub-pixels, two second sub-pixels, and two third sub-pixels. In this case, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel, but is not limited thereto.

[0052] The gate driving regions GA are regions in which gate drivers GD are arranged. The gate driving regions GD may be implemented in the display area AA in a Gate In Active Area (GIA) manner. For example, the gate driving regions GA may be formed in the row and / or column directions between the pixel areas UPA. The gate driving regions GD formed in the gate driving regions GA may provide scan signals to the scan lines SL.

[0053] The gate driver GD disposed in the gate driving region GA may include a circuit for outputting a scan signal. The gate driver GD may include, for example, a plurality of transistors and / or capacitors. The active layers of the plurality of transistors may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. The active layers of the plurality of transistors may be made of the same material or different materials. The active layers of the transistors of the gate driver may be made of the same material or different materials from the active layers of various transistors of the pixel circuit.

[0054] The plurality of upper pad areas include a first upper pad area TPA1 located at a first edge EG1 of the display panel PN, and a second upper pad area TPA2 located at a second edge EG2 of the display panel PN.

[0055] The first upper pad area TPA1 and the second upper pad area TPA2 are areas where a plurality of upper pads TPAD are arranged on the first substrate 110. The plurality of upper pads TPAD can transmit various signals to various wirings extending in the column direction in the display area AA.

[0056] A plurality of first upper pads TPAD1 may be arranged in the first upper pad area TPA1. The plurality of first upper pads TPAD1 may include upper pads TPAD to which different signals are applied. For example, the first upper pads TPAD1 may include an upper data pad TDP for transmitting a data voltage to the upper data line TDL, an upper gate pad TGP for transmitting a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. for driving the gate driver GD to the gate driver GD, and an upper high potential power pad TVP1 for transmitting a high potential power voltage to the upper high potential power line TVL1.

[0057] A plurality of second upper pads TPAD2 may be arranged in the second upper pad area TPA2. In this case, the second upper pads TPAD2 may be upper pads different from the first upper pads TPAD1. For example, the second upper pads TPAD2 may include upper low potential power supply pads TVP2 that transmit low potential power supply voltages to the upper low potential power supply wirings TVL2.

[0058] In this case, the plurality of upper pads TPAD may be formed to have different sizes. For example, the plurality of upper data pads TDP connected to the plurality of upper data lines TDL one-to-one among the plurality of first upper pads TPAD1 may have a relatively narrow width, and the upper high potential power pad TVP1 and the upper gate pad TGP may have a relatively wide width. In addition, the upper low potential power pad TVP2, which is the plurality of second upper pads TPAD2, may also have a relatively wider width than the plurality of upper data pads TDP, and the upper low potential power pads TVP2 may have different widths. However, the widths of the upper data pad TDP, upper gate pad TGP, upper high potential power pad TVP1, and upper low potential power pad TVP2 shown in FIG. 3 are merely examples, and the sizes of the upper pads TPAD may be variously configured and are not limited thereto.

[0059] Meanwhile, in order to reduce the bezel of the display panel PN, the edges of the display panel PN can be cut and removed. A plurality of pixels PX, a plurality of lines, and a plurality of upper pads TPAD can be formed on the initial first substrate 110i, and the edge portion of the initial first substrate 110i can be ground to reduce the bezel area. A portion of the initial first substrate 110i can be removed through the grinding process, and a first substrate 110 having a smaller size can be formed. At this time, a portion of the plurality of upper pads TPAD and a portion of the lines disposed on the edge of the first substrate 110 can be removed. Therefore, only a portion of the plurality of upper pads TPAD can remain on the first substrate 110.

[0060] A plurality of upper data wirings TDL are arranged in a plurality of pixel regions UPA on the first substrate 110 of the display panel PN, extending in the column direction from a plurality of upper pads TPAD. The plurality of upper data wirings TDL may extend from a plurality of upper data pads TDP in the first upper pad region TPA1 toward a plurality of pixel regions UPA. The plurality of upper data wirings TDL may be arranged to extend in the column direction and overlap the plurality of pixel regions UPA. Thus, the plurality of upper data wirings TDL can transmit data voltages to pixel circuits of the respective sub-pixels SP.

[0061] A plurality of upper high potential power supply wirings TVL1 are arranged on the first substrate 110 of the display panel PN, extending in the column direction in a plurality of pixel regions UPA. Some of the plurality of upper high potential power supply wirings TVL1 extend from upper high potential power supply pads TVP1 in the first upper pad region TPA1 toward the plurality of pixel regions UPA to transmit a high potential power supply voltage to the light emitting elements LED of each of the plurality of sub-pixels SP. Other of the plurality of upper high potential power supply wirings TVL1 may be electrically connected to other upper high potential power supply wirings TVL1 through upper auxiliary high potential power supply wirings TAVL1, which will be described later. For convenience of explanation, FIG. 3 shows one upper high potential power supply wiring TVL1 and one upper high potential power supply pad TVP1, but a plurality of upper high potential power supply wirings TVL1 and upper high potential power supply pads TVP1 may be arranged.

[0062] A plurality of upper low potential power supply wirings TVL2 are arranged on the first substrate 110 of the display panel PN, extending in the column direction in a plurality of pixel regions UPA. At least some of the plurality of upper low potential power supply wirings TVL2 extend from upper low potential power supply pads TVP2 in the second upper pad area TPA2 toward the plurality of pixel regions UPA to transmit a low potential power supply voltage to the pixel circuits of the plurality of sub-pixels SP. Other parts of the plurality of upper low potential power supply wirings TVL2 may be electrically connected to other upper low potential power supply wirings TVL2 through upper auxiliary low potential power supply wirings TAVL2, which will be described later.

[0063] A plurality of upper scan lines TSL extending in the row direction are arranged in a plurality of pixel regions UPA on the first substrate 110 of the display panel PN. The plurality of upper scan lines TSL may extend in the row direction and cross the plurality of pixel regions UPA and the plurality of gate driving regions GA. The plurality of upper scan lines TSL may transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0064] A plurality of upper auxiliary high potential power supply wirings TAVL1 are arranged in a row direction in a plurality of pixel regions UPA on the first substrate 110 of the display panel PN. The plurality of upper auxiliary high potential power supply wirings TAVL1 may be arranged in regions between the plurality of pixel regions UPA. The plurality of upper auxiliary high potential power supply wirings TAVL1 extending in the row direction may be electrically connected to the plurality of upper high potential power supply wirings TVL1 extending in the column direction through contact holes to form a mesh structure. Therefore, the plurality of upper auxiliary high potential power supply wirings TAVL1 and the plurality of upper high potential power supply wirings TVL1 are configured to form a mesh structure, thereby minimizing voltage drop and voltage deviation.

[0065] A plurality of upper auxiliary low potential power supply wirings TAVL2 are arranged in a row direction in a plurality of pixel regions UPA on the first substrate 110 of the display panel PN. The plurality of upper auxiliary low potential power supply wirings TAVL2 may be arranged in regions between the plurality of pixel regions UPA. The plurality of upper auxiliary low potential power supply wirings TAVL2 extending in the row direction may be electrically connected to the plurality of upper low potential power supply wirings TVL2 extending in the column direction through contact holes to form a mesh structure. Therefore, the plurality of upper auxiliary low potential power supply wirings TAVL2 and the plurality of upper low potential power supply wirings TVL2 are configured to form a mesh structure, which reduces wiring resistance and minimizes voltage deviation.

[0066] 3, a plurality of upper gate driving lines TGVL are arranged in a plurality of pixel regions UPA on a first substrate 110 of a display panel PN, extending in row and column directions. Some of the upper gate driving lines TGVL extend from upper gate pads TGP in a first upper pad region TPA1 to gate driving regions GA to transmit signals to gate drivers GD. Other of the upper gate driving lines TGVL extend in the row direction to transmit signals to gate drivers GD in the plurality of gate driving regions GA. Various signals are then transmitted from the upper gate driving lines TGVL to the gate drivers GD to drive them.

[0067] The upper gate driving wirings TGVL may include wirings for transmitting a clock signal, a start signal, a gate high voltage, a gate low voltage, etc. to the gate driver GD. Various signals are transmitted from the upper gate driving wirings TGVL to the gate driver GD, thereby driving the gate driver GD.

[0068] For example, the plurality of upper gate driving lines TGVL may include gate power lines for transmitting a power supply voltage to the gate driver GD of the gate driving region GA, and may include a first gate power line for transmitting a gate high voltage to the gate driver GD and a second gate power line for transmitting a gate low voltage to the gate driver GD.

[0069] A plurality of align keys AK1 and AK2 are arranged in areas between the plurality of pixel areas UPA on the display panel PN. The align keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The align keys AK1 and AK2 include a first align key AK1 and a second align key AK2.

[0070] The first align key AK1 may be disposed in the gate driving area GA among the pixel areas UPA. The first align key AK1 may be used to check the alignment of the light emitting elements LED. For example, the first align key AK1 may be formed in a cross shape, but is not limited thereto.

[0071] The second align key AK2 may be disposed in a region between the pixel areas UPA so as to overlap the upper high potential power wiring TVL1. A hole overlapping the second align key AK2 may be formed in the upper high potential power wiring TVL1, thereby separating the second align key AK2 from the upper high potential power wiring TVL1. The second align key AK2 may be used to align the display panel PN and the donor. The second align key AK2 may be used to align the display panel PN and the donor, and transfer the plurality of light emitting elements LED of the donor to the display panel PN. For example, the second align key AK2 may be formed in a circular ring shape, but is not limited thereto.

[0072] FIG. 4 is an enlarged plan view of a second substrate of a display device according to an embodiment of the present specification.

[0073] First, the display panel PN includes a second substrate 130. The second substrate 130 is a substrate that supports components disposed under the display device 100 and may be an insulating substrate. For example, a plurality of flexible films COF and a printed circuit board PCB that transmit signals to the plurality of sub-pixels SP may be disposed under the second substrate 130.

[0074] The second substrate 130 may be made of glass, resin, or the like. The second substrate 130 may also be made of a polymer or plastic. The second substrate 130 may be made of the same material as the first substrate 110. In some embodiments, the second substrate 130 may be made of a flexible plastic material.

[0075] Referring to FIG. 4, the second substrate 130 may include a plurality of lower pad areas, a COF pad area BPA3, and a plurality of wiring areas.

[0076] The plurality of lower pad areas are areas where a plurality of lower pads BPAD are arranged on the lower part of the second substrate 130. For example, the plurality of lower pad areas may include a first lower pad area BPA1 located at a first edge EG1 of the display panel PN and a second lower pad area BPA2 located at a second edge EG2. The plurality of lower pads BPAD may transmit various signals to various wirings arranged in the plurality of lower wiring areas.

[0077] 4, a plurality of first lower pads BPAD1 may be arranged in the first lower pad area BPA1. The plurality of first lower pads BPAD1 may include a plurality of lower pads BPAD to which different signals are applied. For example, the plurality of first lower pads BPAD1 may include a lower data pad BDP, a lower gate pad BGP, and a lower high potential power pad BVP1.

[0078] Meanwhile, the plurality of lower pads BPAD may be formed to have different sizes. For example, the plurality of first lower pads BPAD1 may have different sizes. Specifically, the plurality of lower data pads BDP connected to the plurality of lower data lines BDL in a one-to-one relationship may have a relatively narrow width, and the lower high potential power pad BVP1 and the lower gate pad BGP may have a relatively wide width. However, the widths of the lower data pad BDP, the lower gate pad BGP, and the lower high potential power pad BVP1 shown in FIG. 4 are merely examples, and the sizes of the lower pads BPAD may be variously configured and are not limited thereto.

[0079] A plurality of second lower pads BPAD2 may be arranged in the second lower pad area BPA2. In this case, the plurality of second lower pads BPAD2 may be lower pads BPAD different from the plurality of first lower pads BPAD1. For example, the plurality of second lower pads BPAD2 may include a lower low potential power pad BVP2 that transmits a low potential power voltage to a lower low potential power wiring BVL2.

[0080] Meanwhile, the second lower pads BPAD2 may have different sizes. For example, the second lower pads BPAD2 may have a width narrower than the lower data pads BDP of the first lower pads BPAD1, but is not limited thereto. Also, the width of the lower low potential power supply pad BVP2 shown in FIG. 4 is merely an example, and the size of the lower pad BPAD may be variously configured and is not limited thereto.

[0081] Meanwhile, to reduce the bezel of the display panel PN, the edges of the display panel PN can be cut and removed. A plurality of pixels PX, a plurality of wirings, and a plurality of lower pads BPAD can be formed on the initial second substrate 130i, and the edge portions of the initial second substrate 130i together with the initial first substrate 110i can be ground to reduce the bezel area. A portion of the initial second substrate 130i can be removed through the grinding process, forming a second substrate 130 having a smaller size. At this time, a portion of the lower pads BPAD and wirings disposed on the edge of the second substrate 130 can be removed. Therefore, only a portion of the lower pads BPAD can remain on the second substrate 130.

[0082] The COF pad area BPA3 is disposed between the first lower pad area BPA1 and the second lower pad area BPA2. For example, the COF pad area BPA3 may be disposed adjacent to the first lower pad area BPA1 of the first lower pad area BPA1 and the second lower pad area BPA2, but is not limited thereto.

[0083] A plurality of COF pads BPAD3 are arranged in the COF pad area BPA3.

[0084] The COF pads BPAD3 are connected to the lower wirings arranged in the lower wiring regions, and can electrically connect the lower wirings to the flexible film COFs and the printed circuit board PCB.

[0085] For example, a plurality of lower data link wires BDL may be connected to a plurality of COF pads BPAD3, and the plurality of COF pads BPAD3 may be electrically connected to a plurality of flexible film COFs, so that the plurality of COF pads BPAD3 may electrically connect the plurality of flexible film COFs to the plurality of lower data link wires BDL.

[0086] The multiple COF pads BPAD3 will be described in detail later with reference to FIG.

[0087] Meanwhile, a plurality of flexible film COFs and a printed circuit board PCB may be disposed in the COF pad area BPA3.

[0088] The flexible film COFs may be electrically connected to the COF pads BPAD3. The flexible film COF is a film in which various components are disposed on a flexible base film, and supplies signals to the sub-pixels SP and driving components, and may be electrically connected to the display panel PN.

[0089] Driving ICs such as gate driver ICs and data driver ICs may be mounted on the multiple flexible film COFs. The driving ICs are components that process data for displaying images and driving signals for processing the data. Depending on the mounting method, the driving ICs may be mounted in a chip-on-glass (COG) format, a chip-on-film (COF) format, a tape carrier package (TCP) format, or the like. However, for the sake of convenience, the present invention is not limited to this configuration.

[0090] The printed circuit board PCB is electrically connected to the multiple flexible films COF. The printed circuit board PCB is a component that supplies signals to the driving IC. Various components for supplying various signals to the driving IC may be arranged on the printed circuit board PCB.

[0091] Meanwhile, in FIG. 4, the number of flexible film COFs is three and the number of printed circuit boards PCBs is one, but the number of flexible film COFs and printed circuit boards PCBs may be varied in various ways depending on the design and is not limited thereto.

[0092] The plurality of lower wiring regions are regions in which a plurality of wires connected to the plurality of lower pads BPAD are arranged, and may include a first lower wiring region BLA1 and a second lower wiring region BLA2.

[0093] 4, a first lower wiring region BLA1 and a second lower wiring region BLA2 are disposed between a first lower pad region BPA1 and a second lower pad region BPA2. The first lower wiring region BLA1 and the second lower wiring region BLA2 may be spaced apart with a COF pad region BPA3 interposed therebetween. For example, the first lower wiring region BLA1 may be disposed between the first lower pad region BPA1 and the COF pad region BPA3, and the second lower wiring region BLA2 may be disposed between the second lower pad region BPA2 and the COF pad region BPA3. Thus, the first lower pad region BPA1, the first lower wiring region BLA1, the COF pad region BPA3, the second lower wiring region BLA2, and the second lower pad region BPA2 may be sequentially disposed from the first edge EG1 to the second edge EG2 of the display panel PN.

[0094] In the first lower wiring area BLA1, a lower data link wiring BDL, a lower gate link wiring, a lower high potential power supply wiring BVL1, and a plurality of lower auxiliary high potential power supply wirings BAVL1 can be arranged.

[0095] For example, a plurality of lower data link wires BDL extending in a column direction from the lower data pads BDP are arranged in the first lower wiring area BLA1 on the rear surface of the second substrate 130. The plurality of lower data link wires BDL may extend toward the COF pad area BPA3 and be connected to the plurality of flexible films COF and the printed circuit board PCB. The plurality of lower data link wires BDL may also be arranged to overlap the lower high potential power wires BVL1.

[0096] A plurality of lower gate link wires extending in a column direction from the lower gate pads BGP are arranged in the first lower wiring area BLA1 on the rear surface of the second substrate 130. The plurality of lower gate link wires may extend toward the COF pad area BPA3 and be connected to the plurality of COF pads BPAD3.

[0097] In the first lower wiring area BLA1 on the rear surface of the second substrate 130, a plurality of lower high potential power supply link wires are arranged, extending in the column direction from a plurality of lower high potential power supply pads BVP1.

[0098] Each of the plurality of lower high potential power supply link wires may extend in the column direction and be connected to the lower high potential power supply wire BVL1.

[0099] The lower high-potential power supply wiring BVL1 may have a major axis in the row direction. For example, the width of the lower high-potential power supply wiring BVL1 may correspond to the width of the first lower pad area BPA1. For example, the width of the lower high-potential power supply wiring BVL1 may correspond to the distance between the outermost first lower pads BPAD1 among the plurality of first lower pads BPAD1. Therefore, the lower high-potential power supply wiring BVL1 may contact each of the plurality of lower high-potential power supply link wirings extending in the column direction.

[0100] A plurality of lower auxiliary high potential power supply wirings BAVL1 may be arranged in the first lower wiring area BLA1. The plurality of lower auxiliary high potential power supply wirings BAVL1 may be arranged to overlap the lower high potential power supply wiring BVL1.

[0101] On the other hand, the width of each of the lower auxiliary high potential power supply wirings BAVL1 may be increased as it becomes closer to the lower low potential power supply wiring BVL2. For example, the planar shape of the lower auxiliary high potential power supply wirings BAVL1 may be triangular.

[0102] The plurality of lower auxiliary high potential power wirings BAVL1 may be spaced apart from each other between the flexible films COF and alternately arranged with the flexible films COF in the row direction.

[0103] The plurality of lower auxiliary high potential power supply lines BAVL1 and the plurality of lower data link lines BDL will be described in detail later with reference to FIG.

[0104] In the second lower wiring area BLA2 on the rear surface of the second substrate 130, a plurality of lower low potential power supply link wires are arranged, extending in the column direction from a plurality of second lower pads BPAD2.

[0105] Each of the plurality of lower low potential link lines may extend in the column direction and be connected to the lower low potential power line BVL2.

[0106] The lower low-potential power supply wiring BVL2 may have a major axis in the row direction. For example, the width of the lower low-potential power supply wiring BVL2 may correspond to the width of the second lower pad area BPA2. For example, the width of the lower low-potential power supply wiring BVL2 may correspond to the distance between the second lower pads BPAD2 arranged at the outermost periphery among the plurality of second lower pads BPAD2. Therefore, the lower low-potential power supply wiring BVL2 may be in contact with each of the plurality of lower low-potential power supply link wirings extending in the column direction.

[0107] Meanwhile, the lower data link wiring BDL, the lower gate link wiring, and the lower high potential power link wiring arranged in the first lower wiring area BLA1 of the second substrate 130 may each extend to a plurality of first lower pads BPAD1 and be connected to a plurality of first upper pads TPAD1 arranged on the first substrate 110 through first side wiring described later.

[0108] In addition, each of the lower low potential power link wirings arranged in the second lower wiring area BLA2 of the second substrate 130 can extend to a plurality of second lower pads BPAD2 and be connected to a plurality of second upper pads TPAD2 arranged on the first substrate 110 through second side wiring described later.

[0109] The side wiring SRL will be described in detail later with reference to FIG.

[0110] In the following, the sub-pixels SP of the pixel area UPA will be described in more detail with reference to FIG.

[0111] 5 is a cross-sectional view of a subpixel of a display device according to an embodiment of the present disclosure. Each of the subpixels SP of the display panel PN of the display device 100 according to an embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, an adhesive layer 116, a second planarization layer 117, a third planarization layer 118, a passivation layer 119, a driving transistor DT, a light-emitting element LED, a plurality of reflective electrodes RE1 and RE2, a plurality of connecting electrodes CE1 and CE2, a light-shielding layer LS, and an auxiliary electrode LE.

[0112] First, the first substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. For example, the first substrate 110 may be made of glass or resin. The first substrate 110 may also be made of a flexible material including a polymer or plastic.

[0113] A light-shielding layer LS is disposed in each of the sub-pixels SP on the first substrate 110. The light-shielding layer LS blocks light incident on an active layer ACT of a driving transistor DT (described later) below the first substrate 110. The light-shielding layer LS blocks light incident on the active layer ACT of the driving transistor DT, thereby minimizing leakage current. For example, the light-shielding layer LS may be made of molybdenum (Mo), but is not limited thereto.

[0114] A buffer layer 111 is disposed on the first substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 can be formed of, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of first substrate 110 or the type of transistor, and is not limited thereto.

[0115] The drive transistor DT is disposed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0116] The active layer ACT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0117] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0118] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0119] A first interlayer insulating layer 113 is disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 to connect the source electrode SE and the drain electrode DE to the active layer ACT. The first interlayer insulating layer 113 is an insulating layer for protecting the first interlayer insulating layer 113 and the underlying components, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0120] The capacitor electrode C2 is disposed on the first interlayer insulating layer 113. The capacitor electrode C2 can be disposed so as to overlap the gate electrode GE with the first interlayer insulating layer 113 sandwiched therebetween.

[0121] A second interlayer insulating layer 114 is disposed on the capacitor electrode C2. Contact holes are formed in the second interlayer insulating layer 114 to connect the source electrode SE and the drain electrode DE to the active layer ACT. The second interlayer insulating layer 114 is an insulating layer for protecting the components below the second interlayer insulating layer 114, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0122] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0123] Meanwhile, in this specification, it has been described that the first interlayer insulating layer 113 and the second interlayer insulating layer 114, i.e., multiple insulating layers, are arranged between the gate electrode GE and the source electrode SE and drain electrode DE, but only one insulating layer may be arranged between the gate electrode GE and the source electrode SE and drain electrode DE, and the present invention is not limited to this.

[0124] Furthermore, as shown in the drawing, when multiple insulating layers such as a first interlayer insulating layer 113 and a second interlayer insulating layer 114 are arranged between the gate electrode GE and the source electrode SE and drain electrode DE, an electrode can be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and the further formed electrode can form a capacitor with other components arranged below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0125] An auxiliary electrode LE is disposed on the gate insulating layer 112. The auxiliary electrode LE electrically connects the light-shielding layer LS under the buffer layer 111 to one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to one of the source electrode SE or the drain electrode DE through the auxiliary electrode LE and does not function as a floating gate, thereby minimizing fluctuations in the threshold voltage of the driving transistor DT caused by the floating light-shielding layer LS. Although the light-shielding layer LS is shown connected to the source electrode SE in the drawings, the light-shielding layer LS may also be connected to the drain electrode DE, and is not limited thereto.

[0126] A first planarization layer 115 is disposed on the driving transistor DT. The first planarization layer 115 can planarize the upper surface of the first substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 can be configured as a single layer or multiple layers and can be made of, for example, photoresist or an acrylic organic material, but is not limited thereto.

[0127] A plurality of reflective electrodes RE1 and RE2 spaced apart from each other are disposed on the first planarization layer 115. The reflective electrodes RE1 and RE2 electrically connect the light emitting element LED to the power supply wiring and the driving transistor DT, and also function as a reflector that reflects light emitted from the light emitting element LED toward the upper portion of the light emitting element LED. The reflective electrodes RE1 and RE2 are formed of a conductive material with excellent reflective properties, and can reflect light emitted from the light emitting element LED toward the upper portion of the light emitting element LED.

[0128] For example, the plurality of reflective electrodes RE1 and RE2 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0129] The plurality of reflective electrodes RE1 and RE2 includes a first reflective electrode RE1 and a second reflective electrode RE2. The second reflective electrode RE2 may electrically connect the driving transistor DT and the light emitting element LED. The second reflective electrode RE2 may be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the first planarization layer 115. The second reflective electrode RE2 may also be electrically connected to the first electrode 124 of the light emitting element LED through a second connecting electrode CE2, which will be described later.

[0130] The first reflective electrode RE1 may electrically connect the power supply line to the light emitting element LED. The first reflective electrode RE1 may be connected to the power supply line and may be electrically connected to the second electrode 125 of the light emitting element LED through a first connecting electrode CE1, which will be described later.

[0131] A passivation layer 119 is disposed on the reflective electrodes RE1 and RE2. Contact holes for connecting the reflective electrodes RE1 and RE2 to the first connecting electrode CE1 and the second connecting electrode CE2 are disposed in the passivation layer 119. The passivation layer 119 is an insulating layer for protecting the underlying components and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0132] An adhesive layer 116 is disposed on the plurality of reflective electrodes RE1 and RE2. The adhesive layer 116 is coated on the front surface of the first substrate 110 and can fix the light emitting element LED disposed on the adhesive layer 116. The adhesive layer 116 may be made of, for example, any one of adhesive polymer, epoxy resist, UV resin, polyimide series, acrylate series, urethane series, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0133] A plurality of light emitting elements LED are disposed in each of the plurality of sub-pixels SP on the adhesive layer 116. The plurality of light emitting elements LED are elements that emit light in response to current and may include light emitting elements LED that emit red light, green light, blue light, etc., and various colors including white light can be realized by combining these light emitting elements. For example, the plurality of light emitting elements LED may be, but are not limited to, LEDs (Light Emitting Diodes) or micro LEDs.

[0134] The plurality of light-emitting elements LED may include a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element may be arranged in the first sub-pixel SP1, the second light-emitting element may be arranged in the second sub-pixel SP2, and the third light-emitting element may be arranged in the third sub-pixel SP3. For example, the first light-emitting element may be a red light-emitting element, the second light-emitting element may be a green light-emitting element, and the third light-emitting element may be a blue light-emitting element.

[0135] Each of the plurality of light-emitting elements LED includes a first semiconductor layer 121 , a light-emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 and a sealing film 126 .

[0136] The first semiconductor layer 121 is disposed on the adhesive layer 116, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type and p-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0137] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may have a single layer or a multi-quantum well (MQW) structure and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0138] A first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the driving transistor DT and the first semiconductor layer 121. The first electrode 124 may be disposed on an upper surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0139] A second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on an upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting a power wiring to the second semiconductor layer 123. The second electrode 125 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0140] Next, a sealing film 126 is disposed to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The sealing film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. Contact holes exposing the first electrode 124 and the second electrode 125 are formed in the sealing film 126, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be electrically connected to the first electrode 124 and the second electrode 125.

[0141] A second planarization layer 117 and a third planarization layer 118 are disposed on the adhesive layer 116. The second planarization layer 117 overlaps portions of the side surfaces of the light-emitting elements LED to fix and protect the light-emitting elements LED. Specifically, although FIG. 5 illustrates the encapsulation film 126 surrounding all of the side surfaces of the first semiconductor layer 121, portions of the side surfaces of the first semiconductor layer 121 may be exposed from the encapsulation film 126. The light-emitting elements LED manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, a portion of the encapsulation film 126 may be peeled off during the process of separating the light-emitting elements LED from the wafer. For example, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting element LED may be peeled off during the process of separating the light-emitting elements LED from the wafer, thereby exposing a portion of the lower side surface of the first semiconductor layer 121 to the outside. However, even if the lower portion of the light-emitting element LED is exposed from the encapsulation film 126, the first connecting electrode CE1 and the second connecting electrode CE2 are formed after forming the second planarization layer 117 that covers the side surface of the first semiconductor layer 121, so that short-circuit defects can be minimized.

[0142] In addition, the third planarization layer 118 is formed to cover the second planarization layer 117 and an upper portion of the light emitting element LED, and contact holes exposing the first electrode 124 and the second electrode 125 of the light emitting element LED may be formed therein. The first electrode 124 and the second electrode 125 of the light emitting element LED are exposed from the third planarization layer 118, and the third planarization layer 118 is partially disposed in the region between the first electrode 124 and the second electrode 125, thereby minimizing short circuit defects.

[0143] The second planarization layer 117 and the third planarization layer 118 may be configured as a single layer or multiple layers and may be made of, for example, photoresist or an acrylic organic material, but are not limited thereto. Meanwhile, although the present specification has described the second planarization layer 117 and the third planarization layer 118 as being disposed, the planarization layer may be configured as a single layer and is not limited thereto.

[0144] A plurality of connecting electrodes CE1 and CE2 are disposed on the third planarization layer 118. The plurality of connecting electrodes CE1 and CE2 includes a plurality of first connecting electrodes CE1 and a plurality of second connecting electrodes CE2.

[0145] The second connecting electrode CE2 is disposed in each of the subpixels SP and electrically connects the light emitting element LED and the driving transistor DT. The second connecting electrode CE2 may be connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Therefore, the second connecting electrode CE2 may be electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through the second reflective electrode RE2. The second connecting electrode CE2 may be connected to the first electrode 124 of each of the light emitting elements LED through a contact hole formed in the third planarization layer 118. Therefore, the second connecting electrode CE2 may electrically connect the driving transistor DT and the first electrode 124 of each of the light emitting elements LED.

[0146] The first connecting electrode CE1 is an electrode for electrically connecting the light emitting element LED to a power supply wiring. The first connecting electrode CE1 may be connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. The first connecting electrode CE1 may also be electrically connected to a power supply wiring through the first reflective electrode RE1. The first connecting electrode CE1 may also be connected to the second electrodes 125 of the light emitting elements LEDs through contact holes formed in the third planarization layer 118. Therefore, the first connecting electrode CE1 can electrically connect the power supply wiring to the second electrodes 125 of the light emitting elements LEDs.

[0147] A bank BB is disposed on the first connecting electrode CE1 and the second connecting electrode CE2, and may be spaced apart from the light emitting element LED by a predetermined distance.

[0148] The bank BB may be made of an opaque material to reduce color mixing between the plurality of sub-pixels SP, for example, but is not limited to, black resin.

[0149] A protective layer 190 is disposed on the first connecting electrode CE1, the second connecting electrode CE2, and the bank BB. The protective layer 190 is a layer for protecting the components below the protective layer 190 and may cover at least a portion of the light-emitting element LED. The protective layer 190 may be formed of, but is not limited to, a single layer or multiple layers of transparent epoxy, silicon oxide (SiOx), or silicon nitride (SiNx).

[0150] Meanwhile, the second connecting electrode CE2 connecting the driving transistor DT and the light emitting element LED arranged in each of the sub-pixels SP may be individually arranged in each of the sub-pixels SP.

[0151] The plurality of upper pads TPAD and the plurality of lower pads BPAD will be described in detail below with reference to FIGS. 6 to 7b.

[0152] Figure 6 is a cross-sectional view of a pad region of a display device according to an embodiment of the present disclosure. Figure 7a is a cross-sectional view of an upper pad of a display device according to an embodiment of the present disclosure. Figure 7b is a cross-sectional view of a lower pad of a display device according to an embodiment of the present disclosure. For convenience of illustration, in Figure 7b, the positions of the second substrate 130 and the lower components of the second substrate 130 are reversed so that the second substrate 130 is disposed at the bottom.

[0153] 6 and 7a, each of the plurality of upper pads TPAD may be formed of a plurality of conductive layers. For example, each of the plurality of upper pads TPAD may include a first upper pad electrode TPEa, a second upper pad electrode TPEb, and a third upper pad electrode TPEc. That is, each of the plurality of first upper pads TPAD1 and the plurality of second upper pads TPAD2 may include a first upper pad electrode TPEa, a second upper pad electrode TPEb, and a third upper pad electrode TPEc.

[0154] First, the first upper pad electrode TPEa is disposed on the second interlayer insulating layer 114. The first upper pad electrode TPEa may be made of the same conductive material as the source electrode SE and the drain electrode DE, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0155] A second upper pad electrode TPEb is disposed on the first upper pad electrode TPEa. The second upper pad electrode TPEb may be made of the same conductive material as the plurality of reflective electrodes RE1 and RE2. The second upper pad electrode TPEb may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0156] The third upper pad electrode TPEc is disposed on the second upper pad electrode TPEb. The third upper pad electrode TPEc may be made of the same conductive material as the first connecting electrode CE1 and the second connecting electrode CE2, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0157] At this time, although not shown in the drawing, some of the upper pad electrodes of the upper pad TPAD are electrically connected to a plurality of wirings on the first substrate 110 and can supply various signals to the plurality of wirings and a plurality of sub-pixels SP. For example, the first upper pad electrode TPEa and / or the second upper pad electrode TPEb of the upper pad TPAD are connected to the upper data wiring TDL, the upper high potential power wiring TVL1, the upper low potential power wiring TVL2, etc., arranged in the display area AA and can transmit signals to each of them.

[0158] A first metal layer ML1, a second metal layer ML2, and a plurality of insulating layers may be disposed below the upper pad TPAD. The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers may be disposed below the upper pad TPAD to adjust the step height of the upper pad TPAD. For example, a buffer layer 111, a gate insulating layer 112, a first metal layer ML1, a first interlayer insulating layer 113, and a second metal layer ML2 may be sequentially disposed between the upper pad TPAD and the first substrate 110. The first metal layer ML1 may be made of the same conductive material as the gate electrode GE, and the second metal layer ML2 may be made of the same conductive material as the capacitor electrode C2. However, the plurality of insulating layers and the first metal layer ML1 and second metal layer ML2 below the upper pad TPAD may be omitted depending on the design, and the present invention is not limited thereto.

[0159] The second substrate 130 is disposed below the first substrate 110. The second substrate 130 is a substrate that supports components disposed below the display device 100 and may be an insulating substrate. For example, the second substrate 130 may be made of glass, resin, or the like. The second substrate 130 may also include a polymer or plastic. The second substrate 130 may be made of the same material as the first substrate 110. In some embodiments, the second substrate 130 may be made of a flexible plastic material.

[0160] A bonding layer BL is disposed between the first substrate 110 and the second substrate 130. The bonding layer BL may be made of a material that can be cured through various curing methods to bond the first substrate 110 and the second substrate 130. The bonding layer BL may be disposed only in a portion of the area between the first substrate 110 and the second substrate 130, or may be disposed over the entire area.

[0161] A plurality of lower pads BPAD are arranged on the rear surface of the second substrate 130. The plurality of lower pads BPAD are electrodes for transmitting signals from driving components arranged on the rear surface side of the second substrate 130 to the plurality of side wirings SRL, the plurality of upper pads TPAD and the plurality of wirings on the first substrate 110. The plurality of lower pads BPAD are arranged at the edge of the second substrate 130 in the non-display area NA and may be electrically connected to the side wirings SRL covering the edge of the second substrate 130.

[0162] At this time, a plurality of lower pads BPAD may also be arranged corresponding to a plurality of lower pad regions. Each of the plurality of upper pads TPAD may be arranged corresponding to each of the plurality of lower pads BPAD, and thereafter, the overlapping upper pads TPAD and the lower pads BPAD may be electrically connected to each other through side wirings SRL.

[0163] Each of the plurality of lower pads BPAD includes a plurality of pad electrodes. For example, each of the plurality of lower pads BPAD includes a first lower pad electrode BPEa, a second lower pad electrode BPEb, and a third lower pad electrode BPEc. That is, each of the plurality of first lower pads BPAD1 and the plurality of second lower pads BPAD2 includes a first lower pad electrode BPEa, a second lower pad electrode BPEb, and a third lower pad electrode BPEc.

[0164] In Figure 7b, for convenience of illustration, the lower pad BPAD is shown to be arranged on the second substrate 130, and the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc are shown to be arranged sequentially on the top of the second substrate 130.

[0165] However, the second substrate 130 shown in Fig. 7b is attached to the first substrate 110 with its top and bottom positions reversed. Therefore, when the second substrate 130 and the first substrate 110 are attached to each other, as shown in Fig. 6, a plurality of lower pads BPAD may be arranged under the second substrate 130, and a first lower pad electrode BPEa, a second lower pad electrode BPEb, and a third lower pad electrode BPEc may be arranged sequentially under the second substrate 130.

[0166] In the following, the description will be based on the state when the second substrate 130 is attached to the first substrate 110, and the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc will be sequentially arranged under the second substrate 130.

[0167] First, the first lower pad electrode BPEa is disposed under the second substrate 130. The first lower pad electrode BPEa may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0168] A first insulating layer 131 is disposed under the first lower pad electrode BPEa. Referring to FIG. 7b, the first insulating layer 131 may cover a side portion of the first lower pad electrode BPEa. Meanwhile, the first insulating layer 131 may include an opening that exposes a portion of one surface of the first lower pad electrode BPEa.

[0169] The first insulating layer 131 may be an inorganic insulating layer, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0170] The second lower pad electrode BPEb is disposed under the first insulating layer 131. Referring to FIG. 7b, the second lower pad electrode BPEb may be in contact with one surface of the first lower pad electrode BPEa exposed by the opening in the first insulating layer 131.

[0171] The second lower pad electrode BPEb may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0172] A third lower pad electrode BPEc is disposed under the second lower pad electrode BPEb, and may be in contact with one surface of the second lower pad electrode BPEb, as shown in FIG.

[0173] 7b, the third lower pad electrode BPEc and the second lower pad electrode BPEb may completely overlap each other. For example, the overlapping area between the third lower pad electrode BPEc and the second substrate 130 may be the same as the overlapping area between the second lower pad electrode BPEb and the second substrate 130.

[0174] The third lower pad electrode BPEc may be made of a material that is not corroded even when in contact with air or moisture to prevent corrosion of the second lower pad electrode BPEb. For example, the third lower pad electrode BPEc may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0175] A second insulating layer 132 is disposed below the third lower pad electrode BPEc. The second insulating layer 132 may be an inorganic insulating layer. For example, the second insulating layer 132 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0176] Meanwhile, the second insulating layer 132 may expose a portion of the third lower pad electrode BPEc or cover a portion of the edge of the third lower pad electrode BPEc.

[0177] The third lower pad electrode BPEc exposed by the second insulating layer 132 can be in contact with the side wiring SRL described later.

[0178] Meanwhile, the first lower pad electrode BPEa, the second lower pad electrode BPEb, and the third lower pad electrode BPEc of the plurality of lower pads BPAD may extend toward and be electrically connected to a plurality of flexible film COFs disposed on the rear side of the second substrate 130, and the plurality of flexible film COFs may supply various signals to a plurality of side wirings SRL, a plurality of upper pads TPAD, a plurality of wirings, and a plurality of sub-pixels SP through the plurality of lower pads BPAD. Thus, signals from the driving components may be transmitted to the signal wirings and a plurality of sub-pixels SP on the front side of the first substrate 110 through the plurality of lower pads BPAD, the side wirings SRL of the second substrate 130, and the plurality of upper pads TPAD of the first substrate 110.

[0179] 6, a plurality of side wirings SRL are disposed on the side surfaces of the first substrate 110 and the second substrate 130. The side wirings SRL may electrically connect a plurality of upper pads TPAD formed on the top surface of the first substrate 110 to a plurality of lower pads BPAD formed on the rear surface of the second substrate 130. For example, the side wirings SRL may be disposed in contact with the third upper pad electrodes TPEc and the third lower pad electrodes BPEc, respectively, and surrounding the side surfaces of the display device 100. Each of the side wirings SRL may cover a plurality of upper pads TPAD at an edge of the first substrate 110, a side surface of the first substrate 110, a side surface of the second substrate 130, and a plurality of lower pads BPAD at an edge of the second substrate 130. For example, the side wirings SRL may be formed by a pad printing method using a conductive ink, for example, a conductive ink including silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), etc.

[0180] The multiple side wirings SRL may include multiple first side wirings arranged corresponding to the first edge EG1 of the first substrate 110 and the first edge EG1 of the second substrate 130, and multiple second side wirings arranged corresponding to the second edge EG2 of the first substrate 110 and the second edge EG2 of the second substrate 130.

[0181] Therefore, among the plurality of side wirings SRL, the plurality of first side wirings can connect the plurality of first upper pads TPAD1 and the plurality of first lower pads BPAD1, and the plurality of second side wirings can connect the plurality of second upper pads TPAD2 and the plurality of second lower pads BPAD2.

[0182] 6, a side insulating layer 150 is disposed to cover the side wirings SRL. The side insulating layer 150 may be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 130, and the rear surface of the second substrate 130 to cover the side wirings SRL. The side insulating layer 150 may protect the side wirings SRL.

[0183] On the other hand, if the plurality of side wirings SRL are made of a metal material, problems may occur in that external light is reflected by the plurality of side wirings SRL or light emitted from the light emitting element LED is reflected by the plurality of side wirings SRL and is visible to the user. Therefore, the side insulating layer 150 is configured to include a black material to suppress external light reflection. For example, the side insulating layer 150 may be formed by a pad printing method using an insulating material including a black material, for example, black ink.

[0184] A sealing member 160 is disposed to cover the side insulating layer 150. The sealing member 160 is disposed to surround the side of the display device 100 and can protect the display device 100 from external impacts, moisture, oxygen, etc. For example, the sealing member 160 may be made of an insulating material such as polyimide (PI), polyurethane, epoxy, or acrylic, but is not limited thereto.

[0185] An optical film MF is disposed on the sealing member 160, the side insulating layer 150, and the protective layer 190. The optical film MF may be a functional film that realizes a higher quality image while protecting the display device 100. For example, the optical film MF may include, but is not limited to, a shatterproof film, an anti-glare film, an anti-reflecting film, a low-reflecting film, an OLED transmittance controllable film, or a polarizer.

[0186] Meanwhile, an adhesive layer may be further disposed between the optical film MF and the sealing member 160, the side insulating layer 150, and the protective layer 190, but for convenience of illustration, the adhesive layer is omitted in Figures 5 and 6. Alternatively, the optical film MF may be defined as including an adhesive layer disposed underneath.

[0187] The edge of the sealing member 160 and the edge of the optical film MF may be aligned on the same line. During the manufacturing process of the display device 100, a larger optical film MF may be attached to the top of the first substrate 110, and the sealing member 160 may be formed to cover the side insulating layer 150. Then, a laser may be irradiated onto the sealing member 160 and the optical film MF to cut portions of the sealing member 160 and the optical film MF to correspond to the edges of the display device 100. Therefore, the size of the display device 100 may be adjusted and the edges of the display device 100 may be formed flat through the process of cutting the outer edges of the sealing member 160 and the optical film MF.

[0188] Hereinafter, the COF pad area BPA3 of the display device according to one embodiment of the present specification will be described in detail with reference to FIG.

[0189] Figure 8 is a cross-sectional view of the second substrate taken along line A-A' in Figure 4. Figure 8 is a cross-sectional view of the COF pad area BPA3. For ease of illustration, the flexible film COF is not shown in Figure 8, and only the COF pad BPAD3 is shown. For ease of illustration, the positions of the second substrate 130 and the COF pad BPAD3 are reversed in Figure 8, and the second substrate 130 is shown as being disposed at the bottom in the drawing.

[0190] Referring to FIG. 8, a plurality of COF pads BPAD3 are arranged in a COF pad area BPA3.

[0191] Each of the COF pads BPAD3 may be made of multiple conductive layers, and may include, for example, a first COF pad electrode BPE3a, a second COF pad electrode BPE3b, and a third COF pad electrode BPE3c.

[0192] In FIG. 8, for convenience of illustration, the COF pad BPAD3 is shown to be arranged on the second substrate 130, and the first COF pad electrode BPE3a, the second COF pad electrode BPE3b, and the third COF pad electrode BPE3c are shown to be arranged sequentially on the top of the second substrate 130.

[0193] 8 is attached to the first substrate 110 with its top and bottom positions reversed. Therefore, in a state where the second substrate 130 and the first substrate 110 are attached to each other, a plurality of COF pads BPAD3 may be arranged under the second substrate 130, and a first COF pad electrode BPE3a, a second COF pad electrode BPE3b, and a third COF pad electrode BPE3c may be arranged sequentially under the second substrate 130.

[0194] In the following, the description will be based on the state when the second substrate 130 is attached to the first substrate 110, and the first COF pad electrode BPE3a, the second COF pad electrode BPE3b, and the third COF pad electrode BPE3c are sequentially arranged under the second substrate 130.

[0195] The first COF pad electrode BPE3a is disposed on the lower part of the second substrate 130.

[0196] The first COF pad electrode BPE3a may be made of the same material as the first lower pad electrode BPEa, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0197] The second COF pad electrode BPE3b is disposed under the first COF pad electrode BPE3a and may be in contact with one surface of the first COF pad electrode BPE3a exposed by the first insulating layer 131.

[0198] The second COF pad electrode BPE3b may be made of the same material as the second lower pad electrode BPEb, for example, the second COF pad electrode BPE3b may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0199] The third COF pad electrode BPE3c is disposed under the second COF pad electrode BPE3b and may be in contact with one surface of the second COF pad electrode BPE3b.

[0200] The third COF pad electrode BPE3c and the second COF pad electrode BPE3b may completely overlap each other. For example, the overlapping area between the third COF pad electrode BPE3c and the second substrate 130 may be the same as the overlapping area between the second COF pad electrode BPE3b and the second substrate 130.

[0201] The third COF pad electrode BPE3c may be made of the same material as the third lower pad electrode BPEc. For example, the third COF pad electrode BPE3c may be made of a material that is not corroded even when in contact with air or moisture to prevent corrosion of the second COF pad electrode BPE3b. For example, the third COF pad electrode BPE3c may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0202] The COF pads BPAD3 may be electrically connected to the flexible film COFs through third COF pad electrodes BPE3c among the conductive layers constituting each of the COF pads BPAD3, i.e., may be electrically connected to an external module through the third COF pad electrodes BPE3c.

[0203] For example, the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible film COFs through the third COF pad electrodes BPE3c exposed by the second insulating layer 132.

[0204] Although not shown in FIG. 8, among the plurality of conductive layers constituting each of the plurality of COF pads BPAD3, the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible film COFs through a third COF pad electrode BPE3c.

[0205] The COF pads BPAD3 may be connected to the flexible film COFs through an adhesive layer. For example, the adhesive layer may be an anisotropic conductive film (ACF) or a conductive paste. Also, the flexible film COFs may be electrically connected to the COF pads BPAD3 of the second substrate 130 by heat and pressure.

[0206] The lower power supply wiring will be described in detail below with reference to FIG.

[0207] Figure 9 is a cross-sectional view of the second substrate taken along line B-B' in Figure 4. Figure 9 is a cross-sectional view of the first lower wiring region BLA1 and the second lower wiring region BLA2. For ease of illustration, Figure 9 shows the second substrate 130 and the positions of the components below the second substrate 130 inverted so that the second substrate 130 is located at the bottom.

[0208] Referring to FIG. 9, a lower high potential power supply wiring BVL1, a lower auxiliary high potential power supply wiring BAVL1, and a plurality of lower data link wirings BDL are arranged in a first lower wiring area BLA1.

[0209] 9, for convenience of illustration, the second substrate 130 is shown as having a lower high potential power supply wiring BVL1, a lower auxiliary high potential power supply wiring BAVL1, and a plurality of lower data link wirings BDL arranged thereon.

[0210] 9 is attached to the first substrate 110 in an inverted position. Therefore, when the second substrate 130 and the first substrate 110 are attached to each other, a lower high potential power supply line BVL1, a lower auxiliary high potential power supply line BAVL1, and a plurality of lower data link lines BDL may be disposed below the second substrate 130.

[0211] In the following, the description will be based on the assumption that the second substrate 130 is attached to the first substrate 110, and that a lower high potential power wiring BVL1, a lower auxiliary high potential power wiring BAVL1, and a plurality of lower data link wirings BDL are arranged under the second substrate 130.

[0212] The lower high potential power supply wiring BVL1 is disposed below the second substrate 130.

[0213] The lower high potential power wiring BVL1 may be made of the same material as the first lower pad electrode BPEa and the first COF pad electrode BPE3a. For example, the lower high potential power wiring BVL1 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0214] A first insulating layer 131 is disposed below the lower high-potential power supply wiring BVL1. The first insulating layer 131 may include a plurality of openings disposed at positions overlapping with a plurality of lower auxiliary high-potential power supply wirings BAVL1 (described later). Meanwhile, the first insulating layer 131 is disposed so as to overlap with a plurality of lower data link wirings BDL, and can insulate the lower high-potential power supply wiring BVL1 from the plurality of lower data link wirings BDL.

[0215] Below the first insulating layer 131, a plurality of lower auxiliary high potential power supply lines BAVL1 and a plurality of lower data link lines BDL are arranged.

[0216] First, below the first insulating layer 131, a plurality of lower auxiliary high potential power supply wirings BAVL1 are arranged.

[0217] The plurality of lower auxiliary high potential power wirings BAVL1 may be in contact with the front surface of the lower high potential power wiring BVL1 exposed by the first insulating layer 131. For example, the first insulating layer 131 and the plurality of lower auxiliary high potential power wirings BAVL1 may be disposed below the lower high potential power wiring BVL1, and the first insulating layer 131 may be disposed in an area excluding between the flexible films COF. Thus, the plurality of lower auxiliary high potential power wirings BAVL1 may be in contact with the lower high potential power wiring BVL1 in an area between the flexible films COF where the first insulating layer 131 is exposed.

[0218] Therefore, the plurality of lower auxiliary high potential power supply wirings BAVL1 contact the lower high potential power supply wiring BVL1, thereby minimizing the voltage drop and voltage deviation.

[0219] Each of the plurality of lower auxiliary high potential power supply wirings BAVL1 includes a first lower auxiliary high potential power supply wiring BAVL1a and a second lower auxiliary high potential power supply wiring BAVL1b.

[0220] A first insulating layer 131 is disposed below the second substrate 130, and a first lower auxiliary high potential power supply wiring BAVL1a is disposed below the first insulating layer 131.

[0221] The first lower auxiliary high potential power wiring BAVL1a may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the first lower auxiliary high potential power wiring BAVL1a may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0222] The second lower auxiliary high potential power supply wiring BAVL1b is disposed below the first lower auxiliary high potential power supply wiring BAVL1a.

[0223] The second lower auxiliary high potential power wiring BAVL1b may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the second lower auxiliary high potential power wiring BAVL1b may be made of a material that is not corroded even when in contact with air or moisture to prevent corrosion of the first lower auxiliary high potential power wiring BAVL1a. For example, the second lower auxiliary high potential power wiring BAVL1b may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0224] The second lower auxiliary high-potential power wiring BAVL1b may contact the front surface of the first lower auxiliary high-potential power wiring BAVL1a. Meanwhile, the second lower auxiliary high-potential power wiring BAVL1b may completely overlap the first lower auxiliary high-potential power wiring BAVL1a. For example, the overlapping area between the second lower auxiliary high-potential power wiring BAVL1b and the second substrate 130 may be the same as the overlapping area between the first lower auxiliary high-potential power wiring BAVL1a and the second substrate 130.

[0225] The plurality of lower auxiliary high potential power wirings BAVL1 may be made of the same material as the second lower pad electrodes BPEb and the second COF pad electrodes BPE3b.

[0226] For example, the plurality of lower auxiliary high potential power wirings BAVL1 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0227] Below the first insulating layer 131, a plurality of lower data link wirings BDL are arranged.

[0228] The plurality of lower data link lines BDL can be arranged in the same layer as the plurality of lower auxiliary high potential power supply lines BAVL1.

[0229] The lower data link wirings BDL may be arranged to overlap the lower high-potential power supply wiring BVL1, for example, with the first insulating layer 131 sandwiched therebetween.

[0230] Each of the plurality of lower data link wirings BDL includes a first lower data link wiring BDLa and a second lower data link wiring BDLb.

[0231] A first insulating layer 131 is disposed below the second substrate 130, and a first lower data link wiring BDLa is disposed below the first insulating layer 131.

[0232] The first lower data link wiring BDLa may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the first lower data link wiring BDLa may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0233] The second lower data link wiring BDLb is disposed below the first lower data link wiring BDLa.

[0234] The second lower data link line BDLb may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the second lower data link line BDLb may be made of a material that is not corroded even when in contact with air or moisture to prevent corrosion of the first lower data link line BDLa. For example, the second lower data link line BDLb may be made of a conductive material, such as a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0235] The second lower data link wiring BDLb may contact the front surface of the first lower data link wiring BDLa. Meanwhile, the second lower data link wiring BDLb may completely overlap the first lower data link wiring BDLa. For example, the overlapping area between the second lower data link wiring BDLb and the second substrate 130 may be the same as the overlapping area between the first lower data link wiring BDLa and the second substrate 130.

[0236] The lower low potential power supply wiring BVL2 is arranged in the second lower wiring area BLA2.

[0237] 9, for convenience of illustration, the lower low potential power wiring BVL2 is shown disposed on the second substrate 130, but the second substrate 130 shown in FIG. 9 is attached to the first substrate 110 in a vertically inverted position. Therefore, when the second substrate 130 and the first substrate 110 are attached to each other, the lower low potential power wiring BVL2 may be disposed below the second substrate 130.

[0238] In the following description, it is assumed that the second substrate 130 is attached to the first substrate 110, and that the lower low potential power wiring BVL2 is disposed below the second substrate 130.

[0239] The lower low-potential power supply wiring BVL2 includes a first lower low-potential power supply wiring BVL2a, a second lower low-potential power supply wiring BVL2b, and a third lower low-potential power supply wiring BVL2c.

[0240] The first lower low potential power supply wiring BVL2a is disposed below the second substrate 130.

[0241] The first lower low potential power wiring BVL2a may be made of the same material as the first lower pad electrode BPEa and the first COF pad electrode BPE3a. For example, the first lower low potential power wiring BVL2a may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0242] A first insulating layer 131 may be disposed below the first lower low potential power supply wiring BVL2a, and a second lower low potential power supply wiring BVL2b may be disposed below the first insulating layer 131.

[0243] The second lower low-potential power wiring BVL2b may be in contact with the front surface of the first lower low-potential power wiring BVL2a exposed by the first insulating layer 131. For example, the first insulating layer 131 and the second lower low-potential power wiring BVL2b may be disposed below the first lower low-potential power wiring BVL2a, and the first insulating layer 131 may be disposed in an area excluding the second lower wiring area BLA2. Thus, the second lower low-potential power wiring BVL2b may be in contact with the first lower low-potential power wiring BVL2a in the second lower wiring area BLA2.

[0244] The second lower low potential power wiring BVL2b may be made of the same material as the second lower pad electrode BPEb and the second COF pad electrode BPE3b. For example, the second lower low potential power wiring BVL2b may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0245] A third lower low potential power supply wiring BVL2c may be disposed below the second lower low potential power supply wiring BVL2b.

[0246] The third lower low-potential power supply wiring BVL2c can come into contact with the front surface of the second lower low-potential power supply wiring BVL2b.

[0247] The third lower low potential power wiring BVL2c may be made of the same material as the third lower pad electrode BPEc and the third COF pad electrode BPE3c. For example, the third lower low potential power wiring BVL2c may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0248] Meanwhile, the third lower low potential power wiring BVL2c may completely overlap the second lower low potential power wiring BVL2b. For example, the overlapping area between the third lower low potential power wiring BVL2c and the second substrate 130 may be the same as the overlapping area between the second lower low potential power wiring BVL2b and the second substrate 130.

[0249] When metal layers disposed on a display panel are exposed to the outside, they may react with air or moisture and corrode. For example, a plurality of upper pads disposed on a first substrate and a plurality of lower pads disposed on a second substrate may react with air or moisture and corrode. Therefore, to prevent corrosion of the plurality of upper pads and a plurality of lower pads, a transparent conductive layer is used as a plurality of pad electrodes constituting the plurality of upper pads and a plurality of lower pads. In this case, a plurality of power lines or a plurality of data lines may be disposed on the same layer as the transparent conductive layer of the plurality of upper pads and the plurality of lower pads. However, when the plurality of power lines or a plurality of data lines are formed using a transparent conductive layer, a separate mask process is performed to pattern the transparent conductive layer. For example, a process of forming an insulating layer, such as an organic insulating layer, on or under the transparent conductive layer may be added. This increases the number of masks, which increases manufacturing costs and time.

[0250] Meanwhile, wiring made of a transparent conductive layer may be arranged overlapping metal layer wiring having different loads. For example, low-potential power wiring formed of a transparent conductive layer on the rear surface of the second substrate may be arranged overlapping data wiring and high-potential power wiring. In this case, potential differences may occur between the low-potential power wiring and data wiring, between the low-potential power wiring and high-potential power wiring, and between the data wiring and high-potential power wiring. This may result in parasitic capacitance between the low-potential power wiring, data wiring, and high-potential power wiring, and short circuits may occur between the high-potential power wiring, low-potential power wiring, and data wiring due to external conditions. In particular, the rear surface of the second substrate comes into contact with a support that supports the second substrate during the display device manufacturing process. This contact with the support may cause cuts in the rear surface of the second substrate. Specifically, when attaching an optical film to the first substrate, pressure is applied from the top of the first substrate toward the bottom of the second substrate, which may cut the rear surface of the second substrate, resulting in damage such as scratches. Therefore, there is a problem that an external shock may cause a disconnection path to form between the low potential power supply wiring and the data wiring, or between the low potential power supply wirings.

[0251] Therefore, in the display device 100 according to an embodiment of the present specification, the transparent conductive layer disposed on the rear surface of the second substrate 130 can be formed using the same mask as the metal layer. For example, the third lower pad electrode BPEc, which is disposed at the bottom of the plurality of pad electrodes constituting the plurality of lower pads BPAD and is made of a transparent conductive layer, can be formed in the same process as the second lower pad electrode BPEb, which is made of a metal layer. This reduces the number of masking processes. Furthermore, the same mask as the plurality of wires disposed in the same layer as the second lower pad electrode BPEb can be used to form the plurality of wires disposed in the same layer as the third lower pad electrode BPEc. For example, the second lower data link wiring BDLb disposed in the same layer as the third lower pad electrode BPEc can be formed in the same process as the first lower data link wiring BDLa disposed in the same layer as the second lower pad electrode BPEb. Furthermore, the second lower auxiliary high-potential power wiring BAVL1b disposed in the same layer as the third lower pad electrode BPEc can be formed in the same process as the first lower auxiliary high-potential power wiring BAVL1a disposed in the same layer as the second lower pad electrode BPEb. Therefore, the number of masks can be reduced, and the manufacturing cost and time can be reduced.

[0252] Furthermore, in the display device 100 according to an embodiment of the present specification, the transparent conductive layer disposed on the rear surface of the second substrate 130 may be formed using the same mask as the metal layer, thereby allowing only the second insulating layer 132 to be disposed below the lower data link line BDL. For example, the lower data link line BDL may include a first lower data link line BDLa formed of a metal layer and a second lower data link line BDLb formed of a transparent conductive layer. Therefore, the second lower data link line BDLb having the same potential as the first lower data link line BDLa is disposed below the first lower data link line BDLa, thereby preventing short circuits between lines having different loads that may occur when the rear surface of the second substrate 130 is damaged, such as by scratches. Therefore, the reliability of the display device 100 may be improved by reducing short circuits that may occur on the rear surface of the second substrate 130.

[0253] Display devices according to various embodiments of the present disclosure can be described as follows.

[0254] A display device according to one embodiment of the present specification includes a first substrate including a plurality of upper pads, a second substrate including a plurality of lower pads, and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads, and each of the plurality of lower pads includes a first lower pad electrode disposed on a lower portion of a second substrate, a first insulating layer disposed on a lower portion of the first lower pad electrode, a second lower pad electrode disposed on a lower portion of the first insulating layer, a third lower pad electrode disposed on a lower portion of the second lower pad electrode, and a second insulating layer disposed on a lower portion of the third lower pad electrode, and the third lower pad electrode may be made of a transparent conductive material.

[0255] According to another feature of the present specification, the semiconductor device may further include a plurality of side ground wirings arranged on a side surface of the first substrate and a side surface of the second substrate, and each of the plurality of ground pads may include an upper ground pad arranged on the first substrate and having the same structure as the plurality of upper pads, and a lower ground pad arranged below the second substrate and having the same structure as the plurality of lower pads, and the plurality of side ground wirings may connect the upper ground pad and the lower ground pad.

[0256] According to another feature of the present disclosure, the third lower pad electrode and the second lower pad electrode may completely overlap each other.

[0257] According to another feature of the present specification, the first insulating layer and the second insulating layer are inorganic insulating layers, and the second insulating layer can open a portion of the second lower pad electrode.

[0258] According to another feature of the present specification, the third lower pad electrode may be in contact with a plurality of side wirings.

[0259] According to another feature of the present specification, the second substrate includes a plurality of first lower pads arranged on a first edge of the second substrate and a plurality of second lower pads arranged on a second edge of the second substrate, and a high potential power supply voltage can be applied to the plurality of first lower pads and a low potential power supply voltage can be applied to the plurality of second lower pads.

[0260] According to another feature of the present specification, the plurality of upper pads may include a plurality of first upper pads and a plurality of second upper pads, and the plurality of side wirings may include a plurality of first side wirings connecting the plurality of first upper pads and the plurality of first lower pads, and a plurality of second side wirings connecting the plurality of second upper pads and the plurality of second lower pads.

[0261] According to another feature of the present specification, the second substrate further includes a low potential power supply wiring, a high potential power supply wiring, and a plurality of data wirings arranged thereon, and the plurality of data wirings may overlap with a portion of the high potential power supply wiring.

[0262] According to another feature of the present specification, the power supply device may further include a plurality of flexible films arranged between the high-potential power wiring and the low-potential power wiring, and a plurality of auxiliary high-potential power wirings arranged on top of the high-potential power wiring and in contact with the high-potential power wiring, and each of the plurality of auxiliary high-potential power wirings may be arranged alternately with the plurality of flexible films.

[0263] According to another aspect of the present disclosure, the high potential power supply wiring may be made of the same material as the first lower pad electrode, and the plurality of auxiliary high potential power supply wirings may be made of the same material as the second lower pad electrode.

[0264] According to another aspect of the present disclosure, the width of each of the plurality of auxiliary high potential power supply lines may increase as it becomes adjacent to the low potential power supply line.

[0265] According to another feature of the present specification, the device further includes a plurality of COF pads disposed on the second substrate and having a flexible film attached thereto, the plurality of COF pads including a first COF pad electrode, a second COF pad electrode, and a third COF pad electrode made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode, respectively, and the second COF pad electrode and the third COF pad electrode may completely overlap.

[0266] According to another feature of the present specification, the second substrate may include a plurality of first lower pads arranged on a first edge of the second substrate and a plurality of second lower pads arranged on a second edge of the second substrate, and a high potential power supply wiring may be arranged on the first edge of the second substrate and connected to the plurality of first lower pads, and a low potential power supply wiring may be arranged on the second edge of the second substrate and connected to the plurality of second lower pads.

[0267] According to another feature of the present specification, the width of the high potential power supply wiring may correspond to the distance between the first lower pads arranged at the outermost periphery among the plurality of first lower pads, and the width of the low potential power supply wiring may correspond to the distance between the second lower pads arranged at the outermost periphery among the plurality of second lower pads.

[0268] According to another aspect of the present disclosure, the low potential power wiring may be made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode.

[0269] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are for illustrative purposes only and do not limit the technical concept of the present specification. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. a first substrate including a plurality of upper pads; a second substrate including a plurality of lower pads; and a plurality of side wirings connecting the plurality of upper pads and the plurality of lower pads; Each of the plurality of lower pads comprises: a first lower pad electrode disposed on a lower portion of the second substrate; a first insulating layer disposed below the first lower pad electrode; a second lower pad electrode disposed under the first insulating layer; a third lower pad electrode disposed below the second lower pad electrode; and a second insulating layer disposed below the third lower pad electrode; the third lower pad electrode is made of a transparent conductive material, The plurality of lower pads include: a plurality of first lower pads disposed on a first edge of the second substrate; and a plurality of second lower pads disposed on a second edge of the second substrate opposite the first edge; a high potential power supply voltage is applied to the plurality of first lower pads; a low potential power supply voltage is applied to the second lower pads; Display device.

2. The display device of claim 1 , wherein the third lower pad electrode and the second lower pad electrode completely overlap each other.

3. the first insulating layer and the second insulating layer are inorganic insulating layers, The display device of claim 1 , wherein the second insulating layer exposes a portion of the third lower pad electrode.

4. The display device according to claim 3 , wherein the third lower pad electrode is in contact with the plurality of side wirings.

5. the plurality of upper pads includes a plurality of first upper pads and a plurality of second upper pads; The plurality of side wirings are a plurality of first side wirings connecting the plurality of first upper pads and the plurality of first lower pads; and The display device of claim 1 , further comprising: a plurality of second side wirings connecting the plurality of second upper pads and the plurality of second lower pads.

6. The second substrate further includes a low potential power supply line, a high potential power supply line, and a plurality of data lines, The display device according to claim 1 , wherein the plurality of data wirings overlap a part of the high-potential power supply wiring.

7. a plurality of flexible films disposed between the high-potential power supply wiring and the low-potential power supply wiring; and a plurality of auxiliary high potential power supply wirings arranged above the high potential power supply wirings and in contact with the high potential power supply wirings; The display device according to claim 6 , wherein the plurality of auxiliary high potential power supply wirings are arranged alternately with the plurality of flexible films.

8. the high potential power supply wiring is made of the same material as the first lower pad electrode; The display device of claim 7 , wherein the plurality of auxiliary high potential power supply wirings are made of the same material as the second lower pad electrode and the third lower pad electrode.

9. 8. The display device according to claim 7, wherein the width of each of the plurality of auxiliary high potential power supply wirings increases as it becomes more adjacent to the low potential power supply wiring.

10. The flexible film further includes a plurality of COF pads disposed on the second substrate, the COF pads being attached to the flexible film; The plurality of COF pads include: a first COF pad electrode, a second COF pad electrode, and a third COF pad electrode, each made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode, respectively; The display device according to claim 7 , wherein the second COF pad electrode and the third COF pad electrode completely overlap each other.

11. The high-potential power supply wiring is disposed on a first edge of the second substrate and connected to the plurality of first lower pads; The display device of claim 6 , wherein the low potential power wiring is disposed on a second edge of the second substrate and connected to the second lower pads.

12. a width of the high potential power supply wiring corresponds to a distance between outermost first lower pads among the plurality of first lower pads; The display device of claim 11 , wherein a width of the low potential power wiring corresponds to a distance between outermost second lower pads among the plurality of second lower pads.

13. The display device of claim 12 , wherein the low potential power supply wiring is made of the same material as the first lower pad electrode, the second lower pad electrode, and the third lower pad electrode.

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