Oscillator

Abstract

To provide an oscillator and a device that can achieve both output of a clock signal and data communication.SOLUTION: An oscillator 4 includes: a vibrator 10; an oscillation circuit 30 that generates an oscillation signal OSC by using the vibrator 10; a clock output terminal TCK; an output circuit 90 that outputs a clock signal CK to an external processing apparatus 100 through the clock output terminal TCK; a first terminal TDA; and an interface circuit 80 that performs communication with the processing apparatus 100 using a data signal DA. In the communication, the output circuit 90 outputs the clock signal CK to the processing apparatus 100 being a master in the communication, and the interface circuit 80 being a slave in the communication receives the data signal DA transmitted from the processing apparatus 100 and synchronized with the clock signal CK through the first terminal TDA, or in synchronization with the clock signal CK, transmits the data signal DA to the processing apparatus 100 through the first terminal TDA.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention Vessels etc. Regarding. [Background technology]

[0002] Patent Document 1 discloses an electronic circuit device that uses asynchronous serial communication to perform serial communication even when the number of external terminals is limited. Patent Document 1 also discloses an electronic circuit device that starts serial communication when it detects that a burst signal has been input to an external terminal, as an electronic circuit device that can prevent the start of serial communication from being mistakenly recognized as occurring due to noise in the data signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-250576 Summary of the Invention [Problem to be solved by the invention]

[0004] The electronic circuit device disclosed in Patent Document 1 uses asynchronous serial communication, and therefore there is a risk that noise may cause problems in the serial communication. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to an oscillator including: an oscillator; an oscillation circuit that generates an oscillation signal using the oscillator; a clock output terminal; an output circuit that outputs the clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit that communicates with the processing device using a data signal, wherein in the communication, the output circuit outputs the clock signal to the processing device that is a master of the communication, and the interface circuit that is a slave of the communication receives the data signal synchronized with the clock signal transmitted from the processing device via the first terminal, or transmits the data signal synchronized with the clock signal to the processing device via the first terminal.

[0006] Another aspect of the present disclosure relates to a device including a clock signal generating circuit that generates a clock signal, a clock output terminal, an output circuit that outputs the clock signal to an external processing device via the clock output terminal, a first terminal, and an interface circuit that communicates with the processing device via a data signal, wherein in the communication, the output circuit outputs the clock signal to the processing device that is a master of the communication, and the interface circuit that is a slave of the communication receives the data signal synchronized with the clock signal transmitted from the processing device via the first terminal, or transmits the data signal synchronized with the clock signal to the processing device via the first terminal. [Brief explanation of the drawings]

[0007] [Figure 1] 3 shows an example of the configuration of an oscillator according to the present embodiment. [Figure 2] FIG. 10 is an explanatory diagram of an oscillation mode in a comparative example of the present embodiment. [Figure 3] FIG. 10 is an explanatory diagram of a communication mode in a comparative example of the present embodiment. [Figure 4] FIG. 3 is an explanatory diagram of a communication mode in the present embodiment. [Figure 5] An example of the I / O circuit configuration of an interface circuit. [Figure 6] FIG. 2 is an explanatory diagram of an example of a communication protocol according to the present embodiment. [Figure 7] FIG. 4 is a signal waveform diagram illustrating an example of communication according to the present embodiment. [Figure 8] FIG. 4 is a signal waveform diagram illustrating an example of communication according to the present embodiment. [Figure 9] 3 shows a detailed first configuration example of the oscillator of the present embodiment. [Figure 10] 10 shows a second detailed configuration example of the oscillator of the present embodiment. [Figure 11] Example bit patterns that represent logic levels "0" and "1". [Figure 12] FIG. 10 is an explanatory diagram of a six-terminal oscillator when this embodiment is not applied. [Figure 13] FIG. 10 is an explanatory diagram illustrating a case where this embodiment is applied to a six-terminal oscillator. [Figure 14] 1 shows an example of the configuration of a device according to the present embodiment. [Figure 15] First example of oscillator structure. [Figure 16] Second example of oscillator structure. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0009] 1. Oscillator 1 shows an example of the configuration of an oscillator 4 according to this embodiment. Also shown in FIG. 1 is an example of the configuration of a processing system 200 including the oscillator 4 and a processing device 100. The oscillator 4 is capable of communicating with the processing device 100. The oscillator 4 includes a resonator 10 and a circuit device 20.

[0010] The vibrator 10 is an element that generates mechanical vibrations in response to an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness-shear mode, such as an AT-cut or SC-cut cut angle, a tuning-fork type quartz crystal vibrating piece, or a double-ended tuning-fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built into a temperature-compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Alternatively, the vibrator 10 may be a vibrator built into an SPXO (Simple Packaged Crystal Oscillator). Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces, such as vibrating pieces other than thickness-shear type, tuning-fork type, or double-ended tuning-fork type, or piezoelectric vibrating pieces made of materials other than quartz. For example, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) resonator, which is a silicon resonator formed using a silicon substrate, may be used as the resonator 10. The resonator 10 is electrically connected to the circuit device 20. For example, the resonator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0011] The circuit device 20 generates and outputs a clock signal CK in an oscillator 4. The circuit device 20 can also perform data communication of a data signal DA. The circuit device 20 includes an oscillator circuit 30, an output circuit 90, and an interface circuit 80. The circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate.

[0012] The oscillator circuit 30 is a circuit that oscillates the resonator 10. For example, the oscillator circuit 30 generates an oscillation signal OSC by oscillating the resonator 10. The oscillation signal OSC is an oscillation clock signal. As an example, the oscillator circuit 30 generates an oscillation signal OSC with a frequency of, for example, 32 kHz. However, the oscillation frequency is not limited to 32 kHz. For example, the oscillator circuit 30 can be realized by an oscillation driver circuit electrically connected to one end and the other end of the resonator 10 and passive elements such as capacitors and resistors. The driver circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The driver circuit is the core circuit of the oscillator circuit 30, and the driver circuit drives the resonator 10 with voltage or current to oscillate the resonator 10. Various types of oscillator circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used as the oscillator circuit 30. The oscillator circuit 30 is electrically connected to the resonator 10 via pads PX1 and PX2. Pads PX1 and PX2 are pads for connecting a vibrator. A drive circuit for oscillation of the oscillator circuit 30 is provided between pads PX1 and PX2. The connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that allows information to be transmitted by electrical signals. The electrical connection may be a connection via a passive element or the like.

[0013] The output circuit 90 outputs a clock signal CK based on the oscillation signal OSC. For example, the output circuit 90 buffers the oscillation signal OSC, which is the oscillation clock signal output from the oscillation circuit 30, and outputs it to the clock output pad PCK as a clock signal CK. This clock signal CK is then output to the outside via the clock output terminal TCK of the oscillator 4. For example, the output circuit 90 outputs the clock signal CK in a single-ended CMOS signal format. However, the output circuit 90 may also output the clock signal CK in a signal format other than CMOS.

[0014] The interface circuit 80 is a circuit that serves as an interface with an external processing device 100 or the like. The interface circuit 80 is a circuit for communicating with, for example, the external processing device 100 shown in FIG. 1. In this embodiment, in FIG. 1, data communication of a data signal DA synchronized with a clock signal CK is performed between the oscillator 4 and the processing device 100 via the first terminal TDA. Specifically, as will be described later with reference to FIGS. 9 and 10, temperature detection data DTD can be transmitted to the processing device 100 via the first terminal TDA, and frequency setting data DFS for setting the oscillation frequency generated by the oscillation circuit 30 can be received from the processing device 100 via the first terminal TDA. The interface circuit 80 can be realized, for example, by a serial interface circuit that performs serial interface communication.

[0015] The power supply pad PVDD is a pad to which a power supply voltage VDD is supplied. The pad is a terminal of the circuit device 20, which is a semiconductor chip. For example, in the pad region, a metal layer is exposed from a passivation film, which is an insulating layer, and this exposed metal layer forms a pad, which is a terminal of the circuit device 20. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply pad PVDD. The ground pad PGND is a terminal to which a ground voltage GND is supplied. GND can also be referred to as VSS, and the ground voltage is, for example, the ground potential. In this embodiment, the ground is appropriately referred to as GND. The power supply pad PVDD, the ground pad PGND, the clock output pad PCK, and the first pad PDA are electrically connected to the power supply terminal TVDD, the ground terminal TGND, the clock output terminal TCK, and the first terminal TDA, which are external terminals for external connection of the oscillator 4, respectively. For example, each of these pads and terminals is electrically connected using internal wiring of the package, bonding wires, metal bumps, or the like.

[0016] The processing system 200 shown in FIG. 1 includes an oscillator 4 and a processing device 100 electrically connected to the oscillator 4. The processing system 200 may also include other devices, such as a device that operates based on a clock signal CK from the oscillator 4. The oscillator 4 and the processing device 100 are electrically connected via wiring on a circuit board. The processing system 200 is incorporated into, for example, an electronic device. The electronic device may be, for example, a network-related device such as a base station or a router; a high-precision measuring device that measures physical quantities such as distance, time, flow velocity, or flow rate; a biometric measuring device that measures biometric information; or an in-vehicle device. The electronic device may also be a mesh network device for sensors, an Internet of Things (IoT) device, a wearable device such as a head-mounted display device or a watch-related device, a robot, a printing device, a projection device, a mobile information terminal such as a smartphone, a content provider that distributes content, or an imaging device such as a digital camera or a video camera.

[0017] As described above, the processing device 100 communicates with the interface circuit 80 of the oscillator 4. Specifically, the processing device 100 includes an interface circuit 110, and communication is performed between the interface circuit 80 of the oscillator 4 and the interface circuit 110 of the processing device 100. The processing device 100 has a data terminal EDA through which a data signal DA is input / output, a clock input terminal ECK through which a clock signal CK is input, a power supply terminal EVDD to which VDD is supplied, and a ground terminal EGND to which GND is supplied.

[0018] The processing device 100 can be realized by a processor such as an MPU (Micro Processor Unit), an MCU (Micro Controller Unit), or a CPU (Central Processing Unit), or a circuit device such as an ASIC (Application Specific Integrated Circuit). For example, the processing device 100, which is an external device, may include the circuit device and a circuit board on which the circuit device is mounted.

[0019] The interface circuit 110 of the processing device 100 communicates with the interface circuit 80 of the oscillator 4 using a clock signal CK input to the clock input terminal ECK and a data signal DA input / output via the data terminal EDA. In this communication, the output circuit 90 of the oscillator 4, which is the slave, outputs the clock signal CK to the processing device 100, which is the master. Here, the master in communication refers to a device that controls or operates multiple devices when multiple devices operate in coordination, and the slave refers to a device that operates under the control of the master. In the following, the processing device 100 will be simply referred to as the master, and the interface circuit 80 or the oscillator 4 will be simply referred to as the slave, as appropriate. The master receives the clock signal CK and transmits a data signal DA synchronized with the received clock signal CK to the slave. The slave then receives the data signal DA synchronized with the clock signal CK via the first terminal TDA. The slave also transmits the data signal DA synchronized with the clock signal CK, and the master receives the data signal DA from the slave based on the received clock signal CK. In this way, data communication is carried out between the master and slave in synchronization with the clock signal CK based on the clock signal CK output by the slave.

[0020] As described above, the oscillator 4 of this embodiment includes the vibrator 10, the oscillation circuit 30 that generates the oscillation signal OSC using the vibrator 10, the clock output terminal TCK, the output circuit 90 that outputs the clock signal CK to the external processing device 100 via the clock output terminal TCK, the first terminal TDA, and the interface circuit 80 that communicates with the processing device 100 via the data signal DA.

[0021] In this communication, the output circuit 90 outputs a clock signal CK to the processing device 100, which is the master of the communication. That is, while the master normally outputs the clock signal for communication, in this embodiment, the output circuit 90 on the slave side outputs the clock signal CK. The interface circuit 80, which is the slave of the communication, receives a data signal DA synchronized with the clock signal CK transmitted from the processing device 100 via the first terminal TDA. That is, the processing device 100, which is the master, transmits a data signal DA synchronized with the clock signal CK from the slave, and the interface circuit 80, which is the slave, receives the transmitted data signal DA. Alternatively, the interface circuit 80, which is the slave of the communication, transmits a data signal DA synchronized with the clock signal CK to the processing device 100 via the first terminal TDA. That is, the interface circuit 80, which is the slave, transmits a data signal DA synchronized with the clock signal CK, and the processing device 100, which is the master, receives the transmitted data signal DA. In this way, synchronous communication of the data signal DA becomes possible between the processing device 100, which is the communication master, and the interface circuit 80, which is the communication slave, based on the clock signal CK output by the slave side.

[0022] Also, in FIG. 1, a pull-up resistor RP is provided between the data line for the data signal DA and the power supply line for VDD. This pulls up the data line connecting the processing device 100 and the interface circuit 80. That is, the data line is pulled up to the power supply voltage level of VDD. In this way, when neither the interface circuit 80 nor the processing device 100 drives the data line low, the data line is pulled up to the high level, which is the power supply voltage level of VDD. Specifically, when the interface circuit 80 includes an I / O circuit 82 having an open-drain N-type transistor TR shown in FIG. 5 (described later) and the interface circuit 110 includes an I / O circuit 112, the data line is pulled up to the high level when the transistor TR is turned off. This enables serial data communication using the data line.

[0023] In FIG. 1, a pull-up resistor RP is provided between the data line for the data signal DA and the power supply line for VDD, but the configuration may be such that no pull-up resistor RP is provided.

[0024] 1 is a four-terminal oscillator having a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. With such an oscillator 4 having a small number of terminals, the issue is how to achieve communication with an external processing device 100.

[0025] For example, as a comparative example to Fig. 1, a method of switching the operation mode of the oscillator 4 between an oscillation mode and a communication mode can be considered. For example, this is a method of realizing communication with an external processing device 100 even with a small number of terminals by switching the operation mode to the communication mode during manufacturing and inspection. Figs. 2 and 3 show an overview of this method.

[0026] 2 shows the operating state when the oscillator 4 is in oscillation mode. In oscillation mode, a clock signal CK based on the oscillation signal OSC of the oscillation circuit 30 is transmitted to the external processing device 100, external device SA, and external device SB via the clock output terminal TCK, and the processing device 100 and the like operate based on this clock signal CK. In other words, the processing device 100, which is the master, and other external devices SA and the like operate based on the clock signal CK output from the oscillator 4, which is the slave.

[0027] FIG. 3 shows the operating state of the oscillator 4 in the communication mode. In the communication mode, the clock output terminal TCK is switched to the serial clock input terminal TSCK for communication, and the first terminal TDA, which is the output enable terminal TOE, is switched to the terminal for data communication. In the communication mode, the oscillator 4 performs serial interface communication with, for example, the processing device 100. Specifically, the oscillator 4 receives the serial clock signal SCK output by the processing device 100 via the serial clock input terminal TSCK, and communicates the data signal DA via the first terminal TDA, which has been switched to the terminal for data communication. However, in the method of this comparative example, in the communication mode, the clock output terminal TCK is switched to the serial clock input terminal TSCK for data communication, so the clock signal CK of the oscillator 4 cannot be output from the clock output terminal TCK to, for example, the processing device 100. Therefore, if the processing device 100 operates based on this clock signal CK or if there is an external device SA that operates using the clock signal CK, the processing device 100 or other external devices SA will not be able to operate based on the clock signal CK in the communication mode. In other words, in the communication mode, it is not possible to simultaneously perform data communication between the master processing device 100 and the slave oscillator 4 and continue the operation of the processing device 100 and external device SA, etc., which operate based on the clock signal CK.

[0028] FIG. 4 shows a communication state when the present embodiment of FIG. 1 is applied. As described above, according to the configuration of this embodiment, data communication between the master processing device 100 and the slave oscillator 4 is performed using the clock signal CK output by the slave oscillator 4. Therefore, unlike the method of the comparative example described above, it is not necessary to set the operating state to a communication mode and switch the clock output terminal TCK to the serial clock input terminal TSCK for data communication. As a result, the oscillator 4 can output the clock signal CK from the clock output terminal TCK to the processing device 100, external device SA, etc., while simultaneously performing data communication with the processing device 100 synchronized with the clock signal CK. Therefore, it is possible to simultaneously achieve data communication between the master processing device 100 and the slave oscillator 4 and maintain the operating states of the processing device 100 and external device SA, etc., which operate based on the clock signal CK.

[0029] Furthermore, in this embodiment, the slave oscillator 4 continuously outputs the clock signal CK, thereby maintaining constant power consumption. This leads to the oscillator 4 outputting a clock signal CK with a more stable frequency. That is, when the oscillator 4 continuously outputs the clock signal CK, the amount of heat generated by the oscillator 4 itself remains constant, maintaining a constant thermal relationship between the oscillator 4 and the outside. However, when the oscillator 4 stops outputting the clock signal CK, the thermal relationship with the outside changes, and the temperature of the oscillator 4 is no longer maintained constant. If the temperature of the oscillator 4 fluctuates, temperature compensation by the temperature compensation circuit 60 (see FIG. 9 ) described below is required, which affects the generation of a clock signal CK with a stable frequency. This causes fluctuations in the frequency of the clock signal CK, degrading the clock frequency characteristics of the oscillator 4. Therefore, according to this embodiment, the oscillator 4 continuously outputs the clock signal CK, thereby enabling a clock signal CK with a stable frequency. This enables data communication between the oscillator 4 and the processing device 100 while continuously supplying a clock signal CK with high-quality frequency characteristics to the processing device 100 and other external devices SA.

[0030] For example, in serial data communication, as shown in FIG. 3, it is common for a master to output a serial clock signal SCK to be used in data communication to a slave. Here, the master outputs the serial clock signal SCK to the slave during a communication period during which data communication is performed. During periods other than the communication period, the serial clock signal SCK for synchronizing data communication with the slave is unnecessary, thereby reducing unnecessary power consumption. Here, the communication period specifically refers to a period during which the master writes a data signal DA to the slave or reads a data signal DA from the slave. In contrast, in this embodiment, the slave plays the role of outputting the clock signal CK on behalf of the master during data communication. Unlike the master, the slave must continue to output the clock signal CK even during periods when data communication with the master is not being performed in order to maintain the operating state of external devices SA and the like included in the processing system 200. Thus, in this embodiment, the slave oscillator 4 includes an output circuit 90 that outputs the clock signal CK even during periods other than data communication.

[0031] Furthermore, the oscillator 4 of this embodiment has four external terminals for external connection of the oscillator 4: a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. The power supply terminal TVDD is supplied with a power supply voltage VDD from, for example, an external power supply device. The ground terminal TGND is supplied with a ground voltage GND. Here, the ground voltage GND is, for example, a ground potential. The clock output terminal TCK is a terminal used to output a clock signal CK generated by the output circuit 90 to the outside. The first terminal TDA is a terminal used by the oscillator 4 and the slave to perform data communication with the master.

[0032] As mentioned above, the power supply terminal TVDD, ground terminal TGND, clock output terminal TCK, and first terminal TDA of the oscillator 4 are electrically connected to the power supply pad PVDD, ground pad PGND, clock output pad PCK, and first pad PDA of the circuit device 20, respectively.

[0033] According to this embodiment, in an oscillator 4 in which the number of external terminals is limited to only four, it is possible to continuously output an accurate clock signal CK from the oscillator 4 to the processing device 100, external device SA, etc., regardless of whether data communication is taking place between the processing device 100 and the oscillator 4.

[0034] In the oscillator 4 of this embodiment, the first terminal TDA may be an output enable terminal TOE that switches between enabling and disabling the output of the clock signal CK.

[0035] When the first terminal TDA is used as the output enable terminal TOE, the output circuit 90 outputs the clock signal CK to the outside when the first terminal TDA is set to an active level such as a high level. On the other hand, when the first terminal TDA is set to an inactive level such as a low level, the output circuit 90 sets the clock signal CK to a fixed voltage level such as a low level. In this way, the first terminal TDA can function not only for transmitting and receiving data signals but also as a terminal for controlling the on / off of the clock signal output of the oscillator.

[0036] 5 shows an example of the configuration of the I / O circuit 82 included in the interface circuit 80 of FIG. 1. The I / O circuit 82 includes an open-drain N-type transistor TR and an input buffer BF. The IN / OUT terminal of FIG. 5 corresponds to the first terminal TDA of FIG. 1. The first terminal TDA corresponds to the data terminal of the oscillator 4.

[0037] The output signal OUT from the internal circuit is input to the gate of transistor TR after being buffered by, for example, inverter IV. For example, when the output signal OUT goes low and the gate of transistor TR goes high, transistor TR turns on and the data line is driven low. On the other hand, when the output signal OUT goes high and the gate of transistor TR goes low, transistor TR turns off. In this case, the data line is pulled up to high by resistor RP in Figure 1. This makes it possible to transmit a data signal DA using the output signal OUT. The IN / OUT terminal is also connected to input buffer BF, and the input signal IN at the IN / OUT terminal is buffered by input buffer BF and input to the internal circuit. This makes it possible to receive a data signal DA using the input signal IN.

[0038] Furthermore, in a configuration in which the pull-up resistor RP of FIG. 1 is not provided, the I / O circuit 82 of FIG. 5 may be provided with a push-pull output circuit composed of a P-type transistor and an N-type transistor arranged in series between VDD and GND, for example, instead of the open-drain N-type transistor TR.

[0039] The I / O circuit 112 included in the interface circuit 110 of the processing device 100 has the same configuration as the I / O circuit 82 of FIG.

[0040] The following describes data communication between a master and a slave in the processing system 200 of this embodiment. FIG. 6 is an explanatory diagram of an example of a communication protocol of this embodiment. The upper diagram of FIG. 6 shows the communication protocol for data write, and the lower diagram of FIG. 6 shows the communication protocol for data read. In the data write communication protocol, the master transmits a communication start key, and the slave interface circuit 80 receives this communication start key. In this case, the master transmits the communication start key in synchronization with a clock signal CK from the slave. The slave interface circuit 80 then receives the communication start key synchronized with the clock signal CK and determines whether the received communication start key is a key with an appropriate code according to the protocol. If the received communication start key is a key with an appropriate code, it determines that communication has started. In communication protocols such as data read, the start of communication is determined using a similar procedure. In this way, in this embodiment, the interface circuit 80 starts communication upon receiving a communication start key from the processing device 100. In this way, communication between the master and the slave will start on the condition that an appropriate code for the communication start key has been sent from the master to the slave, preventing the problem of incorrectly determining that communication has started due to noise, etc., contained in the data signal.

[0041] 7 and 8 are signal waveform diagrams illustrating an example of communication in this embodiment. FIG. 7 is a signal waveform diagram for a data write in which the master writes data to the slave. This data write by the master corresponds to data reception by the slave interface circuit 80. FIG. 8 is a signal waveform diagram for a data read in which the master reads data from the slave. This data read by the master corresponds to data transmission by the slave interface circuit 80. Note that in FIGS. 7 and 8, the low level by the slave is shown as a schematic potential lower than the low level by the master, so that it is possible to distinguish between a case in which the master outputs a low level and a case in which the slave outputs a low level.

[0042] In the data write of FIG. 7, after transmitting the communication start key, the master outputs R / XW, which specifies whether it is a write or a read. In this R / XW, X represents negative logic, and the master outputs a high level for a data read and a low level for a data write. Since FIG. 7 is a data write, the master outputs a low level as XW of R / XW. That is, the low level is output when the open-drain N-type transistor of the master-side I / O circuit 112 in FIG. 5 turns on. When the master outputs a low level after the communication start key in this way, the slave outputs SLA, which indicates the slave's acknowledgement. Specifically, the slave outputs a low level as SLA. As mentioned above, the low level by the slave is depicted in FIG. 7 as a low level with a lower potential to distinguish it from the low level by the master.

[0043] When the slave outputs a low level as SLA in this way, the master writes an address to the slave. This address specifies the register in the slave to which data will be written. In this address write, the master sends address information as a data signal DA, and the slave receives this address information.

[0044] After the address write, the master outputs P / XC. P means Stop, which stops communication, and XC means Continue, which continues communication. The X in XC stands for negative logic. In Figure 7, to continue communication, the master outputs a low level as the XC in P / XC. The master then transmits the data to be written to the address specified in the address write as a data signal DA. This causes data from the master to be written to the register with the specified address in oscillator 4. The write address is automatically updated in the slave. Therefore, as long as the slave outputs XC, which indicates the continuation of communication, data is written sequentially to the updated address. Also, in Figures 6 and 7, the data transmitted at one time is represented as 8 bits, but it may be any number of bits, such as 4 or 16 bits. When there is no more data to write, the master outputs a 1-bit P to stop communication and terminates the data write communication.

[0045] In the case of a data read (Figure 8), the master first transmits a communication start key, and the slave receives the communication start key. Here, in the case of a data read, as shown in the lower part of Figure 6, communication to specify the address information where the data to be read is written is first performed in write operation mode. That is, the master transmits a communication start key followed by an XW signal indicating the write operation mode. The slave then outputs an SLA signal indicating an acknowledge. Specifically, the slave outputs a low level as the SLA signal. Upon receiving the SLA signal, the master transmits the specified address information to the slave. Upon receiving the address information, the slave outputs a 1-bit P signal indicating an end of communication, temporarily halting the write mode communication. Figure 8 shows the waveforms of the data communication that then takes place between the master and slave. The master transmits a communication start key again, then outputs a high level as the R signal indicating a read. Upon receiving this, the slave outputs an SLA signal indicating an acknowledge. The slave then reads the information written to the specified address and transmits it to the master. The master then transmits an XC signal indicating the continuation of communication. The address from which the data is read is automatically updated in the slave. Therefore, as long as the master outputs XC, which indicates that communication should continue, the slave sequentially reads data from the next address and transmits it to the master. Also, while the data transmitted at one time is shown as 8 bits in Figures 6 and 8, it may be data of a predetermined number of bits, such as 4 bits or 16 bits. When there is no more data to read next, the master outputs a 1-bit P, which instructs communication to be stopped, and the data read communication ends.

[0046] As described above, in this embodiment, during data write in FIGS. 6 and 7 , when the processing device 100 outputs a low level after receiving a predetermined number of first data bits, the interface circuit 80 determines that communication has continued and receives the next predetermined number of second data bits. That is, during data write by the master in FIGS. 6 and 7 , the interface circuit 80, which is the slave, receives the predetermined number of eight bits of first data bits. Specifically, the first data transmitted by the master is received and written to a register. Note that the predetermined number of bits is not limited to eight bits and may be 16 bits, 32 bits, or the like. Then, when the processing device 100 transmits the first data bits and then outputs a low level as an XC signal to instruct the continuation of communication, the interface circuit 80 determines that communication has continued. Then, when the processing device 100 transmits second data bits after outputting a low level as an XC signal, the interface circuit 80 receives the transmitted second data bits and writes the received second data bits to a register. In this way, the interface circuit 80 can determine whether communication will continue or not by detecting whether the processing device 100 has output a low level after receiving the first data, and can then receive the next second data. This allows the interface circuit 80 to continuously receive multiple pieces of data with a predetermined number of bits, such as the first data and the second data. Furthermore, if the processing device 100 does not output a low level after transmitting the first data, the data line is pulled up by the resistor RP and set to a high level, as shown in Figure 5, so the interface circuit 80 can determine that communication has stopped and will not continue.

[0047] In this embodiment, when reading data as shown in FIGS. 6 and 8, the interface circuit 80 determines that communication has continued when the processing device 100 outputs a low level after transmitting a predetermined number of first data bits, and transmits the next second data bits of the predetermined number. That is, in the master data read operation shown in FIGS. 6 and 8, the slave interface circuit 80 transmits the first data bits of 8 bits, which is the predetermined number of bits. Then, when the processing device 100 subsequently outputs a low level as an XC command to continue communication, the interface circuit 80 determines that communication has continued and transmits the next second data bits. In this manner, the interface circuit 80 can determine whether communication will continue by detecting whether the processing device 100 outputs a low level after transmitting the first data bits, and then transmit the next second data bits. This allows the interface circuit 80 to continuously transmit multiple data bits of a predetermined number, such as the first data bits and the second data bits. Furthermore, if the processing device 100 does not output a low level after the interface circuit 80 transmits the first data, the data line is pulled up by the resistor RP and set to a high level, so that the interface circuit 80 can determine that communication has stopped and not continued.

[0048] 2. Detailed configuration example 9 shows a first detailed configuration example of the oscillator 4 of this embodiment. The oscillator 4 of the first detailed configuration example includes a temperature sensor circuit 40 and a temperature compensation circuit 60 in addition to the configuration of FIG.

[0049] The temperature sensor circuit 40 measures temperatures such as the ambient temperature of the resonator 10 and the circuit device 20 and outputs the results as temperature detection data DTD. Here, the temperature detection data DTD is data for identifying the detected temperature and is data associated with the detected temperature. The temperature detection data DTD is data that, for example, monotonically increases or decreases with temperature within the operating temperature range of the oscillator 4. The temperature sensor circuit 40 can be realized, for example, by a temperature sensor circuit that utilizes the temperature dependency of the oscillation frequency of a ring oscillator. Specifically, the temperature sensor circuit 40 includes a ring oscillator and a counter. The counter counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal CK based on the oscillation signal OSC from the oscillation circuit 30, and outputs the count value as temperature detection data DTD. Note that the temperature sensor circuit 40 is not limited to the above. For example, it may include an analog temperature sensor that outputs a temperature detection voltage by utilizing the temperature dependency of the forward voltage of a PN junction, and an A / D conversion circuit that A / D converts the temperature detection voltage and outputs the temperature detection data DTD.

[0050] The temperature compensation circuit 60 performs temperature compensation processing based on the temperature detection data DTD from the temperature sensor circuit 40. The temperature compensation processing is processing that suppresses and compensates for fluctuations in the oscillation frequency due to temperature fluctuations, for example. That is, the temperature compensation circuit 60 performs temperature compensation processing for the oscillation frequency of the oscillation circuit 30 so that the frequency remains constant even when there is a temperature fluctuation. Specifically, the temperature compensation circuit 60 performs temperature compensation processing based on digital calculations performed using the temperature detection data DTD from the temperature sensor circuit 40.

[0051] In this embodiment, the oscillator circuit 30 also includes a variable capacitance circuit 32. The oscillator circuit 30 is configured to adjust its oscillation frequency by adjusting the capacitance of the variable capacitance circuit 32. The variable capacitance circuit 32 includes, for example, a capacitor array and a switch array connected to the capacitor array. The variable capacitance circuit 32 can also be implemented using variable capacitance elements such as varactors. The switches of the switch array of the variable capacitance circuit 32 are turned on and off based on frequency adjustment data from the temperature compensation circuit 60. For example, the variable capacitance circuit 32 includes a first capacitor array having multiple capacitors with binary-weighted capacitance values. The variable capacitance circuit 32 also includes a first switch array having multiple switches, each of which turns on and off a connection between each capacitor in the first capacitor array and the pad PX1. The variable capacitance circuit 32 may also include a first variable capacitance circuit having a first capacitor array and a first switch array and connected to the pad PX1, and a second variable capacitance circuit having a second capacitor array and a second switch array and connected to the pad PX2. The switches of the first switch array and the second switch array are turned on and off based on the frequency adjustment data.

[0052] That is, in the detailed first configuration example shown in FIG. 9 , the temperature sensor circuit 40 measures temperatures such as the ambient temperature of the resonator 10 and the circuit device 20, and outputs the results as temperature detection data DTD to the temperature compensation circuit 60 and the interface circuit 80. Then, based on the temperature detection data DTD received from the temperature sensor circuit 40, the temperature compensation circuit 60 performs processing to suppress and compensate for fluctuations in the oscillation frequency of the oscillation signal OSC due to temperature fluctuations. Specifically, the temperature compensation circuit 60 obtains frequency adjustment data based on the temperature detection data DTD, and adjusts the capacitance value of the variable capacitance circuit 32 of the oscillation circuit 30 based on the obtained frequency adjustment data. In this way, the oscillator 4 of this embodiment enables temperature compensation processing of the oscillation frequency output by the oscillation circuit 30.

[0053] Furthermore, the interface circuit 80 transmits the temperature detection data DTD as a data signal DA to the external processing device 100 via the first terminal TDA. Specifically, the processing device 100 has an interface circuit 110, which receives the temperature detection data DTD. In this way, in the oscillator 4 of this embodiment, the temperature detection data DTD is transmitted from the interface circuit 80 to the external processing device 100 via the first terminal TDA. This makes it possible to measure the temperature corresponding to the temperature detection data DTD.

[0054] As an application example of the detailed first configuration example shown in FIG. 9 , a 32 kHz clock signal CK from oscillator 4 may be supplied to an RTC circuit of a processing device 100, such as a microcomputer, to perform calendar timekeeping in the RTC. In this case, the calendar timekeeping process must be executed without interruption, so the clock signal CK from oscillator 4 must be constantly supplied to the RTC circuit of the processing device 100. Meanwhile, while performing such calendar timekeeping, the processing device 100 may detect, for example, the environmental temperature and issue a warning if the temperature exceeds an upper limit or falls below a lower limit. In this case, the processing device 100 can effectively utilize the temperature detection data DTD from the temperature sensor circuit 40 of oscillator 4 to detect the temperature based on the temperature detection data DTD output from the oscillator 4 via the interface circuit 80, thereby issuing a warning. 9, the temperature detection data DTD from the oscillator 4 can be transmitted to the processing device 100, and at the same time, the clock signal CK from the oscillator 4 can be continuously supplied to the RTC circuit of the processing device 100 during and outside the data communication period, thereby enabling calendar timing processing. In other words, the processing device 100 can simultaneously perform temperature detection based on the temperature detection data DTD and calendar timing processing based on the clock signal CK.

[0055] 10 shows a second detailed example of the configuration of the oscillator 4 of this embodiment. The oscillator 4 of the second detailed example of the configuration includes a PLL circuit 36 ​​in addition to the configuration of FIG.

[0056] The PLL circuit 36 ​​generates a clock signal CK having a frequency that is a multiplication of the frequency of an oscillation signal OSC, which serves as a reference clock signal. Specifically, the PLL circuit 36 ​​has a voltage-controlled oscillation circuit, and generates the clock signal CK having the multiplied frequency by performing a phase comparison between the oscillation signal OSC, which serves as the reference clock signal, and a feedback clock signal. The PLL circuit 36 ​​may be, for example, a fractional-N PLL circuit capable of fractional frequency multiplication.

[0057] The PLL circuit 36 ​​is provided between the oscillator circuit 30 and the output circuit 90. First, the interface circuit 80, which is the slave, receives frequency setting data DFS transmitted by the processing device 100, which is the master, via the first terminal TDA. Here, the frequency setting data DFS is data containing information for setting the clock frequency of the clock signal CK output by the oscillator 4, and the content of this data can be set in the processing device 100. Next, the frequency setting data DFS received by the interface circuit 80 is set in the PLL circuit 36. For example, a control circuit (not shown) sets the frequency setting data DFS in the PLL circuit 36. Then, the PLL circuit 36 ​​performs processing to generate a clock signal CK of a predetermined frequency based on the frequency setting data DFS. The clock signal CK generated by the PLL circuit 36 ​​is then input to the output circuit 90 and the interface circuit 80. The output circuit 90 outputs the clock signal CK to the processing device 100 via the clock output terminal TCK, and this clock signal CK is used as the operating clock of the processing device 100. Alternatively, the clock signal CK can also be used as the operating clock of other external devices SA, etc. This clock signal CK is also used as a serial clock signal for serial data communication between a master and a slave. That is, according to the detailed second configuration example of this embodiment, the frequency of the clock signal CK output by the oscillator 4 can be set to a desired frequency using the frequency setting data DFS, and clock signals CK of various frequencies required by the processing device 100, other external devices SA, etc. can be generated.

[0058] 10, for example, if the frequency of the clock signal CK is set to a high frequency, the communication between the processing device 100 and the oscillator 4 will be performed using the high-frequency clock signal CK, which may prevent proper communication from being achieved. In such a case, for example, a method such as that described in FIG. 11 may be adopted.

[0059] For example, FIG. 11 shows a case where the waveform of a predetermined bit pattern is defined as logic levels "0" and "1," respectively. The waveform pattern in the upper part of FIG. 11 is, for example, a waveform pattern corresponding to logic level "0," and the waveform pattern in the lower part of FIG. 11 is, for example, a waveform pattern corresponding to logic level "1." The waveform pattern corresponding to logic level "0" is, for example, a pattern in which a low-level data signal DA is output for eight clock periods of the clock signal CK, followed by a high-level data signal DA for four clock periods of the clock signal CK. The waveform pattern corresponding to logic level "1" is, for example, a pattern in which a low-level data signal DA is output for four clock periods of the clock signal CK, followed by a high-level data signal DA for eight clock periods of the clock signal CK. In other words, the logic levels "0" and "1" are determined by determining the ratio between the low-level pulse length and the high-level pulse length. Note that, where n is an integer greater than or equal to 1, n clock periods is a period equal to the length of n clock periods of the clock signal CK.

[0060] For example, in Figures 7 and 8, the communication period for one bit is one clock period, which is a period of one clock cycle. When the frequency of the clock signal CK is low, such as 32 kHz, communication can be performed without any problems even if the communication period for one bit is one clock period. However, when the frequency of the clock signal CK is high, such as several MHz to several tens of MHz, the clock period becomes shorter, and the communication period for one bit becomes shorter, resulting in a communication error. For example, a communication error occurs when the slave fails to receive one bit of information transmitted by the master, or when the master fails to receive one bit of information transmitted by the slave. In such a case, when the logic level of the bit is "0," information is communicated using, for example, the waveform pattern shown in the upper part of Figure 11, and when the logic level of the bit is "1," information is communicated using, for example, the waveform pattern shown in the lower part of Figure 11. This prevents communication errors, such as the slave failing to receive one bit of information transmitted by the master, or the master failing to receive one bit of information transmitted by the slave. This makes it possible to achieve highly reliable and stable communication between the master and slave.

[0061] In the present embodiment, the oscillator 4 may output a clock signal CK having a frequency higher than that at which serial communication is possible. For example, as shown in Fig. 10, this may be the case when the oscillator 4 outputs a clock signal CK having a frequency obtained by multiplying the frequency of the oscillation signal of the oscillation circuit 30 by a PLL circuit 36. When the frequency of the clock signal CK output by the oscillator 4 is high in this way, it is effective to perform communication by defining predetermined waveform patterns corresponding to the logical levels "0" and "1," as shown in Fig. 11.

[0062] Although the above description has been given taking as an example a case where the number of external terminals of oscillator 4 is four, the number of external terminals of oscillator 4 is not limited to four and may be five or more. For example, a case where the number of external terminals of oscillator 4 is six will be described using Figs. 12 and 13.

[0063] Fig. 12 is a diagram showing the communication mode state of oscillator 4 when this embodiment is not applied. The oscillator 4 in Fig. 12 is a six-terminal oscillator having a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, an output enable terminal TOE, a first terminal TDA which is a data terminal, and a serial clock input terminal TSCK. Note that components other than the external terminals in oscillator 4 in Fig. 12 are shown in a simplified manner in order to focus on differences in communication states. The same applies to Fig. 13.

[0064] In FIG. 12 , oscillator 4 outputs a clock signal CK to external processing device 100 (the master) or external device SA. Furthermore, master processing device 100 outputs a serial clock signal SCK via serial clock input terminal ESCK as a communication clock for data communication with oscillator 4 (the slave). The frequency of serial clock signal SCK output by processing device 100 is typically different from the frequency of clock signal CK output by oscillator 4. Therefore, the serial clock signal SCK for communication interferes with clock signal CK, causing jitter noise and other noise in clock signal CK. That is, because the clock signal CK output from oscillator 4 and the serial clock signal SCK for communication from processing device 100 are asynchronous, noise due to the serial clock signal SCK for communication is superimposed on clock signal CK, causing jitter noise and other noise in clock signal CK. This degrades the clock signal characteristics of clock signal CK, adversely affecting the operating states of processing device 100, external device SA, and external device SB, which operate based on the clock signal CK.

[0065] In this regard, in a configuration to which this embodiment is applied, as shown in Fig. 13, data communication is performed using the clock signal CK output by the oscillator 4, which is the slave, instead of the serial clock signal SCK for communication output by the master. That is, the clock signal CK output by the oscillator 4 to the outside is used as a clock signal for the operation of the processing device 100, etc., and at the same time, is used as a clock signal for communication between the master and slave. Therefore, it is possible to effectively prevent the problem of noise due to the serial clock signal SCK for communication being superimposed on the clock signal CK, degrading the clock signal characteristics, as in the case of Fig. 12.

[0066] 3. Devices 14 shows an example of the configuration of the device 5 of this embodiment. Also shown in FIG. 14 is the configuration of a processing system 200 including the device 5 and a processing device 100. The device 5 performs data communication with the processing device 100. The device 5 includes a circuit device 20. The circuit device 20 includes an interface circuit 80, an output circuit 90, and a clock signal generation circuit 34.

[0067] 14 includes a clock signal generation circuit 34 that generates a clock signal CK, a clock output terminal TCK, an output circuit 90 that outputs the clock signal CK to an external processing device 100 via the clock output terminal TCK, a first terminal TDA, and an interface circuit 80 that communicates with the processing device 100 via a data signal DA. In communication, the output circuit 90 outputs the clock signal CK to the processing device 100, which is the master of communication. The interface circuit 80, which is the slave of communication, receives a data signal DA synchronized with the clock signal CK from the processing device 100 via the first terminal TDA, or transmits a data signal DA synchronized with the clock signal CK to the processing device 100 via the first terminal TDA.

[0068] Here, the clock signal generation circuit 34 is a circuit that generates a clock signal CK. The clock signal generation circuit 34 generates the clock signal CK by, for example, crystal oscillation, LC oscillation, CR oscillation, or oscillation using a ceramic element.

[0069] According to this embodiment, data communication between the processing device 100 and the device 5 can be performed using the clock signal CK output by the device 5. Therefore, even if the number of external terminals of the device 5 is small, it is possible to perform both the output of the clock signal CK from the device 5 and data communication between the processing device 100 and the device 5. Alternatively, as described above with reference to FIGS. 12 and 13, it is possible to prevent a situation in which noise due to the serial clock signal SCK for communication is superimposed on the clock signal CK, resulting in a deterioration in clock signal characteristics.

[0070] The device 5 in FIG. 14 can be various devices other than the oscillator 4. For example, the device 5 may be a sensor device such as a gyro sensor or an acceleration sensor, a display device that displays images on a display panel, a communication device that communicates using a predetermined communication standard, a drive device that drives a predetermined mechanism of a printer, or a power supply device that supplies and controls power. The circuit device 20 of this embodiment is not limited to being incorporated into the device 5, but may also be an integrated circuit (IC) incorporated into the above-mentioned sensor device, display device, communication device, or power supply device. For example, if the device 5 is a gyro sensor, the circuit device 20 may include a drive circuit that drives the vibrator of the gyro sensor and a detection circuit that detects a sensor signal from the vibrator 10. If the device 5 is an acceleration sensor, the circuit device 20 may include a drive circuit and a detection circuit for an acceleration sensor element realized by MEMS (Micro Electro Mechanical Systems) or the like. If the sensor is a display device, the circuit device 20 may include a drive circuit for the display panel and a logic circuit that processes display data.

[0071] When a sensor is a communication device, the circuit device 20 may include a communication physical layer circuit, a link layer circuit, and a logic circuit. As described above, circuits of various configurations can be used for the circuit device 20. In each of the above cases, the circuit device 20 has an interface circuit 80 and performs data communication with the processing device 100, which is the master.

[0072] FIG. 15 shows a first structural example of the oscillator 4 of this embodiment. The oscillator 4 has a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 is made of, for example, ceramic or the like, and has an internal housing space in which the resonator 10 and the circuit device 20 are housed. The housing space is hermetically sealed and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the circuit device 20 from impact, dust, heat, moisture, and the like.

[0073] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16, which supports the resonator 10 and the circuit device 20, and the lid 17, which is bonded to the upper surface of the base 16 so as to form an accommodation space between the base 16 and the lid 17. The resonator 10 is supported via terminal electrodes on a stepped portion provided on the inside of the base 16. The circuit device 20 is disposed on the inside bottom surface of the base 16. Specifically, the circuit device 20 is disposed so that its active surface faces the inside bottom surface of the base 16. The active surface is the surface on which circuit elements of the circuit device 20 are formed. Bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inside bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, and the resonator 10 and the circuit device 20 are electrically connected via the bumps BMP, the internal wiring of the package 15, and the terminal electrodes. The circuit device 20 is also electrically connected to external terminals 18 and 19 of the oscillator 4 via bumps BMP and internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This makes it possible to output a clock signal or the like to the external device.

[0074] 15, the circuit device 20 is flip-mounted so that the active surface of the circuit device 20 faces downward, but this embodiment is not limited to such mounting. For example, the circuit device 20 may be mounted so that the active surface of the circuit device 20 faces upward. In other words, the circuit device 20 is mounted so that the active surface faces the vibrator 10.

[0075] FIG. 16 shows a second structural example of an oscillator 4. The oscillator 4 includes a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 includes a base 16 and a lid 17. The base 16 includes a first substrate 6, which is an intermediate substrate; a second substrate 7 having a substantially rectangular frame shape and stacked on the top surface of the first substrate 6; and a third substrate 8 having a substantially rectangular frame shape and stacked on the bottom surface of the first substrate 6. The lid 17 is bonded to the top surface of the second substrate 7, and the resonator 10 is housed in a housing space S1 formed by the first substrate 6, the second substrate 7, and the lid 17. For example, the resonator 10 is hermetically sealed in the housing space S1, preferably in a reduced pressure state close to a vacuum. This allows the resonator 10 to be suitably protected from impact, dust, heat, moisture, and the like. The housing space S2 formed by the first substrate and the third substrate 8 houses a circuit device 20, which is a semiconductor chip. Furthermore, external terminals 18 and 19, which are electrode terminals for external connection of oscillator 4, are formed on the bottom surface of third substrate 8.

[0076] In the accommodation space S1, the vibrator 10 is connected to a first electrode terminal and a second electrode terminal (not shown) formed on the upper surface of the first substrate 6 via conductive connection parts CDC1 and CDC2. The conductive connection parts CDC1 and CDC2 may be implemented by conductive bumps such as metal bumps or by a conductive adhesive. Specifically, for example, a first electrode pad (not shown) formed on one end of the tuning-fork-shaped vibrator 10 is connected to a first electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC1. The first electrode terminal is then electrically connected to a pad PX1 of the circuit device 20. A second electrode pad (not shown) formed on the other end of the tuning-fork-shaped vibrator 10 is connected to a second electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC2. The second electrode terminal is then electrically connected to a pad PX2 of the circuit device 20. This allows one end and the other end of the vibrator 10 to be electrically connected to the pads PX1 and PX2 of the circuit device 20 via the conductive connection parts CDC1 and CDC2. Furthermore, conductive bumps BMP are formed on a plurality of pads of the circuit device 20, which is a semiconductor chip, and these conductive bumps BMP are connected to a plurality of electrode terminals formed on the bottom surface of the first substrate 6. The electrode terminals connected to the pads of the circuit device 20 are then electrically connected to external terminals 18, 19 of the oscillator 4 via internal wiring or the like.

[0077] The oscillator 4 may be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes a semiconductor substrate, a base having a through electrode penetrating between the first and second surfaces of the semiconductor substrate, a resonator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding material such as a metal bump, and external terminals provided on the second surface of the semiconductor substrate via an insulating layer such as a relocation wiring layer. An integrated circuit serving as the circuit device 20 is formed on the first or second surface of the semiconductor substrate. In this case, a first semiconductor wafer having multiple bases on which the resonators 10 and the integrated circuits are arranged is bonded to a second semiconductor wafer having multiple lids, and the multiple bases and lids are then bonded together. The oscillators 4 are then individually separated using a dicing saw or the like. This allows for the realization of a wafer-level package oscillator 4, enabling high-throughput, low-cost manufacturing of the oscillators 4.

[0078] As described above, the oscillator of this embodiment includes a vibrator, an oscillation circuit that generates an oscillation signal using the vibrator, a clock output terminal, an output circuit that outputs the clock signal to an external processing device via the clock output terminal, a first terminal, and an interface circuit that communicates with the processing device via a data signal, and in communication, the output circuit outputs a clock signal to the processing device that is the master of the communication, and the interface circuit that is the slave of the communication receives a data signal synchronized with the clock signal transmitted from the processing device via the first terminal, or transmits a data signal synchronized with the clock signal to the processing device via the first terminal.

[0079] According to this embodiment, data communication between a processing device and an oscillator can be performed using the clock signal output by the oscillator, which makes it possible to simultaneously perform clock signal output from the oscillator and data communication between an external device acting as a master and an oscillator acting as a slave.

[0080] In this embodiment, the first terminal may be an output enable terminal that switches between enabling and disabling the output of the clock signal.

[0081] In this way, the first terminal can function not only for transmitting and receiving data signals but also as a terminal for controlling the on / off of the output of the clock signal from the oscillator.

[0082] In this embodiment, the interface circuit may start communication on the condition that it receives a communication start key from the processing device.

[0083] In this way, communication between the master and slave begins on the condition that an appropriate code for the communication start key is transmitted from the master to the slave, thereby preventing the problem of incorrectly determining that communication has begun due to noise, etc., contained in the data signal.

[0084] In this embodiment, the oscillator may have four terminals including a power supply terminal, a ground terminal, a clock output terminal, and a first terminal.

[0085] In this way, in an oscillator with only four external terminals, a clock signal can be continuously output from the oscillator regardless of whether data communication is taking place between the master external device and the slave oscillator.

[0086] In this embodiment, the output circuit may also output a clock signal during periods other than the period of communication.

[0087] In this way, the oscillator can output a clock signal as a slave in communication, and can maintain the operating state of the processing device or other external devices.

[0088] In this embodiment, the data line connecting the processing device and the interface circuit is pulled up, and the interface circuit may include an I / O circuit having an open-drain N-type transistor.

[0089] In this way, even if neither the master nor the slave drives the data line of the data signal to a low level using an open-drain N-type transistor, the data line will be pulled up to a high level, making serial data communication possible using the data line.

[0090] In addition, in this embodiment, when the processing device outputs a low level after receiving a predetermined number of bits of first data, the interface circuit may determine that communication has continued and receive the next predetermined number of bits of second data.

[0091] In this way, the interface circuit can continuously receive data signals in units of a predetermined number of bits, and can determine that communication has stopped if the processing device does not output a low level.

[0092] In addition, in this embodiment, when the processing device outputs a low level after transmitting a predetermined number of bits of first data, the interface circuit may determine that communication has continued and transmit the next predetermined number of bits of second data.

[0093] In this way, the interface circuit can continuously transmit data signals in units of a predetermined number of bits, and if the processing device does not output a low level, it can determine that communication has stopped.

[0094] In addition, this embodiment may include a temperature sensor circuit that outputs temperature detection data and a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data, and the interface circuit may transmit the temperature detection data to the processing device via the first terminal.

[0095] In this way, temperature compensation of the oscillation frequency based on the temperature detection data becomes possible, and the master processing device can also perform temperature detection using the temperature detection data.

[0096] In this embodiment, the interface circuit may also receive frequency setting data for the clock signal from the processing device via the first terminal.

[0097] In this way, while the oscillator is outputting a clock signal, the frequency of the clock signal output by the oscillator can be set to a desired frequency using frequency setting data from the processing unit.

[0098] The device of this embodiment also includes a clock signal generating circuit that generates a clock signal, a clock output terminal, an output circuit that outputs the clock signal to an external processing device via the clock output terminal, a first terminal, and an interface circuit that communicates with the processing device via a data signal, and in communication, the output circuit outputs the clock signal to the processing device that is the master of the communication, and the interface circuit that is the slave of the communication receives a data signal synchronized with the clock signal transmitted from the processing device via the first terminal, or transmits a data signal synchronized with the clock signal to the processing device via the first terminal.

[0099] According to this embodiment, data communication between a processing device and a device can be performed using a clock signal output by the device, which makes it possible to simultaneously perform clock signal output from the device and data communication between an external device acting as a master and a device acting as a slave.

[0100] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the oscillators, devices, processing devices, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0101] 4...oscillator, 5...device, 6...first substrate, 7...second substrate, 8...third substrate, 10...resonator, 15...package, 16...base, 17...lid, 18...external terminal, 19...external terminal, 20...circuit device, 30...oscillator circuit, 32...variable capacitance circuit, 34...clock signal generation circuit, 36...PLL circuit, 40...temperature sensor circuit, 60...temperature compensation circuit, 80...interface circuit, 82...I / O circuit, 90...output circuit, 100...processing device, 110...interface circuit, 112...I / O circuit, 200...processing system, BF...input buffer, BMP...bump, CDC1, CDC2...connection part, CK...clock signal, DA...data signal, DFS...frequency setting data, DTD... Temperature detection data, ECK...clock input terminal, EDA...data terminal, EGND...ground terminal, EVDD...power supply terminal, GND...ground voltage, IN...input signal, IV...inverter, OSC...oscillation signal, OUT...output signal, PCK...clock output pad, PDA...first pad, PGND...ground pad, PVDD...power supply pad, PX1...pad, PX2...pad, RP...resistor, SA...external device, SB...external device, SCK...serial clock signal, TCK...clock output terminal, TDA...first terminal, TGND...ground terminal, TOE...output enable terminal, TR...transistor, TSCK...serial clock input terminal, TVDD...power supply terminal, VDD...power supply voltage

Claims

1. A four-terminal oscillator including a power supply terminal, a ground terminal, a clock output terminal, and an output enable terminal, A vibrator and an oscillation circuit that generates an oscillation signal using the oscillator; an output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output terminal; an interface circuit; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that temperature-compensates the oscillation frequency of the oscillation signal based on the temperature detection data; Including, before the interface circuit receives a communication start key from the processing device via the output enable terminal, the output circuit switches output of the clock signal between enabled and disabled in accordance with the potential of the output enable terminal; the interface circuit starts communication with the processing device on the condition that it receives the communication start key from the processing device via the output enable terminal, the output circuit outputs the clock signal to the processing device that is the master of the communication, and the interface circuit that is the slave of the communication receives a data signal synchronized with the clock signal transmitted from the processing device via the output enable terminal, or transmits the data signal synchronized with the clock signal to the processing device via the output enable terminal; In the data signal, one bit corresponds to a plurality of pulses of the clock signal, and a logic level of the one bit is defined by a ratio of the number of low level pulses to the number of high level pulses among the plurality of pulses, The interface circuit In the communication, the temperature detection data is transmitted to the processing device via the output enable terminal.

2. 2. The oscillator according to claim 1, The interface circuit In the communication, the oscillator receives frequency setting data of the clock signal from the processing device via the output enable terminal.

3. 3. The oscillator according to claim 1, The output circuit An oscillator that outputs the clock signal even during periods other than the period of the communication.

4. 4. The oscillator according to claim 1, a data line connecting the processing device and the interface circuit is pulled up; The interface circuit An oscillator comprising an I / O circuit having an open-drain N-type transistor.

5. 5. The oscillator according to claim 1, The interface circuit An oscillator characterized in that, when the processing device outputs a low level after receiving first data of a predetermined number of bits, it determines that the communication is continued and receives the next second data of the predetermined number of bits.

6. 5. The oscillator according to claim 1, The interface circuit An oscillator characterized in that, when the processing device outputs a low level after transmitting first data of a predetermined number of bits, it determines that the communication has continued and transmits the next second data of the predetermined number of bits.

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