Image pixel with coupled gate structure

Abstract

To provide an image sensor pixel circuit including a small number of transistors or other elements while providing sufficient pixel operation, an image sensor, and a method for operating an image sensor pixel.SOLUTION: One or more image pixels 22 in an array of image pixels include a coupled-gates structure in which a photodiode 40 in each input terminal is coupled to a capacitor 52 in a first output terminal and a floating diffusion region 46 in a second output terminal. The coupled-gates structure includes a first transistor 42 that sets a potential barrier defining overflow portions of the photodiode-generated charge. A second transistor 44 and a third transistor 50 in the coupled-gates structure are modulated so as to transfer the overflow charge to the capacitor and the floating diffusion region in a suitable time. The second transistor and the third transistor form a conductive path between the capacitor and the floating diffusion region in a low conversion gain operation mode.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] This application relates generally to imaging systems, and more particularly to pixel circuits in image sensors.

[0002] Image sensors are commonly used in electronic devices to capture images. In a typical configuration, an image sensor includes an array of image pixels arranged in pixel rows and pixel columns.

[0003] Typically, each image pixel includes a photosensitive element for generating charge in response to incident light, a charge storage structure for storing the generated charge, and a transistor for coupling one or more pixel elements together. In some applications, it may be desirable to provide an image pixel with one or more low-gain capacitors (e.g., for a low-gain mode of operation in which a low-gain signal is generated). However, including such capacitors or other charge storage structures may result in including additional transistors or other elements (for connectivity within the image pixel) that require additional pixel area. This becomes particularly problematic as image pixels shrink in size.

[0004] Therefore, it would be desirable to provide pixel circuits and pixel configurations that have a small number of transistors or other components while still providing sufficient pixel operation (eg, in a low gain mode of operation). [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a diagram of an exemplary imaging system having one or more image sensors and processing circuitry for capturing images, according to some embodiments. [Figure 2] FIG. 2 is a diagram of an exemplary image sensor circuit having a pixel array and control and readout circuits for the pixel array, in accordance with some embodiments. [Figure 3]FIG. 2 is a circuit diagram of an exemplary image pixel having a coupled gate structure, according to some embodiments. [Figure 4] 4 is an exemplary timing diagram for operating an image pixel such as the image pixel of FIG. 3 according to some embodiments. [Figure 5A] 4 is an exemplary timing diagram for operating an image pixel such as the image pixel of FIG. 3 according to some embodiments. [Figure 5B] 4 is an exemplary timing diagram for operating an image pixel such as the image pixel of FIG. 3 according to some embodiments. [Figure 6] 4 is an exemplary pixel layout for implementing a coupled gate structure such as that of FIG. 3, according to some embodiments. [Figure 7] FIG. 1 is a circuit diagram of an exemplary image pixel having a coupled gate structure with three output terminals, according to some embodiments. [Figure 8] 8 is an exemplary timing diagram for operating an image pixel such as the image pixel of FIG. 7 according to some embodiments. [Figure 9] 8 is an exemplary pixel layout for implementing a coupled gate structure such as that of FIG. 7, according to some embodiments. [Figure 10] 8A-8C are additional exemplary pixel layouts for implementing a coupled gate structure such as that of FIG. 7, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0006] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include image sensors that collect incident light to capture images. The image sensor may include an array of image pixels. The pixels in the image sensor may include photosensitive elements such as photodiodes that convert incident light into image charges (e.g., image signals). The image sensor may have any number of pixels (e.g., hundreds, thousands, or more). A typical image sensor may have, for example, hundreds of thousands or millions of pixels (e.g., megapixels). The image sensor may include control circuitry, such as circuitry for operating the image pixels and readout circuitry for reading out image signals corresponding to the charges generated by the photosensitive elements.

[0007] FIG. 1 is a diagram of an exemplary imaging system, such as an electronic device that captures images using an image sensor. The imaging system 10 of FIG. 1 may be a portable electronic device such as a camera, a mobile phone, a tablet computer, a laptop computer, a webcam, or a video camera, or may be another type of imaging system such as a video surveillance system, an automotive imaging system, a video game system with imaging capabilities, an augmented reality and / or virtual reality system, an unmanned aerial system (e.g., a drone), or an industrial system, or any other suitable imaging system or device that captures image data. A camera module 12 (sometimes referred to as an imaging module) may be used to convert incident light into digital image data. The camera module 12 may include one or more lenses 14 and one or more corresponding image sensors 16. The lens 14 may include a fixed lens and / or an adjustable lens and may include microlenses formed on the imaging surface of the image sensor 16 and other macrolenses. During an image capture operation, light from a scene may be focused by the lens 14 onto the image sensor 16. The image sensor 16 may include circuitry for converting analog pixel image signals into corresponding digital image data that is provided to storage and processing circuitry 18. If desired, camera module 12 may be provided with an array of lenses 14 and a corresponding array 16 of image sensors.

[0008] The storage and processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, storage devices such as random access memory and non-volatile memory, etc.) and may be implemented using components separate from and / or forming part of the camera module (e.g., circuitry forming part of an integrated circuit that includes the image sensor 16 or an integrated circuit in a module associated with the image sensor 16). If the storage and processing circuitry 18 is included on an integrated circuit (e.g., a chip) different from the integrated circuit of the image sensor 16, the integrated circuit with the processing circuitry 18 may be stacked or packaged with the integrated circuit with the image sensor 16. Image data captured by the camera module 12 may be processed and stored using the processing circuitry 18 (e.g., using an image processing engine on the processing circuitry 18, using an imaging mode selection engine on the processing circuitry 18, etc.). The processed image data may be provided to external equipment (e.g., a computer, an external display, or other device), if desired, using wired and / or wireless communication paths coupled to the processing circuitry 18.

[0009] As shown in FIG. 2 , the image sensor 16 may include a pixel array 20 (sometimes referred to herein as image pixels, or simply pixels) including image sensor pixels 22, and control and processing circuitry 24. In some configurations described herein as illustrative examples, the image pixels 22 may be arranged in rows and columns. The array 20 may include, for example, hundreds or thousands of rows and columns of image pixels 22. The control circuitry 24 may be coupled to row control circuitry 26 (sometimes referred to as row driver circuitry) and column readout and control circuitry 28 (sometimes referred to as column control circuitry, column readout circuitry, or simply readout circuitry). The row control circuitry 26 may receive a row address from the control circuitry 24 and provide corresponding row control signals, such as a reset signal, an anti-blooming signal, a row select signal, a charge transfer signal, a double conversion gain signal (e.g., a low conversion gain signal), and a readout control signal, to each row of pixels 22 via one or more control paths, such as row control path 30. One or more conductive lines, such as column lines 32, may be coupled to each column of pixels 22 in the array 20. The column lines 32 may be used to read out image signals from the pixels 22 and to supply bias signals (e.g., bias currents or bias voltages) to the pixels 22. If desired, during a pixel readout operation, a row of pixels in the array 20 may be selected using the row control circuitry 26, and the image signals generated by the image pixels 22 in that pixel row may be read out along the column lines 32.

[0010] Column readout circuitry 28 may receive image signals (e.g., analog pixel values ​​generated by pixels 22) via column lines 32. Column readout circuitry 28 may include memory circuitry for temporarily storing calibration signals (e.g., reset level signals, reference level signals) and / or image signals (e.g., image level signals) read out from array 20, amplifier circuitry, analog to digital conversion (ADC) circuitry, biasing circuitry, latch circuitry for selectively enabling or disabling column circuitry, or other circuitry coupled to one or more pixel columns in array 20 for operating pixels 22 and reading out image signals from pixels 22. The ADC circuitry in readout circuitry 28 may convert analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Column readout circuitry 28 may provide digital pixel data associated with pixels in one or more pixel columns to control and processing circuitry 24 and / or processor 18 (FIG. 1).

[0011] The pixel array 20 may also be provided with a filter array having multiple (color) filter elements (each corresponding to one or more respective pixels) that enable a single image sensor to sample light of different colors or wavelengths. As an example, image sensor pixels, such as image pixels in array 20, may be provided with a color filter array having red, green, and blue filter elements, thereby enabling a single image sensor to sample red, green, and blue (RGB) light using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern. In another example, the green pixel of the Bayer pattern may be replaced with a broadband image pixel having a broadband color filter element (e.g., a transparent color filter element, a yellow color filter element, etc.). In yet another example, one of the green pixels of the Bayer pattern may be replaced with an infrared (IR) image pixel formed under an IR color filter element, and / or the remaining red, green, and blue image pixels may also be sensitive to IR light (e.g., formed under filter elements that pass IR light in addition to light of their respective colors). These examples are merely illustrative, and in general, filter elements of any desired color and / or wavelength and in any desired pattern may be formed over any number of image pixels 22 .

[0012] 3 is a circuit diagram of an exemplary image pixel 22. As shown in FIG. 3, the pixel 22 may include a photosensitive element such as a photodiode 40. The photodiode 40 has a first terminal coupled to a voltage terminal 38 that receives a reference voltage (e.g., a ground voltage). Charge from incident light may be collected by the photodiode 40. The photodiode 40 may generate charge (e.g., electrons) in response to receiving incident light (e.g., impinging photons). The amount of charge collected by the photodiode 40 may depend on the intensity of the impinging light and the exposure duration (or integration time).

[0013] Pixel 22 of FIG. 3 also includes a floating diffusion region, such as floating diffusion region 46. Floating diffusion region 46 may be a doped semiconductor region (e.g., a region in a silicon substrate that is doped by ion implantation, impurity diffusion, or other doping process). Thus, floating diffusion region 46 may have an associated charge storage capacitance (e.g., shown schematically as a capacitor in FIG. 3). Photodiode charge or other charge (e.g., reset voltage level charge, dark current charge, etc.) may be transferred and stored in floating diffusion region 46 for a pixel readout operation.

[0014] In some applications, it may be desirable to operate pixel 22 in a low (conversion) gain mode of operation by extending the storage capacitance of floating diffusion region 46 and including a low (conversion) gain capacitor. As shown in Figure 3, pixel 22 includes a charge storage structure such as capacitor 52 (e.g., a low-gain capacitor). To more efficiently couple floating diffusion region 46 to capacitor 52, pixel 22 of Figure 3 may include a coupled gate structure (e.g., a structure including multiple transistors or gates coupled to each other) between capacitor 52 and floating diffusion region 46.

[0015] In particular, pixel 22 may include transistors 42, 44, and 50 (e.g., as part of a coupled gate structure within pixel 22). As shown in FIG. 3 , transistors 42 and 44 couple (e.g., selectively connect) photodiode 40 to floating diffusion region 46, thereby enabling photodiode-generated charge to be transferred from photodiode 40 to floating diffusion region 46 using transistors 42 and 44. Transistors 42 and 50 couple photodiode 40 to capacitor 52, thereby enabling photodiode-generated charge to be transferred from photodiode 40 to capacitor 52 using transistors 42 and 50. Capacitor 52 may be configured to integrate multiple instances of received charge and store the integrated charge. Transistors 44 and 50 couple floating diffusion region 46 to capacitor 52, thereby enabling transistors 44 and 50 to connect capacitor 52 with a conductive path between floating diffusion region 46 and capacitor 52 (e.g., in a charge transfer operation, a charge sharing operation, etc.).

[0016] The transistor 50 may be coupled to a first terminal of a charge storage structure 52 (e.g., a first terminal of the capacitor 52). A second terminal of the charge storage structure 52 (e.g., a second terminal of the capacitor 52) may be coupled to a voltage terminal 54 that receives a reference voltage (signal). By way of example, the voltage terminal 54 may provide a fixed reference voltage to the second terminal of the capacitor 52, or may provide a variable reference voltage signal (e.g., exhibiting a first voltage value during a first time period and a second voltage value during a second time period) to the second terminal of the capacitor 52.

[0017] Because the photodiode 40 provides the generated charge to the coupled gate structure, the terminal of the transistor 42 coupled to the photodiode 40 may be referred to as the input terminal of the coupled gate structure. Similarly, because the coupled gate structure outputs the photodiode-generated charge to the floating diffusion region 46 and the capacitor 52, the terminal of the transistor 44 coupled to the floating diffusion region 46 and the terminal of the transistor 50 coupled to the capacitor 52 may be referred to as the first and second output terminals of the coupled gate structure, respectively.

[0018] If desired, an intermediate node or region within the (shared) coupled gate structure between transistors 42, 44, and 50 can be a depleted node. More generally, the coupled gate structure can be configured such that each transfer of photodiode-generated overflow charge to a corresponding region (e.g., overflow charge from photodiode 40 to floating diffusion region 46 or capacitor 52) can completely transfer all corresponding overflow charge to the corresponding region. If desired, the coupled gate structure can include any other suitable structure to facilitate this complete transfer of all overflow charge, and, if desired, to facilitate the transfer of other (remaining) photodiode-generated charge.

[0019] To reset one or more pixel elements (e.g., to a reset voltage level), pixel 22 may include a reset transistor, such as reset transistor 48. As shown in FIG. 3 , transistor 48 couples a voltage terminal 56, which receives a reference voltage (e.g., a power supply voltage associated with the reset voltage level), to floating diffusion region 46. In particular, when transistor 48 is activated (e.g., by asserting control signal RST), floating diffusion region 46 may be reset to the reset voltage level (e.g., a power supply voltage). Additionally, when transistor 48 is activated along with other transistors (e.g., along with transistors 42, 44, and 50 by asserting corresponding control signals TX_BR, TX_FD, and TX_E2), it may also reset photodiode 40 and capacitor 52 to the reset voltage level. Transistors 42, 44, and 48 may also provide an anti-blooming path (e.g., to voltage terminal 56) for photodiode 40, by way of example.

[0020] As shown in FIG. 3 , pixel 22 includes a source follower transistor 60 and a pixel select (or row select) transistor 62, which form the readout portion of pixel 22. In particular, select transistor 62 has a gate terminal controlled by select signal SEL. When select signal SEL is asserted, transistor 62 is activated, and a corresponding pixel output signal having a magnitude proportional to the amount of charge in floating diffusion region 46 is passed through source follower transistor 60 to a pixel output path, such as column line 68 (e.g., line 32 in FIG. 2 ). When floating diffusion region 46 is storing photodiode-generated charge during readout, the corresponding pixel output signal may be referred to as an image (level) signal. When floating diffusion region 46 is storing reset level charge during readout, the corresponding pixel output signal may be referred to as a reset level signal.

[0021] In an exemplary image pixel array configuration, there are many rows and columns of pixels 22. A column line 68 may be associated with each column of pixels 22 (e.g., each image pixel 22 in a column may be coupled to the same column line 68 via a corresponding row select transistor 62). A control signal SEL may be asserted to read out pixel output signals from selected image pixels 22 onto column lines 68. The pixel output signals may be provided to readout circuitry 28 (FIG. 2) and processing circuitry 18 (FIG. 1) for further processing.

[0022] An image sensor having an array of image pixels, such as pixel 22 of Figure 3, may operate in a variety of light conditions (e.g., a relatively low light environment, a relatively high light environment, an intermediate light environment between a low light environment and a high light environment, etc.) In some applications (e.g., to provide high dynamic range images), it may be desirable for pixel 22 of Figure 3 to generate more than one image signal (e.g., two image signals) per integration cycle (e.g., per integration period).

[0023] A configuration in which pixel 22 of Figure 3 generates a low conversion gain image signal based on overflow charge (e.g., one or more overflow portions of the photodiode-generated charge) and a high conversion gain image signal based on remaining charge (e.g., a portion of the photodiode-generated charge that remains stored in the photodiode after removing one or more overflow portions of the photodiode-generated charge) is described herein as an illustrative example. Accordingly, Figure 4 is an exemplary timing diagram showing how a pixel such as pixel 22 of Figure 3 may be operable to generate these low and high conversion gain signals.

[0024] In the example of FIG. 4 , control signals SEL, TX_BR, TX_E2, TX_FD, RST, CLG_REF, and SH may be used to control operation of pixel 22. In particular, a control circuit ( FIG. 2 ), such as row control circuit 26 and / or control circuit 24, may be configured to provide one or more (e.g., all) of these control signals to corresponding elements within pixel 22 (and other circuits, such as readout circuit 28) via respective control lines 30 ( FIG. 2 ). Referring to pixel 22 of FIG. 3 , the control circuit may provide control signal SEL to transistor 62, control signal TX_BR to transistor 42, control signal TX_E2 to transistor 50, control signal TX_FD to transistor 44, control signal RST to transistor 48, control signal (or reference voltage signal) CLG_REF to voltage terminal 54, and control signal SH to corresponding readout circuit components, such as a sample and hold circuit and sampling switch or circuit, of readout circuit 28 ( FIG. 2 ).

[0025] 4, the control circuit may operate pixel 22 during a shutter period T1, an integration period T2, and a readout period T3. During the shutter period T1, the control circuit may fully assert control signals SEL, TX_BR, TX_E2, TX_FD, and RST to reset pixel elements in pixel 22 (e.g., floating diffusion region 46, photodiode 40, capacitor 52, etc.) to a reset voltage level (e.g., a pixel supply voltage provided to voltage terminal 56). After photodiode 40 is reset to the reset voltage level (e.g., after deassertion of control signal TX_BR during shutter period T1), an integration period for photodiode 40 may begin (e.g., photodiode 40 may begin accumulating charge in response to incident light).

[0026] During integration period T2, the transfer of the overflow portion of the photodiode-generated charge may be modulated (e.g., selectively transferred) between the floating diffusion region 46 and the capacitor 52 using control signals TX_BR, TX_E2, and TX_FD. This selective transfer of the photodiode overflow charge may be performed repeatedly over several pulse periods. The transistor 42 may be configured to function as (e.g., form, define, etc.) a potential barrier that separates the photodiode-generated charge in the photodiode 40 into first and second portions (e.g., a first overflow portion above the potential barrier and a second remaining portion below the potential barrier). Specifically, the control circuit may (in part) assert the control signal TX_BR to a suitable voltage to control the transistor 42 to form the potential barrier. Along with this partial assertion of TX_BR, the control circuit may also (in part) assert one of the control signals TX_FD or TX_E2 to transfer the overflow portion of the photodiode-generated charge to the floating diffusion region 46 or the capacitor 52, respectively.

[0027] As an illustrative example, the control circuit may provide the control signals at a first voltage level to fully assert the control signals, may provide the control signals at a second voltage level to de-assert the control signals, and may provide the control signals at a third suitable voltage level between the first and second voltage levels to partially assert the control signals. The third voltage level of each control signal may vary and be adjusted as needed depending on the type and function of the control signal (e.g., to provide a desired potential barrier level, ensure sufficient charge transfer, etc.).

[0028] In the example of Figure 4, integration period T2 may include a number of pulse periods T2-1, T2-2, ..., T2-N, during which the transfer of overflow charge to floating diffusion region 46 and capacitor 52 occurs. Although three such pulse periods are shown in the example of Figure 4, this is for illustrative purposes only. If desired, integration period T2 may include any suitable number of pulse periods. During each period, a respective overflow charge portion of the photodiode-generated charge may be transferred first to floating diffusion region 46 and then to capacitor 52.

[0029] As shown in FIG. 4 , each pulse period may include a partial assertion of the control signal TX_BR concurrently with a (partial) assertion of TX_FD (e.g., an assertion pulse of the control signals TX_BR and TX_FD) to define an overflow portion of the photodiode-generated charge and set up a suitable potential barrier for transferring the defined overflow portion of the photodiode-generated charge to the floating diffusion region 46 (e.g., via transistors 42 and 44). A suitable time after the pulses of the control signals TX_BR and TX_FD, the control signals TX_BR and TX_E2 may also pulse within the pulse period. In particular, the control signal TX_BR may be partially asserted concurrently with a (partial) assertion of the control signal TX_E2 to define an overflow portion of the photodiode-generated charge and set up a suitable potential barrier for transferring the defined overflow portion of the photodiode-generated charge to the capacitor 52 (e.g., via transistors 42 and 50). The overflow portions of the photodiode-generated charge transferred to the capacitor 52 over multiple pulse periods may be accumulated or combined with each other.

[0030] During the integration period, the control circuit may partially assert (periodically or continuously) the control signal RST to provide an anti-blooming path for the photodiode-generated charge (e.g., for the overflow portion of the charge that is transferred to the floating diffusion region 46 and is not used to generate any image signal).

[0031] The operation of pixel 22 during each pulse period as shown in FIG. 4 is merely exemplary. If desired, the control circuit may assert control signals TX_BR, TX_E2, and TX_FD in any other suitable manner. As a first illustrative example shown in FIG. 5A, during each pulse period, the control circuit may assert control signals TX_BR and TX_FD multiple times (e.g., in multiple pulses) before simultaneously asserting control signals TX_BR and TX_E2. As a second illustrative example shown in FIG. 5B, during each pulse period, instead of pulsing control signal TX_BR (as shown in FIGS. 4 and 5A), the control circuit may continuously (and partially) assert control signal TX_BR and assert control signal TX_FD for a longer period (e.g., a substantial amount of time during which control signal TX_E2 is not asserted) before pulsing control signal TX_E2. If desired, the control circuit may operate pixel 22 during one or more pulse periods within an integration period using the scheme shown in FIG. 5A or 5B (instead of the scheme of FIG. 4).

[0032] 4 , the control circuit may operate pixel 22 to perform a pixel readout operation during a readout period T3 following the final pulse period T2_N. The control circuit may assert control signal SEL throughout the pixel readout operation during readout period T3 (or at least when the pixel output signal is being passed to the pixel output or column line). Readout period T3 may include a first readout period T3-1 for overflow charge accumulated in capacitor 52 and a second readout period T3-2 for remaining charge accumulated in photodiode 40.

[0033] During readout period T3-1, the control circuit may (partially) assert control signals TX_BR and TX_FD and assert control signal RST to transfer and remove a portion of the overflow charge from photodiode 40 and reset floating diffusion region 46 to a reset voltage level (e.g., pixel supply voltage). Thereafter, the control circuit may (fully) simultaneously assert control signals TX_E2 and TX_FD to conductively connect capacitor 52 to floating diffusion region 46 via transistors 44 and 50. This may enable a low-conversion-gain readout of the overflow charge in capacitor 52 (e.g., overflow charge that combines or integrates the overflow charge from each of the pulse periods) by using capacitor 52 to extend the storage capacitance of floating diffusion region 46. In particular, the control circuit may assert control signal SH to activate a sampling circuit within the readout circuit to sample and store (e.g., in the sampling circuit) a low-conversion-gain image signal associated with the overflow charge shared between capacitor 52 and floating diffusion region 46.

[0034] The control circuit may then assert the control signal RST (while the control signals TX_E2 and TX_FD remain asserted) to reset the floating diffusion region 46 and the capacitor 52 to a reset voltage level (e.g., the pixel supply voltage supplied to the voltage terminal 56). After the control signal RST is deasserted, the control circuit may assert the control signal SH (while the control signals TX_E2 and TX_FD remain asserted) to sample and store a reset level signal generated based on the reset level voltage at the floating diffusion region 46 (whose storage capacitance is extended by the capacitor 52 in the low conversion gain operation mode). This reset level signal may be associated with the overflow charge low conversion gain image signal and may be used to compensate for noise in the overflow charge low conversion gain image signal.

[0035] After readout period T3-1 and during readout period T3-2, the control circuit may again assert control signal RST to reset the floating diffusion region to a reset voltage. After control signal RST is deasserted, the control circuit may assert control signal SH (while control signals TX_E2 and TX_FD are deasserted) to sample and store another reset level signal generated based on the reset level voltage at the floating diffusion region 46 (in a high conversion gain operating mode, capacitor 52 is disconnected from the floating diffusion region 46). This reset level signal may be associated with the photodiode accumulated charge high conversion gain image signal, and the subsequently read and sampled photodiode accumulated charge high conversion gain image signal may form a correlated double sampling readout.

[0036] In particular, after sampling this reset level signal, the control circuit may simultaneously (fully) assert the control signals TX_BR and TX_FD to transfer the photodiode accumulated charge from the photodiode 40 to the floating diffusion region 46 via the transistors 42 and 44. The control circuit may then assert the control signal SH to activate the sampling circuitry in the readout circuit to sample and store the high conversion gain image signal associated with the photodiode accumulated charge transferred from the photodiode 40 to the floating diffusion region 46 (in the high conversion gain operating mode, the capacitor 52 is disconnected from the floating diffusion region 46).

[0037] If desired, the reference voltage signal provided at voltage terminal 54 (FIG. 3) can be different voltages during different periods of pixel operation to provide different reference voltages at the second terminal of capacitor 52. As an illustrative example shown in FIG. 4, the control circuit can provide a first reference voltage level during shutter and readout periods T1 and T3 and a second reference voltage level during integration period T2. This is merely an example.

[0038] In the manner described above with reference to Figures 4, 5A, and 5B, the control circuit may operate pixel 22 to generate and read out an overflow charge image signal and a corresponding reset level signal in a low conversion gain operating mode, and to generate and read out a photodiode accumulated charge image signal and a corresponding reset level signal in a high conversion gain operating mode (and correlated double sampling readout). Advantageously, through the use of a coupled-gate structure, pixel 22 is configured to generate these pixel signals while omitting several elements (e.g., a transistor directly connecting capacitor 52 to floating diffusion region 46). In other words, capacitor 52 is connected to floating diffusion region 46 only through at least two transistors (both of which serve overflow charge modulation purposes); a separate transistor directly connecting capacitor 52 to floating diffusion region 46 is not required. This desirably reduces area requirements when implementing the pixel and provides an improved pixel configuration, particularly in applications utilizing pixels having small pixel sizes.

[0039] FIG. 6 is a schematic plan view of an exemplary pixel layout for implementing a coupled gate structure (e.g., transistors 42, 44, and 50 of FIG. 3 ), such as the coupled gate structure in pixel 22 of FIG. 3 . As shown in FIG. 6 , transistor (or gate) 42 may be interposed along a first direction between photodiode 40 and transistors (or gates) 44 and 50. Transistors 50 and 44 may be interposed along a second direction perpendicular to the first direction between terminal 53 (e.g., connected to the second terminal of capacitor 52 opposite the terminal connected to voltage terminal 54) and terminal 47 (e.g., connected to or forming a portion of floating diffusion region 46). Configured in this manner, transistor 42 (in part by receiving an asserted control signal) may form a potential barrier within region 43 (sometimes referred to as an overflow barrier that defines overflow charge from photodiode 40).

[0040] During an integration period (e.g., during each pulse period in one of FIGS. 4, 5A, or 5B), control signals TX_FD (for transistor 44) and TX_E2 (for transistor 50) may be asserted one at a time with a suitable frequency and duration to modulate the flow of overflow charge defined by potential barrier region 43 to one of terminals 47 (e.g., floating diffusion region 46) or 53 (e.g., capacitor 52), as indicated by arrows 72 and 74, respectively. During a readout period (e.g., readout period T3-1 in FIG. 4), control signals TX_FD and TX_E2 may be asserted to conductively connect terminals 53 and 47, as indicated by arrow 76, thereby connecting capacitor 52 and floating diffusion region 46 for a low conversion gain mode of operation (while control signal TX_BR for transistor 42 is deasserted, isolating photodiode 40 from capacitor 52 and floating diffusion region 46).

[0041] The layout of the coupling gate structure in a pixel as shown in Figure 6 is merely exemplary. If desired, any suitable pixel layout may be used to implement the coupling gate structure (e.g., the coupling gate structure in pixel 22 of Figure 3).

[0042] 3, pixel 22 includes a coupled gate structure having two output terminals (e.g., a first output terminal coupled to low-gain capacitor 52 and a second output terminal coupled to floating diffusion region 46). This is merely an example. If desired, an image pixel may include a coupled gate structure having any suitable number of output terminals coupled to appropriate corresponding elements.

[0043] FIG. 7 is a circuit diagram of an exemplary image pixel 22′ having a coupled gate structure with three output terminals. In some exemplary embodiments, array 20 (FIG. 2) may include image pixel 22′ of FIG. 7. Pixel 22′ includes some of the same or similar elements as pixel 22 of FIG. 3 (e.g., photodiode 40, transistors 42, 44, 48, 50, 60, and 62, capacitor 52, floating diffusion region 46). Descriptions of these same or similar elements have been omitted so as not to unnecessarily obscure the embodiment of FIG. 7. Unless otherwise specified, corresponding elements in pixel 22′ may perform the same or similar functions, be coupled and connected to each other in the same or similar manner, and be configured and operable in the same or similar manner as elements described in connection with pixel 22 of FIGS. 3-6.

[0044] 7, pixel 22′ includes two charge storage structures, such as two low-gain capacitors 52 and 82 (compared to the single low-gain capacitor 52 in pixel 22 of FIG. 3). Pixel 22′ thus includes a coupled-gate structure having one input terminal (e.g., a terminal of transistor 42 coupled to photodiode 40) and three output terminals (e.g., a terminal of transistor 50 coupled to capacitor 52, a terminal of transistor 44 coupled to floating diffusion region 46, and a terminal of transistor 80 coupled to capacitor 82). The flow of overflow charge from photodiode 40 can be modulated between three output terminals in the example of FIG. 7 (instead of two output terminals in the example of FIG. 3).

[0045] 7, and similar to capacitor 52, capacitor 82 is coupled at a first terminal to transistor 80 and at a second terminal to voltage terminal 84. Voltage terminal 84 may receive a reference voltage (signal). By way of example, voltage terminal 84 may provide a fixed reference voltage to the second terminal of capacitor 82, or may provide a variable reference voltage signal (e.g., exhibiting a first voltage value during a first time period and a second voltage value during a second time period) to the second terminal of capacitor 82. If desired, voltage terminals 54 and 84 may receive the same reference voltage (signal).

[0046] 7 , transistors 42 and 80 couple photodiode 40 to capacitor 82, thereby enabling capacitor 82 to receive overflow charge from photodiode 40 that overcomes a potential barrier established by transistor 42 using transistors 42 and 80. Transistors 44 and 80 couple floating diffusion region 46 to capacitor 82, thereby enabling capacitor 82 to form a conductive path between floating diffusion region 46 and capacitor 82 using transistors 44 and 80 (e.g., in a charge transfer operation, in a charge sharing operation). Similar to capacitor 52, capacitor 82 may be configured to integrate overflow charge received from photodiode 40 over multiple pulse periods and store the integrated overflow charge.

[0047] 8 is an exemplary timing diagram illustrating how a pixel such as pixel 22′ of FIG. 7 may be operable to generate multiple image signals based on a single integration cycle (e.g., a single integration period). In particular, because capacitors 52 and 82 may each be configured to separately store a corresponding integrated overflow charge and extend the storage capacity of floating diffusion region 46, pixel 22′ may be operable to generate two low-gain image signals (e.g., larger than the one low-gain image signal generated for pixel 22 in the illustrative example described in connection with FIGS. 3-6).

[0048] The timing diagram of FIG. 8 (e.g., described in connection with pixel 22′ of FIG. 7 ) includes some of the same or similar features as the timing diagram of FIG. 4 (e.g., described in connection with pixel 22 of FIG. 3 ). Descriptions of these same or similar features have been omitted so as not to unnecessarily obscure the embodiment of FIG. 8 . Unless otherwise specified, corresponding features in the timing diagram of FIG. 8 perform the same or similar function, have the same or similar characteristics, and may configure and operate pixels (e.g., pixel columns, pixel arrays) in the same or similar manner as the features described in connection with the timing diagram of FIG. 4 .

[0049] In the example of FIG. 8, in addition to the control signals SEL, TX_BR, TX_E2, TX_FD, RST, CLG_REF, and SH (as described in connection with FIG. 4), a control signal TX_E3 may be used to control the operation of pixel 22′ of FIG. 7. As similarly described in connection with FIGS. 3 and 4, each control signal may be provided to a corresponding element within pixel 22′ of FIG. 7. Referring to control signal TX_E3, a control circuit may provide the control signal TX_E3 to transistor 80 within pixel 22′ of FIG. 7. In particular, control circuitry such as row control circuitry 26 and / or control circuitry 24 (FIG. 2) may be configured to provide one or more (e.g., all) of these control signals to corresponding elements within pixel 22′ (and other circuitry such as readout circuitry 28).

[0050] 8, the control circuit may operate pixel 22′ during a shutter period T1, an integration period T2, and a readout period T3. During the shutter period T1, the control circuit may fully assert control signals SEL, TX_BR, TX_E2, TX_FD, and RST, as well as control signal TX_E3, to reset pixel elements in pixel 22′ (e.g., capacitor 82, floating diffusion region 46, photodiode 40, capacitor 52, etc.) to a reset voltage level (e.g., the pixel supply voltage supplied to voltage terminal 56).

[0051] During integration period T2, the control circuit may similarly pulse pixel 22′ through a number of pulse periods T2-1, T2-2, ..., T2-N. In addition to modulating control signals TX_FD (for transistor 44) and TX_E2 (for transistor 50) during each pulse period as described in connection with FIG. 4 , the control circuit may also modulate between control signal TX_E3 for transistor 80 (in combination with control signals TX_FD and TX_E2). This may serve to distribute overflow charge defined by transistor 42 to one of floating diffusion region 46, capacitor 82, or capacitor 52 (one at a time). Respective overflow charges may be transferred to each of floating diffusion region 46, capacitor 82, and capacitor 52 during any given pulse period.

[0052] In the example of FIG. 8 , simultaneous (partial) assertion of control signals TX_BR and TX_E3 may occur between simultaneous (partial) assertion of control signals TX_BR and TX_FD and simultaneous (partial) assertion of control signals TX_BR and TX_E2 for each pulse period. Furthermore, for each pulse period, a first period between simultaneous assertion of TX_BR and TX_FD and simultaneous assertion of TX_BR and TX_E3 may be shorter than a second period between simultaneous assertion of TX_BR and TX_E3 and simultaneous assertion of TX_BR and TX_E3. This may allow capacitor 82, as an example, to accumulate charge for higher (brighter) light conditions than capacitor 52. As described in connection with FIG. 4 , capacitor 52 may integrate or combine overflow charge received over multiple pulse periods. Similarly, capacitor 82 may also integrate or combine overflow charge received over multiple pulse periods.

[0053] During readout period T3, the control circuit may perform pixel readout operations of signals associated with capacitor 52 (e.g., a CAP_E2 readout) and photodiode 40 (PD readout) during periods T3-1 and T3-2, respectively, for pixel 22′ in a manner similar to that described in connection with FIG. 4 for pixel 22. Additionally, when operating pixel 22′, the control circuit may also perform readout operations to include readout of signals associated with capacitor 82 (e.g., a CAP_E3 readout) during readout period T3-0, which is before readout period T3-1 and after integration period T2.

[0054] Similar to the read operation of capacitor 52 (e.g., during period T3-1 in FIG. 4), during read period T3-0, the control circuit may first reset floating diffusion region 46, assert control signal RST, and remove any additional overflow excess charge from photodiode 40 by partially asserting control signals TX_BR and TX_FD.

[0055] The control circuit may then simultaneously assert (fully) control signals TX_E3 and TX_FD to conductively connect capacitor 82 to floating diffusion region 46 via transistors 44 and 80. This may enable a low conversion gain readout of overflow charge in capacitor 82 (e.g., overflow charge that combines or integrates overflow charge from each of the pulse periods) by using capacitor 82 to extend the storage capacitance of floating diffusion region 46. In particular, the control circuit may assert control signal SH to activate a sampling circuit within the readout circuit to sample and store (e.g., in the sampling circuit) a low conversion gain image signal associated with the overflow charge shared between capacitor 82 and floating diffusion region 46.

[0056] The control circuit may then assert the control signal RST (while the control signals TX_E3 and TX_FD remain asserted) to reset the floating diffusion region 46 and the capacitor 82 to a reset voltage level (e.g., the pixel supply voltage supplied to the voltage terminal 56). After the control signal RST is deasserted, the control circuit may assert the control signal SH (while the control signals TX_E3 and TX_FD remain asserted) to sample and store a reset level signal generated based on the reset voltage level at the floating diffusion region 46 (whose storage capacitance is extended by the capacitor 82 in the low conversion gain operating mode). This reset level signal may be associated with the overflow charge low conversion gain image signal and may be used to compensate for noise in the overflow charge low conversion gain image signal.

[0057] Because the floating diffusion region 46 has already been reset to the reset voltage level after read period T3-0, read period T3-1 may omit another floating diffusion region reset operation (e.g., as opposed to read period T3-1 as described in connection with FIG. 4). Otherwise, the control circuit may operate pixel 22′ during read periods T3-1 and T3-2 as similarly described in connection with FIG. 4 for pixel 22 of FIG. 3. Additionally, if desired, a reference voltage signal CLG_REF may be provided to voltage terminal 84 (in addition to voltage terminal 54).

[0058] 3-6, pixel 22 may generate a first (E2) low conversion gain signal (associated with overflow charge accumulated in capacitor 52) that is optimal for relatively high light conditions and a second (E1) high conversion gain signal (associated with remaining charge accumulated in photodiode 40) that is optimal for relatively low light conditions. In the examples of FIGS. 7 and 8, pixel 22′ may also generate a first (E2) low conversion gain signal (associated with overflow charge accumulated in capacitor 52) that is optimal for relatively high light conditions and a second (E1) high conversion gain signal (associated with remaining charge accumulated in photodiode 40) that is optimal for relatively low light conditions. Additionally, pixel 22′ may generate an additional (E3) low conversion gain signal (associated with overflow charge accumulated in capacitor 82) that is optimal for even higher light conditions, thereby further extending the dynamic range of pixel 22′ (e.g., when compared to pixel 22).

[0059] 9 and 10 are schematic plan views of exemplary pixel layouts for implementing a coupled gate structure such as the coupled gate structure in pixel 22′ of FIG. 7 (e.g., transistors 42, 44, 50, and 80 of FIG. 7). As shown in FIG. 9, transistor (or gate) 42 may be interposed between photodiode 40 and transistors (or gates) 44, 50, and 80. Transistor 42 may be adjacent to transistor 50 on one side, transistor 80 on the opposite side, or transistor 44 in the center. Similarly, transistor 44 may be adjacent to transistor 50 on one side, transistor 80 on the opposite side, or transistor 42 in the center. Transistors 50 and 80 may be separated from each other by portions of transistors 42 and 44. Transistor 50 may be coupled to a terminal connected to a first terminal of capacitor 52. Transistor 80 may be coupled to a terminal connected to a first terminal of capacitor 82. Transistor 44 may be coupled to a terminal connected to floating diffusion region 46.

[0060] Configured in this manner, transistor 42 (by receiving a partially asserted control signal) can form a potential barrier that defines overflow charge from photodiode 40. During an integration period (e.g., during each pulse in FIG. 8 ), control signals TX_FD (for transistor 44), TX_E2 (for transistor 50), and TX_E3 (for transistor 80) can be modulated (e.g., asserted one at a time with a suitable frequency and duration) to direct overflow charge beyond the formed potential barrier to one of floating diffusion region 46, capacitor 52, or capacitor 82. During a readout period (e.g., readout period T3-1 in FIG. 8 ), control signals TX_FD and TX_E2 can be asserted to conductively connect capacitor 52 and floating diffusion region 46 for a low conversion gain mode of operation (while control signals TX_BR for transistor 42 and TX_E3 for transistor 80 are deasserted to isolate photodiode 40 and capacitor 82 from capacitor 52 and floating diffusion region 46). During a readout period (e.g., readout period T3-0 in FIG. 8), control signals TX_FD and TX_E3 may be asserted to conductively connect capacitor 82 and floating diffusion region 46 in a low conversion gain operating mode (while control signals TX_BR for transistor 42 and TX_E2 for transistor 50 are deasserted to isolate photodiode 40 and capacitor 52 from capacitor 82 and floating diffusion region 46).

[0061] In an alternative layout shown in FIG. 10 , transistors 42, 50, 80, and 44 may be formed at the four corners of a rectangular pixel outline. A (conductive) implant region 90 may be overlapped by transistors 42 (e.g., protruding portion 42-1), 50, 80, and 44, thereby enabling transfer of overflow charge to the corresponding charge storage structure (e.g., capacitor 52, capacitor 82, and floating diffusion region 46 connected to transistor 44). Another (conductive) implant region 92 may be overlapped by transistors 50 and 44, thereby providing a conductive path between capacitor 52 and floating diffusion region 46 (e.g., via transistors 50 and 44 and through implant region 92). Yet another (conductive) implant region 94 may be overlapped by transistors 80 and 44, thereby providing a conductive path between capacitor 82 and floating diffusion region 46 (e.g., via transistors 80 and 44 and through implant region 94). The configuration of FIG. 10 may configure pixel 22 to exhibit the same functionality as that of FIG. 9 .

[0062] The layout of the coupled gate structure with three output terminals in the pixel as shown in Figures 9 and 10 is merely exemplary. If desired, any suitable pixel layout may be used to implement the coupled gate structure (e.g., the coupled gate structure in pixel 22' of Figure 7).

[0063] Various embodiments are described illustrating image sensors having image pixels with coupled gate structures.

[0064] As an illustrative example, an image sensor pixel may include a photosensitive element (e.g., a photodiode), a floating diffusion region, first and second transistors coupling the photosensitive element to the floating diffusion region, a charge storage structure (e.g., a capacitor), and a third transistor. The second and third transistors may be configured to form a conductive path between the floating diffusion region and the charge storage structure during a pixel readout operation (e.g., during low conversion gain readout of overflow charge stored in the charge storage structure). The first transistor may be configured to form a potential barrier that defines an overflow portion of charge generated by the photosensitive element. The first and third transistors may be configured to transfer the overflow portion of charge from the photosensitive element to the charge storage structure. The image sensor pixel may further include a reset transistor coupling the floating diffusion region to a supply voltage terminal and a source follower transistor coupling the floating diffusion region to a pixel output path. If desired, the image sensor pixel may be configured to output a low conversion gain image signal based on the overflow portion of the charge, and a high conversion gain image signal based on the remaining portion of the charge stored in the photosensitive element.

[0065] If desired, the image sensor pixel may further include an additional charge storage structure (e.g., an additional capacitor) and a fourth transistor. The first and fourth transistors may be configured to transfer an overflow portion of charge from the photosensitive element to the additional charge storage structure. The second and fourth transistors may be configured to form an additional conductive path between the floating diffusion region and the additional charge storage structure during a pixel readout operation (e.g., during low conversion gain readout of the overflow charge stored in the additional charge storage structure). If desired, the image sensor pixel may be configured to output a first low conversion gain image signal based on a first portion of the charge stored in the charge storage structure, a second low conversion gain image signal based on a second portion of the charge stored in the additional charge storage structure, and a high conversion gain image signal based on the remaining portion of the charge stored in the photosensitive element.

[0066] As another illustrative example, an image sensor may include control circuitry (e.g., row control circuitry), readout circuitry (e.g., column readout circuitry), and an array of image pixels coupled to the control circuitry and coupled to the readout circuitry. One or more image pixels in the array may each include a photosensitive element, a floating diffusion region, a capacitor, and a coupling gate structure having an input terminal coupled to the photosensitive element, a first output terminal coupled to the floating diffusion region, and a second output terminal coupled to the capacitor. The control circuitry may be configured to control the coupling gate structure to form a conductive path between the first output terminal and the second output terminal and connect the floating diffusion region to the capacitor via the coupling gate structure.

[0067] In particular, the coupled gate structure may include a first transistor coupled to the photosensitive element, a second transistor coupled to the floating diffusion region, and a third transistor coupled to the capacitor. A control circuit may be configured to control the first transistor to define an overflow portion of the charge generated by the photosensitive element and to define a remaining portion of the charge generated and stored by the photosensitive element. The control circuit may be configured to operate the second transistor to transfer a first set of the overflow portion of the charge to the diffusion region and to operate the third transistor to transfer a second set of the overflow portion of the charge to the capacitor. A readout circuit may be configured to receive (e.g., from the image pixel) a first image signal generated based on the second set of the overflow portion of the charge and a second image signal generated based on the remaining portion of the charge stored in the photosensitive element.

[0068] As yet another illustrative example, a method of operating an image sensor pixel may include generating charge in a photosensitive element in response to incident light; defining an overflow portion of the generated charge in a first transistor; modulating a transfer of the overflow portion of the generated charge between a floating diffusion region and a charge storage structure (e.g., a capacitor) using second and third transistors (e.g., selectively activating the second and third transistors one at a time to transfer the overflow portion to the respective floating diffusion region or charge storage structure); and connecting the floating diffusion region to the charge storage structure using the second and third transistors during a read operation (e.g., during a low conversion gain readout of the overflow charge stored in the charge storage structure).

[0069] The method may further include using the second and third transistors to output a low conversion gain image signal while connecting the floating diffusion region to the charge storage structure, using the first and second transistors to transfer a remaining portion of the generated charge to the floating diffusion region during a read operation (e.g., for a high conversion gain readout of the remaining charge stored in the photosensitive element), and outputting a high conversion gain image signal after using the first and second transistors to transfer the remaining portion of the generated charge to the floating diffusion region. If desired, the method may further include using the second and third transistors to remove an overflow portion of any generated charge transferred to the floating diffusion region (e.g., by resetting the floating diffusion region to a reset voltage level) before connecting the floating diffusion region to the charge storage structure.

[0070] According to one embodiment, an image sensor pixel may include a photosensitive element, a floating diffusion region, first and second transistors coupling the photosensitive element to the floating diffusion region, a charge storage structure, and a third transistor, wherein the second and third transistors may be configured to form a conductive path between the floating diffusion region and the charge storage structure during a pixel readout operation.

[0071] According to another embodiment, the charge storage structure may include a capacitor.

[0072] According to another embodiment, a capacitor may be configured to extend the storage capacitance of the floating diffusion region in a low conversion gain mode of operation.

[0073] According to another embodiment, the first transistor may be configured to form a potential barrier that defines an overflow portion of the charge generated by the photosensitive element.

[0074] According to another embodiment, the first and third transistors may be configured to transfer an overflow portion of the charge from the photosensitive element to the capacitor.

[0075] According to another embodiment, the image sensor pixel may be configured to output a low conversion gain image signal based on the overflow portion of the charge, and a high conversion gain image signal based on the remaining portion of the charge accumulated in the photosensitive element.

[0076] According to another embodiment, the image sensor pixel may further include a reset transistor coupling the floating diffusion region to a supply voltage terminal, and a source follower transistor coupling the floating diffusion region to the pixel output path.

[0077] According to another embodiment, the first transistor, the second transistor, and the reset transistor may form an anti-blooming path for the photosensitive element.

[0078] According to another embodiment, the image sensor pixel may further include an additional charge storage structure and a fourth transistor, wherein the second and fourth transistors may be configured to form an additional conductive path between the floating diffusion region and the additional charge storage structure during a pixel readout operation.

[0079] According to another embodiment, the image sensor pixel may be configured to output a first low conversion gain image signal based on a first portion of the charge stored in the charge storage structure, a second low conversion gain image signal based on a second portion of the charge stored in the additional charge storage structure, and a high conversion gain image signal based on the remaining portion of the charge stored in the photosensitive element.

[0080] According to one embodiment, an image sensor may include a control circuit, a readout circuit, and an array of image pixels coupled to the control circuit and coupled to the readout circuit. An image pixel in the array may include a photosensitive element, a floating diffusion region, a capacitor, and a coupling gate structure having an input terminal coupled to the photosensitive element, a first output terminal coupled to the floating diffusion region, and a second output terminal coupled to the capacitor. The control circuit may be configured to control the coupling gate structure to form a conductive path between the first output terminal and the second output terminal and connect the floating diffusion region to the capacitor via the coupling gate structure.

[0081] According to another embodiment, a coupled gate structure may include a first transistor coupled to the photosensitive element, a second transistor coupled to the floating diffusion region, and a third transistor coupled to the capacitor.

[0082] According to another embodiment, the control circuit may be configured to control the first transistor to define an overflow portion of the charge generated by the photosensitive element and to define a remaining portion of the charge generated and stored by the photosensitive element.

[0083] According to another embodiment, the control circuit may be configured to operate the second transistor to transfer a first set of the overflow portion of the charge to the diffusion region and to operate the third transistor to transfer a second set of the overflow portion of the charge to the capacitor.

[0084] According to another embodiment, a readout circuit may be configured to receive a first image signal generated based on a second set of overflow portions of the charges and a second image signal generated based on a remaining portion of the charges accumulated in the photosensitive elements.

[0085] According to one embodiment, a method of operating an image sensor pixel may include generating charge in a photosensitive element in response to incident light; defining an overflow portion of the generated charge in a first transistor; modulating a transfer of the overflow portion of the generated charge between a floating diffusion region and a charge storage structure using second and third transistors; and connecting the floating diffusion region to the charge storage structure using the second and third transistors during a read operation.

[0086] According to another embodiment, the method may further include outputting a low conversion gain image signal using second and third transistors while connecting the floating diffusion region to the charge storage structure.

[0087] According to another embodiment, the method may further include transferring a remaining portion of the generated charge to the floating diffusion region using the first and second transistors during a read operation.

[0088] According to another embodiment, the method may further include outputting a high conversion gain image signal after transferring a remaining portion of the generated charge to a floating diffusion region using the first and second transistors.

[0089] According to another embodiment, the method may further include using the second and third transistors to remove an overflow portion of any generated charge transferred to the floating diffusion region before connecting the floating diffusion region to the charge storage structure.

[0090] The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. 1. An image sensor pixel, comprising: a photosensitive element; a floating diffusion region; a first transistor and a second transistor coupling the photosensitive element to the floating diffusion region; a charge storage structure; a third transistor, wherein the second transistor and the third transistor are configured to form a conductive path between the floating diffusion region and the charge storage structure during a pixel readout operation.

2. 2. The image sensor pixel of claim 1, wherein the charge storage structure comprises a capacitor configured to extend the storage capacity of the floating diffusion region in a low conversion gain operation mode, the first transistor is configured to form a potential barrier that defines an overflow portion of charge generated by the photosensitive element, the first and third transistors are configured to transfer the overflow portion of charge from the photosensitive element to the capacitor, and the image sensor pixel is configured to output a low conversion gain image signal based on the overflow portion of charge and a high conversion gain image signal based on the remaining portion of charge stored in the photosensitive element.

3. a reset transistor coupling the floating diffusion region to a supply voltage terminal; 10. The image sensor pixel of claim 1, further comprising: a source follower transistor coupling the floating diffusion region to a pixel output path, wherein the first transistor, the second transistor, and the reset transistor form an anti-blooming path for the photosensitive element.

4. Further comprising an additional charge storage structure and a fourth transistor; the first and fourth transistors are configured to transfer an overflow portion of charge from the photosensitive element to the additional charge storage structure; 2. The image sensor pixel of claim 1, wherein the second and fourth transistors are configured to form additional conductive paths between the floating diffusion region and the additional charge storage structure during the pixel readout operation.

5. An image sensor pixel as described in claim 4, wherein the first, second, third and fourth transistors form a coupled gate structure and share a common terminal, the first transistor configured to connect the photosensitive element to the common terminal, the second transistor configured to connect the floating diffusion region to the common terminal, the third transistor configured to connect the charge storage structure to the common terminal, and the fourth transistor configured to connect the additional charge storage structure to the common terminal.

6. An image sensor pixel as described in claim 1, wherein the charge storage structure has a terminal directly coupled to only one transistor, and that one transistor is the third transistor.

7. An image sensor pixel as described in claim 1, wherein the charge storage structure is connected to the floating diffusion region by only one conductive path, the conductive path passing through at least the second transistor and the third transistor, and the third transistor being coupled between the photosensitive element and the charge storage structure.

8. 1. An image sensor, comprising: a control circuit; a readout circuit; An image sensor comprising an array of image pixels having image sensor pixels according to claim 1 coupled to said control circuit and coupled to said readout circuit.

9. The image sensor of claim 8, wherein the control circuit is configured to control the first transistor to define an overflow portion of the charge generated by the photosensitive element and to define a remaining portion of the charge generated and stored by the photosensitive element, the control circuit is configured to operate the second transistor to transfer a first set of the overflow portion of the charge to the floating diffusion region and to operate the third transistor to transfer a second set of the overflow portion of the charge to a capacitor, and the readout circuit is configured to receive a first image signal generated based on the second set of the overflow portion of the charge and receive a second image signal generated based on the remaining portion of the charge stored in the photosensitive element.

10. 1. A method of operating an image sensor pixel, comprising: generating charge in a photosensitive element in response to incident light; defining an overflow portion of the generated charge in a first transistor; modulating the transfer of the overflow portion of the generated charge between a floating diffusion region and a charge storage structure using a second transistor and a third transistor; and connecting the floating diffusion region to the charge storage structure using the second transistor and a third transistor during a read operation.

11. outputting a low conversion gain image signal while connecting the floating diffusion region to the charge storage structure using the second transistor and the third transistor; transferring a remaining portion of the generated charge to the floating diffusion region using the first transistor and the second transistor during the read operation; outputting a high conversion gain image signal after transferring the remaining portion of the generated charge to the floating diffusion region using the first transistor and the second transistor; 11. The method of claim 10, further comprising: removing an overflow portion of the generated charge transferred to the floating diffusion region before connecting the floating diffusion region to the charge storage structure using the second transistor and the third transistor.

12. The method of claim 11, further comprising: connecting the photosensitive element to an additional charge storage structure using the first transistor and a fourth transistor; connecting the floating diffusion region to the additional charge storage structure using the second transistor and the fourth transistor during the read operation; The method of claim 10 further comprising:

13. A method described in any one of claims 10 to 12, wherein the charge storage structure has a terminal directly coupled to only one transistor, and that one transistor is the third transistor.

14. A method described in any one of claims 10 to 12, wherein the charge storage structure is connected to the floating diffusion region only by one conductive path, the one conductive path passing through at least the second transistor and the third transistor, and the third transistor being coupled between the photosensitive element and the charge storage structure.

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