Imaging device

Abstract

This relaxes the constraints on the layout of the stacked structure of semiconductor chips on which logarithmic transformation transistors and current-voltage transformation transistors used for event detection are formed. [Solution] The imaging device comprises a photoelectric conversion element, a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the optical current into an output voltage based on the optical voltage generated by the logarithmic transistor. A second chip is stacked on a first chip on which the photoelectric conversion element is formed, and at least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip.

Description

Technical Field

[0001] The present technology relates to an imaging device. Specifically, the present technology relates to an imaging device capable of event detection.

Background Art

[0002] In an imaging device, in order to improve noise characteristics, a stacked structure of semiconductor chips may be used. For example, a technique has been disclosed in which a photoelectric conversion element that generates charges according to the amount of received light and a detection unit that detects a current based on the charges generated in the photoelectric conversion element are arranged on different semiconductor chips (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above-described conventional technology, the photoelectric conversion element is formed on the lower chip, and the logarithmic conversion transistor and the current-voltage conversion transistor used for event detection are formed on the upper chip. Therefore, it is necessary to secure the layout space for the logarithmic conversion transistor and the current-voltage conversion transistor on the upper chip, which may increase the constraints on the layout of the upper chip.

[0005] The present technology has been created in view of such a situation, and an object thereof is to relax the layout constraints of a stacked structure of semiconductor chips on which a logarithmic conversion transistor and a current-voltage conversion transistor used for event detection are formed.

Means for Solving the Problems

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is an imaging device comprising a photoelectric conversion element, a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the optical current into an output voltage based on the optical voltage generated by the logarithmic transistor, wherein a second chip is stacked on a first chip on which the photoelectric conversion element is formed, and at least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip. This has the effect of relaxing the constraints on the layout of the second chip compared to a configuration in which both the logarithmic transistor and the current-voltage conversion transistor are placed on the second chip.

[0007] Furthermore, in the first aspect, the source of the logarithmic transistor and the gate of the current-voltage conversion transistor may be connected to the cathode of the photoelectric conversion element, and the gate of the logarithmic transistor may be connected to the drain of the current-voltage conversion transistor. This results in the generation of an output voltage in which the photovoltage obtained by logarithmically converting the photocurrent output from the photoelectric conversion element is amplified.

[0008] Furthermore, in the first aspect, the first chip may be provided with a first wiring that is formed on the first chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor. This has the effect of relaxing the constraints on the layout of the logarithmic transistor and the current-voltage conversion transistor based on the first wiring.

[0009] Furthermore, in the first aspect, the second chip may be provided with a second wiring that is formed on the second chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor. This has the effect of relaxing the constraints on the layout of the logarithmic transistor and the current-voltage conversion transistor based on the second wiring.

[0010] Furthermore, in the first aspect, the first chip may include a first contact formed on the first chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor, and a second contact formed on the second chip and positioned to overlap with the first contact. This has the effect of reducing the wiring capacitance of the logarithmic transistor and the current-voltage conversion transistor.

[0011] Furthermore, in the first aspect, the current-voltage conversion transistor may be formed on the first chip, and the logarithmic transistor may be formed on the second chip. This has the effect of relaxing the constraints on the layout of the second chip.

[0012] Furthermore, in the first aspect, the logarithmic transistor may be formed on the first chip, and the current-voltage conversion transistor may be formed on the second chip. This reduces the layout area of ​​the first chip while easing the constraints on the layout of the second chip.

[0013] Furthermore, in the first aspect, the logarithmic transistor and the current-voltage conversion transistor may be formed on the first chip. This has the effect of relaxing the constraints on the layout of the second chip compared to a configuration in which either the logarithmic transistor or the current-voltage conversion transistor is placed on the second chip.

[0014] Furthermore, in the first aspect, the logarithmic transistor may comprise a first logarithmic transistor and a second logarithmic transistor connected in series with the first logarithmic transistor. This has the effect of increasing the driving force of the logarithmic transistor while easing the constraints on the layout of the second chip.

[0015] Furthermore, in the first aspect, the current-voltage conversion transistor may include a first current-voltage conversion transistor and a second current-voltage conversion transistor connected in series with the first current-voltage conversion transistor. This has the effect of increasing the driving force of the current-voltage conversion transistor while easing the constraints on the layout of the second chip.

[0016] Furthermore, in the first aspect, the logarithmic transistor may be formed on the second chip and include a first interlayer wiring that extends from the first chip and is connected to the lower surface side of the source of the logarithmic transistor. This has the effect of shortening the source wiring of the logarithmic transistor while easing the constraints on the layout of the second chip.

[0017] Furthermore, in the first aspect, the current-voltage conversion transistor may be formed on the second chip and include a second interlayer wiring that extends from the first chip and is joined to the gate of the current-voltage conversion transistor. This has the effect of shortening the gate wiring of the current-voltage conversion transistor while easing the constraints on the layout of the second chip.

[0018] Furthermore, in the first aspect, at least one of the logarithmic transistor and the current-voltage conversion transistor formed on the first chip may be a BEOL (Back End Of Line) transistor. This has the effect of reducing the parasitic capacitance of at least one of the logarithmic transistor and the current-voltage conversion transistor.

[0019] Furthermore, in the first aspect, the device includes a pixel array section in which grayscale pixels for detecting grayscale signals and event pixels for detecting event signals are formed, and the event pixels include a photoelectric conversion element, a logarithmic transistor for generating an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, and a current-voltage conversion transistor for converting the optical current to an output voltage based on the optical voltage generated by the logarithmic transistor, and a second chip is stacked on the first chip on which the photoelectric conversion element is formed, and at least one of the logarithmic transistor and the current-voltage conversion transistor may be formed on the first chip. This provides the effect of combining grayscale pixels and event pixels while relaxing the constraints on the layout of the second chip.

[0020] Furthermore, in the first aspect, the layout pattern of the photoelectric conversion elements formed on the grayscale pixels and the layout pattern of the photoelectric conversion elements formed on the event pixels may be the same as each other. This has the effect of eliminating the difference between the storage capacity of grayscale pixels adjacent to the event pixels and the storage capacity of grayscale pixels not adjacent to the event pixels.

[0021] Furthermore, in the first aspect, the amplification transistors for the grayscale pixels may be formed on the first chip, and the selection transistors for the grayscale pixels may be formed on the second chip. This results in an increase in the area of ​​the amplification transistors for the grayscale pixels.

[0022] Furthermore, in the first aspect, the pixel array portion comprises pixel regions partitioned in a matrix manner in the row direction and column direction, and the pixel regions comprise a first pixel region and a second pixel region that are not adjacent to each other in the row direction and column direction, the logarithmic transistor may be formed in the first pixel region, and the current-voltage conversion transistor may be formed in the second pixel region. This has the effect of easing the constraints on the layout of the second chip while arranging the logarithmic transistor and the current-voltage conversion transistor at separate locations.

[0023] Also, on the first side, a photoelectric conversion element of the gradation pixel and a photoelectric conversion element of the event pixel are formed on the first chip, and on the second chip, a pixel transistor of the gradation pixel may be formed at a position overlapping at least one of the photoelectric conversion element of the gradation pixel and the photoelectric conversion element of the event pixel. This results in the effect of relaxing the layout constraints of the pixel transistors of the gradation pixels and suppressing the interference between the pixel transistors of the gradation pixels and the event transistors of the event pixels.

[0024] Also, the second side includes a photoelectric conversion element and a logarithmic transistor that generates a photovoltage obtained by logarithmically converting the photocurrent output from the photoelectric conversion element. A second chip may be stacked on the first chip on which the photoelectric conversion element is formed, and the logarithmic transistor may be formed on the first chip. This results in the effect of relaxing the layout constraints of the second chip compared to a configuration in which the logarithmic transistor is arranged on the second chip.

[0025] Also, the third side includes a photoelectric conversion element, a logarithmic transistor that generates a photovoltage obtained by logarithmically converting the photocurrent output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor. A second chip is stacked on the first chip on which the photoelectric conversion element is formed, the logarithmic transistor and the current-voltage conversion transistor are formed on the second chip, and it is an imaging device including an interlayer wiring that extends from the first chip and is connected to the lower surface side of the source of the logarithmic transistor. This results in the effect of relaxing the layout constraints of the second chip while shortening the source wiring of the logarithmic transistor.

[0026] Further, the fourth side surface includes a photoelectric conversion element, a logarithmic transistor that generates a photovoltage obtained by logarithmically converting a photocurrent output from the photoelectric conversion element, and a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor. A second chip is laminated on a first chip on which the photoelectric conversion element is formed. The logarithmic transistor and the current-voltage conversion transistor are formed on the second chip, and the imaging device includes an interlayer wiring that extends from the first chip and is joined to the gate of the current-voltage conversion transistor. This results in an effect of relaxing the layout constraints of the second chip while shortening the gate wiring of the current-voltage conversion transistor.

Brief Description of Drawings

[0027] [Figure 1] It is a block diagram showing a configuration example of an imaging device according to the first embodiment. [Figure 2] It is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. [Figure 3] It is a diagram showing a configuration example of a gradation pixel and an event pixel according to the first embodiment. [Figure 4] It is a plan view showing a layout example of gradation pixels and event pixels of a lower-layer chip according to the first embodiment. [Figure 5] It is a plan view showing a layout example of gradation pixels of an upper-layer chip according to the first embodiment. [Figure 6] It is a cross-sectional view showing a configuration example of a gradation pixel and an event pixel according to the first embodiment. [Figure 7] It is a plan view showing a layout example of gradation pixels and event pixels of a lower-layer chip according to the second embodiment. [Figure 8] It is a plan view showing a layout example of gradation pixels of an upper-layer chip according to the second embodiment. [Figure 9] It is a cross-sectional view showing a configuration example of a gradation pixel and an event pixel according to the second embodiment. [Figure 10]This is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the third embodiment. [Figure 11] This is a plan view showing an example of the layout of grayscale pixels and event pixels of the lower layer chip according to the fourth embodiment. [Figure 12] This is a plan view showing an example of the layout of grayscale pixels in the upper chip according to the fourth embodiment. [Figure 13] This is a circuit diagram showing an example of the configuration of the logarithmic transformation unit according to the fifth embodiment. [Figure 14] This is a circuit diagram showing another configuration example of the logarithmic transformation unit according to the fifth embodiment. [Figure 15] This is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment. [Figure 16] This is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment. [Figure 17] This is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment. [Figure 18] This is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment. [Figure 19] This is a plan view showing an example of the layout of grayscale pixels and event pixels of the lower layer chip according to the sixth embodiment. [Figure 20] This is a cross-sectional view showing an example of the configuration of an event pixel according to the sixth embodiment. [Figure 21] This is a plan view showing an example of the layout of grayscale pixels and event pixels of the lower layer chip according to the seventh embodiment. [Figure 22] This is a cross-sectional view showing an example of the configuration of an event pixel according to the seventh embodiment. [Figure 23] This is a plan view showing an example of the layout of grayscale pixels and event pixels of the lower layer chip according to the eighth embodiment. [Figure 24] This is a cross-sectional view showing an example of the configuration of an event pixel according to the eighth embodiment. [Figure 25] This is a cross-sectional view showing an example of the configuration of an event pixel according to the ninth embodiment. [Figure 26] This is a plan view showing an example of the layout of grayscale pixels and event pixels of the lower layer chip according to the tenth embodiment. [Figure 27] This is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the tenth embodiment. [Figure 28] This is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the 11th embodiment. [Figure 29] This is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the twelfth embodiment. [Figure 30] This is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the 13th embodiment. [Figure 31] This is a cross-sectional view showing an example of the configuration of grayscale pixels according to the 14th embodiment. [Figure 32] This is a perspective view showing an example of stacking of a solid-state imaging device according to the 15th embodiment. [Figure 33] This is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 34] This is an explanatory diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0028] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (An example in which logarithmic transistors and current-voltage conversion transistors are placed on the lower layer chip, and pixel transistors are also placed on the lower layer chip) 2. Second Embodiment (An example in which a logarithmic transistor and a current-voltage conversion transistor are placed on a lower layer chip, and the wiring connecting the logarithmic transistor and the current-voltage conversion transistor is also placed on a lower layer chip) 3. Third Embodiment (An example in which a logarithmic transistor and a current-voltage conversion transistor are placed on the lower layer chip, and the input terminal of the event pixel is also placed on the lower layer chip) 4. Fourth Embodiment (An example in which logarithmic transistors and current-voltage conversion transistors are placed in non-adjacent pixel regions of the lower layer chip) 5. Fifth Embodiment (Example in which the logarithmic transformation section of the event pixel is configured with transistors) 6. Sixth Embodiment (An example in which a current-voltage conversion transistor is placed on the lower layer chip and a logarithmic transistor is placed on the upper layer chip) 7. Seventh Embodiment (An example in which logarithmic transistors are placed on the lower layer chip and current-voltage conversion transistors are placed on the upper layer chip) 8. Eighth Embodiment (An example in which a series circuit of logarithmic transistors is placed on the lower layer chip and a current-voltage conversion transistor is placed on the upper layer chip) 9. A ninth embodiment (an example in which a current-voltage conversion transistor is placed on the lower layer chip and a series circuit of logarithmic transistors is placed on the upper layer chip) 10. Tenth Embodiment (An example in which current-voltage conversion transistors and amplification transistors are placed on a lower layer chip, and logarithmic transistors and selection transistors are placed on an upper layer chip) 11. Eleventh Embodiment (An example in which a current-voltage conversion transistor and a logarithmic transistor are placed on an intermediate chip, and interlayer wiring extending from the lower layer chip is connected to the underside of the source of the logarithmic transistor) 12. Twelfth Embodiment (An example in which a current-voltage conversion transistor and a logarithmic transistor are placed on an intermediate chip, and interlayer wiring extending from the lower layer chip is joined to the gate of the current-voltage conversion transistor) 13. Thirteenth Embodiment (An example in which a current-voltage conversion transistor and a logarithmic transistor are placed on an intermediate chip, and the intermediate chip is bonded to the lower and upper chips based on a Cu-Cu junction) 14. Fourteenth Embodiment (An example in which a current-voltage conversion transistor is placed on the lower layer chip, a logarithmic transistor is placed on the upper layer chip, and the logarithmic transistor is composed of a BEOL transistor) 15. Fifteenth Embodiment (Example of stacked pixel array sections) 16. Examples of applications to mobile devices

[0029] <1. First Embodiment>

[0030] Figure 1 is a block diagram showing an example configuration of an imaging device according to the first embodiment.

[0031] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, or incorporated into an authentication device or a monitoring device.

[0032] The optical system 101 directs light from the subject into the solid-state imager 102 and forms an image of the subject on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0033] The solid-state imaging device 102 converts light from the subject into an electrical signal for each pixel, and outputs that electrical signal digitized. The solid-state imaging device 102 can output a gradation signal corresponding to the brightness of the incident light and an event signal that detects a change in the brightness of the incident light in the same direction as an event. In this case, the solid-state imaging device 102 can be provided with gradation pixels for detecting gradation signals and event pixels for detecting event signals.

[0034] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0035] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0036] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The captured images may include grayscale images and event images. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0037] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0038] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0039] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0040] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, an event signal output unit 113, a grayscale signal output unit 114, an access control unit 115, a timing control unit 116, an event signal processing unit 117, and a grayscale signal processing unit 118.

[0041] The pixel array section 111 has event pixels EPX and gradation pixels KPX arranged in a matrix in the row direction (also called the horizontal direction) and column direction (also called the vertical direction). The event pixels EPX may be arranged adjacent to the gradation pixels KPX in the row direction or column direction. In this case, the event pixels EPX and gradation pixels KPX can be formed in a stacked structure of a chip. The event pixels EPX detect event signals. The event signal is a signal that indicates an event when the brightness of the incident light changes in the same direction. A photodiode or a SPAD (Single Photon Avalanche Diode) may be provided as the photoelectric conversion part of the event pixels EPX. The gradation pixels KPX detect gradation signals. The gradation signal is a signal that indicates a level corresponding to the brightness of the incident light.

[0042] The event pixel EPX and the grayscale pixel KPX may each be a single pixel, two-pixel shared, four-pixel shared, or eight-pixel shared. The grayscale pixel KPX may support rolling shutter readout or global shutter readout. The grayscale pixel KPX may also be an HDR (High Dynamic Range) pixel capable of switching conversion efficiency for output. Furthermore, the grayscale pixel KPX may form a Bayer array or a quad-Bayer array. The light received by the event pixel EPX and the grayscale pixel KPX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0043] Event pixels (EPX) and grayscale pixels (KPX) can be driven row by row via the horizontal control line (HSL). Event pixels (EPX) can output signals column by column via the vertical event signal line (ESL). Grayscale pixels (KPX) can output signals column by column via the vertical grayscale signal line (VSL).

[0044] The event signal output unit 113 outputs the event signal output from the event pixel EPX in a predetermined format. For example, the event signal output unit 113 may digitize the event signal output from the event pixel EPX and output it.

[0045] The gradation signal output unit 114 outputs the gradation signal output from the gradation pixel KPX in a predetermined format. For example, the gradation signal output unit 114 may digitize the gradation signal output from the gradation pixel KPX and output it.

[0046] The access control unit 115 controls access to the event pixel EPX and the grayscale pixel KPX via the horizontal control line HSL. At this time, the access control unit 115 can drive the event pixel EPX and the grayscale pixel KPX row by row via the horizontal control line HSL.

[0047] The timing control unit 116 can control the timing of exposure, readout, selection, and reset for event pixels EPX and grayscale pixels KPX. In this case, the timing control unit 116 can cause the accumulation operation, shutter operation, and read operation to be performed row by row in each frame.

[0048] The event signal processing unit 117 processes the event signal output from the event pixel EPX. For example, the event signal processing unit 117 can generate an event image based on the event signal.

[0049] The gradation signal processing unit 118 processes the gradation signal output from the gradation signal output unit 114. The gradation signal processing unit 118 may, for example, perform correlated double sampling (CDS) processing based on the gradation signal output from the gradation signal output unit 114.

[0050] Figure 3 shows an example of the configuration of grayscale pixels and event pixels according to the first embodiment.

[0051] In the figure, the grayscale pixel KPX comprises a photodiode KPD, a transfer transistor 153, a reset transistor 154, an amplification transistor 155, a selection transistor 156, and a floating diffusion KFD. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 153, the reset transistor 154, the amplification transistor 155, and the selection transistor 156.

[0052] The amplification transistor 155 and the selection transistor 156 are connected in series. The cathode of the photodiode KPD is connected to the floating diffusion KFD via the transfer transistor 153. The floating diffusion KFD is connected to the power supply Vdd via the reset transistor 154. The power supply Vdd is connected to the vertical grayscale signal line VSL via the series circuit of the amplification transistor 155 and the selection transistor 156. The gate of the amplification transistor 155 is connected to the floating diffusion KFD.

[0053] The transfer signal TG is applied to the gate of the transfer transistor 153. The reset signal RST is applied to the gate of the reset transistor 154. The selection signal SEL2 is applied to the gate of the selection transistor 156. The transfer signal TG, the reset signal RST, and the selection signal SEL2 can be transmitted to the grayscale pixel KPX via the horizontal control line HSL shown in Figure 2.

[0054] When the transfer transistor 153 is turned on, the charge accumulated in the photodiode KPD is transferred to the floating diffusion KFD. Then, when the selection transistor 156 is turned on, the source potential of the amplification transistor 155 changes according to the potential of the floating diffusion KFD. The source potential of the amplification transistor 155 is then applied to the vertical grayscale signal line VSL via the selection transistor 156 and transmitted through the vertical grayscale signal line VSL. Furthermore, when the reset transistor 154 is turned on, the charge accumulated in the floating diffusion KFD is discharged.

[0055] The event pixel EPX comprises a light receiving unit 201, a logarithmic transformation unit 211, a buffer 221, a differentiator 231, and a comparator 241.

[0056] The light receiving unit 201 converts incident light into an electrical signal and transfers it to the logarithmic conversion unit 211. The light receiving unit 201 comprises a photodiode EPD and a transfer transistor 210. The photodiode EPD is connected to the logarithmic conversion unit 211 via the transfer transistor 210. A transfer signal ETG is applied to the gate of the transfer transistor 210.

[0057] The logarithmic conversion unit 211 performs logarithmic conversion on the output of the light receiving unit 201. By logarithmically converting the output of the light receiving unit 201, it becomes possible to convert the same luminance change rate into the same voltage change at any illuminance. The logarithmic conversion unit 211 is connected downstream of the light receiving unit 201. The logarithmic conversion unit 211 comprises a logarithmic transistor 212, a current-voltage conversion transistor 214, and a current source transistor 213. The logarithmic transistor 212 and the current-voltage conversion transistor 214 can be N-channel field-effect transistors, and the current source transistor 213 can be a P-channel field-effect transistor. The current source transistor 213 and the current-voltage conversion transistor 214 are connected in series with each other. The connection point between the current source transistor 213 and the current-voltage conversion transistor 214 is used as the output VO of the logarithmic conversion unit 211. The connection point between the current source transistor 213 and the current-voltage conversion transistor 214 is also connected to the gate of the logarithmic transistor 212. A bias voltage Vb1 is applied to the gate of the current source transistor 213. The gate of the current-voltage conversion transistor 214 is connected to the cathode of the photodiode EPD via the transfer transistor 210, and also to the source of the logarithmic transistor 212. The drains of the current source transistor 213 and the logarithmic transistor 212 are supplied with power supply Vdd.

[0058] Buffer 221 passes the output of the logarithmic transformer 211 to the differentiator 231. Buffer 221 is connected downstream of the logarithmic transformer 211. Buffer 221 includes N-channel field-effect transistors 222 and 223. The N-channel field-effect transistors 222 and 223 are connected in series. The connection point of the N-channel field-effect transistors 222 and 223 is used as the output of buffer 221. The gate of N-channel field-effect transistor 222 is connected to the output of the logarithmic transformer 211. A bias voltage Vb2 is applied to the gate of N-channel field-effect transistor 223. Power supply Vdd is supplied to the drain of N-channel field-effect transistor 222.

[0059] The differentiator 231 is connected downstream of the buffer 221. The differentiator 231 differentiates the output of the logarithmic transformation unit 211, which is passed through the buffer 221. The differentiator 231 can detect changes in the brightness of incident light by, for example, using the output level of the logarithmic transformation unit 211 in the past as a reference level and calculating the difference between that and the current output level of the logarithmic transformation unit 211. Here, the differentiator 231 can time-division detect events in which the brightness of incident light increases (positive events) and events in which the brightness of incident light decreases (negative events).

[0060] The differentiator 231 comprises a capacitor 232, N-channel field-effect transistors 233 and 235, a P-channel field-effect transistor 234, and a switch 236. Capacitor 232 is connected between the output of buffer 221 and the input of differentiator 231. P-channel field-effect transistors 234 and N-channel field-effect transistors 235 are connected in series with each other. The connection point between P-channel field-effect transistors 234 and N-channel field-effect transistors 235 is used as the output of differentiator 231. The connection point between P-channel field-effect transistors 234 and N-channel field-effect transistors 235 is connected to the gate of P-channel field-effect transistor 234 via N-channel field-effect transistor 233. A bias voltage Vb3 is applied to the gate of N-channel field-effect transistor 233. Switch 236 is connected to the gate of N-channel field-effect transistor 235. Power supply Vdd is supplied to the drain of P-channel field-effect transistor 234.

[0061] Switch 236 switches the reset signal AZ, the positive bias signal POS, and the negative bias signal NEG, applying them to the gate of the N-channel field-effect transistor 235. At this time, switch 236 can switch the reset signal AZ, the positive bias signal POS, and the negative bias signal NEG based on the switching signal BS. The reset signal AZ, the positive bias signal POS, and the negative bias signal NEG are input to the differentiator 231 via the horizontal control line HSL.

[0062] At this time, the differentiator 231 resets the reference level to the current output level of the logarithmic transformer 211 based on the reset signal AZ. From the moment the reference level is reset, the differentiator 231 can newly detect changes in the brightness of the incident light based on the change in the output level of the logarithmic transformer 211. At this time, after the reference level is reset based on the reset signal AZ, the positive bias signal POS and the negative bias signal NEG are applied to the gate of the N-channel field-effect transistor 235 in a time-division manner. As a result, the differentiator 231 can time-division detect changes in the direction of increasing brightness and changes in the direction of decreasing brightness of the incident light.

[0063] The comparator 241 outputs the detected value from the differentiator 231 in a time-division manner as a change in the direction of increasing brightness of the incident light and a change in the direction of decreasing brightness of the incident light. The comparator 241 is connected downstream of the differentiator 231. The comparator 241 comprises a P-channel field-effect transistor 242 and an N-channel field-effect transistor 243. The P-channel field-effect transistor 242 and the N-channel field-effect transistor 243 are connected in series with each other. The connection point between the P-channel field-effect transistor 242 and the N-channel field-effect transistor 243 is used as the output of the comparator 241. The connection point between the P-channel field-effect transistor 242 and the N-channel field-effect transistor 243 is connected to the vertical event signal line ESL. The gate of the P-channel field-effect transistor 242 is connected to the output of the differentiator 231. A bias voltage Vb4 is applied to the gate of the N-channel field-effect transistor 243.

[0064] Here, by setting the positive bias signal POS and the negative bias signal NEG to the differentiator 231 in a time-division manner, the comparator 241 can be shared for both the increase and decrease in the brightness of the incident light. Therefore, it is not necessary to provide separate comparators 241 for detecting the increase and decrease in the brightness of the incident light, and the circuit size of the comparator 241 can be reduced.

[0065] The output of the photodiode EPD is input to the logarithmic transformation unit 211. Based on the source follower operation in the logarithmic transformation unit 211, the output of the photodiode EPD is logarithmically transformed and input to the differentiator 231 via the buffer 221. In the differentiator 231, after the reset signal AZ is applied, the positive bias signal POS and the negative bias signal NEG are applied in a time-division manner to detect changes in the direction of increasing and decreasing brightness of the incident light in a time-division manner. Then, in the comparator 241, positive and negative events are detected in a time-division manner based on the output of the differentiator 231.

[0066] Figure 4 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the first embodiment, Figure 5 is a plan view showing an example layout of grayscale pixels of the upper layer chip according to the first embodiment, and Figure 6 is a cross-sectional view showing an example configuration of grayscale pixels and event pixels according to the first embodiment. Note that Figures 4 to 6 show only excerpts of the configuration of the grayscale pixels KPX and event pixels EPX.

[0067] In the figure, the solid-state imaging device 102 includes semiconductor chips P11 and P12. Semiconductor chip P12 is stacked on semiconductor chip P11. Here, the solid-state imaging device 102 can be configured as a back-illuminated image sensor. In this case, a light-receiving surface is formed on the back side of semiconductor chip P11.

[0068] The semiconductor chip P11 includes pixel regions RK1 and RE1. Pixel region RK1 contains a photodiode KPD for the grayscale pixel KPX and a transfer transistor 210. Pixel region RK1 may be divided into four sections. In this case, each pixel region RK1 contains four photodiodes KPD and transfer transistors 153. Pixel region RE1 contains a photodiode EPD for the event pixel EPX, a logarithmic transistor 212, and a current-voltage conversion transistor 214.

[0069] The semiconductor chip P11 comprises a semiconductor substrate SUB1. A pixel isolation region ISG1 is formed on the semiconductor substrate SUB1 to separate the pixel regions PK1 and RE1. The pixel isolation region ISG1 may be FDTI (Front Deep Trench Isolation) or RDTI (Rear Deep Trench Isolation). A well WL1 is formed on the semiconductor substrate SUB1 to isolate the active region AK11. The material of the semiconductor substrate SUB1 may be Si, GaAs, SiC, GaN, InGaAs, or InP. The active region AK11 can be used to form the channel regions, source / drain layers, and contacts of photodiodes KPD, EPD, logarithmic transistor 212, and current-voltage conversion transistor 214.

[0070] In the pixel region RK1, photodiodes KPD for four grayscale pixels KPX are formed on the back side of the semiconductor substrate SUB1. A gate electrode GK11 is formed on the semiconductor substrate SUB1 at a position adjacent to the photodiode KPD. The gate electrode GK11 can be used for the transfer transistor 210. A contact CK11 is formed on the gate electrode GK11. A contact CK12 is formed on the semiconductor substrate SUB1 at a position adjacent to the gate electrode GK11. The contact CK12 can be shared by the four photodiodes KPD. In this case, the four gate electrode GK11s can be arranged adjacent to each other in the row direction and column direction.

[0071] In the pixel region RE1, a photodiode EPD of the event pixel EPX is formed on the back side of the semiconductor substrate SUB1. Token gates GE11 and GE12 are formed on the semiconductor substrate SUB1 at positions that cross the active region AK11. The gate gates GE11 and GE12 may overlap with the photodiode EPD. The gate gate GE11 can be used in the logarithmic transistor 212. As shown in Figure 6, impurity diffusion layers FE11 and FE12 can be formed on both sides of the channel region below the gate gate GE11 in the active region AK1. The impurity diffusion layers FE11 and FE12 can be used as the source / drain of the logarithmic transistor 212. The impurity diffusion layer FE11 can be connected to the power supply potential Vdd. The gate gate GE12 can be used in the current-voltage conversion transistor 214. A contact CE12 is formed on each gate gate GE11 and GE12. On the active region AK11, a contact CE13 is formed at a position adjacent to each gate gate GE11 and GE12.

[0072] The semiconductor chip P12 includes a pixel region RK2. The pixel transistors for the grayscale pixel KPX are located in the pixel region RK2. Furthermore, as shown in Figure 6, wiring H22 and H23, used for connecting the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX, are formed in the pixel region RK2. The pixel region RK2 can be placed on top of the pixel regions RK1 and RE1. In this case, the pixel transistors for the grayscale pixel KPX can be positioned to overlap with the photodiode KPD of the grayscale pixel KPX and the photodiode EPD of the event pixel EPX.

[0073] The semiconductor chip P12 comprises a semiconductor substrate SUB2. A pixel isolation region ISG2 is formed on the semiconductor substrate SUB2 to isolate the pixel region PK2. A well WL2 is formed on the semiconductor substrate SUB2 to isolate the active region AK12. The material of the semiconductor substrate SUB2 may be Si, GaAs, SiC, GaN, InGaAs, or InP, etc. The active region AK12 can be used to form the channel region, source / drain layers, and contacts of the pixel transistors of the grayscale pixel KPX.

[0074] In the pixel region RK2, a gate electrode GK21 is formed on the semiconductor substrate SUB2 at a position that crosses the active region AK12. The gate electrode GK21 can be used as the pixel transistor of the grayscale pixel KPX. Here, as shown in Figure 6, impurity diffusion layers FK21 and FK22 can be formed on both sides of the channel region below the gate electrode GK21 in the active region AK2. The impurity diffusion layers FK21 and FK22 can be used as the source / drain of the pixel transistor of the grayscale pixel KPX. For example, the gate electrode GK21 can be used as the selection transistor 156. The impurity diffusion layer FK21 is connected to wiring 21 via via BA21. Also, in the pixel region RK2, contacts CK21, CK22, CE22, and CE23 are formed on the semiconductor chip P12.

[0075] Contacts CK11 and CK21 are connected to each other. In this case, contacts CK11 and CK21 can be positioned in overlapping positions. Contacts CK12 and CK22 are connected to each other. In this case, contacts CK12 and CK22 can be positioned in overlapping positions. Contacts CE12 and CE22 are connected to each other. In this case, contacts CE12 and CE22 can be positioned in overlapping positions. Contacts CE13 and CE23 are connected to each other. In this case, contacts CE13 and CE23 can be positioned in overlapping positions.

[0076] Here, as shown in Figure 6, the gate electrode GE11 is connected to wiring H22 via interlayer wiring BA12. Interlayer wiring BA12 can penetrate the semiconductor substrate SUB2. The impurity diffusion layer FE11 is connected to wiring H23 via interlayer wiring BA11. Interlayer wiring BA11 can penetrate the semiconductor substrate SUB2.

[0077] Thus, in the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P11, and the pixel transistors of the grayscale pixel KPX are arranged on the semiconductor chip P12. This allows for a relaxation of layout constraints on the semiconductor chip P12 compared to a configuration where the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P12. Furthermore, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are not arranged adjacent to the pixel transistors of the grayscale pixel KPX, and interference via inter-wiring parasitic capacitance can be suppressed even when event pixels EPX and grayscale pixels KPX are mixed on the same semiconductor chip.

[0078] <2. Second Embodiment> In the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on semiconductor chip P11, and the pixel transistor of the grayscale pixel KPX is arranged on semiconductor chip P12. In this second embodiment, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on a lower layer chip, and the wiring connecting the logarithmic transistor 212 and the current-voltage conversion transistor 214 is also arranged on the lower layer chip.

[0079] Figure 7 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the second embodiment, Figure 8 is a plan view showing an example layout of grayscale pixels of the upper layer chip according to the second embodiment, and Figure 9 is a cross-sectional view showing an example configuration of grayscale pixels and event pixels according to the second embodiment. Figures 7 to 9 show only excerpts of the configuration of the grayscale pixels KPX and event pixels EPX.

[0080] In the figure, this imaging device is equipped with semiconductor chips P21 and P22 instead of semiconductor chips P11 and P12 of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0081] The semiconductor chip P21 includes a pixel region RE12 instead of the pixel region RE1 of the first embodiment described above. The other configurations of the semiconductor chip P21 are the same as those of the semiconductor chip P11 of the first embodiment described above.

[0082] Pixel region RE12 includes an active region AK21, gate electrodes GE13, GE14, and contacts CE14 to CE16, instead of the active region AK11, gate electrodes GE11, GE12, and contacts CE12, CE13 of the first embodiment described above. In addition, pixel region RE12 has wiring HE11 to HE14 added to the pixel region RE1 of the first embodiment described above. The other configurations of this pixel region RE12 are the same as those of pixel region RE1 of the first embodiment described above.

[0083] In the pixel region RE12, a photodiode EPD of the event pixel EPX is formed on the back side of the semiconductor substrate SUB1. Token gates GE13 and GE14 are formed on the semiconductor substrate SUB1 at positions that cross the active region AK21. The gate gates GE13 and GE14 may overlap with the photodiode EPD. The gate gate GE13 can be used in the logarithmic transistor 212. Here, as shown in Figure 6, impurity diffusion layers FE13 and FE14 can be formed on both sides of the channel region below the gate gate GE13 in the active region AK21. The impurity diffusion layers FE13 and FE14 can be used as the source / drain of the logarithmic transistor 212. The gate gate GE14 can be used in the current-voltage conversion transistor 214. Wirings HE11 to HE14 are formed on the gate gates GE13 and GE14. Wiring HE11 is connected to one side of the active region AK21 where the gate gate GE14 is located. Wiring HE12 is connected to the other side of the active region AK21 where the gate gate GE14 is located and to the gate gate GE13. Wiring HE13 connects to one side of the active region AK21 where the gate electrode GE13 is located, and to the gate electrode GE13. Wiring HE14 connects to the other side of the active region AK21 where the gate electrode GE13 is located, and to the gate electrode GE14. Contact CE14 is formed on wiring HE11. Contact CE15 is formed on wiring HE12. Contact CE16 is formed on wiring HE13.

[0084] The semiconductor chip P22 includes a pixel region RK22 in place of the pixel region RK2 of the first embodiment described above. The other configurations of the semiconductor chip P22 are the same as those of the semiconductor chip P12 of the first embodiment described above.

[0085] Pixel region RK22 includes contacts CE24 to CE26 instead of contacts CE12 and CE13 of the first embodiment described above. The other configurations of this pixel region RK22 are the same as those of pixel region RK2 of the first embodiment described above.

[0086] In pixel region RK22, contacts CE14 and CE24 are connected to each other. In this case, contacts CE14 and CE24 can be positioned in overlapping locations. Contacts CE15 and CE25 are connected to each other. In this case, contacts CE15 and CE25 can be positioned in overlapping locations. Contacts CE16 and CE26 are connected to each other. In this case, contacts CE16 and CE26 can be positioned in overlapping locations.

[0087] Here, as shown in Figure 6, the gate electrode GE13 is connected to wiring HE12 via via BA13. Wiring HE12 is connected to wiring H23 via interlayer wiring BA14. Interlayer wiring BA14 can penetrate the semiconductor substrate SUB2.

[0088] Thus, in the second embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P21, and the wiring HE11 to HE14 connecting the logarithmic transistor 212 and the current-voltage conversion transistor 214 are also arranged on the semiconductor chip P21. This makes it possible to alleviate the constraints on the arrangement of contacts CE14 to CE16 connected to the logarithmic transistor 212 and the current-voltage conversion transistor 214, and to relax the constraints on the layout of the semiconductor chip P22.

[0089] <3. Third Embodiment> In the second embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on the semiconductor chip P21, and the wiring HE11 to HE14 connecting the logarithmic transistor 212 and the current-voltage conversion transistor 214 is also placed on the semiconductor chip P21. In this third embodiment, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on a lower layer chip, and the input terminal of the event pixel EPX is also placed on a lower layer chip.

[0090] Figure 10 is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the third embodiment. The layout of the grayscale pixels KPX and event pixels EPX in the third embodiment is the same as the layout of the grayscale pixels KPX and event pixels EPX in the second embodiment described above. In addition, Figure 10 shows an excerpt of the configuration of the grayscale pixels KPX and event pixels EPX.

[0091] In the figure, a gate electrode GE14 is formed on semiconductor substrate SUB1 at a position that crosses the active region AK21. On semiconductor substrate SUB2, impurity diffusion layers FE15 and FE16 can be formed on both sides of the channel region below the gate electrode GE14 in the active region AK21. The impurity diffusion layers FE15 and FE16 can be used as the source / drain of the current-voltage conversion transistor 214. The gate electrode GE14 can be connected to the impurity diffusion layer FE14 sequentially via via BA14, wiring HE13, and via BA15. The input terminal of the event pixel EPX can be connected to wiring HE13.

[0092] On the semiconductor substrate SUB2, a gate electrode GK22 is formed at a position that crosses the active region AK12. On the active region AK12 of the semiconductor chip P22, impurity diffusion layers FK23 and FK24 can be formed on both sides below the channel region of the gate electrode GK22. The impurity diffusion layers FK23 and FK24 can be used as the source / drain of the pixel transistor of the grayscale pixel KPX. The gate electrode GK22 is connected to wiring H24 via via BA22. For example, the gate electrode GK22 can be used for the reset transistor 154. Wiring H21 can be used for the vertical grayscale signal line VSL. Wiring H24 can be used for the horizontal control line HSL.

[0093] Thus, in the third embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P21, and the input terminal of the event pixel EPX is provided on the wiring HE13 of the semiconductor chip P21. This allows the input terminal of the event pixel EPX to be placed on a different layer from the vertical grayscale signal line VSL and horizontal control line HSL while easing the layout constraints of the semiconductor chip P22, and makes it possible to suppress interference to the input terminal of the event pixel EPX while mixing the event pixel EPX and grayscale pixel KPX.

[0094] <4. Fourth Embodiment> In the second embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are placed on the semiconductor chip P21, and the wiring HE11 to HE14 connecting the logarithmic transistor 212 and the current-voltage conversion transistor 214 is also placed on the semiconductor chip P21. In this fourth embodiment, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are placed in a non-adjacent pixel region of the lower layer chip.

[0095] Figure 11 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the fourth embodiment, and Figure 12 is a plan view showing an example layout of grayscale pixels of the upper layer chip according to the fourth embodiment. In Figures 11 and 12, only a portion of the configuration of the grayscale pixels KPX and event pixels EPX is shown.

[0096] In the figure, this imaging device is equipped with semiconductor chips P41 and P42 instead of semiconductor chips P11 and P12 of the first embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the first embodiment described above.

[0097] The semiconductor chip P41 includes pixel regions RE31 and RE32 in place of the pixel region RE1 of the first embodiment described above. The other configurations of the semiconductor chip P41 are the same as those of the semiconductor chip P11 of the first embodiment described above.

[0098] Pixel regions RE31 and RE32 are arranged so as not to be adjacent. In this case, pixel region RK1 can be placed adjacent to each pixel region RE31 and RE32 in the row and column directions.

[0099] In the pixel region RE31, a photodiode EPD of the event pixel EPX is formed on the back side of the semiconductor substrate SUB1. A gate electrode GE15 is formed on the semiconductor substrate SUB1 at a position that crosses the active region AK31. The gate electrode GE15 may be positioned overlapping with the photodiode EPD. The gate electrode GE15 can be used as a logarithmic transistor 212.

[0100] In the pixel region RE41, a photodiode EPD of the event pixel EPX is formed on the back side of the semiconductor substrate SUB1. A gate electrode GE16 is formed on the semiconductor substrate SUB1 at a position that crosses the active region AK41. The gate electrode GE16 may be positioned overlapping with the photodiode EPD. The gate electrode GE16 can be used in the current-voltage conversion transistor 214.

[0101] On the gate electrode GE15, wirings HE15 and HE16 are formed, spanning the pixel regions RE31 and RE41. Wiring HE15 is connected to one side of the active region AK41 where the gate electrode GE16 is located and to the gate electrode GE15. Wiring HE16 is connected to one side of the active region AK31 where the gate electrode GE15 is located and to the gate electrode GE16. Wiring HE17 is also formed in the pixel region RE31. Wiring HE17 is connected to the other side of the active region AK31 where the gate electrode GE15 is located. Wiring HE18 is also formed in the pixel region RE41. Wiring HE18 is connected to the other side of the active region AK41 where the gate electrode GE165 is located. Contact CE19 is formed on wiring HE15. Contact CE17 is formed on wiring HE17. Contact CE18 is formed on wiring HE18.

[0102] The semiconductor chip P42 includes pixel regions RE32 and RE42 in place of pixel region RE1 of the first embodiment described above. The other configurations of the semiconductor chip P42 are the same as those of the semiconductor chip P12 of the first embodiment described above.

[0103] Pixel region RK32 includes contacts CE27 and CE29 in place of the two upper contacts CE21 of the first embodiment described above. The other configurations of this pixel region RK32 are the same as those of pixel region RK2 of the first embodiment described above.

[0104] In pixel region RK32, contacts CE17 and CE27 are connected to each other. In this configuration, contacts CE17 and CE27 can be positioned in overlapping locations. Contacts CE19 and CE29 are also connected to each other. In this configuration, contacts CE19 and CE29 can be positioned in overlapping locations.

[0105] Pixel region RK42 includes contact CE28 in place of the two lower contacts CE21 of the first embodiment described above. The other configurations of this pixel region RK42 are the same as those of pixel region RK2 of the first embodiment described above.

[0106] In the pixel region RK42, contacts CE18 and CE28 are connected to each other. In this case, contacts CE18 and CE28 can be positioned so that they overlap each other.

[0107] Thus, in the fourth embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged in non-adjacent pixel regions RE31 and RE41 of the semiconductor chip P41. This allows the logarithmic transistor 212 and the current-voltage conversion transistor 214 to be placed at separate locations while easing the layout constraints of the semiconductor chip P42, thereby improving the degree of freedom in the arrangement of the event pixel EPX.

[0108] <5. Fifth Embodiment> In the first embodiment described above, the logarithmic transistor and current-voltage conversion transistor of the event pixel EPX are placed on the lower layer chip, and the pixel transistor of the grayscale pixel KPX is also placed on the lower layer chip. In this fifth embodiment, the logarithmic conversion section of the event pixel EPX is composed of transistors.

[0109] Figure 13 is a circuit diagram showing an example of the configuration of the logarithmic transformation unit according to the fifth embodiment.

[0110] In the figure, this logarithmic conversion unit includes a logarithmic transistor 212. The source of the logarithmic transistor 212 is connected to the cathode of the photodiode EPD. In this case, the current-voltage conversion transistor 214 of the first embodiment described above is removed. The connection point between the source of the logarithmic transistor 212 and the cathode of the photodiode EPD is used as the output VO of the logarithmic conversion unit. Power supply Vdd is supplied to the gate and drain of the logarithmic transistor 212.

[0111] Figure 14 is a circuit diagram showing another example of the configuration of the logarithmic transformation unit according to the fifth embodiment.

[0112] In the figure, in this logarithmic conversion unit, the source of the logarithmic transistor 212 is connected to the cathode of the photodiode EPD. At this time, the transfer transistor 210 of the first embodiment described above is removed. The logarithmic transistor 212 generates an optical voltage by logarithmically converting the optical current output from the photodiode IPD. The current-voltage conversion transistor 214 converts the optical current into an output voltage based on the optical voltage generated by the logarithmic transistor 212. The other configurations of this logarithmic conversion unit are the same as those of the logarithmic conversion unit of the first embodiment described above.

[0113] Figure 15 is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment.

[0114] In the same figure, this logarithmic conversion unit includes logarithmic transistors 212A, 212B and current-voltage conversion transistors 214A, 214B, instead of the logarithmic transistor 212 and current-voltage conversion transistor 214 in Figure 14. The other configurations of this logarithmic conversion unit are the same as those of the logarithmic conversion unit in Figure 14.

[0115] Logarithmic transistors 212A and 212B are connected in series with each other. Current-voltage conversion transistors 214A and 214B are connected in series with each other. The series circuit of current-voltage conversion transistors 214A and 214B is connected in series with current source transistor 213. The source of logarithmic transistor 212A and the gate of current-voltage conversion transistor 214A are connected to the cathode of photodiode EPD. The connection point of logarithmic transistors 212A and 212B is connected to the gate of current-voltage conversion transistor 214B. The connection point of current-voltage conversion transistors 214A and 214B is connected to the gate of logarithmic transistor 212A. The connection point of current-voltage conversion transistor 214B and current source transistor 213 is connected to the gate of logarithmic transistor 212B. The connection point of current-voltage conversion transistor 214B and current source transistor 213 is used as the output VO of the logarithmic conversion section. Power supply Vdd is supplied to the drain of logarithmic transistor 212B.

[0116] Figure 16 is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment.

[0117] In the same figure, this logarithmic conversion unit includes logarithmic transistors 212A to 212C and current-voltage conversion transistors 214A to 214C, instead of the logarithmic transistor 212 and current-voltage conversion transistor 214 in Figure 14. The other configurations of this logarithmic conversion unit are the same as those of the logarithmic conversion unit in Figure 14.

[0118] Logarithmic transistors 212A to 212C are connected in series with each other. Current-voltage conversion transistors 214A to 214C are connected in series with each other. The series circuit of current-voltage conversion transistors 214A to 214C is connected in series with current source transistor 213. The source of logarithmic transistor 212A and the gate of current-voltage conversion transistor 214A are connected to the cathode of photodiode EPD. The connection point of logarithmic transistors 212A and 212B is connected to the gate of current-voltage conversion transistor 214B. The connection point of current-voltage conversion transistors 214A and 214B is connected to the gate of logarithmic transistor 212A. The connection point of logarithmic transistors 212A and 212B is connected to the gate of current-voltage conversion transistor 214B. The connection point of current-voltage conversion transistors 214B and 214C is connected to the gate of logarithmic transistor 212B. The connection point of current-voltage conversion transistor 214C and current source transistor 213 is connected to the gate of logarithmic transistor 212C. The connection point between the current-voltage conversion transistor 214C and the current source transistor 213 is used as the output VO of the logarithmic conversion section. Power supply Vdd is supplied to the drain of the logarithmic transistor 212C.

[0119] Figure 17 is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment.

[0120] In the same figure, this logarithmic conversion unit includes logarithmic transistors 212A and 212B instead of the logarithmic transistor 212 in Figure 14. The other configurations of this logarithmic conversion unit are the same as those of the logarithmic conversion unit in Figure 14.

[0121] Logarithmic transistors 212A and 212B are connected in series with each other. The source of logarithmic transistor 212A and the gate of current-voltage conversion transistor 214 are connected to the cathode of photodiode EPD. The gate of logarithmic transistor 212A is connected to the drain of logarithmic transistor 212A. Power supply Vdd is supplied to the drain of logarithmic transistor 212B.

[0122] Figure 18 is a circuit diagram showing yet another configuration example of the logarithmic transformation unit according to the fifth embodiment.

[0123] In the same figure, this logarithmic conversion unit includes logarithmic transistors 212A to 212C instead of the logarithmic transistor 212 in Figure 14. The other configurations of this logarithmic conversion unit are the same as those of the logarithmic conversion unit in Figure 14.

[0124] Logarithmic transistors 212A through 212C are connected in series with each other. The source of logarithmic transistor 212A and the gate of current-voltage conversion transistor 214A are connected to the cathode of photodiode EPD. The gate of logarithmic transistor 212A is connected to the drain of logarithmic transistor 212A. The gate of logarithmic transistor 212B is connected to the drain of logarithmic transistor 212B. Power supply Vdd is supplied to the drain of logarithmic transistor 212C.

[0125] Thus, in the fifth embodiment described above, the logarithmic conversion section of the event pixel EPX is configured with transistors. This makes it possible to improve the driving force of the logarithmic conversion section or to simplify the configuration of the logarithmic conversion section depending on the event detection application.

[0126] <6. Sixth Embodiment> In the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on semiconductor chip P11, and the pixel transistor of the grayscale pixel KPX is placed on semiconductor chip P12. In this sixth embodiment, the current-voltage conversion transistor 214 of the event pixel EPX is placed on the lower layer chip, and the logarithmic transistor 212 is placed on the upper layer chip.

[0127] Figure 19 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the sixth embodiment, and Figure 20 is a cross-sectional view showing an example configuration of event pixels according to the sixth embodiment. Figures 19 and 20 show only excerpts of the configuration of grayscale pixels KPX and event pixels EPX. Figure 19 also shows an example in which 4-pixel shared cells are arranged in 2 rows and 4 columns. In this case, Figure 19 shows an example in which grayscale pixels KPX are assigned to 2 rows and 3 columns of the 4-pixel shared cells in the 2 rows and 4 columns, and event pixels EPX are assigned to 2 rows and 1 column of the 4-pixel shared cells.

[0128] In the figure, this solid-state imaging device comprises semiconductor chips P61 and P62. Semiconductor chip P62 is stacked on semiconductor chip P61. Here, this solid-state imaging device can be configured as a back-illuminated image sensor. In this case, a light-receiving surface is formed on the back side of semiconductor chip P61.

[0129] The semiconductor chip P61 includes pixel regions KCL and ECL. The pixel region KCL contains the photodiode KPD for the grayscale pixel KPX, the floating diffusion KFD, and the transfer transistor 153. The pixel region KCL may be divided into four sections. In this case, the pixel region KCL contains four photodiodes KPD and transfer transistors 153.

[0130] The pixel region ECL contains the photodiode EPD of the event pixel EPX, the floating diffusion EFD, and the transfer transistor 210. The pixel region ECL may be divided into four sections. In this case, the pixel region ECL contains photodiode EPDs and transfer transistors 210 for four pixels. A current-voltage conversion transistor 214 is placed between the pixel region ECLs.

[0131] The semiconductor chip P61 comprises a semiconductor substrate SUB1. An element isolation region ISA is formed on the semiconductor substrate SUB1 to isolate the active region AK61. The element isolation region ISA1 may also be an STI (Shallow Trench Isolation). The active region AK61 can be used to form the channel regions, source / drain layers, and contacts of photodiodes KPD, EPD, current-voltage conversion transistors 214, and pixel transistors.

[0132] In the pixel region KCL, photodiodes KPD for four grayscale pixels KPX are formed on the back side of the semiconductor substrate SUB1. A gate electrode GK61 is formed on the semiconductor substrate SUB1 at a position adjacent to the photodiode EPD. The gate electrode GK61 can be used for the transfer transistor 153. A floating diffusion KFD is formed on the semiconductor substrate SUB1 at a position over which the gate electrode GK61 is located. The floating diffusion KFD can be shared by the four photodiodes KPD. In this case, the four gate electrode GK61s can be arranged adjacent to each other in the row direction and column direction.

[0133] In the pixel region ECL, four event pixel EPX photodiodes (EPDs) are formed on the back side of the semiconductor substrate SUB1. A gate electrode GE60 is formed on the semiconductor substrate SUB1 at a position adjacent to the photodiode EPDs. The gate electrode GE60 can be used for the transfer transistor 210. A floating diffusion EFD is formed on the semiconductor substrate SUB1 at a position over which the gate electrode GE60 is located. The floating diffusion EFD can be shared by the four photodiode EPDs. In this case, the four gate electrode GE60s can be arranged adjacent to each other in the row and column directions.

[0134] The layout patterns of each pixel region KCL and ECL can be made equal to each other. For example, the layout patterns of the photodiode KPD, gate electrode GK61, and floating diffusion KFD in pixel region KCL can be made equal to the layout patterns of the photodiode EPD, gate electrode GE60, and floating diffusion EFD in pixel region ECL. This eliminates the difference between the storage capacity of a grayscale pixel KPX adjacent to an event pixel EPX and the storage capacity of a grayscale pixel KPX not adjacent to an event pixel EPX.

[0135] Between the pixel regions ECL, a gate electrode GE62 is formed on the semiconductor substrate SUB1 at a position that crosses the active region AK61. The gate electrode GE62 can be used in the current-voltage conversion transistor 214. Here, as shown in Figure 20, impurity diffusion layers FE17 and FE18 can be formed on both sides of the channel region below the gate electrode GE62 in the active region AK61. The impurity diffusion layers FE17 and FE18 can be used as the source / drain of the current-voltage conversion transistor 214. As shown in Figure 18, a floating diffusion EFD is connected via wiring H61 to one side of the active region AK61 where the gate electrode GE62 is located. A contact CE62 is formed on the gate electrode GE62. A contact CE61 is formed on the active region AK61 at a position adjacent to the gate electrode GE62.

[0136] As shown in Figure 20, an insulating layer ZE1 is formed on the semiconductor substrate SUB1 so as to cover the gate electrodes GE60 and GE62. Vias BA16 to BA18 are embedded in the insulating layer ZE1. Via BA16 is connected to the floating diffusion layer EFD. Via BA17 is connected to the gate electrode GE62. Via BA18 is connected to the impurity diffusion layer FE18.

[0137] The semiconductor chip P62 contains the pixel transistors for the grayscale pixels KPX. Additionally, the semiconductor chip P62 contains logarithmic transistors 212. These logarithmic transistors 212 can be superimposed on the photodiode EPD.

[0138] The semiconductor chip P62 includes a semiconductor layer SBL. The semiconductor layer SBL can be placed on an insulating layer ZE1. The material of the semiconductor layer SBL may be Si, GaAs, SiC, GaN, InGaAs, or InP, etc.

[0139] A gate electrode GE61 is formed on the semiconductor layer SBL at a position that crosses the semiconductor layer SBL. The gate electrode GE61 can be used in the logarithmic transistor 212. Impurity diffusion layers FE21 and FE22 are formed on both sides of the channel region below the gate electrode GK61. The impurity diffusion layers FE21 and FE22 can be used as the source / drain of the logarithmic transistor 212. In this case, the logarithmic transistor 212 may be configured as a thin-film transistor. The impurity diffusion layer FE21 is connected to the floating diffusion EFD via via BA16. The impurity diffusion layer FE21 is also connected to the gate electrode GE62 via via BA17.

[0140] An insulating layer ZE2 is formed on the semiconductor layer SBL so as to cover the gate electrode GE61. Vias BA23, BA24 and wiring H62 are embedded in the insulating layer ZE2. Wiring H62 is connected to the gate electrode GE61 via via BA24. Wiring H62 is also connected to the impurity diffusion layer FE18 via vias BA23 and BA18.

[0141] Thus, in the sixth embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P61, and the logarithmic transistor 212 is placed on semiconductor chip P62. This makes it possible to shorten the gate wiring of the logarithmic transistor 212 and the gate wiring of the current-voltage conversion transistor 214 of the event pixel EPX. As a result, the inter-gate capacitance of the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX can be reduced, and the latency characteristics can be improved.

[0142] <7. Seventh Embodiment> In the sixth embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P61, and the logarithmic transistor 212 is placed on semiconductor chip P62. In this seventh embodiment, the logarithmic transistor 212 of the event pixel EPX is placed on the lower layer chip, and the current-voltage conversion transistor 214 is placed on the upper layer chip.

[0143] Figure 21 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the seventh embodiment, and Figure 22 is a cross-sectional view showing an example configuration of event pixels according to the seventh embodiment.

[0144] In the figure, this imaging device is equipped with semiconductor chips P71 and P72 instead of semiconductor chips P61 and P62 in the sixth embodiment described above. The other configurations of this imaging device are the same as those of the imaging device in the sixth embodiment described above.

[0145] In semiconductor chip P71, between the pixel regions ECL, an active region AK71 and a gate electrode GE71 are provided instead of the active region AK61 and gate electrode GE61 of the sixth embodiment described above. The other configurations of semiconductor chip P71 are the same as those of semiconductor chip P61 of the sixth embodiment described above.

[0146] Between the pixel regions ECL, a gate electrode GE71 is formed on the semiconductor substrate SUB1 at a position that crosses the active region AK71. The gate electrode GE71 can be used for the logarithmic transistor 212. Here, as shown in Figure 22, a floating diffusion EFD and an impurity diffusion layer FE19 can be formed on both sides of the channel region below the gate electrode GE71 in the active region AK71. As shown in Figure 21, the floating diffusion EFD is connected via wiring H71 to one side of the active region AK71 where the gate electrode GE71 is located. A contact CE72 is formed on the gate electrode GE71. A contact CE72 is formed on the active region AK71 at a position adjacent to the gate electrode GE71.

[0147] As shown in Figure 22, an insulating layer ZE1 is formed on the semiconductor substrate SUB1 so as to cover the gate electrodes GE60 and GE71. Vias BA19 and BA110 are embedded in the insulating layer ZE1. Via BA19 is connected to the floating diffusion EFD. Via BA110 is connected to the gate electrode GE71.

[0148] The semiconductor chip P72 contains the pixel transistors for the grayscale pixels KPX. The semiconductor chip P72 also contains a current-voltage conversion transistor 214. The current-voltage conversion transistor 214 can be superimposed on the photodiode EPD.

[0149] The semiconductor chip P72 includes a semiconductor layer SBL. A gate electrode GE72 is formed on the semiconductor layer SBL at a position that crosses the semiconductor layer SBL. The gate electrode GE72 can be used in a current-voltage conversion transistor 214. Impurity diffusion layers FE23 and FE24 are formed on both sides of the channel region below the gate electrode GE72. The impurity diffusion layers FE23 and FE24 can be used as the source / drain of the current-voltage conversion transistor 214. In this case, the current-voltage conversion transistor 214 may be configured as a thin-film transistor. The impurity diffusion layer FE23 is connected to the gate electrode GE71 via a via BA110.

[0150] An insulating layer ZE2 is formed on the semiconductor layer SBL so as to cover the gate electrode GE72. Vias BA25, BA26 and wiring H72 are embedded in the insulating layer ZE2. Wiring H72 is connected to the gate electrode GE72 via via BA26. Wiring H72 is also connected to the floating diffusion EFD via vias BA25 and BA19.

[0151] Thus, in the seventh embodiment described above, the logarithmic transistor 212 of the event pixel EPX is placed on semiconductor chip P71, and the current-voltage conversion transistor 214 is placed on semiconductor chip P72. This allows for the miniaturization of the event pixel EPX while shortening the gate wiring of the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX. As a result, the inter-gate capacitance of the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX can be reduced, improving latency characteristics and enabling miniaturization of the imaging device.

[0152] <8. Eighth Embodiment> In the seventh embodiment described above, the logarithmic transistor 212 of the event pixel EPX is placed on semiconductor chip P71, and the current-voltage conversion transistor 214 is placed on semiconductor chip P72. In this eighth embodiment, the series circuit of logarithmic transistors is placed on the lower chip, and the current-voltage conversion transistor is placed on the upper chip.

[0153] Figure 23 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the eighth embodiment, and Figure 24 is a cross-sectional view showing an example configuration of event pixels according to the eighth embodiment.

[0154] In the figure, this imaging device is equipped with semiconductor chips P81 and P82 instead of semiconductor chips P71 and P72 in the seventh embodiment described above. The other configurations of this imaging device are the same as those of the imaging device in the seventh embodiment described above.

[0155] In semiconductor chip P81, between the pixel regions ECL, active region AK81 and gate electrodes GE81A and GE81B are provided instead of the active region AK71 and gate electrode GE71 of the seventh embodiment described above. The other configurations of semiconductor chip P81 are the same as those of semiconductor chip P71 of the seventh embodiment described above.

[0156] Between the pixel regions ECL, gate electrodes GE81A and GE81B are formed on the semiconductor substrate SUB1 at positions that cross the active region AK81. The gate electrodes GE81A and GE81B can be arranged side by side at positions that cross the active region AK81. The gate electrodes GE81A and GE81BG can be used in the logarithmic transistor 212. Here, as shown in Figure 24, a floating diffusion EFD and an impurity diffusion layer FE110 can be formed on both sides of the channel region below the gate electrode GE81A in the active region AK81. Also, impurity diffusion layers FE110 and FE111 can be formed on both sides of the channel region below the gate electrode GE81B in the active region AK81. Furthermore, an impurity diffusion layer FE112 can be formed adjacent to the impurity diffusion layer FE111 in the active region AK81. As shown in Figure 23, the floating diffusion EFD is connected via wiring H81 to one side of the active region AK81 where the gate electrode GE81A is located. A contact CE83 is formed on the gate electrode GE81B. On the active region AK81, contacts CE81 and CE82 are formed on both sides of the gate electrode GE81A.

[0157] As shown in Figure 24, an insulating layer ZE1 is formed on the semiconductor substrate SUB1 so as to cover the gate electrodes GE60, GE81A, and GE81B. Vias BA19, BA110 to BA113 are embedded in the insulating layer ZE1. Via BA110 is connected to the gate electrode GE81A. Via BA111 is connected to the impurity diffusion layer FE110. Via BA112 is connected to the gate electrode GE81B. Via BA113 is connected to the impurity diffusion layer FE112.

[0158] The semiconductor chip P82 contains the pixel transistors for the grayscale pixels KPX. The semiconductor chip P82 also contains a current-voltage conversion transistor 214. The current-voltage conversion transistor 214 can be superimposed on the photodiode EPD.

[0159] The semiconductor chip P82 includes a semiconductor layer SBL. A gate electrode GE72 is formed on the semiconductor layer SBL at a position that crosses the semiconductor layer SBL. Impurity diffusion layers FE23 and FE24 are formed on both sides of the channel region below the gate electrode GE72. Impurity diffusion layer FE23 is connected to gate electrode GE81B via via BA112. Impurity diffusion layer FE24 is connected to impurity diffusion layer FE112 via via BA113.

[0160] An insulating layer ZE2 is formed on the semiconductor layer SBL so as to cover the gate electrode GE72. Vias BA23, BA25, BA26 and wiring H82 are embedded in the insulating layer ZE2. Wiring H82 is connected to the gate electrode GE72 via via BA26. Wiring H82 is also connected to the floating diffusion layer EFD via vias BA25 and BA19. Wiring H82 is also connected to the impurity diffusion layer FE110 via vias BA23 and BA111.

[0161] Thus, in the eighth embodiment described above, the series circuit of the logarithmic transistor 212 of the event pixel EPX is arranged on semiconductor chip P81, and the current-voltage conversion transistor 214 is arranged on semiconductor chip P82. This makes it possible to improve the driving force of the logarithmic transistor 212 while reducing the inter-gate capacitance of the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX, thereby improving latency characteristics.

[0162] <9. The ninth embodiment> In the sixth embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P61, and the logarithmic transistor 212 is placed on semiconductor chip P62. In this ninth embodiment, the current-voltage conversion transistor is placed on the lower layer chip, and the series circuit of the logarithmic transistor is placed on the upper layer chip.

[0163] Figure 25 is a cross-sectional view showing an example of the configuration of an event pixel according to the ninth embodiment. The layout of the event pixel EPX in the ninth embodiment is the same as the layout of the event pixel EPX in the sixth embodiment described above.

[0164] In the figure, this imaging device is equipped with a semiconductor chip P92 instead of the semiconductor chip P62 of the sixth embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the sixth embodiment described above.

[0165] The semiconductor chip P92 contains the pixel transistors for the grayscale pixels KPX. Additionally, the semiconductor chip P92 contains a series circuit of logarithmic transistors 212. This series circuit of logarithmic transistors 212 can be superimposed on the photodiode EPD.

[0166] The semiconductor chip P92 includes a semiconductor layer SBL. Grid gates GE91A and GE91B are formed on the semiconductor layer SBL, at positions that cross the SBL. Impurity diffusion layers FE21 and FE23 are formed on both sides of the channel region beneath grid gate GE91A. Impurity diffusion layers FE22 and FE23 are formed on both sides of the channel region beneath grid gate GE91B. Impurity diffusion layer FE21 is connected to the floating diffusion EFD via via BA16. Furthermore, impurity diffusion layer FE21 is connected to grid gate GE62 via via BA17.

[0167] An insulating layer ZE2 is formed on the semiconductor layer SBL so as to cover the gate electrodes GE91A and BGE91B. Vias BA23 to BA26 and wirings H92 and H993 are embedded in the insulating layer ZE2. Wiring H92 is connected to the gate electrode GE91B via via BA24. Wiring H92 is also connected to the impurity diffusion layer FE18 via vias BA23 and BA18. Wiring H93 is connected to the gate electrode GE91A via via BA25. Wiring H93 is also connected to the impurity diffusion layer FE23 via via BA26.

[0168] Thus, in the ninth embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P81, and the series circuit of the logarithmic transistor 212 is placed on semiconductor chip P82. This makes it possible to improve the driving force of the logarithmic transistor 212 while reducing the inter-gate capacitance of the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX, thereby improving latency characteristics.

[0169] <10. Tenth Embodiment> In the seventh embodiment described above, the logarithmic transistor 212 of the event pixel EPX is placed on the semiconductor chip P71. In this tenth embodiment, the logarithmic transistor 212 of the event pixel EPX and the amplification transistor 155 of the grayscale pixel KPX are placed on the lower layer chip, and the logarithmic transistor 212 of the event pixel EPX and the selection transistor 156 of the grayscale pixel KPX are placed on the upper layer chip.

[0170] Figure 26 is a plan view showing an example layout of grayscale pixels and event pixels of the lower layer chip according to the 10th embodiment, and Figure 27 is a cross-sectional view showing an example configuration of event pixels according to the 10th embodiment.

[0171] In the figure, this imaging device is equipped with semiconductor chips P101 and P102 instead of semiconductor chips P61 and P62 in the sixth embodiment described above. The other configurations of this imaging device are the same as those of the imaging device in the sixth embodiment described above.

[0172] A gate electrode GK62 is positioned between the pixel regions KCL of the semiconductor chip P101. The other configurations of this semiconductor chip P101 are the same as those of the semiconductor chip P61 in the sixth embodiment described above.

[0173] Between the pixel regions KCL of the semiconductor chip P101, a gate electrode GK62 is formed on the semiconductor substrate SUB1 at a position that crosses the active region AK71. The gate electrode GK62 can be used in the amplification transistor 155. Here, as shown in Figure 27, impurity diffusion layers FE112 and FE113 can be formed on both sides of the channel region below the gate electrode GK62 in the active region AK71. In addition, a floating diffusion KFD can be formed adjacent to the impurity diffusion layer FE112 in the active region AK71.

[0174] An insulating layer ZE1 is formed on the semiconductor substrate SUB1 so as to cover the gate electrodes GE60, GE71, and GK62. Vias BA19, BA110, and BA114 through BA116 are embedded in the insulating layer ZE1. Via BA114 is connected to the floating diffusion KFD. Via BA115 is connected to the gate electrode GK62. Via BA116 is connected to the impurity diffusion layer FE113.

[0175] The semiconductor chip P102 contains a selection transistor 156 for the grayscale pixel KPX. The semiconductor chip P72 contains a current-voltage conversion transistor 214. The current-voltage conversion transistor 214 can be superimposed on the photodiode EPD. The selection transistor 156 can also be superimposed on the photodiode KPD.

[0176] The semiconductor chip P102 includes a semiconductor layer SBL. A gate electrode GK63 is formed on the semiconductor layer SBL at a position that crosses the semiconductor layer SBL. The gate electrode GK63 can be used in the amplification transistor 155. Impurity diffusion layers FE25 and FE26 are formed on both sides of the channel region below the gate electrode GK63. An impurity diffusion layer FE27 is also formed adjacent to the impurity diffusion layer FE25. The impurity diffusion layers FE25 and FE26 can be used as the source / drain of the selection transistor 156. In this case, the selection transistor 156 may be configured as a thin-film transistor. The impurity diffusion layer FE25 is connected to the impurity diffusion layer FE113 via a via BA116.

[0177] An insulating layer ZE2 is formed on the semiconductor layer SBL so as to cover the gate electrodes GE72 and GK63. The impurity diffusion layer FE27 is connected to the floating diffusion KFD via via BA114. The impurity diffusion layer FE27 is also connected to the gate electrode GK62 via via BA115. The rest of the configuration of the semiconductor chip P102 is the same as that of the semiconductor chip P62 in the sixth embodiment described above.

[0178] As described above, in the tenth embodiment, the logarithmic transistor 212 of the event pixel EPX and the amplification transistor 155 of the grayscale pixel KPX are arranged on semiconductor chip P101, and the logarithmic transistor 212 of the event pixel EPX and the selection transistor 156 of the grayscale pixel KPX are arranged on semiconductor chip P102. This makes it possible to shorten the gate wiring of the logarithmic transistor 212 of the event pixel EPX and the gate wiring of the current-voltage conversion transistor 214 while increasing the area of ​​the amplification transistor 155. As a result, the inter-gate capacitance of the logarithmic transistor 212 of the event pixel EPX and the current-voltage conversion transistor 214 can be reduced, improving latency characteristics and increasing the driving force of the amplification transistor 155.

[0179] <11. Eleventh Embodiment> In the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on the lower layer chip, and the pixel transistor of the grayscale pixel KPX is also placed on the lower layer chip. In this eleventh embodiment, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on an intermediate chip, and the interlayer wiring extending from the lower layer chip is connected to the lower side of the source of the logarithmic transistor 212.

[0180] Figure 28 is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the 11th embodiment. Note that Figure 28 shows only a portion of the configuration of the grayscale pixels KPX and event pixels EPX.

[0181] In the figure, this solid-state imaging device comprises semiconductor chips P111 to P113. Semiconductor chip P112 is stacked on semiconductor chip P111. Semiconductor chip P113 is stacked on semiconductor chip P112. At this time, semiconductor chip P112 is positioned between semiconductor chips P111 and P113. Here, this solid-state imaging device can be configured as a back-illuminated image sensor. At this time, a light-receiving surface is formed on the back side of semiconductor chip P111.

[0182] The semiconductor chip P111 comprises a P-type semiconductor substrate 1110. A planarization film 1113 is formed on the back side of the P-type semiconductor substrate 1110. Pixel isolation regions 1111 are formed on the P-type semiconductor substrate 1110 and the planarization film 1113 to separate pixels. The pixel isolation regions 1111 can penetrate the P-type semiconductor substrate 1110 and the planarization film 1113. On each pixel, an on-chip lens 1114 is formed on the pixel isolation regions 1111 and the planarization film 1113. An N-type impurity diffusion layer 1112 is formed on each pixel of the P-type semiconductor substrate 1110. The N-type impurity diffusion layer 1112 can be used in a photodiode KPD.

[0183] Furthermore, in the P-type semiconductor substrate 1110, an N-type impurity diffusion layer 1115 is formed on the N-type impurity diffusion layer 1112. A gate electrode 1117 is formed on the P-type semiconductor substrate 1110. The gate electrode 1117 may penetrate the N-type impurity diffusion layer 1115 and enter the N-type impurity diffusion layer 1112. In this case, the gate electrode 1117 can constitute an embedded transfer gate. A contact layer 1116 is formed on the N-type impurity diffusion layer 1115 adjacent to the gate electrode 1117. The gate electrode 1117 can be used as a pixel transistor for the grayscale pixel KPX. An interlayer insulating layer 1118 is formed on the P-type semiconductor substrate 1110 and the pixel isolation region 1111 at a position covering the gate electrode 1117.

[0184] The semiconductor chip P112 comprises a semiconductor substrate 1120. A hydrogen diffusion prevention film 1126 is formed on the back side of the semiconductor substrate 1120. The hydrogen diffusion prevention film 1126 can be a silicon nitride film with a low hydrogen content. The semiconductor chip P112 can be bonded to the semiconductor chip P111 via the hydrogen diffusion prevention film 1126. In this case, it is possible to reduce the diffusion of hydrogen atoms from the semiconductor chip P112 to the photodiode, and the decrease in quantum efficiency due to binning between pixels can be suppressed.

[0185] Tokens 1123 and 1124 are formed on the semiconductor substrate 1120. Token 1123 can be used in a current-voltage conversion transistor 214. Token 1124 can be used in a logarithmic transistor 212. An impurity diffusion layer 1122 is formed on the semiconductor substrate 1120 adjacent to the channel region below the gates 1124. The impurity diffusion layer 1122 can be used as the source for the logarithmic transistor 212. The back side of the impurity diffusion layer 1122 is connected to the contact layer 1116 via interlayer wiring 1119. In this case, the interlayer wiring 1119 can penetrate the interlayer insulating layer 1118 and the hydrogen diffusion prevention film 1126. Furthermore, an interlayer insulating layer 1121 is formed on the semiconductor substrate 1120 in a position covering the gates 1123 and 1124. Wiring 1125 is embedded in the interlayer insulating layer 1121. Wiring 1125 can connect the gate 1123 and the impurity diffusion layer 1122. An interlayer insulating layer 1127 is formed on the interlayer insulating layer 1121 in a position that covers the wiring 1125. A hydrogen supply film 1128 is formed on the interlayer insulating layer 1127. The hydrogen supply film 1128 can be made of a silicon nitride film with a high hydrogen content. In this case, lattice defects at the interface of the hydrogen supply film 1128 can be repaired based on the hydrogen atoms diffused from the hydrogen supply film 1128. An interlayer insulating layer 1219 is formed on the hydrogen supply film 1128. The wiring HA2 and junction electrode DE2 are embedded in the interlayer insulating layer 1219. The junction electrode DE2 can be exposed on the surface of the interlayer insulating layer 1219.

[0186] The semiconductor chip P113 comprises a semiconductor substrate 1131. A gate electrode 1133 is formed on the semiconductor substrate 1131. The gate electrode 1133 can be used in logic circuits and the like. An impurity diffusion layer 1134 is formed on the semiconductor substrate 1131 adjacent to the channel region beneath the gate electrode 1133. An interlayer insulating layer 1130 is also formed on the semiconductor substrate 1131 in a position covering the gate electrode 1133. An interlayer insulating layer 1139 is formed on the interlayer insulating layer 1130. Wiring HA3 and junction electrode DE3 are embedded in the interlayer insulating layer 1139. The junction electrode DE3 can be exposed on the surface of the interlayer insulating layer 1139. The junction electrodes DE2 and DE3 are arranged opposite each other. The material for the junction electrodes DE2 and DE3 can be Cu. In this case, the semiconductor chips P112 and P113 can be stacked based on a Cu-Cu junction.

[0187] Thus, in the 11th embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P112, and the interlayer wiring 1119 extending from the semiconductor chip P111 is connected to the lower side of the source of the logarithmic transistor 212. This eliminates the need to route the wiring connecting the semiconductor chip P111 to the source of the logarithmic transistor 212 through the semiconductor chip P112, thereby improving the efficiency of the semiconductor chip P112 layout.

[0188] <12. Twelfth Embodiment> In the 11th embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P112, and the interlayer wiring 1119 extending from the semiconductor chip P111 is connected to the lower side of the source of the logarithmic transistor 212. In this 12th embodiment, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on an intermediate chip, and the interlayer wiring extending from the lower layer chip is joined to the gate of the current-voltage conversion transistor 214.

[0189] Figure 29 is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the twelfth embodiment.

[0190] In the figure, this imaging device is equipped with a semiconductor chip P122 instead of the semiconductor chip P112 of the 11th embodiment described above. The other configurations of this imaging device are the same as those of the imaging device of the 11th embodiment described above.

[0191] The semiconductor chip P122 includes interlayer wiring 1219 instead of the interlayer wiring 1119 of the 11th embodiment described above. The other configurations of the semiconductor chip P122 are the same as those of the semiconductor chip P112 of the 11th embodiment described above.

[0192] The gate electrode 1123 is connected to the contact layer 1116 via an interlayer wiring 1219. At this time, the interlayer wiring 1219 is joined to the gate electrode 1123. The joining location of the interlayer wiring 1219 can include the side or top surface of the gate electrode 1123. In this case, the interlayer wiring 1219 can penetrate the interlayer insulating layer 1118 and the hydrogen diffusion prevention film 1126.

[0193] Thus, in the twelfth embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P122, and the interlayer wiring 1219 extending from the semiconductor chip P111 is joined to the gate electrode 1123 of the current-voltage conversion transistor 214. This eliminates the need to route the wiring connecting the semiconductor chip P111 to the gate electrode 1123 of the current-voltage conversion transistor 214 through the semiconductor chip P122, making it possible to optimize the layout of the semiconductor chip P122 and reduce the parasitic capacitance of the gate electrode 1123 of the current-voltage conversion transistor 214.

[0194] <13. The 13th Embodiment> In the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on the lower layer chip, and the pixel transistors of the grayscale pixel KPX are also placed on the lower layer chip. In this thirteenth embodiment, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are placed on an intermediate chip, and the intermediate chip is bonded to the lower layer chip and the upper layer chip based on a Cu-Cu junction.

[0195] Figure 30 is a cross-sectional view showing an example of the configuration of grayscale pixels and event pixels according to the 13th embodiment.

[0196] In the figure, this solid-state imaging device comprises semiconductor chips P131 to P133. Semiconductor chip P132 is stacked on semiconductor chip P131. Semiconductor chip P133 is stacked on semiconductor chip P132. At this time, semiconductor chip P132 is positioned between semiconductor chips P131 and P133. Here, this solid-state imaging device can be configured as a back-illuminated image sensor. At this time, a light-receiving surface is formed on the back side of semiconductor chip P131.

[0197] The semiconductor chip P111 comprises a semiconductor substrate 1310. Pixel isolation regions 1319 are formed on the semiconductor substrate 1310 to separate pixels. A planarization film 1316 is formed on the back side of the semiconductor substrate 1310. Color filters 1313 are formed on the planarization film 1316 for each pixel. The color filters 1313 are separated for each pixel by a light-shielding layer 1318. On-chip lenses 1314 are formed on the color filters 1313 for each pixel. An impurity diffusion layer 1312 is formed on the semiconductor substrate 1310 for each pixel. The impurity diffusion layer 1312 can be used in the photodiode KPD.

[0198] Furthermore, a gate electrode 1317 is formed on the semiconductor substrate 1310. The gate electrode 1317 may be configured as an embedded transfer gate. In this case, a portion of the gate electrode 1317 can be embedded in the semiconductor substrate 1310 so as to be adjacent to the photodiode KPD. An interlayer insulating layer 1311 is formed on the semiconductor substrate 1310 in a position that covers the gate electrode 1317. Wiring HA11 and junction electrode DE11 are embedded in the interlayer insulating layer 1311. The junction electrode DE11 can be exposed on the surface of the interlayer insulating layer 1311.

[0199] The semiconductor chip P132 comprises a semiconductor substrate 1320. A well 1322 is formed on the semiconductor substrate 1320. Token electrodes 1323 and 1324 are formed on the semiconductor substrate 1320. Token electrode 1123 can be used in a logarithmic transistor 212. Token electrode 1124 can be used in a current-voltage conversion transistor 214. An impurity diffusion layer 1125 is formed in the well 1322 adjacent to the channel region beneath the gate electrode 1123. The impurity diffusion layer 1125 is isolated from the element via an element isolation region 1326. An interlayer insulating layer 1321 is formed on the semiconductor substrate 1320 in a position covering the gate electrodes 1323 and 1324. Wiring HA12 and junction electrode DE12A are embedded in the interlayer insulating layer 1321. Junction electrodes DE11 and DE12A are positioned opposite each other. The material for junction electrodes DE11 and DE12A can be Cu. In this configuration, semiconductor chips P131 and P132 can be stacked based on a Cu-Cu junction. Here, semiconductor chips P131 and P132 can be connected face to face. An interlayer insulating layer 1328 is formed on the back side of the semiconductor substrate 1320. A junction electrode DE12B is embedded in the interlayer insulating layer 1328. The junction electrode DE12B is connected to the wiring HA12 via a through electrode 1327. In this configuration, the through electrode 1327 can penetrate the semiconductor substrate 1320.

[0200] The semiconductor chip P133 comprises a semiconductor substrate 1330. A gate electrode 1333 is formed on the semiconductor substrate 1330. The gate electrode 1333 can be used in logic circuits and the like. A well 1322 is formed on the semiconductor substrate 1330. An element isolation region 1334 is formed in the well 1322. An interlayer insulating layer 1331 is formed on the semiconductor substrate 1330 in a position covering the gate electrode 1333. Wiring HA13 and junction electrode DE13 are embedded in the interlayer insulating layer 1331. Junction electrodes DE12B and DE13 are arranged facing each other. The material of junction electrodes DE12B and DE13 can be Cu. In this case, semiconductor chips P132 and P133 can be stacked based on a Cu-Cu junction. Here, semiconductor chips P132 and P133 can be bottom-to-face connected.

[0201] Thus, in the 13th embodiment described above, the logarithmic transistor 212 and the current-voltage conversion transistor 214 of the event pixel EPX are arranged on the semiconductor chip P132, and the semiconductor chip P132 is bonded to semiconductor chips P131 and P133 based on Cu-Cu junctions. This eliminates the need to route wiring connecting the semiconductor chip P131 to the logarithmic transistor 212 and the current-voltage conversion transistor 214 on the logarithmic transistor 212 and the current-voltage conversion transistor 214, thereby making the layout of the semiconductor chip P132 more efficient.

[0202] <14. The 14th Embodiment> In the sixth embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P61, and the logarithmic transistor 212 is placed on semiconductor chip P62. In this fourteenth embodiment, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P61, the logarithmic transistor 212 is placed on semiconductor chip P62, and the logarithmic transistor 212 is configured as a BEOL transistor.

[0203] Figure 31 is a cross-sectional view showing an example of the configuration of grayscale pixels according to the 14th embodiment.

[0204] In the figure, this solid-state imaging device comprises semiconductor chips P141 and P142. Semiconductor chip P142 is stacked on semiconductor chip P141. Here, this solid-state imaging device can be configured as a back-illuminated image sensor. In this case, a light-receiving surface is formed on the back side of semiconductor chip P141.

[0205] The semiconductor chip P141 includes a semiconductor substrate 1410. Pixel isolation regions 1416 are formed on the semiconductor substrate 1410 to separate pixels. An impurity diffusion layer 1412 is formed on the semiconductor substrate 1410 for each pixel. The impurity diffusion layer 1412 can be used in a photodiode KPD. Token gates 1415 and 1418 are formed on the semiconductor substrate 1410. The gate gate 1415 may be configured as an embedded transfer gate. In this case, a portion of the gate gate 1415 can be embedded in the semiconductor substrate 1410 so as to be in contact with the impurity diffusion layer 1412. The gate gate 1415 can be used in a transfer transistor 210. Furthermore, an impurity diffusion layer 1413 is formed on the semiconductor substrate 1410 at a position adjacent to the channel region below the gate gate 1415. A high-concentration impurity diffusion layer 1414 is formed on the impurity diffusion layer 1413. The impurity diffusion layer 1413 can be used in a floating diffusion EFD. The gate electrode 1418 can be used in the current-voltage conversion transistor 214. Furthermore, an interlayer insulating layer 1411 is formed on the semiconductor substrate 1410 in a position covering the gate electrodes 1415 and 1418. Wiring 1419 is embedded in the interlayer insulating layer 1411. The high-concentration impurity diffusion layer 1414 and the gate electrode 1418 are connected to each other via the wiring 1419.

[0206] The semiconductor chip P142 includes a semiconductor layer 1420. A gate electrode 1423 is formed on the semiconductor layer 1420 via a gate insulating film 1422. An interlayer insulating layer 1421 is formed on the semiconductor chip P141 at the location where the semiconductor layer 1420, gate insulating film 1422, and gate electrode 1423 are embedded. Wiring 1424 is embedded in the interlayer insulating layer 1421. Wiring 1424 is connected to the back side of the semiconductor layer 1420. At this time, the semiconductor layer 1420 is connected to wiring 1419 via wiring 1424. The semiconductor layer 1420 and the gate electrode 1423 can be used in a logarithmic transistor 212. At this time, the logarithmic transistor 212 can constitute a BEOL transistor.

[0207] Thus, in the 14th embodiment described above, the current-voltage conversion transistor 214 of the event pixel EPX is placed on semiconductor chip P141, the logarithmic transistor 212 is placed on semiconductor chip P142, and the logarithmic transistor 212 is configured as a BEOL transistor. This eliminates the need to route the wiring connecting semiconductor chip P141 to the source of the logarithmic transistor 212 through semiconductor chip P142, thereby improving the layout of semiconductor chip P142.

[0208] <15. The 15th Embodiment> In the first embodiment described above, the logarithmic transistor 212 and current-voltage conversion transistor 214 of the event pixel EPX are arranged on semiconductor chip P11, and the pixel transistor of the grayscale pixel KPX is arranged on semiconductor chip P12. In this 15th embodiment, semiconductor chips, each provided with a pixel array section in which pixels are arranged in a matrix, are stacked.

[0209] Figure 32 is a perspective view showing an example of stacking of pixel arrays according to the 15th embodiment.

[0210] In the figure, the solid-state imaging device comprises semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

[0211] A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. The pixels 931 may include event pixels EPX as described in the above-described embodiment. The pixel array section 923 may also contain a mixture of event pixels EPX and grayscale pixels KPX as described in the above-described embodiment. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0212] Peripheral circuits 924 are formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction.

[0213] The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of semiconductor chips 921 and 922. In this case, semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0214] Thus, in the 15th embodiment described above, the semiconductor chip 922 on which the pixel array 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0215] <16. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0216] Figure 33 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0217] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 33, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0218] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0219] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0220] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0221] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0222] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0223] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0224] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0225] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0226] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 33, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0227] Figure 34 shows an example of the installation position of the imaging unit 12031.

[0228] In Figure 34, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0229] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0230] Figure 34 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0231] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0232] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0233] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0234] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0235] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology described herein to the vehicle control system 12000, the performance of the imaging unit 12031 can be improved.

[0236] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0237] Furthermore, this technology can also be configured as follows. (1) Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. At least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip. Imaging device. (2) The source of the logarithmic transistor and the gate of the current-voltage conversion transistor are connected to the cathode of the photoelectric conversion element, The gate of the logarithmic transistor is connected to the drain of the current-voltage conversion transistor. The imaging device described in (1) above. (3) Wiring formed on the first chip or the second chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor. The imaging apparatus according to (1) or (2) above, comprising: (4) A first contact formed on the first chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor, A second contact formed on the second tip and positioned to overlap with the first contact, An imaging device according to any one of (1) to (3) above, comprising: (5) The current-voltage conversion transistor is formed on the first chip, and the logarithmic transistor is formed on the second chip. The imaging device described in any of (1) to (4) above. (6) The logarithmic transistor is formed on the first chip, and the current-voltage conversion transistor is formed on the second chip. The imaging device described in any of (1) to (5) above. (7) The logarithmic transistor and the current-voltage conversion transistor are formed on the first chip. The imaging device described in any of (1) to (6) above. (8) The logarithmic transistor is First logarithmic transistor and A second logarithmic transistor connected in series with the first logarithmic transistor and An imaging device according to any one of (1) to (7) above, comprising: (9) The current-voltage conversion transistor is First current-voltage conversion transistor, A second current-voltage conversion transistor connected in series with the first current-voltage conversion transistor and An imaging device according to any one of (1) to (8) above, comprising: (10) The logarithmic transistor is formed on the second chip, First interlayer wiring extending from the first chip and connected to the lower surface side of the source of the logarithmic transistor. An imaging device according to any one of (1) to (9) above, comprising: (11) The current-voltage conversion transistor is formed on the second chip, A second interlayer wiring extends from the first chip and is joined to the gate of the current-voltage conversion transistor. An imaging device according to any one of (1) to (10) above, comprising: (12) At least one of the logarithmic transistor and the current-voltage conversion transistor formed on the first chip is a BEOL (Back End Of Line) transistor. An imaging device according to any of (1) to (11) above. (13) A pixel array section comprising grayscale pixels for detecting grayscale signals and event pixels for detecting event signals, The aforementioned event pixel is Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. At least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip. The imaging device described in any of (1) to (12) above. (14) The layout pattern of the photoelectric conversion elements formed in the grayscale pixels and the layout pattern of the photoelectric conversion elements formed in the event pixels are equal to each other. The imaging device described in (13) above. (15) The amplification transistor for the grayscale pixel is formed on the first chip, The selection transistor for the grayscale pixel is formed on the second chip. The imaging apparatus described in (13) or (14) above. (16) The pixel array portion comprises pixel regions partitioned in a matrix manner in the row direction and the column direction, The pixel region comprises a first pixel region and a second pixel region that are not adjacent to each other in the row direction and the column direction, The logarithmic transistor is formed in the first pixel region, The current-voltage conversion transistor is formed in the second pixel region. The imaging device described in any of (13) to (15) above. (17) The first chip has a photoelectric conversion element for the grayscale pixel and a photoelectric conversion element for the event pixel formed thereon. On the second chip, the pixel transistor of the grayscale pixel is formed at a position that overlaps with at least one of the photoelectric conversion elements of the grayscale pixel and the photoelectric conversion element of the event pixel. The imaging device described in any of (13) to (16) above. (18) Photoelectric conversion element, The system comprises a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, A second chip is laminated on the first chip on which the photoelectric conversion element is formed. The logarithmic transistor is formed on the first chip. Imaging device. (19) A photoelectric conversion element, A logarithmic transistor that generates a photovoltage obtained by logarithmically converting the photocurrent output from the photoelectric conversion element, A current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is laminated on the first chip on which the photoelectric conversion element is formed. The logarithmic transistor and the current-voltage conversion transistor are formed on the second chip. An interlayer wiring that extends from the first chip and is connected to the lower surface side of the source of the logarithmic transistor An imaging device comprising the same. (20) A photoelectric conversion element, A logarithmic transistor that generates a photovoltage obtained by logarithmically converting the photocurrent output from the photoelectric conversion element, A current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is laminated on the first chip on which the photoelectric conversion element is formed. [[ID=2七杀7]] The logarithmic transistor and the current-voltage conversion transistor are formed on the second chip. An interlayer wiring that extends from the first chip and is joined to the gate of the current-voltage conversion transistor An imaging device comprising the same.

Explanation of Signs

[0238] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Storage unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel Array Section 113 Event signal output section 114-level tone signal output section 115 Access Control Unit 116 Timing Control Unit 117 Event Signal Processing Unit 118-level grayscale signal processing unit EPX Event Pixel KPX tonal pixels ESL Vertical Event Signal Line VSL Vertical Grayscale Signal Line HSL horizontal control line 201 Light receiving section EPD photodiode 210 Transfer Transistors 211 Logarithmic transformation section 212 logarithmic transistors 214 Current-Voltage Conversion Transistor 213 Current Source Transistor

Claims

1. Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. At least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip. Imaging device.

2. The source of the logarithmic transistor and the gate of the current-voltage conversion transistor are connected to the cathode of the photoelectric conversion element. The gate of the logarithmic transistor is connected to the drain of the current-voltage conversion transistor. The imaging apparatus according to claim 1.

3. Wiring formed on the first chip or the second chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor. The imaging apparatus according to claim 1, comprising:

4. A first contact formed on the first chip and connected to at least one of the logarithmic transistor and the current-voltage conversion transistor, A second contact formed on the second chip and positioned to overlap with the first contact, The imaging apparatus according to claim 1, comprising:

5. The current-voltage conversion transistor is formed on the first chip, and the logarithmic transistor is formed on the second chip. The imaging apparatus according to claim 1.

6. The logarithmic transistor is formed on the first chip, and the current-voltage conversion transistor is formed on the second chip. The imaging apparatus according to claim 1.

7. The logarithmic transistor and the current-voltage conversion transistor are formed on the first chip. The imaging apparatus according to claim 1.

8. The logarithmic transistor is, First logarithmic transistor and A second logarithmic transistor connected in series with the first logarithmic transistor and The imaging apparatus according to claim 1, comprising:

9. The current-voltage conversion transistor is First current-voltage conversion transistor, A second current-voltage conversion transistor connected in series with the first current-voltage conversion transistor and The imaging apparatus according to claim 1, comprising:

10. The logarithmic transistor is formed on the second chip, First interlayer wiring extending from the first chip and connected to the lower surface side of the source of the logarithmic transistor. The imaging apparatus according to claim 1, comprising:

11. The current-voltage conversion transistor is formed on the second chip, A second interlayer wiring extending from the first chip and joined to the gate of the current-voltage conversion transistor. The imaging apparatus according to claim 1, comprising:

12. At least one of the logarithmic transistor and the current-voltage conversion transistor formed on the first chip is a BEOL (Back End Of Line) transistor. The imaging apparatus according to claim 1.

13. It comprises a pixel array section in which grayscale pixels for detecting grayscale signals and event pixels for detecting event signals are formed, The aforementioned event pixel is Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. At least one of the logarithmic transistor and the current-voltage conversion transistor is formed on the first chip. The imaging apparatus according to claim 1.

14. The layout pattern of the photoelectric conversion elements formed in the grayscale pixels and the layout pattern of the photoelectric conversion elements formed in the event pixels are equal to each other. The imaging device according to claim 13.

15. The amplification transistor for the grayscale pixel is formed on the first chip. The selection transistor for the grayscale pixel is formed on the second chip. The imaging device according to claim 13.

16. The pixel array portion comprises pixel regions partitioned in a matrix-like manner in the row direction and the column direction, The pixel region comprises a first pixel region and a second pixel region that are not adjacent to each other in the row direction and the column direction, The logarithmic transistor is formed in the first pixel region, The current-voltage conversion transistor is formed in the second pixel region. The imaging device according to claim 13.

17. The first chip has a photoelectric conversion element for the grayscale pixel and a photoelectric conversion element for the event pixel formed on it. On the second chip, the pixel transistor of the grayscale pixel is formed at a position that overlaps with at least one of the photoelectric conversion elements of the grayscale pixel and the photoelectric conversion element of the event pixel. The imaging device according to claim 13.

18. Photoelectric conversion element, The system comprises a logarithmic transistor that generates an optical voltage by logarithmically converting the optical current output from the photoelectric conversion element, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. The logarithmic transistor is formed on the first chip. Imaging device.

19. Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. The logarithmic transistor and the current-voltage conversion transistor are formed on the second chip. Interlayer wiring extending from the first chip and connected to the lower surface side of the source of the logarithmic transistor. An imaging device equipped with the following features.

20. Photoelectric conversion element, A logarithmic transistor that generates an optical voltage by logarithmically transforming the photocurrent output from the aforementioned photoelectric conversion element, The system comprises a current-voltage conversion transistor that converts the photocurrent into an output voltage based on the photovoltage generated by the logarithmic transistor, A second chip is stacked on the first chip on which the photoelectric conversion element is formed. The logarithmic transistor and the current-voltage conversion transistor are formed on the second chip. Interlayer wiring extending from the first chip and joined to the gate of the current-voltage conversion transistor. An imaging device equipped with the following features.

Images