Received Signal Quality Monitor

Abstract

To provide a reception signal quality monitor capable of accurately monitoring the quality of a reception signal while reducing the circuit size and the power consumption thereof.SOLUTION: In a receiving device RX including a reception signal quality monitor and a deserializer, a phase adjustment circuit 11 of the reception signal quality monitor can perform a phase sweep of a sampling clock signal φe of a reference sampler, within a phase range that is a multiple of a unit interval (UI) of a serial data signal. A first synchronization circuit 13A receives input of a first output signal from one sampler included in a plurality of data reception samplers, and a second output signal from a reference sampler SMe. A comparative logic circuit 15 receives input of a first output signal and a second output signal output synchronously from the first synchronization circuit 13A. The comparative logic circuit 15 outputs comparison results pertaining to the quality of the reception signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a received signal quality monitor. [Background technology]

[0002] Patent Document 1, Patent Document 2, Patent Document 3, Non-Patent Document 1, and Non-Patent Document 2 disclose receiving devices. When a received signal quality monitor capable of outputting data for generating an eye diagram (a quality monitor signal for the received signal) is incorporated into the receiving device, the quality of the received signal can be evaluated by evaluating the data. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-152731 [Patent Document 2] U.S. Patent No. 10,720,910 [Patent Document 3] U.S. Patent No. 10,735,116 [Non-patent literature]

[0004] [Non-Patent Document 1] Yu-Chuan Lin, H. Tsao, "A10-Gb / s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nmCMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1January 2020 [Non-patent document 2] Hyosup Won, Joon-Yeong Lee, et.al., "A 28-Gb / s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor", IEEE Transactions on Circuits and Systems I, Regular Papers, Volume 64, Issue 3, March 2017 Summary of the Invention [Problem to be solved by the invention]

[0005] There is a demand for a received signal quality monitor that can accurately monitor the quality of a received signal while reducing the circuit area and power consumption. [Means for solving the problem]

[0006] This received signal quality monitor comprises a plurality of data receiving samplers that receive a serial data signal, are connected in parallel, and each receive a multiphase sampling clock signal; a reference sampler that receives the serial data signal; a phase adjustment circuit that can sweep the phase of the sampling clock signal that is input to the reference sampler within a phase range of N times (2≦N) the unit interval (UI) of the serial data signal; a first synchronization circuit that receives the output signal of one of the plurality of data receiving samplers and the output signal of the reference sampler; and a comparison logic circuit that receives the two output signals that are output in synchronization from the first synchronization circuit.

[0007] When the phase sweep range of the phase adjustment circuit is narrow, a delay adjustment circuit may be placed before multiple data receiving samplers to prevent errors. In this device, the phase sweep range is wide, so the area where errors occur can be sufficiently separated from the eye diagram formation area, making it possible to omit such a circuit, thereby reducing the circuit area and power consumption while accurately monitoring the quality of the received signal.

[0008] In a received signal quality monitor, it is preferable that the phase range adjusted by the phase adjustment circuit be one period or more of the sampling clock signal input to the reference sampler, and by expanding the phase range, it becomes easier to acquire the eye opening even if the position of the eye opening moves.

[0009] Preferably, the received signal quality monitor further comprises a counter for counting the output result of the comparison logic circuit.

[0010] It is preferable that the reference sampler has a first input terminal for receiving the serial data signal and a second input terminal for inputting a variable reference threshold voltage, and samples the comparison result between the serial data signal and the reference threshold voltage in synchronization with the sampling clock signal, which is capable of phase sweep.

[0011] Preferably, each sampler included in the plurality of data receiving samplers has a first input terminal for receiving the serial data signal and a second input terminal for inputting a threshold voltage, and samples the comparison result between the serial data signal and the threshold voltage in synchronization with the sampling clock signal included in the multiphase sampling clock signal and corresponding to the sampler.

[0012] It is preferable that the received signal quality monitor comprises a second synchronization circuit to which the multiple output signals output from the multiple data reception samplers are input, and a CDR (Clock and Data Recovery) circuit to which the multiple output signals output from the second synchronization circuit are input and which generates the polyphase sampling clock signals.

[0013] In the received signal quality monitor, it is preferable that the serial data signal is a pulse amplitude modulation (PAM) signal having multiple values ​​of k levels (3≦k, k is an integer), each of the plurality of data receiving samplers includes k−1 samplers, each of which receives the serial data signal along with threshold voltages of different levels, and each of which outputs k−1 comparison results.

[0014] In the received signal quality monitor, it is preferable that one sampler included in the plurality of data reception samplers outputs the k-1 comparison results, the k-1 comparison results and an output signal of the reference sampler are input to the first synchronization circuit, the comparison logic circuit includes k-1 sub-comparison logic circuits, and each of the k-1 sub-comparison logic circuits receives an output signal synchronously output from the first synchronization circuit. At least two output signals synchronously output from the first synchronization circuit are input.

[0015] The phase adjustment circuit preferably includes a selection circuit to which the polyphase sampling clock signals output from the CDR circuit are input, and a phase interpolation circuit to which the output signal of the selection circuit is input. [Effects of the Invention]

[0016] The received signal quality monitor can accurately monitor the quality of the received signal while reducing the circuit area and power consumption. [Brief explanation of the drawings]

[0017] [Figure 1]FIG. 1 is a block diagram showing a transmission / reception system and an external device 300. As shown in FIG. [Figure 2] FIG. 2 is a block diagram of the receiving device RX. [Figure 3] FIG. 3 is a block diagram of the reference sampler SMe. [Figure 4] FIG. 4 is a block diagram of the phase adjustment circuit 11. [Figure 5] FIG. 5 is a block diagram of the phase interpolator 11B. [Figure 6] FIG. 6 is a block diagram showing the structure of the first synchronization circuit 13A. [Figure 7] FIG. 7 is a diagram showing a truth table of a comparison logic circuit (XOR circuit). [Figure 8] FIG. 8 is a diagram in which the output of the error counter is plotted two-dimensionally. [Figure 9] FIG. 9 is a timing chart for explaining the setup time ST and the hold time HD. [Figure 10] FIG. 10 is a block diagram of a typical CDR circuit. [Figure 11] FIG. 11 is a timing chart for explaining the operation of the CDR circuit shown in FIG. [Figure 12] FIG. 12 is a block diagram of the CDR circuit 17. [Figure 13] FIG. 13 is a timing chart for explaining the phase difference of data in the CDR circuit shown in FIG. [Figure 14] FIG. 14 is a block diagram showing the structure of the second synchronization circuit 13B. [Figure 15] FIG. 15(A) is a timing chart of the serial data signal DATA-S, and FIG. 15(B) is a timing chart showing the reference sampling clock signal φe. [Figure 16] FIG. 16 is a timing chart showing the serial data signal, the multiphase clock signals φ1 to φ10, and the clock signal φe. [Figure 17]FIG. 17 is a timing diagram of the serial data signal and the signals output from the synchronization circuits 13A and 13B. [Figure 18] FIG. 18 is a block diagram of another receiving device RX. [Figure 19] FIG. 19 is a block diagram of the phase adjustment circuit 11 shown in FIG. [Figure 20] FIG. 20 is a block diagram showing the structure of a multi-value sampler. [Figure 21] FIG. 21 is a graph showing the change in the input voltage (V) to the multi-level sampler over time. [Figure 22] FIG. 22 is a block diagram showing the multi-value sampler and the subsequent circuit configuration. [Figure 23] FIG. 23 is a graph showing the change over time of the input voltage (V) to the first data receiving sampler SM1high and the reference sampler SMe. [Figure 24] FIG. 24 is a block diagram showing the structure of a multi-value sampler and a subsequent circuit. [Figure 25] FIG. 25 is a block diagram showing the structure of a multi-value sampler and subsequent circuits. [Figure 26] 26(A) and 26(B) are timing charts of exemplary serial data signals. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate explanations will be omitted. The present invention is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0019] FIG. 1 is a block diagram showing a transmission / reception system and an external device 300. As shown in FIG.

[0020] The transmission / reception system comprises a receiving device RX and a transmitting device TX. An external device 300 for inspecting signal quality can be connected to the receiving device RX.

[0021] The transmitter TX has an input terminal for an input parallel data signal DATA-PI and an output terminal for a serial data signal DATA-S. The serial data signal DATA-S transmitted from the transmitter TX is transmitted via a communication cable CB and received by the receiver RX. For example, when transmitting an 8-bit parallel data signal, the parallel data signal is converted to serial and then encrypted using the 8b / 10b method to embed a clock in the serial data, and a 10-bit serial data signal DATA-S is transmitted.

[0022] The receiver RX is equipped with a digitalizer that converts the received serial data signal DATA-S to parallel, an output terminal for the output parallel data signal DATA-PO, and a received signal quality monitor (eye monitor). The received signal quality monitor in the receiver RX is equipped with an output terminal for the quality monitor signal OUTPUT, an input terminal for the external input threshold control signal CNT-TH, and an input terminal for the external input phase control signal CNT-PH. The quality monitor signal OUTPUT is a signal that indicates the state of the received signal, such as an eye diagram, and contains information about the signal quality.

[0023] The external device 300 is a computer, and includes a memory 301, a central processing unit (CPU) 302, an interface 303, a bus 304, a display 305, an output terminal for an external input threshold control signal CNT-TH, and an output terminal for an external input phase control signal CNT-PH.

[0024] The central processing unit 302 performs arithmetic processing according to a control signal generation program stored in the memory 301, generating an external input phase control signal CNT-PH and an external input threshold control signal CNT-TH. The external input phase control signal CNT-PH controls the phase of the sampling clock signal φe of the phase adjustment circuit 11 (see FIG. 2) at a time (tφe) corresponding to the horizontal axis of the drawing. The external input threshold control signal CNT-TH controls the reference threshold voltage Ve of the voltage generator 12 (see FIG. 2) at a time (tVe) corresponding to the vertical axis of the drawing. These times (tφe, tVe) are periodically reset to 0 when the horizontal and vertical axes reach their maximum values ​​during drawing. Furthermore, rather than these control signals directly controlling the target parameters (phase, voltage), these control signals may be used as triggers to control the target parameters within the receiving device RX.

[0025] The external device 300 receives a quality monitor signal OUTPUT from the receiver RX, and the central processing unit 302 performs calculations in accordance with an eye diagram drawing program stored in memory 301, allowing the display 305 to display the received signal status, such as an eye diagram. The eye diagram drawing program stores the quality monitor signal OUTPUT, which is output in time series, in memory 301 and then draws an eye diagram. The quality monitor signal OUTPUT contains time information (tφe) of the phase of the reference sampling clock signal φe (see FIG. 2) as the X-axis coordinate information of the eye diagram according to the timing of reception, and time information (tVe) of the reference threshold voltage Ve (see FIG. 2) to be swept as the Y-axis coordinate information. The number of errors counted by the error counter (counter) 16 (see FIG. 2) is recorded at a position defined by the two-dimensional coordinates (tφe, tVe) at the time of drawing, and the eye diagram information is stored in a two-dimensional memory space. Next, this program sends the image information of the obtained eye diagram to the display 305. Of course, it is also possible to obtain an eye diagram by storing the data contained in the quality monitor signal in the computer's memory 301 and inputting this data into spreadsheet software.

[0026] The external device 300 can be realized by a general personal computer, a single-board computer, or a dedicated device or a portable information terminal that performs the same signal processing as these computers.

[0027] FIG. 2 is a block diagram of the receiving device RX.

[0028] The receiving device RX has an input terminal for a serial data signal DATA-S, and the serial data signal DATA-S is input to an amplifier 101. In this example, the amplifier 101 is a simple buffer amplifier, but may also include an equalizer and a filter. The serial data signal DATA-S output from the amplifier 101 is input to a received signal quality monitor, which outputs a quality monitor signal OUTPUT from its output terminal. The serial data signal DATA-S output from the amplifier 101 is also input to a deserializer equipped with multiple data receiving samplers SM1 to SMm (e.g., m = 10). The deserializer converts the received serial data signal DATA-S into output parallel data signals DATA-PO and outputs them from multiple output terminals. The sampling timing of the received signal is adjusted by a CDR (Clock and Data Recovery) circuit 17, and the voltage and phase during sampling are controlled by a control circuit 18. In this way, the receiving device RX has a received signal quality monitor and a deserializer.

[0029] (Received signal quality monitor) The received signal quality monitor uses output signals from multiple data receiving samplers SM1 to SMm. The digitalizer includes m samplers, of which the nth sampler is designated sampler SMn. 1≦n≦m, where m and n are integers. The multiple data receiving samplers SM1 to SMm each receive a serial data signal DATA-S and are connected in parallel, with each clock signal included in the polyphase sampling clock signals (φ1 to φm) being input to the input terminal of each sampling clock signal φn. In the figure, m=10 is used as a specific example, but m may be greater or less than 10.

[0030] The received signal quality monitor includes a plurality of data receiving samplers SM1 to SMm, a reference sampler SMe that receives the serial data signal DATA-S, a phase adjustment circuit 11, a voltage generator 12, a first synchronization circuit 13A, a comparison logic circuit 15, an error counter 16, and a CDR circuit 17. These will be explained in detail below.

[0031] (Reference sampler) FIG. 3 is a block diagram of the reference sampler SMe.

[0032] The reference sampler SMe receives the serial data signal DATA-S. The received serial data signal DATA-S is compared with the reference threshold voltage Ve by the comparator COMP, and this comparison result is sampled at the reference sampling timing (the rising edge of the sampling clock signal φe), and the comparison result is output. As an example, a D flip-flop FF1 is used for sampling. In D flip-flop FF1, when the truth value to be stored is input to the D terminal and the rising edge of the clock signal φe is input to the C terminal, the D flip-flop stores the truth value of the D terminal and outputs the stored truth value from the Q terminal. The output of the Q terminal (comparison result) is held until the next rising edge of the sampling clock signal φe is input.

[0033] The comparison result (second output signal (reference signal Se)) output from the reference sampler SMe indicates "1" if the serial data signal DATA-S is greater than the reference threshold voltage Ve, and indicates "0" if it is less than the reference threshold voltage Ve. The sampling clock signal φe is output from the phase adjustment circuit 11, and the reference threshold voltage Ve is output from the voltage generator 12.

[0034] Thus, in the received signal quality monitor, the reference sampler SMe has a first input terminal SMe1 that receives the serial data signal DATA-S, a second input terminal SMe2 that receives the reference threshold voltage Ve, and an input terminal SMe3 for the sampling clock signal φe, and samples the comparison result (reference signal Se) between the serial data signal DATA-S and the reference threshold voltage Ve in synchronization with the sampling clock signal φe.

[0035] (Multiple data receiving samplers) The structure of each of the multiple data receiving samplers SM1 to SMm is the same as the structure of the reference sampler SMe. The operation of each sampler SMn (n = 1 to m) can be explained by replacing the reference threshold voltage Ve with the threshold voltage Vn (n = 1 to m), the sampling clock signal φe with the sampling clock signal φn (n = 1 to m), and the reference signal Se with the output signal Sn (n = 1 to m) in the explanation of Figure 3.

[0036] (Phase adjustment circuit) FIG. 4 is a block diagram of the phase adjustment circuit 11.

[0037] The phase adjustment circuit 11 has one or more input terminals and an output terminal for a sampling clock signal φe. In this example, the number of input terminals of the phase adjustment circuit 11 is two or more. Two or more sampling clock signals (φ1 to φm) included in the multi-phase clock signals (φ1 to φm) are input to these input terminals. The sampling clock signal φe is output from the output terminal of the phase adjustment circuit 11. The output terminal of the phase adjustment circuit 11 is connected to the input terminal for the sampling clock signal φe of the reference sampler SMe (see Figures 2 and 3). The phase adjustment circuit 11 can sweep the phase of the sampling clock signal φe. In this example, the phase adjustment circuit 11 receives a phase control signal PH-SEL and adjusts the phase of the sampling clock signal φe in accordance with the received phase control signal PH-SEL. The phase control signal PH-SEL is output from the control circuit 18 (see Figure 2). The control circuit 18 can generate the phase control signal PH-SEL based on an externally input phase control signal CNT-PH. The external input phase control signal CNT-PH and the phase control signal PH-SEL may be the same signal, in which case the control circuit 18 (see FIG. 2) may be omitted.

[0038] The phase adjustment circuit 11 may have a variety of configurations, but the phase adjustment circuit shown in the figure includes a multiplexer 11A (selection circuit) and a phase interpolator 11B (phase interpolator). The multiplexer 11A selects two clock signals φA and φB from the multiphase clock signals φ1 to φm in accordance with the instruction of a clock selection signal SEL0 in the phase control signal PH-SEL (the values ​​of A and B are specified by the clock selection signal PH-SEL). The phase interpolator 11B generates and outputs a clock signal φe having a phase between the two input clock signals φA and φB. The time tE of the rising edge Eφe of the clock signal φe is set to a time a predetermined time ΔT has elapsed since the time tA of the rising edge EφA of the clock signal φA. The time of the rising edge EφB of the clock signal φB is defined as time tB. The predetermined time ΔT has a value obtained by multiplying the time difference (tB−tA) by a coefficient equal to or less than 1, and this coefficient is given by the interpolation position selection signal SEL1 in the phase control signal PH-SEL.

[0039] As described above, the phase adjustment circuit 11 includes a multiplexer 11A to which the multiphase clock signals φ1 to φm output from the CDR circuit are input, and a phase interpolator 11B to which the output signal of the multiplexer 11A is input. The multiplexer is a selection circuit that selects and outputs a desired signal from the input signals. The multiphase clock signals have multiple phases, and the phase interpolator 11B can output a reference clock signal φe having a desired phase according to the phases of the two input signals and a phase control signal.

[0040] (Phase interpolator) FIG. 5 is a block diagram of the phase interpolator 11B.

[0041] The phase interpolator 11B includes a first inverter 11BA receiving a clock signal φA, a second inverter 11BB receiving a clock signal φB, and a third inverter 11BC connected to the output terminals of the first and second inverters. The first and second inverters 11BA and 11BB each include a plurality of gated inverters connected in parallel. The inverters have gates (transistor switches) connected in series, and the number of gates that are turned ON can be controlled by an interpolation position selection signal SEL1. Turning on α gates in the first inverter 11BA and (1-α) gates in the second inverter 11BB allows the rising edge time tE of the output signal φE to be changed according to the interpolation parameter α (0<α<1).

[0042] (voltage generator) The voltage generator 12 shown in FIG. 2 generates multiple threshold voltages V1 to Vm (e.g., m=10) that are input to multiple data receiving samplers SM1 to SMm, and a reference threshold voltage Ve that is input to the reference sampler SMe. In this example, the voltage generator 12 receives a threshold selection signal or threshold control signal TH-SEL and changes the reference threshold voltage Ve in response to the received threshold control signal TH-SEL. The reference threshold voltage Ve is swept to obtain an eye diagram. While the voltage generator 12 can also be configured to sweep the reference threshold voltage Ve itself, this example uses the threshold control signal TH-SEL. In this example, the threshold control signal TH-SEL is output from a control circuit 18. The control circuit 18 can generate the threshold control signal TH-SEL based on an externally input threshold control signal CNT-TH. The externally input threshold control signal CNT-TH and the threshold control signal TH-SEL may be the same signal, in which case the control circuit 18 can be omitted. There are numerous known structures for changing the threshold voltage in response to a threshold control signal. For example, by connecting multiple resistors in parallel downstream of the node that applies the threshold voltage, connecting each switch in series to each resistor, and controlling the ON / OFF of these switches with a threshold control signal, the threshold voltage can be changed.

[0043] The multiple threshold voltages V1 to Vm input to the multiple data receiving samplers SM1 to SMm may be fixed values, or may be set to the center voltage of the amplitude of the serial data signal DATA-S received by the samplers. The multiple threshold voltages V1 to Vm can also be changed as needed using feedback control or the like. For example, it is possible to input a threshold control signal to voltage generator 12 that integrates the digital values ​​of each output signal from the deserializer over a reference period, and if the integrated value exceeds a first integrated threshold, it is determined that the current threshold voltage is low and the input threshold voltage to the corresponding sampler is increased; if the integrated value falls below a second integrated threshold, it is determined that the current threshold voltage is high and the input threshold voltage is decreased.

[0044] Thus, in the received signal quality monitor, each sampler SMn (n is an arbitrary number selected from 1 to m) included in the plurality of data receiving samplers SM1 to SMm has a first input terminal that receives the serial data signal DATA-S, a second input terminal to which the threshold voltage Vn is input, and an input terminal for the sampling clock signal φn, and samples and outputs the comparison result Sn (S1 to Sm) between the serial data signal DATA-S and the threshold voltage Vn in synchronization with the sampling clock signal φn (φ1 to φm) that is included in the polyphase sampling clock signal and corresponds to the sampler SMn (SM1 to SMm).

[0045] (1st synchronous circuit) FIG. 6 is a block diagram showing the structure of the first synchronization circuit 13A.

[0046] The first synchronization circuit 13A receives an evaluation target signal Sx (first output signal (e.g., S2)) and a reference signal Se (second output signal). The evaluation target signal Sx (e.g., S2) is an output signal of one sampler included in the multiple data receiving samplers SM1 to SMm. The reference signal Se is an output signal of the reference sampler SMe. The first synchronization circuit 13A synchronizes the evaluation target signal Sx and the reference signal Se. The first synchronization circuit 13A outputs a synchronized evaluation target signal SxOUT and a synchronized reference signal SeOUT. The timing of the rising edge of the evaluation target signal SxOUT and the rising edge of the reference signal SeOUT coincide with each other.

[0047] As an example, the first synchronization circuit 13A includes a flip-flop 13A1 having a D terminal to which the evaluation target signal Sx is input, and a flip-flop 13A2 having a D terminal to which the output signal Sx' of the flip-flop 13A1 is input. The first synchronization circuit 13A also includes a flip-flop 13A3 having a D terminal to which a reference signal Se is input, and a flip-flop 13A4 having a D terminal to which the reference signal Se' output from the flip-flop 13A3 is input. Each flip-flop is a D flip-flop, and a synchronization sampling clock signal φK (e.g., φ7) is input to a clock input terminal (C terminal).

[0048] The first synchronization circuit 13A may include a frequency divider 13DIV. The frequency divider 13DIV is not essential, but it can reduce the frequency of the sampling clock signal. If the frequency divider 13DIV divides the sampling clock signal φK (e.g., φ7) input to the first synchronization circuit 13A by two, the frequency of the sampling clock signal will be halved and the period will be doubled.

[0049] (Comparison logic circuit) FIG. 7 is a diagram showing a truth table of a comparison logic circuit (XOR circuit).

[0050] The comparison logic circuit 15 receives the evaluation target signal SxOUT and the reference signal SeOUT, which are synchronized and output from the first synchronization circuit 13A. The comparison logic circuit 15 is a circuit that compares the logic of the input digital signals, and in this example, is an XOR circuit (exclusive OR circuit). The XOR circuit outputs "0" if the logic of the input data matches, and "1" if the logic of the input data differs. The XOR circuit can also be replaced with four NAND circuits. Depending on the signal processing form in the subsequent stage, a structure that outputs a different logic configuration is also possible. For example, a circuit in which the output of the XOR circuit is inverted by a NOT circuit can also be used. Therefore, the comparison logic circuit 15 is not limited to an XOR circuit, as long as it is a logic circuit that compares the logic of the input data.

[0051] (Error counter) FIG. 8 is a diagram in which the output of the error counter is plotted two-dimensionally.

[0052] The error counter 16 (see Figure 2) counts the output result (digital data) of the comparison logic circuit 15. The error counter 16 counts up when the input data (evaluation target signal Sx, reference signal Se) to the comparison logic circuit 15 do not match. It counts and accumulates the comparison results for a certain period (denoted as E-COUNT) and outputs a count value. The phase of the reference rising edge (e.g., Eφ8) is set to 0°. The reference signal Se is a signal sampled at the rising edge Eφe, which is separated from the reference rising edge by a phase Pφe (degrees). The count value indicates the degree of mismatch between the evaluation target signal Sx and the reference signal Se at the coordinate (Pφe, Ve) (pixel). If a two-dimensional graph is drawn with the phase Pφe on the horizontal axis and the reference threshold voltage Ve on the vertical axis, the count value of the error counter 16 at the coordinate (Pφe, Ve) draws an eye diagram. Pixels with low count values ​​indicate areas within the eye diagram opening, where the count value is essentially zero.

[0053] The phase range of the eye diagram formation region R(EYE) depicted in two dimensions is at least 1 / 2 of the maximum value of the phase Pφe (N × UI, 360°) in this example, preferably 1 / 3 or less, and more preferably 1 / 4 or less. Note that N is a natural number, and UI represents the unit interval of the serial data signal DATA-S. In other words, the maximum value of the phase Pφe is greater than the phase range of the eye diagram formation region R(EYE) required for data acquisition. The center of the error-tolerant region R(VIO) is set at a position approximately (N × UI × 1 / 2, 180°) phase away from the center of the eye diagram formation region R(EYE). The phase range of the error-tolerant region R(VIO) is at least 1 / 2 of the maximum value of the phase Pφe, preferably 1 / 3 or less, and more preferably 1 / 4 or less. In the error-tolerant region R(VIO), a setup time violation and / or a hold time violation may occur between the reference signal Se and the sampling clock signal φ7 in the first synchronization circuit 13A. In other words, errors occur in the error-tolerant region R(VIO). In this example, the error-tolerant region R(VIO) is separated from the eye diagram forming region R(EYE), which has the advantage that the eye diagram forming region R(EYE) is not affected by errors.

[0054] The positions on the horizontal axis of the eye diagram formation region R(EYE) and error tolerance region R(VIO) shift from their reference positions along the horizontal axis depending on the unintended inherent delay caused by factors such as the operating temperature and manufacturing variations of the phase adjustment circuit. Furthermore, the position of phase Pφe = 360° and the position of phase Pφe = 0° are the same position, and the left and right ends of the graph may be continuously connected. As the inherent delay increases, part of the eye diagram may appear near the left end of the graph, and the remaining part may appear near the right end of the graph. In this device, even if the inherent delay of the phase adjustment circuit changes, the eye diagram formation region R(EYE) remains far from the error tolerance region R(VIO), providing the advantage of being unaffected by errors.

[0055] FIG. 9 is a timing chart for explaining the setup time ST and the hold time HD.

[0056] 2, a sampling clock signal φ7 is input to the first synchronization circuit 13A as a synchronization signal, and the evaluation target signal Sx and the reference signal Se are set as input signals to be synchronized. In this example, the evaluation target signal Sx (e.g., S2) is sampled by the sampler SM2 using the sampling clock signal φ2.

[0057] An example is shown in which the phase Pφe varies within a range R(Pφe) of five UIs of the serial data signal DATA-S.

[0058] In the first case (Case 1), the rising edge Eφe of the sampling clock signal φe coincides with the position of data D1 and the position of data D6, and the true value of data D6 is output in the reference signal Se after the true value of data D1. In this case, there is no boundary position between data in the reference signal Se within the vicinity of the rising edge Eφ7 of the sampling clock signal φ7 (setup time ST, hold time HD), so no setup time violation or hold time violation occurs.

[0059] In the second case (Case 2), the rising edge Eφe of the sampling clock signal φe coincides with the position of data D3 and the position of data D8, and the truth value of data D3 is output followed by the truth value of data D8 in the reference signal Se. In this case, the boundary position between data in the reference signal Se is within the vicinity (setup time ST) of the rising edge Eφ7 of the sampling clock signal φ7, resulting in a setup time violation.

[0060] In the third case (Case 3), the rising edge Eφe of the sampling clock signal φe coincides with the position of data D4 and the position of data D9, and the truth value of data D4 is output followed by the truth value of data D9 in the reference signal Se. In this case, the boundary position between data in the reference signal Se is within the vicinity (hold time HD) of the rising edge Eφ7 of the sampling clock signal φ7, so a hold time violation occurs.

[0061] In this example, to sufficiently separate the region where these errors occur from the eye diagram formation region, the time from the rising edge Eφ2 of the sampling clock signal φ2 of the evaluation target signal Sx (e.g., S2) to the rising edge Eφ7 of the sampling clock signal φ7 is set to R(Pφe) / 2 (2.5 UI). For this purpose, it can be set to, for example, 2≦(R(Pφe) / 2)≦8.

[0062] (CDR circuit) FIG. 10 is a block diagram of a typical CDR circuit.

[0063] This CDR circuit includes a phase difference detector 72, a filter 73, and a voltage-controlled oscillator 74. A serial data signal Data and a clock signal Clock are input to the phase difference detector 72. The CDR circuit generates a clock signal based on edge information of the input data.

[0064] FIG. 11 is a timing chart for explaining the operation of the CDR circuit shown in FIG.

[0065] The phase difference detector 72 detects the phase difference between the transition edge position of the serial data signal Data and the rising edge position of the clock signal Clock. If the serial data signal Data is ahead, it outputs a positive pulse signal UP having a width corresponding to this phase difference. If it is behind, it outputs a negative pulse signal DOWN having a width corresponding to this phase difference. The (low-pass) filter 73 integrates and smooths the positive pulse signal UP and the negative pulse signal DOWN to output a voltage corresponding to the phase difference. The voltage-controlled oscillator 74 reduces the repetition frequency of the clock signal Clock if the phase is ahead of the reference (if the integrated value of the width of the positive pulse signal is large and the input voltage is positive), and increases the repetition frequency of the clock signal Clock if the phase is behind the reference (if the integrated value of the width of the negative pulse signal is large and the input voltage is negative).

[0066] 2 is arranged after the second synchronization circuit 13B, a parallel data signal is input thereto, and the CDR circuit 17 is different from the CDR circuit having the structure shown in Fig. 10. When the CDR circuit having the structure shown in Fig. 10 is applied to the receiving device shown in Fig. 2, for example, a configuration can be adopted in which the serial data signal DATA-S and the individual sampling clock signals φn (φ1 to φm) are input to the CDR circuit, and the sampling clock signals φn (φ1 to φm) are generated based on these input signals.

[0067] FIG. 12 is a block diagram of the CDR circuit 17.

[0068] The CDR circuit 17 is disposed after the second synchronization circuit 13B, and includes a phase difference detector 172, a filter 173, a voltage-controlled oscillator 174, and a multi-phase clock signal generator 175. The CDR circuit 17 receives the parallel data signals (digital signals S1OUT to SmOUT) output from the second synchronization circuit 13B.

[0069] Each digital signal S1OUT to SmOUT has information of "1" or "0." The arrangement of these "1"s and "0"s as a whole contains phase difference information. In other words, this phase difference information is information about the phase difference between the phase of the serial data signal DATA-S and the phase of the sampling clock signal in the data receiving samplers SM1 to SMm. This phase difference information is information about whether the phase of each sampling clock signal φ1 to φm is ahead of the phase of the serial data signal DATA-S (FAST) or behind (SLOW).

[0070] FIG. 13 is a timing chart for explaining the phase difference of data in the CDR circuit shown in FIG.

[0071] Of the digital signals S1OUT to SmOUT shown in Fig. 12, the odd-numbered signals (S1OUT, S3OUT, S5OUT, S7OUT, S9OUT) have data sampled at the edge positions of the serial data signal DATA-S by the odd-numbered samplers (SM1, SM3, SM5, SM7, SM9) in Fig. 2. The even-numbered signals (S2OUT, S4OUT, S6OUT, S8OUT, S10OUT) are sampled at the center positions of the pulse width of the serial data signal DATA-S.

[0072] In this case, if the data arrangement of the digital signals S2OUT, S3OUT, and S4OUT sampled with the sampling clock signals φ2, φ3, and φ4 is, for example, "0,0,1" or "1,1,0," the rising edge of the sampling clock signal φ3 is ahead of the edge of the serial data signal DATA-S (FAST).

[0073] Conversely, if the data arrangement of the digital signals S4OUT, S5OUT, and S6OUT sampled with the sampling clock signals φ4, φ5, and φ6 is "0, 1, 1" or "1, 0, 0," the rising edge of the sampling clock signal φ5 is delayed (SLOW) from the edge of the serial data signal DATA-S.

[0074] Data arrays other than these, such as "1,0,1" or "1,1,1", are ignored as exceptions.

[0075] Referring back to FIG. 12, the phase difference detector 172 detects whether the rising edges of the odd-numbered sampling clock signals (φ1, φ3, φ5, φ7, φ9) are ahead or behind the data boundary positions of the serial data signal based on the data sequence of the input digital signals S1OUT through SmOUT, e.g., 10-digit digital data. The phase difference detector 172 stores a determination table for leading (FAST) data sequences and lagging (SLOW) data sequences, and outputs "1" if the data sequence matches the former and "0" if the data sequence matches the latter, thereby making it possible to determine whether the input data is in FAST or SLOW status. The logic circuit that determines whether the three data are a match can be configured, for example, by arranging three AND circuits in parallel and inputting the three outputs into a three-input AND circuit.

[0076] When the phase difference detector 172 outputs a phase difference information signal (for example, four FASTs and one SLOW, resulting in an arrangement of "1, 1, 1, 1, 0"), the (low-pass) filter 173 outputs, for example, a DC voltage obtained by integrating and smoothing these pulse signals. In this case, it can be determined that the phase of the sampling clock signal is advanced overall, so the voltage-controlled oscillator 174 reduces the repetition frequency of the clock signal. This operation is the same as that of the general CDR circuit shown in FIG. 10; if it is determined that the phase is delayed overall, the opposite operation is performed. Note that other methods are known for controlling the repetition frequency of the clock signal in a CDR circuit, and such methods can also be used.

[0077] As described above, in the CDR circuit 17, if the number of FASTs is large, the clock frequency of the voltage-controlled oscillator is lowered, and if the number of SLOWs is large, the clock frequency of the voltage-controlled oscillator is raised. By repeating this process, the odd-numbered rising edges of the sampling clock signals φ1 to φm are aligned with the edges of the serial data signal DATA-S, thereby obtaining a sampling clock signal that is aligned with the serial data signal.

[0078] The clock signal output from the voltage-controlled oscillator 174 is input to a multi-phase clock signal generator 175. The multi-phase clock signal generator 175 generates multiple sampling clock signals φ1 to φm with different phases from a single input clock signal. The multi-phase clock signal generator 175 can be configured using, for example, one or multiple frequency dividers. It is also possible to connect multiple delay circuits in series after a single frequency divider and output each sampling clock signal from the output terminal of each delay circuit. It is also possible to connect multiple frequency dividers in parallel and set the reset timing of each frequency divider to a different value. Many types of multi-phase clock signal generators are known, so known circuits can be used.

[0079] As described above, the received signal quality monitor includes a second synchronization circuit 13B to which a plurality of output signals S1-Sm output from a plurality of data reception samplers SM1-SMm are input, and a CDR circuit 17 to which a plurality of output signals S1OUT-SmOUT output from the second synchronization circuit 13B are input and which generates multiphase clock signals (φ1-φm). Note that the CDR circuit 17 may be input with a selected portion of the output signals S1OUT-SmOUT rather than all of these output signals.

[0080] (Control circuit) The control circuit 18 generates and outputs a phase control signal PH-SEL that is input to the phase adjustment circuit 11 and a threshold control signal TH-SEL that is input to the voltage generator 12. The control circuit 18 outputs a reset control signal CNT-RESET and a stop control signal CNT-STOP that are input to the error counter 16. As described above, when a two-dimensional eye diagram is drawn, the error counter 16 counts the number of errors corresponding to each pixel of the eye diagram for a certain period (E-COUNT). This certain period (E-COUNT) is given from the input timing of the reset control signal CNT-RESET to the input timing of the stop control signal CNT-STOP, with the former input resetting the error counter 16 and the latter input terminating the count and causing the count value to be output.

[0081] (Desi Realizer) The digitalizer includes a plurality of data receiving samplers SM1 to SMm and a second synchronization circuit 13B.

[0082] The structure of each sampler SMn (SM1 to SMm) is the same as the structure of the reference sampler SMe shown in Figure 3. The multiple data reception samplers SM1 to SMm are also part of a received signal quality monitor. The serial data signal DATA-S received by the multiple data reception samplers SM1 to SMm is sampled in synchronization with the polyphase sampling clock signals φ1 to φm, respectively. The multiple data reception samplers receive the serial data signal, are connected in parallel, and are input with the polyphase sampling clock signals φ1 to φm, respectively.

[0083] (2nd synchronous circuit) FIG. 14 is a block diagram showing the structure of the second synchronization circuit 13B.

[0084] The second synchronization circuit 13B receives output signals S1 to Sm (e.g., m=10) output from a plurality of data receiving samplers SM1 to SMm. The second synchronization circuit 13B synchronizes the timing of the received output signals S1 to Sm and outputs them as parallel data output signals DATA-PO (S1OUT to SmOUT). Each output signal Sn (S1 to Sm) is input to a flip-flop group, which consists of two flip-flops connected in series. Each flip-flop is a D flip-flop.

[0085] The first output signal Sn (1≦n≦m) is input to the D terminal of the flip-flop preceding the nth flip-flop group. When n=1, 2, 3, 4, 10, the clock input terminal (C terminal) of the flip-flop preceding the flip-flop group receives the synchronizing sampling clock signal φK (e.g., φ7). When n=5, 6, 7, 8, 9, the clock input terminal (C terminal) of the flip-flop preceding the flip-flop group receives the synchronizing sampling clock signal φL (e.g., φ2).

[0086] The first output signal Sn' (1≦n≦m) sampled by the previous flip-flop is input to the D terminal of the subsequent flip-flop of the n-th flip-flop group. The synchronizing sampling clock signal φK (e.g., φ7) is input to the clock input terminal (C terminal) of the subsequent flip-flop of the n-th flip-flop group.

[0087] That is, the second synchronization circuit 13B performs final synchronization using the sampling clock signal φK (e.g., φ7). When n is an even number (2, 4, 6, 8, 10), the data is sampled at the median value of the pulse width of the serial data signal DATA-S. The output data can also be arranged in the order of n=10, 2, 4, 6, 9.

[0088] Next, a supplementary explanation will be given regarding data sampling.

[0089] FIG. 15(A) is a timing chart of the serial data signal DATA-S, and FIG. 15(B) is a timing chart showing the reference sampling clock signal φe.

[0090] The reference sampler SMe receives the serial data signal DATA-S and a sweepable reference threshold voltage Ve. Assume that the serial data signal DATA-S is, for example, "1, 0, 1, 0, 0, 1." The position of the rising edge Eφe of the sampling clock signal φe can be moved along the time axis and swept by the phase adjustment circuit 11 (see Figure 2). The figure also shows the threshold voltage V2 for the sampler SMn (e.g., SM2) used in the deserializer and the rising edge Eφn (e.g., Eφ2) of its sampling clock signal φn (e.g., φ2). The sampler SM2 samples the serial data signal at the rising edge Eφ2 and outputs a "1." The width of one data bit of the serial data signal DATA-S is the unit interval (UI).

[0091] For example, the reference position (0°) of the sweepable rising edge Eφe is the position of the first eighth rising edge Eφ8. The phase Pφe of the rising edge Eφe can be swept to the position of the next eighth rising edge Eφ8. Converted to UI, the phase Pφe can vary from 0 to N×UI (e.g., N=5), with a phase change range R(Pφe)=N×UI. Expressed in phase angle, the phase Pφe can vary from 0° to 360° (0°≦Pφe≦360°), with a phase change range R(Pφe)=360°. The period Tφe of the sampling clock signal φe can be set to Tφe=N×UI, but since the position of the rising edge Eφe is what is required, a different period may be used. For the same reason, the duty ratio of the sampling clock signal φe does not necessarily have to be 50%.

[0092] With respect to the period of the sampling clock signal φe (Tφe = N × UI), 2 ≦ N is preferable to reduce the sampling frequency. Furthermore, as mentioned above, to suppress the impact of setup time and hold time violations on the eye diagram, 3 ≦ N is preferable, and 4 ≦ N is even more preferable. Furthermore, if the duty ratio of the sampling clock signal is 50% and N is an odd number, the phase of the rising edge is doubled due to signal inversion. Therefore, it is preferable to set the parallel data signal to X = 2 × N bits (e.g., 10 bits). Therefore, although N = 5 or 7 is preferable, similar effects can be expected even when N = 2, 3, 4, or 6.

[0093] Note that when the clock frequency f of the sampling clock signal φe (or sampling clock signals φ1 to φ10) is given as the reciprocal (f=1 / T) of the time T of one unit of data, it is called full-rate transmission. When the clock frequency f is 1 / 4T, it is called quarter-rate transmission. When the clock frequency f is 1 / (N×T), it can be called (1 / N)-rate transmission. For example, in the above example, an m-phase clock (m=10) is used to transmit at a 1 / N rate (e.g., N=5) (m and N are integers, 2≦m, 2≦N, N≦m). Note that the number of clock signal lines required to transmit the clock signal is determined by the number of required clock signal phases, but is often N or 2×N.

[0094] As described above, the reference threshold voltage Ve is varied and swept by the voltage generator 12. In this way, the received signal quality monitor includes the voltage generator 12 that generates the variable reference threshold voltage Ve, and the reference threshold voltage Ve provides the vertical coordinate when drawing an eye diagram. By varying the reference threshold voltage Ve, the coordinate (Pφe, Ve) when drawing a two-dimensional eye diagram can be changed along the vertical axis. By varying the value of the phase Pφe using the phase adjustment circuit 11, the coordinate (Pφe, Ve) when drawing a two-dimensional eye diagram can be changed along the horizontal axis.

[0095] The threshold voltage Vn (e.g., V2) of any sampler can also be changed by the voltage generator 12. In this way, the received signal quality monitor is equipped with the voltage generator 12 that generates variable threshold voltages Vn (V1 to Vm). Furthermore, the threshold voltages Vn (V1 to Vm) input to the multiple data receiving samplers can be feedback controlled so that they are at the center of the amplitude of the serial data signal input to each sampler SMn (SM1 to SMm). For example, if the serial data signal DATA-S is a signal encoded using the 8b10b format, the number of "1s" and "0s" output from each sampler can be counted for a predetermined period of time. If the number of "1s" is greater than the number of "0s," it is determined that the threshold voltage Vn is lower than the center voltage of the amplitude of the serial data signal DATA-S, and the reference threshold voltage Ve is increased; if not, the reference threshold voltage Ve is decreased.

[0096] The threshold voltages Vn input to the multiple data receiving samplers are preferably set so that the input signal levels can be clearly distinguished. For example, if the level of data "1" is 1V and the level of "0" is -1V, the threshold voltage is set to 0V. Also, if the level of data "1" is 2V and the level of "0" is 0V, the threshold voltage is set to 1V.

[0097] FIG. 16 is a timing chart showing the serial data signal, the multiphase clock signals φ1 to φ10, and the clock signal φe.

[0098] Two signals are input to the first synchronization circuit 13A (see Figure 2). One signal is a signal obtained by sampling the serial data signal DATA-S at the rising edge Eφ2 of the sampling clock signal φ2. The other signal is a signal obtained by sampling the serial data signal DATA-S at the rising edge Eφe of the sampling clock signal φe. A signal sampled with a sampling clock signal φn (e.g., φ1 to φ10) is input to the second synchronization circuit 13B (see Figure 2). These synchronization circuits output the sampled data at the timing of the synchronization sampling clock signal φ7.

[0099] The phase Pφe of the rising edge Eφe moves within a phase change range R(Pφe). When one of the signals input to the first synchronization circuit 13A is obtained by sampling at the rising edge Eφn (e.g., Eφ2), it is preferable to set the phase interval from Eφ2 to Eφ7 to R(Pφe) / 2 (=2.5 UI). In other words, when the parallel data signal converted from the serial data signal has X bits, the phase interval (time) from the first rising edge Eφn to the second rising edge Eφ(n+X / 2) is set to (X / 4)×UI. As described above, the phase change range R(Pφe) is preferably set to 5×UI (=(X / 2)×UI).

[0100] FIG. 17 is a timing diagram of the serial data signal and the signals output from the synchronization circuits 13A and 13B.

[0101] The data of digital signals S2, S4, S6, and S8 sampled by sampler SMn (n is an even number), where n is an even number, is converted into data of digital signals S2', S4', S6', and S8' by the flip-flops in the previous stage in the second synchronization circuit 13B (see Figure 14), and then converted into data of digital signals S2OUT, S4OUT, S6OUT, and S8OUT by the flip-flops in the subsequent stage, and output from the second synchronization circuit 13B with the edge phases between the data aligned.

[0102] FIG. 18 is a block diagram of another receiving device RX.

[0103] The receiver RX in Fig. 18 differs from the receiver RX in Fig. 2 only in the configurations of the phase adjustment circuit 11 and the input unit 110, with the other configurations being the same. The input unit 110 in this example has a connection structure that inputs only one sampling clock signal φ1 to the phase adjustment circuit 11. The sampling clock signal input to the phase adjustment circuit 11 may be a sampling clock signal other than φ1.

[0104] FIG. 19 is a block diagram of the phase adjustment circuit 11 shown in FIG.

[0105] A single sampling clock signal φ1 is input to the phase adjustment circuit 11. Multiple inverter circuits (NOT circuits 11a, 11b, 11c, 11d, . . . 11s, and 11t) are connected in series, and every two output terminals of the inverter circuits are input to a multiplexer 11C (selection circuit). A pair of inverter circuits forms a delay circuit, which delays the input sampling clock signal φ1 and outputs it. Multiple sampling clock signals with different rising edge times are input to the multiplexer 11C. A phase control signal PH-SEL (phase or clock selection signal SEL0) selects one sampling clock signal from the m sampling clock signals input to the multiplexer 11C and outputs a sampling clock signal φe with a specific phase. The phase of the sampling clock signal φe can be adjusted and swept by switching the signal selected by the phase control signal PH-SEL (phase or clock selection signal SEL0).

[0106] The transmission method for the above-mentioned serial data signal is, for example, an NRZ (Non Return to Zero) signal, and the serial data signal has two voltage levels. Therefore, one threshold voltage is input to each sampler, and two levels can be determined. PAM4 (Pulse Amplitude Modulation 4) is a signal transmission method that uses four voltage levels. When a PAMk (3≦k) signal transmission method is used and the voltage level is three or more, a multi-level sampler that can distinguish these levels is used. Although multiple data reception samplers SM1 to SMm are shown above, they have the same structure. Therefore, the following describes the structure in which one data reception sampler SM1 is changed to a multi-level sampler as a representative of these samplers.

[0107] FIG. 20 is a block diagram showing the structure of a multi-value sampler.

[0108] When receiving a serial data signal (PAM4) with four voltage levels, three threshold voltages are required to distinguish between them, resulting in an eye diagram with three eye openings. Generalizing, when receiving a serial data signal with k levels, k-1 threshold voltages are required to distinguish between them, resulting in an eye diagram with k-1 eye openings. This figure shows the case of receiving a PAM4 serial data signal. The data receiving sampler SM1 includes a first data receiving sampler SM1high, a second data receiving sampler SM1mid, and a third data receiving sampler SM1low. The structure of each sampler is the same as that shown in Figure 3. A high-level threshold voltage V1high (first threshold voltage), a mid-level threshold voltage V1mid (second threshold voltage), and a low-level threshold voltage V1low (third threshold voltage) are input to each sampler. A first sampling clock signal φ1 is input to each sampler, and a first output signal S1high, a second output signal S1mid, and a third output signal S1low are output.

[0109] FIG. 21 is a graph showing the change in the input voltage (V) to the multi-level sampler over time.

[0110] If the data contained in the serial data signal is the first data DATA1, and this is input to the first data receiving sampler SM1high, the second data receiving sampler SM1mid, and the third data receiving sampler SM1low, at the sampling timing of the sampling clock signal φ1, the input voltage is higher than all threshold voltages, so the outputs of the first, second, and third samplers are (S1high, S1mid, S1low) = (1,1,1). Using a data conversion table, (1,1,1) can be converted to "11".

[0111] Similarly, if the data contained in the serial data signal is the second data DATA2, and this is input to the first data receiving sampler SM1high, the second data receiving sampler SM1mid, and the third data receiving sampler SM1low, the outputs of the first, second, and third samplers at the sampling timing of the sampling clock signal φ1 will be (S1high, S1mid, S1low) = (0, 1, 1). Using a data conversion table, (0, 1, 1) can be converted to "10."

[0112] Similarly, if the data contained in the serial data signal is third data DATA3, and this is input to the first data receiving sampler SM1high, the second data receiving sampler SM1mid, and the third data receiving sampler SM1low, the outputs of the first, second, and third samplers will be (S1high, S1mid, S1low) = (0,0,1) at the sampling timing of the sampling clock signal φ1. Using a data conversion table, (0,0,1) can be converted to "01."

[0113] Similarly, if the data contained in the serial data signal is the fourth data DATA4, and this is input to the first data receiving sampler SM1high, the second data receiving sampler SM1mid, and the third data receiving sampler SM1low, the outputs of the first, second, and third samplers will be (S1high, S1mid, S1low) = (0,0,0) at the sampling timing of the sampling clock signal φ1. Using a data conversion table, (0,0,0) can be converted to "00".

[0114] As described above, using a multi-level sampler makes it possible to separate and distinguish PAM4 signal levels and deserialize them. Similar to the above, a synchronization circuit can be installed after multiple multi-level samplers. Note that it is not necessary to use all of the sampler output signals to obtain an eye diagram.

[0115] FIG. 22 is a block diagram showing the multi-value sampler and the subsequent circuit configuration.

[0116] The structure of the data reception sampler SM1 is as shown in FIG. 20. The output signal S1high of the first data reception sampler SM1high and the reference signal Se of the reference sampler SMe are input to a first synchronization circuit 13A. The structure of the reference sampler SMe is the same as that shown in FIG. 3, and the subsequent circuits and remaining circuits may be the same as those described above. That is, the receiving device includes a comparison logic circuit 15 and an error counter 16. A serial data signal and a reference threshold voltage Ve are input to the reference sampler SMe, and sampling is performed using a sampling clock signal φe. This reference threshold voltage Ve is variable, and only one voltage is required. In this example, an eye diagram can be obtained in the same manner as above.

[0117] When the signal transmission method is PAM4, using all three levels of sampler output using thresholds allows for more precise signal quality measurement, but signal quality can also be evaluated using only one level of threshold judgment output. This has the advantage of simplifying the circuit configuration. While the figure shows an example in which a high-level threshold voltage V1high is used as one level of threshold, examples in which a mid-level threshold voltage V1mid or a low-level threshold voltage V1low are also possible.

[0118] FIG. 23 is a graph showing the change over time of the input voltage (V) to the first data receiving sampler SM1high and the reference sampler SMe.

[0119] If the data included in the serial data signal is first data DATA1, when this is input to the first data receiving sampler SM1high, the output signal S1high of the first data receiving sampler SM1high becomes "1" at the timing of the sampling clock signal φ1. When the first data DATA1 is input to the reference sampler SMe, the reference signal Se output from the reference sampler SMe becomes "1" at the sampling timing of the sampling clock signal φe.

[0120] Similarly, if the data included in the serial data signal is second data DATA2, when this is input to the first data receiving sampler SM1high, the output signal S1high of the first data receiving sampler SM1high becomes "0" at the timing of the sampling clock signal φ1. When the second data DATA2 is input to the reference sampler SMe, the output signal Se of the reference sampler SMe becomes "1" at the sampling timing of the sampling clock signal φe.

[0121] Similarly, if the data included in the serial data signal is the third data DATA3 or the fourth data DATA4, when this is input to the first data receiving sampler SM1high, the output signal S1high of the first data receiving sampler SM1high will be "0" at the timing of the sampling clock signal φ1. When the third data DATA3 or the fourth data DATA4 is input to the reference sampler SMe, the output signal Se of the reference sampler SMe will be "0" at the sampling timing of the sampling clock signal φe.

[0122] FIG. 24 is a block diagram showing the structure of a multi-value sampler and a subsequent circuit.

[0123] The circuit shown in FIG. 24 differs from the circuit shown in FIG. 22 in that a multiplexer 131 (selection circuit) is provided on the input side of the first synchronization circuit 13A, but the other configurations are the same. The multiplexer 131 receives multiple output signals from the first data reception sampler SM1high. These output signals are a first output signal S1high determined based on a high-level threshold, a second output signal S1mid determined based on a medium-level threshold, and a third output signal S1low determined based on a low-level threshold. These output signals (S1high, S1mid, S1low) are input to the multiplexer 131, and one of them is selected and output. The output signal selected by the multiplexer 131 is input to the first synchronization circuit 13A. By switching the signal selected by the multiplexer 131, three eye diagrams determined based on three threshold levels can be obtained. A selection signal for switching the output signals (S1high, S1mid, S1low) can be input to the multiplexer 131 from a control circuit or an external device. In this example, the input signal from the sampler to the first synchronization circuit 13A is switched, so the circuit size can be relatively small. The remaining circuit structure is the same as that shown in FIG. 22.

[0124] FIG. 25 is a block diagram showing the structure of a multi-value sampler and subsequent circuits.

[0125] The circuit shown in Fig. 25 omits the multiplexer shown in Fig. 24 and has a circuit configuration that processes all output signals (S1high, S1mid, S1low) of the first sampler in parallel without switching by a multiplexer. All output signals from the first sampler (first output signal S1high, second output signal S1mid, third output signal S1low) are input to a first synchronization circuit 13A.

[0126] The first synchronization circuit 13A receives the first output signal S1high, the second output signal S1mid, the third output signal S1low, and the reference signal Se output from the reference sampler SMe. The first synchronization circuit 13A synchronizes and outputs these input signals. The comparison logic circuit 15 described above is made up of a plurality of sub-comparison logic circuits.

[0127] The first output signal S1high is input to one input terminal of the first comparison logic circuit 15high. The second output signal S1mid is input to one input terminal of the second comparison logic circuit 15mid. The third output signal S1low is input to one input terminal of the third comparison logic circuit 15low. A reference signal Se is input to the other input terminal of each comparison logic circuit. Like the comparison logic circuit 15 shown in FIG. 2, each comparison logic circuit is preferably an XOR circuit, and outputs "0" if the logic of the input data matches, and "1" if they do not.

[0128] The output terminal of the first comparison logic circuit 15high is connected to the input terminal of the first error counter 16high. The output terminal of the second comparison logic circuit 15mid is connected to the input terminal of the second error counter 16mid. The output terminal of the third comparison logic circuit 15low is connected to the input terminal of the third error counter 16low. The processing in each error counter is the same as that of the error counter shown in Figure 2. With this circuit, parallel processing is performed on the three sampler outputs, making it possible to obtain a multi-value eye diagram in a short time.

[0129] As described above, in the received signal quality monitors of FIGS. 20 to 25, the serial data signal is a pulse amplitude modulated (PAM) signal having multiple values ​​of k levels (3≦k, k is an integer), and each of the multiple data receiving samplers includes k−1 samplers. To each of the k−1 samplers, threshold voltages (V1high, V1mid, V1low) of different levels are input along with the serial data signal. Each of the k−1 samplers outputs k−1 comparison results (S1high, S1mid, S1low). This configuration also makes it possible to process multi-value serial data signals.

[0130] 25, one sampler included in the plurality of data reception samplers outputs k-1 comparison results (S1high, S1mid, S1low) as a first output signal, and the k-1 comparison results and a second output signal (reference signal Se) of the reference sampler are input to first synchronization circuit 13A. Comparison logic circuit 15 includes k-1 sub-comparison logic circuits (15high, 15mid, 15low), and each of the k-1 sub-comparison logic circuits receives the k-1 comparison results (S1high, S1mid, S1low) synchronized and output from first synchronization circuit 13A and the second output signal (reference signal Se).

[0131] 26(A) and 26(B) are timing charts of exemplary serial data signals.

[0132] The serial data signal in Figure 26(A) is a periodic signal. The serial data signal in Figure 26(B) is a signal with a random or pseudo-random pattern. In the case of 1 / 5 rate transmission, when data sampling for an eye diagram is performed, data sampling is performed every 5 data and displayed overlaid in the center of the eye diagram. In other words, in either case of signal, after the data D1 is sampled, the data D6 is sampled.

[0133] The size of the eye diagram opening obtained from a periodic serial data signal (Figure 26(A)) is generally larger than the size of the eye diagram opening obtained from a serial data signal with a random pattern (Figure 26(B)). Since it is preferable to measure transmission line characteristics assuming all possible inputs, when accurately evaluating the quality of a received signal, it is preferable to receive a serial data signal with a random or pseudo-random pattern.

[0134] As explained above, the above-mentioned received signal quality monitor comprises a plurality of data receiving samplers SM1 to SMm, each of which receives a serial data signal DATA-S and is connected in parallel, and each of which receives a clock signal included in a multi-phase clock signal as input to an input terminal of a sampling clock signal φn (1≦n≦m, m and n are integers), a reference sampler SMe that receives a serial data signal, one or more input terminals to which one or more clock signals included in the multi-phase clock signal are input, and an input terminal of a sampling clock signal φe of the reference sampler. The signal processing circuit includes a phase adjustment circuit 11 having an output terminal connected to a terminal and capable of sweeping the phase of an output sampling clock signal φe within a phase range (N×UI) of N times the unit interval (UI) of the serial data signal (2≦N), a first synchronization circuit 13A that receives a first output signal of one sampler included in a plurality of data receiving samplers and a second output signal of a reference sampler SMe and outputs the first and second output signals in synchronization with each other, and a comparison logic circuit 15 that receives the first and second output signals in synchronization with each other from the first synchronization circuit 13A. The comparison logic circuit 15 receives the first and second output signals in synchronization with each other from the first synchronization circuit 13A and outputs a comparison result related to the quality of the received signal.

[0135] In the above-described receiving device, the frequency of the sampling clock signal φn is preferably 1 / N (2≦N) of the frequency of the serial data signal DATA-S. The received signal quality monitor is equipped with a phase adjustment circuit 11 capable of sweeping the phase of the output sampling clock signal φe within a phase range (N×UI) that is N times (2≦N) the unit interval (UI) of the serial data signal (within a phase range several times larger). The phase sweep of the sampling clock signal φe is possible within a phase range several times larger than the UI. Preferably, if the frequency of the received sampling clock signal φn is 1 / N (e.g., N=5) of the frequency given by the reciprocal of the time width of one data bit of the input serial data signal, the swept phase range is N×UI (e.g., N=5 (phase sweep range 360°)). This phase range is effective in reducing the effects of setup and hold violations, even when the phase range is greater than (N / 2)×UI (e.g., 2.5UI). Furthermore, it is preferable that the phase range (phase change range R(Pφe)) adjusted by the phase adjustment circuit 11 be equal to or greater than one period (N×UI in the example of Figure 15) of the sampling clock signal φe input to the reference sampler. By expanding the phase range, it becomes easier to acquire the eye opening even if its position moves.

[0136] In the above-described receiving device, the phase adjustment circuit 11 is placed before the reference sampler SMe, but no phase adjustment circuits for delay adjustment are placed before the other samplers. Compared to receiving devices that require such phase adjustment circuits for delay adjustment, the above-described receiving device can reduce circuit area and power consumption. Furthermore, by setting the phase sweep range as described above, if a delay adjustment circuit is not placed before each sampler, the effect of the inherent delay of such a delay adjustment circuit can be suppressed. Furthermore, even if an unintended inherent delay occurs in the phase adjustment circuit 11 due to changes in the operating environment, etc., an eye diagram can be obtained because the phase sweep range is as wide as described above.

[0137] We have thus disclosed a phase adjustment circuit technology for an eye monitor in a data receiving device that uses a multiphase clock signal. In this technology, the input data is preferably a random pattern. The phase adjustment range by the phase adjustment circuit is set wide. Furthermore, synchronization is achieved in the comparison logic circuit to prevent synchronization errors in the portion related to the eye diagram opening. This eliminates the need to add a dummy circuit for the phase adjustment circuit or a phase compensation circuit to the path of the multiphase clock signal to cancel out the inherent delay of the phase adjustment circuit, thereby reducing power consumption and area.

[0138] Here is some additional information about evaluating signal quality. Signals received via transmission lines are subject to degradation due to factors such as the load on each line. The quality of a transmission signal can be determined by looking at the eye opening of an eye diagram. An eye diagram is a signal superimposed on another, with one cycle consisting of two of the smallest units of transmission data. Eye opening refers to the size of the opening at the center of the eye diagram. The higher and wider the opening, the better the signal quality is evaluated to be. Signal quality can also be evaluated by evaluating a portion of the quality monitor signal, rather than the entire eye opening. Only evaluate the opening dimension along the vertical axis passing through the center of the eye opening. Only evaluate the opening dimension along the horizontal axis passing through the center of the eye opening. Evaluate the opening dimension passing through an appropriate position on the eye opening. Evaluate the opening dimension in the diagonal direction of the eye opening. As such, various evaluation methods are possible.

[0139] In recent years, the data rates required for communication data have been increasing due to the widespread use of communication devices, paperless systems, and the spread of telecommuting. The above-mentioned receiving device transmits data using a multi-phase clock (m-phase clock), so it can handle high data rate communications. The above-mentioned receiving device consumes little power and has a small area. This effect becomes greater as N in 1 / N rate transmission increases, but the above-mentioned device can also perform appropriate synchronization. [Explanation of symbols]

[0140] 11...phase adjustment circuit, 11A...multiplexer, 11B...phase interpolator, 11C...multiplexer, 12...voltage generator, 13A...first synchronization circuit, 13B...second synchronization circuit, 13DIV...frequency divider, 15...comparison logic circuit, 16...error counter, 17...CDR circuit, 18...control circuit, 72...phase difference detector, 73...filter, 74...voltage controlled oscillator, 101...amplifier, 110...input section, 131...multiplexer, 172...phase difference detector, 173...filter, 174...voltage controlled oscillator, 175...multiphase clock signal generator, 300...external device, 301...memory, 303...interface, 304...bus, 305...display, CB...communication cable, COMP...comparator, OUTPUT...quality monitor signal, SM1 to SMm...data receiving sampler, SMe...reference sampler.

Claims

1. a plurality of data receiving samplers that receive serial data signals, are connected in parallel, and each receive a multiphase sampling clock signal; a reference sampler receiving the serial data signal; a phase adjustment circuit capable of sweeping the phase of a sampling clock signal input to the reference sampler within a phase range of N times (2≦N) the unit interval (UI) of the serial data signal; a first synchronization circuit to which an output signal of one of the plurality of data receiving samplers and an output signal of the reference sampler are input; a comparison logic circuit to which the two output signals outputted in synchronization from the first synchronization circuit are input; A received signal quality monitor.

2. The phase range adjusted by the phase adjustment circuit is:

2. The received signal quality monitor according to claim 1, wherein the reference sampler receives one or more periods of the sampling clock signal.

3. further comprising a counter that counts the output result of the comparison logic circuit; 2. The received signal quality monitor of claim 1.

4. The reference sampler comprises: a first input terminal for receiving the serial data signal; a second input terminal to which a variable reference threshold voltage is input; Equipped with sampling a comparison result between the serial data signal and the reference threshold voltage in synchronization with the sampling clock signal capable of phase sweep; 2. The received signal quality monitor of claim 1.

5. Each sampler included in the plurality of data receiving samplers comprises: a first input terminal for receiving the serial data signal; a second input terminal to which a threshold voltage is input; Equipped with sampling the result of the comparison between the serial data signal and the threshold voltage in synchronization with a sampling clock signal that is included in the multiphase sampling clock signal and that corresponds to the sampler; 5. The received signal quality monitor of claim 4.

6. a second synchronization circuit to which a plurality of output signals output from the plurality of data receiving samplers are input; a CDR circuit that receives the plurality of output signals from the second synchronization circuit and generates the multiphase sampling clock signals; Equipped with 2. The received signal quality monitor of claim 1.

7. the serial data signal is a pulse amplitude modulated (PAM) signal having multiple values ​​of k levels (3≦k, k is an integer); Each of the plurality of data receiving samplers includes k-1 samplers, and threshold voltages having different levels are input to each of the k-1 samplers together with the serial data signal, and k-1 comparison results are output from each of the k-1 samplers.

2. The received signal quality monitor of claim 1.

8. one sampler included in the plurality of data receiving samplers outputs the k-1 comparison results; the k-1 comparison results and the output signal of the reference sampler are input to the first synchronization circuit; the comparison logic circuit comprises k-1 sub-comparison logic circuits; The k-1 sub-comparison logic circuits each receive an output signal synchronously output from the first synchronization circuit.

8. A received signal quality monitor according to claim 7.

9. The phase adjustment circuit a selection circuit to which the multiphase sampling clock signals output from the CDR circuit are input; a phase interpolator to which the output signal of the selection circuit is input; Equipped with 7. A received signal quality monitor according to claim 6.

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