Memory Erase Using Proximity Heater

Abstract

A memory array having memory cells can include one or more heaters embedded between the memory cells in the memory array, and a processor in communication with the heaters can signal the heaters to activate when a trigger event occurs.

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of digital memory, and more particularly to erasing data from memory devices. [Background technology]

[0002] Elements of secure computing include authentication, sending data to authorized sources, or loading data onto designated devices, or a combination of these. Cryptographic keys are stored in non-volatile memory and may reside on integrated circuits (ICs). Unauthorized access can compromise the security of the data by retrieving the cryptographic keys from the device. Summary of the Invention

[0003]

[0001] Embodiments of the present disclosure relate to a memory system, a method for manufacturing the same, a computer system, a computer program product, and a method for erasing memory. Some embodiments of the present disclosure for erasing memory may include a memory array having memory cells. The memory array may incorporate one or more heaters between the memory cells. When a trigger event occurs, a processor in communication with the heaters may signal the heaters to activate.

[0004] The above summary is not intended to describe each example embodiment or every implementation of the present disclosure.

[0005] The drawings included in this disclosure are incorporated into and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of particular embodiments and do not limit the disclosure. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 illustrates an exemplary circuit with built-in memory erase functionality according to the present disclosure. [Figure 2a] FIG. 1 is a side view of an exemplary memory device with built-in memory erasure functionality in accordance with an embodiment of the present disclosure. [Figure 2b] FIG. 1 is a top view of a memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 3a] FIG. 1 is a side view of an exemplary memory device with built-in memory erasure functionality in accordance with an embodiment of the present disclosure. [Figure 3b] FIG. 1 is a top view of a memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 4a] FIG. 1 is a side view of an exemplary memory device with built-in memory erasure functionality in accordance with an embodiment of the present disclosure. [Figure 4b] FIG. 1 is a top view of a memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 5a] 1 is a side cross-sectional view of an exemplary memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 5b] 1 is a top cross-sectional view of a memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 6] 1 illustrates a method for manufacturing an exemplary memory device with built-in memory erase functionality according to an embodiment of the present disclosure. [Figure 7] FIG. 1 illustrates a memory erasure system according to an embodiment of the present disclosure. [Figure 8] FIG. 1 illustrates a cloud computing environment according to an embodiment of the present disclosure. [Figure 9] FIG. 1 illustrates abstraction model layers according to an embodiment of the present disclosure. [Figure 10] FIG. 1 illustrates a high-level block diagram of an exemplary computer system that can be used to implement one or more of the methods, means, and modules and any associated functionality described herein, in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] While the embodiments described herein are susceptible to various modifications and alternative forms, specific details of the embodiments have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that the particular embodiments described are not to be construed in a limiting sense. On the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure.

[0008]

[0001] The present disclosure relates generally to the field of memory, and more particularly to erasing data from a memory device. Further aspects of the present disclosure will be apparent to those skilled in the art. Some of these aspects are further described below.

[0009] Embodiments of the present disclosure include memory systems, methods for manufacturing the same, computer systems, computer program products, and methods for memory erasure. Some embodiments may include a memory array having memory cells. The memory array may incorporate one or more heaters between the memory cells. When a trigger event occurs, a processor in communication with the heaters may signal the heaters to activate.

[0010] In some embodiments of the present disclosure, the memory cells can be non-volatile phase change memory. In some embodiments, activation of a heater causes at least one non-volatile phase change memory cell to change from a first phase to a second phase, and in some embodiments, the first phase is amorphous and the second phase is crystalline. In some embodiments, the memory cell is an encryption memory that stores an encryption key.

[0011] Some embodiments of the present disclosure include using a thermally conductive and electrically insulating material to separate the heater from the memory cell. In some embodiments, the material is boron nitride or aluminum nitride.

[0012] Some embodiments of the present disclosure may include a power supply capable of powering the notification system, the heater, or both. In some embodiments of the present disclosure, the power supply may be integrated into the memory system.

[0013] In some embodiments of the present disclosure, the processor is the tamper detection unit. In some embodiments of the present disclosure, the tamper detection unit may be embedded in the memory system.

[0014] To aid in understanding the present disclosure, FIG. 1 illustrates a cross-sectional view of a memory system 100 with built-in memory erasure capabilities in accordance with the present disclosure. Before describing the figures in detail, it should be noted that like reference numerals are used to designate like parts throughout the accompanying drawings. Memory system 100 includes a substrate 110, which may be a semiconductor (e.g., crystalline silicon, germanium, gallium arsenide, some other similar material, or some combination thereof). Memory system 100 also includes one or more dielectric layers 112 and 160 and a transistor 114. Memory system 100 also includes electrodes 116 and 118 (e.g., metal, such as tungsten vias and first layer metal).

[0015] The memory system 100 further includes a phase change memory (PCM) 120. One or more heaters 140 can be thermally coupled to the PCM 120. The heaters 140 can be separated from the PCM 120 by a material 130. The material 130 can be thermally conductive to facilitate heat transfer between the heaters 140 and the PCM 120. The material 130 can be electrically insulating to keep the heaters 140 and the PCM 120 circuitry separated. A processor 150 communicates with the heaters 140 and signals them to activate when a trigger event occurs, thereby heating the PCM 120 through the thermally conductive, electrically insulating material 130. The processor 150 can be, for example, a notification unit, a tamper detection unit, or any other device that can activate the heaters 140. The processor 150 can activate the heaters 140 as a result of the trigger event.

[0016] A trigger event may be used to activate memory erasure. A trigger event may be any occurrence that results in activation of a particular protocol. In this disclosure, a trigger event refers to a threshold that may be met to activate memory erasure. Trigger events include, for example, reaching the end of a subscription (e.g., the threshold is a date), receiving a manual command to delete (e.g., the threshold is a configuration input value), identifying a tampering attempt (e.g., the threshold is recognition of attempted unauthorized access), or other similar occurrences. An expiration trigger may be tied to an external system (e.g., a remote subscription calendar), an internal system (e.g., a date and / or time entered into a calendar on a local device), or some combination of these. Attempted tampering may be identified by various means, including, for example, removing a memory module from a rack without providing the proper access code, attempting to circumvent the device's enclosure, or otherwise recognizing unauthorized tampering with the device.

[0017] Tampering may involve reverse engineering the contents of a memory selection, such as reverse engineering the contents of a cryptographic key. Many physical reverse engineering techniques require access to the chip structure by imaging (e.g., electron beam from a scanning electron microscope, focused ion beam, x-ray, etc.), thus generating radiation (e.g., photocurrent, laser beam induced current, electron beam induced current, etc.). Some embodiments of the present disclosure can utilize this principle, using a photovoltaic cell to convert radiation from a tamper attempt into a current that triggers a tamper response (e.g., heater activation power supply) to erase data.

[0018] Tampering may involve unauthorized physical access (e.g., unauthorized removal of a computer board from a computer or opening a box containing a computer chip). Tampering may include unauthorized access of a secure room. In some embodiments, intrusion may be detected by sensors, which may include, for example, light, temperature, humidity, pressure sensors, similar detectors, or some combination thereof.

[0019] Tampering may include electrical probing and delayering to extract secret keys in order to introduce faults (e.g., flipping states) to force the device into unauthorized operation. Unauthorized access attempts typically employ a series of techniques to locate specific circuits and structures. These techniques usually involve imaging or radiation to induce currents and faults. Again, some embodiments of the present disclosure can redirect energy from the radiation or current to activate a tamper-resistant device and erase the target memory and / or memory containing the target memory's encryption key. For example, a photovoltaic cell can automatically capture energy from a tamper attempt and redirect it to power operation of the heater 140.

[0020] Heating the PCM120 can change the state of the phase change material in the PCM120 (e.g., from amorphous to crystalline). Changing the state of the phase change material in the PCM120 changes the data held in the PCM120. The PCM120 can be heated to change the state of the phase change material in the PCM120. Alternatively, the phase change material in the PCM120 can be heated and remain in the same state (e.g., if the phase change material in the PCM120 is already in a crystalline state, it will remain in the crystalline state when heated). PCM120 cells may be clustered together to contain data. The collective data contained in a cluster of PCM120 cells can be changed by changing the state of the phase change material in one or more of the PCM120 cells in the cluster. Some of the PCM120 cells can maintain their original state (e.g., remain in a crystalline state). Changing the state of the phase change material in one or more of the PCM120 cells in a cluster changes the collective data held by the cluster. Thus, changing the state of the phase change material in the PCM120 cells within a cluster of PCM120 cells erases the data contained within the cluster.

[0021] It is not necessary for all PCM120 cells to change from one state to another (e.g., from amorphous to crystalline) for the data held by the memory cluster to be erased. In fact, some PCM120 cells may already be in a crystalline state and will remain in the crystalline state when the heater 140 is activated. Data stored in the memory of a PCM120 cell cluster can be erased, for example, by resetting some or all of the PCM120 cells to the amorphous phase or by setting all of the cells to the crystalline state.

[0022] A memory cell cluster may be any grouping or collection of memory. For example, a cluster of PCM120 cells may be an 8-bit array of PCM120. A memory cell cluster may also be an array of memory cells, a memory chip, a subsection of a memory chip (e.g., a dedicated storage memory section, a section dedicated to storing cryptographic keys, an encoder / decoder, etc.), a cache, a hard drive, or the like.

[0023] Processor 150 can trigger activation of heater 140 when a trigger event occurs. Processor 150 can be, for example, a tamper detection unit that can be used to identify attempted unauthorized access to data held by memory protected by memory system 100. For example, the tamper detection unit can be used to identify unauthorized physical access to a memory chip or unauthorized access to the packaging of a memory chip.

[0024] In some embodiments, processor 150 may be communicatively coupled to a subscription service database such that expiration of a particular user's subscription can trigger a notification system to erase that particular user's login credentials. In some embodiments, processor 150 may be coupled in a manner that allows the subscription service database to erase a designated PCM 120 cell only if a triggering event occurs (e.g., the subscription service database may be physically disconnected from processor 150 except at a pre-set date, at which time the subscription service database may verify the subscription status and erase login information for expired accounts). In some embodiments, memory system 100 may not be connected to any external systems such that PCM 120 cells can be erased only through on-site access. Preventing external access may be preferable, for example, as a security measure against unauthorized memory erasure via external access.

[0025] Memory system 100 with memory erasure functionality may be part of or incorporated into another system. In some embodiments, the memory erasure circuitry is electrically isolated from the rest of the memory chip; for example, the memory erasure circuitry may be incorporated into the memory chip but not part of the same circuitry as the memory storage. As shown, memory system 100 includes wiring 180 that may be connected to external memory, encryption devices, memory readers, processor registers, or other components, or a combination thereof. The memory erasure functionality of memory system 100 may be used to protect a larger system and the information it holds, for example, by erasing the memory of PCM 120 cells that hold encryption keys. For example, a trigger event may cause the erasure of memory holding encryption keys, such that data encrypted using the encryption keys and held in main memory is rendered essentially worthless. In some embodiments, erasing only the encryption keys prevents decryption, and a copy of the encryption keys may be kept elsewhere to prevent unauthorized access by protecting the data from being wasted.

[0026] Encryption keys according to the present disclosure can be used in any encrypted memory system. In some embodiments, memory system 100 may include an encryption key for an encrypted database such that erasure of data held within memory system 100 prevents unauthorized users from interpreting data retrieved from the encrypted database. In such embodiments, another copy of the encryption key may exist such that upon regaining control of the encrypted database, the database can be decrypted and used using another copy of the encryption key, thereby maintaining protection for the encrypted database while preventing loss of data in the encrypted database by eliminating the need to delete data in the event of unauthorized access.

[0027] 2a illustrates a cross-sectional view of a memory system 200 with embedded memory erasure capabilities according to an embodiment of the present disclosure, and FIG. 2b illustrates a top view of the memory system 200 with embedded memory erasure capabilities according to an embodiment of the present disclosure. The memory system 200 includes a substrate 210 and a dielectric 212. The memory system 200 further includes top electrodes 238, 258, and 278 to the storage elements and bottom electrodes 234, 254, and 274. The memory system 200 further includes electrodes 222, 226, 242, 246, 262, 266, 282, and 286 to the heaters, and the memory system 200 further includes vias 232, 252, and 272 connecting the bottom electrodes 234, 254, and 274 to the substrate 210. Memory system 200 also includes PCM cells 236, 256, and 276, heaters 224, 244, 264, and 284, and materials 291, 292, 293, 294, 295, and 296. Materials 291, 292, 293, 294, 295, and 296 may be thermal coupling materials.

[0028] Heaters 224, 244, 264, and 284 are proximate to PCM cells 236, 256, and 276. Materials 291, 292, 293, 294, 295, and 296 are disposed between heaters 224, 244, 264, and 284 and PCM cells 236, 256, and 276. Materials 291, 292, 293, 294, 295, and 296 may be thermally conductive to facilitate heating of PCM cells 236, 256, and 276 by heaters 224, 244, 264, and 284. Materials 291, 292, 293, 294, 295, and 296 may be electrically insulating to maintain heaters 224, 244, 264, and 284 insulated and separated from PCM cells 236, 256, and 276. Electrically isolating heaters 224, 244, 264, and 284 from PCM cells 236, 256, and 276 can prevent unintentional or intentional writing, rewriting, or overwriting data (e.g., a back door used for authorized access) to the memory system via heaters 224, 244, 264, and 284. Materials 291, 292, 293, 294, 295, and 296 can be, for example, boron nitride, aluminum nitride, diamond, other thermally conductive and / or electrically insulating materials, or some combination thereof.

[0029] Electrical flows 226a, 246a, 266a, and 286a are shown as moving electricity through electrodes 226, 246, 266, and 286. Electricity is shown flowing through top electrodes 226, 246, 266, and 286. In this embodiment, electricity flows through top electrodes 226, 246, 266, and 286, through heaters 224, 244, 264, and 284, through bottom electrodes 222, 242, 262, and 282, and through substrate 210. Note that, according to embodiments of the present disclosure, current may flow in other directions (e.g., from the top electrode through the heater to the bottom electrode, or orthogonally across the heater) such that heaters 224, 244, 264, and 284 can be powered by a power source and, when activated, heat PCM cells 236, 256, and 276. In some embodiments, if the heater is implemented using a resistive element, the direction of the current is not important.

[0030] In a cluster of PCM cells 236, 256, and 276, each cell may be heated individually (e.g., only one cell or one cell at a time), cluster-wise (e.g., heating one heater adjacent to multiple PCM memory cells), sequentially (e.g., heating the first PCM cell, then the second PCM cell, etc.), or simultaneously (e.g., all of the PCM cells 236, 256, and 276 in the cluster at once). Simultaneous heating of the PCM cells 236, 256, and 276 in a system may be used as a rapid response to a trigger event. For example, simultaneous heating of an entire PCM cluster may require as little as 10 nanoseconds to erase the data contained in the PCM cluster. Simultaneous erasure may be the preferred response to a trigger event because it can provide the fastest response and requires less power per heater to perform a full erase of the array.

[0031] The annealing time of PCM cells 236, 256, and 276, or the time required to fully crystallize the phase change material, depends on the phase change material used in the cells and the strength of the current pulse. Typical times for commonly used phase change materials are less than 1 microsecond. The materials used for the various components of memory system 200, including the PCM clusters, can affect the time required to erase the data held by the PCM clusters. Using certain materials for the various components of memory system 200, including the PCM clusters being erased, can require 300 nanoseconds to fully erase the PCM cluster data.

[0032] For the phase-change material to crystallize, the temperature of the PCM cells 236, 256, and 276 must exceed the crystallization temperature of the phase-change material. For example, the crystallization temperature of Ge2Sb2Te5 (GST225) is approximately 170°C. GST225 may be doped with elements such as nitrogen, oxygen, or carbon. This doping can alter the crystallization temperature. Oxygen doping can result in a GST225 crystallization temperature above 200°C, while carbon doping can push the crystallization temperature to approximately 300°C. A higher crystallization temperature may be necessary if the memory will operate in a high-temperature environment, such as an automobile. PCM cells 236, 256, and 276 are components of the memory system 200; therefore, the material of PCM cells 236, 256, and 276 can affect the time it takes to erase data in a PCM cluster. The time required must be sufficient to heat the PCM cells 236, 256, and 276 to a temperature high enough to achieve the crystalline phase. Reaching a temperature high enough for the PCM cells 236, 256, and 276 to reach the crystalline phase depends on the materials used in the PCM cells 236, 256, and 276. Generally, assuming standard atmospheric conditions, the PCM cells 236, 256, and 276 need to reach approximately 200 degrees Celsius to achieve the crystalline phase.

[0033] The time and energy required to heat PCM cells 236, 256, and 276 to a sufficient temperature will further depend on the heat capacity of heaters 224, 244, 264, and 284 and the materials used to fabricate memory system 200. In particular, heaters 224, 244, 264, and 284 can be positioned in various orientations and geometries with respect to memory cell 200, which can affect the time required to heat PCM cells 236, 256, and 276. In general, the closer the heaters 224, 244, 264, and 284 are to the PCM cells 236, 256, and 276, the denser the heaters 224, 244, 264, and 284 are, and the more effective the orientation of the heaters 224, 244, 264, and 284 is at transferring heat to the PCM cells 236, 256, and 276, and the shorter the time required to reach the crystalline phase of the PCM cells 236, 256, and 276. The time required to anneal the PCM cells 236, 256, and 276 can be minimized by applying stronger electrical pulses to the heaters 224, 244, 264, and 284, thereby increasing the heat output of the heaters 224, 244, 264, and 284.

[0034] Additionally, heaters 224, 244, 264, and 284 can be configured to reach various temperatures when triggered; the higher the temperatures reached by heaters 224, 244, 264, and 284, the shorter the time required for PCM cells 236, 256, and 276 to reach a crystalline phase. In any case, PCM cells 236, 256, and 276 only need to reach a crystalline phase; reaching temperatures beyond that is a waste of energy since it serves no purpose in erasing memory. Additionally, PCM cells 236, 256, and 276 should not be heated above 600°C because overheating can render them unusable. To maintain memory reusability, PCM cells 236, 256, and 276 generally should not be heated above 400°C for extended periods of time.

[0035] Because energy transfer takes time, heaters 224, 244, 264, and 284 may be heated to above 600° Celsius to achieve faster heating of PCM cells 236, 256, and 276. In some embodiments, heaters 224, 244, 264, and 284 may reach a “flash” temperature to rapidly heat PCM cells 236, 256, and 276 to the crystalline phase. The flash temperature is a temperature that can be reached in a short time such that the heat is not dissipated to the surrounding material quickly enough to allow the surrounding material to reach the same temperature. Heaters 224, 244, 264, and 284 may be configured to reach the flash temperature to more quickly transfer enough energy to PCM cells 236, 256, and 276 to enable them to reach the crystalline phase faster than would otherwise be achievable. For example, heaters 224, 244, 264 and 284 can be set to reach a flash temperature of 800° Celsius in a time long enough to allow PCM cells 236, 256 and 276 to reach 200° Celsius, but not long enough to allow PCM cells 236, 256 and 276 to reach 600° Celsius.

[0036] Depending on the material of memory cell 200 and the flash temperature, heaters 224, 244, 264, and 284 may only need to be activated for a shorter time than it takes to reach the crystalline phase of PCM cells 236, 256, and 276. For example, if heaters 224, 244, 264, and 284 reach a high enough flash temperature, heaters 224, 244, 264, and 284 may only need to be activated for 3 nanoseconds to transfer enough energy to bring PCM cells 236, 256, and 276 to a sufficient temperature over 10 nanoseconds to achieve the crystalline phase.

[0037] In some embodiments, one or more power sources (not shown) may be communicatively coupled to memory system 200. The power source may transmit power to heaters 224, 244, 264, and 284 via the same connections used to communicate trigger events, or via connections used solely for power transmission, or some combination thereof. In some embodiments, one or more power sources may be incorporated into memory system 200 to provide power to memory system 200. A power source may be incorporated into memory system 200 and communicatively coupled to heaters 224, 244, 264, and 284 to power them such that when activated, heaters 224, 244, 264, and 284 can draw power from the power source to enable heaters 224, 244, 264, and 284 to reach a particular temperature. The power source may include, for example, a battery, a photovoltaic cell, a fuel cell, an electrical connection, or any other unit capable of providing power. In some embodiments, the power source may be capable of storing power in addition to being able to supply power (eg, a battery).

[0038] Heaters 224, 244, 264, and 284 are incorporated into memory system 200. Heaters 224, 244, 264, and 284 may be any heat source. In some embodiments, heaters 224, 244, 264, and 284 are preferably reusable heat sources so that heaters 224, 244, 264, and 284 can heat PCM cells 236, 256, and 276 multiple times. Heaters 224, 244, 264, and 284 may be proximity heaters embedded in memory system 200. Heaters 224, 244, 264, and 284 may be interdigitated between materials 291, 292, 293, 294, 295, and 296 and / or PCM cells 236, 256, and 276, for example. Examples of resistive heater materials can include TaN, TiN and carbon.

[0039] In some embodiments, a single heater 224, 244, 264, or 284 may be used for the memory array. The heater 224, 244, 264, or 284 is in close proximity to one or more PCM cells 236, 256, and / or 276 that are specifically positioned to heat them to an annealing temperature. Generally, in an otherwise similar structure of the memory system 200, the greater the density of the heaters 224, 244, 264, and 284, the faster the annealing time can be. Similarly, the closer the PCM cells 236, 256, and 276 are to the heat source, the faster the PCM cells 236, 256, and 276 will anneal if a trigger event occurs. Thus, typically, the more heat sources there are and the closer the heat sources are to the PCM cells 236, 256, and 276, the faster the annealing time will be.

[0040] Further embodiments, including other memory system designs and configurations, methods of manufacture, and uses, are further described herein.

[0041] FIG. 3a illustrates a cross-sectional view of a memory system 300 with built-in memory erasure capabilities according to an embodiment of the present disclosure. FIG. 3b illustrates a top view of a memory system 300 with built-in memory erasure capabilities according to an embodiment of the present disclosure. Memory system 300 includes a substrate 310 and a dielectric 312. Memory system 300 further includes electrodes 332, 334, 338, 352, 354, 358, 372, 374, and 378. Memory system 300 also includes PCM cells 336, 356, and 376, heaters 324, 344, 364, and 384, and materials 391, 392, 393, 394, 395, and 396. Materials 391, 392, 393, 394, 395 and 396 can be used to thermally conduct heat between heaters 324, 344, 364 and 384 and PCM cells 336, 356 and 376. Materials 391, 392, 393, 394, 395 and 396 can be used to electrically insulate PCM cells 336, 356 and 376 from heaters 324, 344, 364 and 384.

[0042] Heaters 324, 344, 346, and 384 are proximate to PCM cells 336, 356, and 376. Materials 391, 393, 394, 395, and 396 are disposed between heaters 324, 344, 364, and 384 and PCM cells 336, 356, and 376. Materials 391, 392, 393, 394, 395, and 396 can be thermally conductive to facilitate heating of PCM cells 336, 356, and 376 by heaters 324, 344, 364, and 384. Materials 391, 392, 393, 394, 395, and 396 can be electrically insulating to prevent heaters 324, 344, 364, and 384 from writing, rewriting, or overwriting data on memory system 300.

[0043] Electrical flow 324a, 344a, 364a, and 384a is shown transferring energy to or through heaters 324, 344, 364, and 384. The direction of electrical flow is described as flowing upward through the page from heaters 324, 344, 364, and 384. Note that current may flow in other directions (e.g., downward through the page or parallel to the page) according to the present disclosure, such that heaters 324, 344, 364, and 384, when powered by a power source and activated thereby, can heat PCM cells 336, 356, and 376. PCM cells 336, 356, and 376 may be heated individually, sequentially, or simultaneously. Simultaneous heating of PCM cells 336, 356, and 376 in a system can be used as a rapid response to a trigger event.

[0044] In some embodiments, the material between the heater and the PCM cell may be eliminated. Figure 4a illustrates a cross-sectional view of a memory system 400 with built-in memory erasure capabilities in accordance with an embodiment of the present disclosure. Figure 4b illustrates a top view of a memory system 400 with built-in memory erasure capabilities in accordance with an embodiment of the present disclosure. The memory system 400 includes a substrate 410 and a dielectric 412. The memory system 400 further includes electrodes 422, 426, 432, 434, 438, 442, 446, 452, 454, 458, 462, 466, 472, 474, 478, 482, and 486. The memory system 400 also includes PCM cells 436, 456, and 476 and heaters 424, 444, 464, and 484.

[0045] Heaters 422, 444, 464, and 484 are in close proximity to PCM cells 436, 456, and 476. Electrical currents 426a, 446a, 466a, and 486a are shown transferring energy through electrodes 426, 446, 466, and 486. Current can flow in various directions according to the present disclosure, such that heaters 424, 444, 464, and 484 are powered by a power source and, therefore, can heat PCM cells 436, 456, and 476 when activated. PCM cells 436, 456, and 476 may be heated individually, sequentially, or simultaneously. Simultaneous heating of PCM cells 436, 456, and 476 in a system can be used as a rapid response to a trigger event.

[0046] In memory system 400, there is no material between heaters 424, 444, 464, and 484 and PCM cells 436, 456, and 476. Such embodiments may have lower thermal conductivity such that additional energy may be required to heat PCM cells 436, 456, and 476 to the crystalline phase. Additionally, embodiments without electrically resistive material between heaters 424, 444, 464, and 484 and PCM cells 436, 456, and 476 may be more susceptible to writing, rewriting, and / or overwriting data on memory system 400.

[0047] FIG. 5a illustrates a cross-sectional view of a memory system 500 with embedded memory erasure capabilities according to an embodiment of the present disclosure. FIG. 5b illustrates a top cross-sectional view of a memory system 500 with embedded memory capabilities according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 5b is indicated by the dashed line in FIG. 5a. The memory system 500 includes a substrate 510 and a dielectric 512. The memory system 500 further includes metal lines (interconnects), vias 522A-522H, and electrodes 524A-524F. The memory system 500 also includes PCM cells 536, 556, and 576, and heaters 528, 548, 568, and 588. The heaters 528, 548, 568, and 588 are adjacent to the PCM cells 536, 556, and 576 with the dielectric 512 disposed therebetween. In some embodiments, a thermally conductive, electrically insulating thermal coupling material may be disposed between heaters 528, 548, 568, and 588 and PCM cells 536, 556, and 576. See materials 291-296 in Figure 2a for an example where a thermal coupling material is used.

[0048] Currents 528a, 538a, 548a, 558a, 568a, 578a, and 588a are shown entering the page through heaters 528, 538, 548, 558, 568, 578, and 588. In some embodiments, in accordance with the present disclosure, current flows in various directions, and heaters 528, 538, 548, 558, 568, 578, and 588 are powered via a power supply. If resistive elements are used to implement heaters 528, 538, 548, 558, 568, 578, and 588, the directionality of the current does not affect the heat generated by the heaters. Figure 5b illustrates various configurations for heater placement relative to the PCM memory cells. In one embodiment, heaters 568 and 588 are adjacent to two opposing sides of PCM cell 576. In another embodiment, heaters 528, 538, and 548 are adjacent to three of the faces of PCM cell 536. In yet another embodiment, heaters 548, 558, 568, and 578 are adjacent to four faces of PCM cell 566 (full surface heating). Also, note that when PCM cells 536, 556, 576 are arranged in a two-dimensional array, each of the four heaters 548, 558, 568, 578 surrounding PCM cell 536, 556, 576 is shared with another PCM cell 536, 556, 576 (except for the PCM cells at the edge of the array).

[0049] Embodiments of the present disclosure include a method of memory erasure. Some embodiments may include monitoring a memory array by a processor, where the memory array may have a plurality of memory cells. The method may further include determining that a trigger threshold has been exceeded. The processor may communicate to at least one heater that the trigger threshold has been exceeded, and the method may further include heating at least one of the memory cells with at least one heater disposed between the memory cells. In some embodiments of the present disclosure, the memory cells may include nonvolatile phase-change memory cells. In some embodiments of the present disclosure, the heating may anneal the phase-change memory cells.

[0050] Embodiments of the present disclosure include methods for fabricating a memory system with erasure capabilities. Some embodiments may include forming a nonvolatile memory cell on a first electrode embedded in a dielectric material and forming a heater on a second electrode embedded in the dielectric material. The heater may be proximate to the nonvolatile memory cell. The method may further include forming a first top electrode on the nonvolatile memory cell and forming a second top electrode on the heater.

[0051] FIG. 6 illustrates a method 600 for fabricating an exemplary memory system 650 with built-in memory erasure capabilities according to an embodiment of the present disclosure. A substrate 610 is provided, and electrodes 622, 632, 634, and 642 can be formed within a dielectric 612 using known processing techniques, such as lithography, reactive ion etching, metal deposition, and chemical-mechanical polishing. A non-volatile memory cell 636 (e.g., PCM) can be added on top of one of the electrodes 622, 632, 634, or 642 (electrode 634 as shown). Materials 691 and 692 can be added around the memory cell 636, and can be thermally conductive and electrically insulating. One or more heaters 624 and 644 can be embedded within the materials 691 and 692 to form the heaters 624 and 644. An additional dielectric 612a can be added. Top electrodes 626, 638, and 646 can be formed within the dielectric 612a.

[0052] FIG. 7 illustrates a memory system 700 with erase capabilities according to an embodiment of the present disclosure. The memory system 700 may include one or more package integrity sensors 712 and one or more environmental sensors 714. The package integrity sensors 712 may be capable of detecting physical tampering with the device, such as by identifying attempts to tamper with the device housing. The environmental sensors 714 may be capable of detecting changes to the device's environment, such as removal of the device from the memory rack, by detecting changes in speed, rotational movement, stability, ambient temperature, or ambient humidity, or a combination thereof. In some embodiments, an authorization code may be used to identify authorized access, such as authorized maintenance that may require tampering with the device housing and / or removal from a particular environment.

[0053] An emergency power supply 716 may provide energy to the package integrity sensor 712, the environmental sensor 714, or both. The emergency power supply 716 may also provide power, directly or indirectly, to the tamper detector 720. The tamper detector 720 may be, for example, a notification device (e.g., relaying input commands), a tamper detection unit (e.g., an anti-tamper device), a unit that identifies a particular event (e.g., subscription expiration), a combination of these, or any other unit that can be used to identify a trigger event. The tamper detector 720 can communicate with the package integrity sensor 712 and the environmental sensor 714 such that the tamper detector 720 receives information from the package integrity sensor 712 and the environmental sensor 714.

[0054] Some embodiments of the present disclosure include a tamper-proof device for detecting physical tampering and responding to the tampering by erasing data. Erasing memory cluster 750 erases any data stored within memory cluster 750, including encryption keys 770, 772, and 774. Erasing the encryption keys stored within memory cluster 750 prevents encryption module 760 from using the encryption keys to decrypt data. In some embodiments, such a memory cluster 750 can be implemented using PCM memories 752, 754, and 756, as described with reference to FIG. 2, and (proximate) heaters 732, 734, and 736. For example, processor 720 may activate heaters 732, 734, and 736 embedded between PCM memories 752, 754, and 756 to erase the data contained in the memory cluster.

[0055] The tamper detector 720 may further be in communication with one or more heaters 732, 734, and 736. In some embodiments (not shown), the heaters 732, 734, and 736 may abut a thermal coupling material, which may be thermally conductive, to facilitate efficient thermal energy transfer from the heaters 732, 734, and 736 to the PCM memories 752, 754, and 756. In such embodiments, the thermal coupling material may be electrically insulating to prevent electrical pulses from being passed between the heaters 732, 734, and 736 and the PCM memories 752, 754, and 756.

[0056] PCM memories 752, 754, and 756 may be coupled to encryption module 760. PCM memories 752, 754, and 756 may function as encryption keys for encryption module 760. For example, PCM memories 752, 754, and 756 may store encryption keys 770, 772, and 774 for encryption module 760. For example, data written to storage memory 762 may be encrypted when written to storage memory 762. Similarly, encrypted data read from storage memory 762 may be decrypted when retrieved from memory. In such an embodiment, both encryption and decryption may be based on one or more encryption keys stored in PCM memories 752, 754, and 756.

[0057] The encryption module 760 can be in communication with a memory storage module 762. The storage memory 762 can be any type of memory (e.g., PCM, dynamic random access memory (DRAM), flash, etc.) or any combination thereof. The encryption module 760 can also be in communication with a data source. The encryption module 760 can, for example, receive data from a data source, encrypt the data, and store the encrypted data in the storage memory 762.

[0058] A memory system according to the present disclosure may be accessible only locally (e.g., on-site physical access), only virtually (e.g., via a local area connection or an internet connection), or some combination thereof. In some embodiments, a local-only connection may be preferred to prevent any virtual access, as virtual access may enable unauthorized remote access. In some embodiments, virtual access may be preferred to enable remote access, such as via a specifically authorized remote machine that can communicate with memory system 700 via end-to-end encryption, e.g., to enable triggering an erase of memory system 700 based on a non-local event.

[0059] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present disclosure can be implemented with any other type of computing environment now known or later developed.

[0060] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0061] The features are as follows:

[0062] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capabilities such as server time and network storage automatically as needed, without the need for human interaction with the service provider.

[0063] Wide network access: Functionality is available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin-client or thick-client platforms (e.g., cell phones, laptops, and PDAs).

[0064] Resource Pooling: To accommodate multiple consumers using a multi-tenant model, a provider's computing resources are pooled, with different physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have no control or knowledge over the exact portion of the resources provided, but there is a sense of portion independence in that they may be able to specify portions at a higher level of abstraction (e.g., country, state, or data center).

[0065] Rapid Elasticity: Rapid elasticity allows you to quickly scale out, sometimes automatically, by provisioning capabilities, and quickly release capabilities to quickly scale in. To the consumer, the capabilities available for provisioning often appear infinite, and you can buy as many as you want, whenever you want.

[0066] Metered Services: Cloud systems automatically control and optimize resource utilization by utilizing metering capabilities at some level of abstraction appropriate for the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, giving both providers and consumers transparency into the services utilized.

[0067] The service model is as follows:

[0068] Software as a Service (SaaS): The functionality offered to the consumer is the use of the provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functions, with the possible exception of limited user-specific application configuration settings.

[0069] Platform as a Service (PaaS): The capability offered to consumers is the deployment of consumer-created or acquired applications, written using programming languages ​​and tools supported by the provider, on a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the application-hosting environment configuration.

[0070] Infrastructure as a Service (IaaS): The capability offered to consumers is the provisioning of processing, storage, networking, and other basic computing resources onto which they can deploy and run any software, which may include operating systems and applications. While consumers do not manage or control the underlying cloud infrastructure, they do have control over the operating systems, storage, and deployed applications, and may have limited control over selected networking components (e.g., host firewalls).

[0071] The deployment model is as follows:

[0072] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by the organization or a third party and can reside on-premise or off-premise.

[0073] Community Cloud: This cloud infrastructure is shared by several organizations and can be managed by an organization or a third party that supports a specific community with common concerns (e.g., mission, security requirements, policies, and compliance concerns, or a combination thereof), and can reside on-premises or off-premises.

[0074] Public Cloud: This cloud infrastructure is available to the public or large industry organizations and is owned by an organization that sells cloud services.

[0075] Hybrid Cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that remain their own entities but are joined by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0076] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0077] 8 illustrates a cloud computing environment 810 according to an embodiment of the present disclosure. As shown, the cloud computing environment 810 includes one or more cloud computing nodes 800 with which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or mobile phone 800A, a desktop computer 800B, a laptop computer 800C, or an automotive computer system 800N, or combinations thereof, can communicate. The nodes 800 can communicate with each other. The nodes 800 may be physically or virtually grouped (not shown) in one or more networks, such as the private cloud, community cloud, public cloud, or hybrid cloud described above, or combinations thereof.

[0078] This allows the cloud computing environment 810 to provide infrastructure, platform, and / or software as a service for which the cloud consumer does not need to maintain resources on a local computing device. It is understood that the types of computing devices 800A-800N shown in Figure 8 are intended to be exemplary only, and that the computing nodes 800 and the cloud computing environment 810 can communicate with any type of computerized device via any type of network connection or network-addressable connection or combination thereof (e.g., using a web browser).

[0079] Figure 9 illustrates abstraction model layers 900 provided by cloud computing environment 810 (of Figure 8) in accordance with an embodiment of the present disclosure. It should be understood in advance that the components, layers, and functions illustrated in Figure 9 are intended to be illustrative only, and embodiments of the present disclosure are not limited thereto. As shown below, the following layers and corresponding functions are provided:

[0080] The hardware and software layer 915 includes hardware and software components, such as a mainframe 902, a reduced instruction set computer (RISC) architecture-based server 904, a server 906, a blade server 908, storage devices 911, and network and networking components 912. In some embodiments, the software components include network application server software 914 and database software 916.

[0081] The virtualization layer 920 provides an abstraction layer that can instantiate virtual entities such as virtual servers 922, virtual storage 924, virtual networks 926, including virtual private networks, virtual applications and operating systems 928, and virtual clients 930.

[0082] In one embodiment, management layer 940 may provide the following functionality: Resource provisioning 942 dynamically procures computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 944 tracks costs as resources are utilized within the cloud computing environment and bills or invoices for the consumption of those resources. In one embodiment, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks and protection of data and other resources. User portal 946 provides consumers and system administrators with access to the cloud computing environment. Service level management 948 allocates and manages cloud computing resources to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 950 proactively arranges for and procures cloud computing resources for anticipated future demand in accordance with SLAs.

[0083] Workload tier 960 provides examples of functionality that can utilize a cloud computing environment. Examples of workloads and functionality that can be provided from this tier include mapping and navigation 962, software development and lifecycle management 964, virtual classroom instruction delivery 966, data analytics processing 968, transaction processing 970, and one or more memory systems with erasure capabilities 972.

[0084] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0085] 10 illustrates a high-level block diagram of an exemplary computing system 1001 that can be used to implement (e.g., using one or more processor circuits of a computer or computer processor) one or more of the methods, means, and modules and any associated functionality described herein, in accordance with embodiments of the present disclosure. In some embodiments, the major components of the computer system 1001 may include a processor 1002 with one or more central processing units (CPUs) 1002A, 1002B, 1002C, and 1002D, a memory subsystem 1004, a terminal interface 1012, a storage interface 1016, an I / O (input / output) device interface 1014, and a network interface 1018, all of which may be communicatively coupled, directly or indirectly, for inter-component communication via a memory bus 1003, an I / O bus 1008, and an I / O bus interface unit 1010.

[0086] Computer system 1001 may include one or more general-purpose programmable CPUs 1002A, 1002B, 1002C, and 1002D, collectively referred to herein as CPUs 1002. In some embodiments, computer system 1001 may include multiple processors typical of larger systems, while in other embodiments, computer system 1001 may instead be a single-CPU system. Each CPU 1002 can execute instructions stored in memory subsystem 1004 and may include one or more levels of on-board cache.

[0087] The system memory 1004 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 1022 or cache memory 1024. The computer system 1001 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 1026 may be provided for reading from and writing to non-removable, non-volatile magnetic media, such as a "hard drive." Although not shown, a magnetic disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), or an optical disk drive may be provided for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. Additionally, the memory 1004 may include flash memory, such as a flash memory stick drive or flash drive. Memory devices may be connected to the memory bus 1003 by one or more data media interfaces. The memory 1004 may include at least one program product having a set (eg, at least one) program module configured to implement the functionality of various embodiments.

[0088] One or more programs / utilities 1028, each having at least one set of program modules 830, may be stored in memory 1004. The programs / utilities 1028 may include a hypervisor (also called a virtual machine monitor), one or more operating systems, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. The programs 1028 and / or program modules 1030 generally perform the functions or methods of various embodiments.

[0089] 10 illustrates memory bus 1003 as a single bus structure providing a direct communication path between CPU 1002, memory subsystem 1004, and I / O bus interface 1010, memory bus 1003, in some embodiments, may include multiple different buses or communication paths, which may be arranged in any of a variety of configurations, such as point-to-point links in a hierarchical, star, or web configuration, multi-tiered buses, parallel and redundant paths, or any other suitable type of configuration. Also, while I / O bus interface 1010 and I / O bus 1008 are shown as single respective units, computer system 1001, in some embodiments, may include multiple I / O bus interface units 1010, or multiple I / O buses 1008, or both. Also, although multiple I / O interface units 1010 are shown isolating the I / O bus 1008 from the various communication paths leading to the various I / O devices, in other embodiments some or all of the I / O devices may be directly connected to one or more system I / O buses 1008.

[0090] In some embodiments, computer system 1001 may be a multi-user mainframe computer system, a single-user system, a server computer, or similar device that has little or no direct user interface but receives requests from other computer systems (clients). Also, in some embodiments, computer system 1001 may be implemented as a desktop computer, a portable computer, a laptop or notebook computer, a tablet computer, a pocket computer, a telephone, a smartphone, a network switch or router, or any other suitable type of electronic device.

[0091] Figure 10 is intended to illustrate representative major components of an exemplary computer system 1001. However, in some embodiments, individual components may have greater or less complexity than those shown in Figure 10, components other than or in addition to those shown in Figure 10 may be present, and the number, type, and configuration of such components may vary.

[0092] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to implement aspects of the present disclosure.

[0093] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as ridge structures in grooves on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted over wires.

[0094] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or any combination thereof. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage.

[0095] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or procedural programming languages, such as object-oriented programming languages ​​like Smalltalk, C++, and the "C" programming language, or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer as a standalone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present disclosure, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer-readable program instructions by personalizing the electronic circuitry using state information of the computer-readable program instructions.

[0096] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams that illustrate methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0097] These computer-readable program instructions may be supplied to a processor of a computer or other programmable data processing apparatus to cause the machine to implement the instructions, which, when executed by the processor, form means for implementing the functions / acts specified in the blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium capable of instructing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in the blocks of the flowcharts and / or block diagrams.

[0098] The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to realize a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in the flowchart and / or block diagram blocks.

[0099] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be completed as a single step, or may be executed in parallel, substantially in parallel, partially or fully overlapping in time, or the blocks may possibly be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0100] While the present disclosure has been described in terms of specific embodiments, it is expected that changes and modifications to these embodiments will become apparent to those skilled in the art. The description of various embodiments of the present disclosure has been provided for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Numerous modifications and variations will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements of the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Therefore, it is intended that the following claims cover all such changes and modifications as fall within the scope of this disclosure.

Claims

1. 1. A memory system comprising: a memory array having a plurality of memory cells; a heater embedded between the plurality of memory cells in the memory array; a processor in communication with the heater, the processor notifying the heater to activate when a trigger event occurs; Including, the heater includes a plurality of heaters respectively disposed between each of the plurality of memory cells; Memory system.

2. 10. The system of claim 1, wherein the plurality of memory cells are non-volatile phase change memory cells.

3. 3. The system of claim 2, wherein activation of the heater heats at least a portion of the memory array and causes at least one of the non-volatile phase change memory cells to change from a first phase to a second phase.

4. The system of claim 3 , wherein the first phase is an amorphous phase and the second phase is a crystalline phase.

5. 5. The system of claim 1, further comprising a material separating said heater from said plurality of memory cells, said material being thermally conductive and electrically insulating.

6. The system of claim 1 , further comprising at least one package integrity sensor in communication with the processor.

7. The system of claim 1 , further comprising a power source in communication with at least one of the processor and the heater.

8. 8. The system of claim 1, wherein the processor is a tamper detection unit.

9. 1. A computer system comprising: Storage memory and a memory cluster including a plurality of heaters interdigitated between each memory cell of a plurality of memory cells, the plurality of memory cells storing one or more encryption keys for encrypting or decrypting data stored in the storage memory; a tamper detector in communication with the plurality of heaters, the tamper detector signaling at least one of the plurality of heaters to activate upon the occurrence of a tamper event; 1. A computer system comprising:

10. 10. The system of claim 9, wherein the plurality of memory cells are non-volatile phase change memory cells.

11. 11. The system of claim 10, wherein activation of the plurality of heaters heats at least a portion of the plurality of memory cells and causes at least one of the non-volatile phase change memory cells to change from a first phase to a second phase.

12. 12. The system of claim 11, wherein the first phase is an amorphous phase and the second phase is a crystalline phase.

13. 13. The system of claim 9, further comprising a material separating the heater from the plurality of memory cells, the material being thermally conductive and electrically insulating.

14. 14. The system of any of claims 9 to 13, further comprising at least one package integrity sensor in communication with the tamper detector.

15. 15. The system of claim 9, further comprising a power source in communication with at least one of the one or more heaters and the tamper detector.

16. 16. The system of claim 9, wherein the tampering event is an unauthorized removal of the memory system or at least one of its components.

17. A memory erasing method, comprising: monitoring, by a processor, a memory array having a plurality of memory cells; determining that a trigger threshold has been exceeded; heating at least one of the plurality of memory cells with the processor in communication with each of a plurality of heaters; wherein each of the plurality of heaters is disposed between each memory cell of the plurality of memory cells. method.

18. 20. The method of claim 17, wherein the at least one of the plurality of memory cells is a phase change memory cell, and the heating anneals the phase change memory cell.

19. A computer program for memory erasure, the computer program causing the processor to carry out the steps of the method according to claim 17 or 18.

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