Inverter circuits and methods, for example for use in power factor correction

Abstract

An inverter circuit receives an AC input signal and performs an electrical inversion function using at least two bidirectional switches between an input terminal and a junction node, a primary inductor between the junction node and a second node, and a capacitor arrangement between the second node and the input terminal to form a resonant circuit.

Description

[Technical Field]

[0001] The present invention relates to an inverting circuit and method that, inter alia, eliminates the need for a diode bridge rectifier, for example to form part of a power factor correction circuit. [Background technology]

[0002] A function implemented within power converters supplied with mains (or other AC) power is power factor correction (PFC). The power factor of an AC power system is defined as the ratio of the real power flowing to the load to the apparent power in the circuit. A power factor less than one means that the voltage and current waveforms are not in phase and / or do not have the same shape. A phase shift, for example, reduces the instantaneous product of the two waveforms and the average power delivered over a mains cycle. Real power is the capacity of a circuit to perform work in a specific time. Apparent power is the product of the current and voltage in a circuit. Apparent power may be greater than real power due to energy stored in the load and returned to the source, or due to nonlinear loads that distort the waveform of the current drawn from the source.

[0003] If the power supply is operating at a low power factor, the load will draw more current for the same amount of useful power to be transferred than if the power supply were operating at a higher power factor.

[0004] The power factor can be increased using power factor correction. For linear loads, this can involve the use of a passive network of capacitors or inductors. Nonlinear loads generally require active power factor correction to cancel distortion and increase the power factor. Power factor correction brings the power factor of an AC power circuit closer to unity by supplying reactive power of opposite sign, for example by adding capacitors or inductors that act to cancel the inductive or capacitive effects of the load.

[0005] Active PFC uses power electronics to change the waveform of the current drawn by the load to improve the power factor. Active PFC circuits are most often based on a boost switch-mode converter topology. Non-isolated flyback or isolated flyback converter topologies may also be used. Active power factor correction can be single-stage or multi-stage.

[0006] In the case of a switched-mode power supply, for example, a PFC boost converter is inserted between the reservoir capacitor and the bridge rectifier at the output of the PFC circuit. The boost converter may, for example, attempt to maintain a constant DC bus voltage at its output while drawing a current that has the same frequency and shape as the line voltage and is always in phase with the line voltage. Another switched-mode converter in the power supply may generate the desired output voltage or current from the DC bus. This forms a two-stage system and is a common configuration for high-power LED applications (e.g., greater than 25 W and up to about 1000 W).

[0007] Due to their very wide input voltage range, many power supplies with active PFC can automatically adjust to operate on AC mains from, for example, about 110V to 277V.

[0008] The diode bridge rectifier used in a typical boost converter PFC circuit takes up a significant amount of space and contributes significantly to the power consumption of the circuit.

[0009] Bridgeless boost converters and boost derived converters have been proposed for example since the 1980s.

[0010] More recently, in conjunction with emerging high voltage (“HV”) GaN transistors (e.g., 650 V), traditional boost PFC circuits featuring a diode rectifier bridge have been replaced with bridgeless versions in various industrial applications.

[0011] In that case, bridge rectifier losses can be significantly reduced: for example, at 120Vac or in the case of a wide mains voltage range (IntelliVolt®), the worst-case losses in the mains input rectifier contribute to about 1 / 3 of the total losses in the PFC front end.

[0012] A bridgeless version of the boost converter can be obtained relatively easily by connecting a mains voltage source and a boost inductor in series between the two transistor half-bridge junction nodes, which then share the voltage rectification and boost action so that the voltage across the bridge is still unipolar. An electrolytic bus capacitor can then be used.

[0013] However, this approach does not apply to PFC stages that comprise resonant half or full bridge converters.

[0014] It is also known that monolithically integrated bidirectional switches can be constructed based on GaN HEMT (High Electron Mobility Transistor) technology. For example, a common drain type bidirectional GaN e-mode HEMT has been disclosed.

[0015] An isolated bridgeless PFC converter using a semi-resonant boost converter with an active clamp capacitor and polarity reversal circuit is described in "Single stage true bridgeless AC / DC power factor corrected converter" by CD Davidson, 2015 IEEE International Telecommunications Energy Conference (INTELEC).

[0016] In this proposal, three bidirectional switches formed by separate back-to-back connected IGBTs and MOSFETs are employed. Summary of the Invention [Problem to be solved by the invention]

[0017] A disadvantage of the typical boost converter type bridgeless front end is that it has limited potential for size reduction: for example, the circuit described in the reference by C.D. Davidson has relatively bulky clamp and polarity reversal circuitry, a relatively large boost inductor and transformer, and an additional bidirectional switch. [Means for solving the problem]

[0018] The invention is defined by the claims.

[0019] According to an example according to an aspect of the present invention, an input for receiving an unrectified AC input signal; a first terminal and a second terminal for receiving power from the input; a first bidirectional switch between the first terminal and a junction node; a second bidirectional switch between the second terminal and the junction node; a primary inductor between the junction node and a second node; and a capacitor arrangement between the second node and the first terminal and / or the second terminal.

[0020] This inverter circuit is "bridgeless" in the sense that no diode bridge is required. This means that the inverter can be used, for example, in a bridgeless power factor correction (PFC) circuit. This inverter circuit combines the size and efficiency advantages of a resonant converter front end with the loss reduction and power factor improvement advantages of a bridgeless input circuit. Rectifier-related disturbances are avoided so that total harmonic distortion (THD) can be lowered.

[0021] The capacitor arrangement may, for example, include a first capacitor between the second node and the first terminal, and a second capacitor between the second node and the second terminal.

[0022] The first and second bidirectional switches preferably each comprise a first and second transistor in anti-series. In this manner, the switching function of the bidirectional switch may be divided between the two transistors, each having its own gate contact, to create a switching sequence that may depend on the polarity of the input. One of the transistors may act as a master and the other as a slave. For example, one of the transistors may act as a switch and the other as a diode, with the role depending on the polarity of the input.

[0023] Each pair of first and second transistors in series may have a common source or a common drain at the junction node between the first and second transistors, thus allowing a common source or common drain connection for the pair of transistors.

[0024] The circuit preferably further comprises a control circuit for controlling the switching of the transistors, the control circuit comprising, for example, for each bidirectional switch: an on mode in which each of the first transistor and the second transistor is turned on; a first transition mode in which the first transistor is turned on and the second transistor is turned off; and a second transition mode in which the second transistor is turned on and the first transistor is turned off.

[0025] Different transition modes may be used, for example, during different polarities of the input. For example, the controller may: a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal; When the voltage at the first terminal is lower than the voltage at the second terminal, the control sequence for each bidirectional switch may be adapted to implement a control sequence utilizing the on mode and the second transition mode.

[0026] The control circuit may further be adapted to implement, for each bidirectional switch, an off mode in which the respective first and second transistors are turned off.

[0027] In that case, the controller a control sequence for each bidirectional switch utilizing the on mode, the off mode, and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal; When the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch is adapted to implement a control sequence utilizing the on mode, the off mode, and the second transition mode.

[0028] This provides an alternative control scheme.

[0029] Each bidirectional switch comprises, for example, a GaN dual transistor switch.

[0030] The present invention also provides a power factor correction circuit having an inverter circuit as defined above and an output circuit including a secondary inductor coupled to the primary inductor. The power factor correction circuit may further include a second inverter circuit as defined above. The capacitor arrangement provides DC blocking and therefore may not form part of a resonant tank. The power factor correction circuit may optionally be a resonant circuit, in which case the capacitor arrangement functions as part of the resonant tank.

[0031] The present invention also provides a resonant converter having an inverter circuit as defined above and an output circuit including a secondary inductor coupled to said primary inductor.

[0032] The present invention is a method for providing electrical reversal, comprising: receiving an unrectified AC input signal at a first terminal and a second terminal; controlling switching of a first bidirectional switch between the first terminal and a junction node (x) and a second bidirectional switch between the second terminal and the junction node (x), wherein a primary inductor is between the junction node and a second node, and a capacitor arrangement is between the second node and the first terminal and / or the second terminal; The method further comprises, for each bidirectional switch: an on mode in which each of the first transistor and the second transistor is turned on; a first transition mode in which the first transistor is turned on and the second transistor is turned off; and implementing a second transition mode in which the second transistor is turned on and the first transistor is turned off.

[0033] The method comprises: a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal; When the voltage at the first terminal is lower than the voltage at the second terminal, the control sequence for each bidirectional switch may include the step of implementing a control sequence that utilizes the on mode and the second transition mode.

[0034] The method may include the step of implementing an off mode for each bidirectional switch, in which the respective first transistor and the second transistor are turned off. In this case, when the voltage at the first terminal is higher than the voltage at the second terminal, the control sequence for each bidirectional switch utilizes the on mode, the off mode, and the first transition mode, when the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch may be configured to utilize the on mode, the off mode, and the second transition mode.

[0035] These and other aspects of the present invention will be described and clarified with reference to the following embodiments.

Brief Description of the Drawings

[0036] For a better understanding of the present invention and to more clearly show how the present invention can be implemented, reference is made here, by way of example only, to the accompanying drawings. [Figure 1] Shows the front end of a power factor correction circuit having a resonant LLC converter and an inverter with a common source configuration. [[ID=​​​​​​​v(l)>v(n), that is, one shape of the high-frequency pulse when on the left side of FIG. 3 is shown on the left, and v(l)<v(n), that is, one shape of the high-frequency pulse when on the right side of FIG. 3 is shown on the right. [Figure 5] An example of a circuit diagram of a bidirectional switch and a table of operating modes are shown. [Figure 6] A control sequence for the operation of four transistors in the circuit of FIG. 1 is shown. [Figure 7] The structure of a bidirectional GaN switch is shown. [Figure 8] The waveforms of the junction node voltage v(x) and the individual gate drive voltages for this alternative drive method are shown. [Figure 9] A control sequence for the operation of four transistors for the drive method of FIG. 8 is shown. [Figure 10] An alternative configuration of the gate drive circuit is shown.

Embodiments for Carrying out the Invention

[0037] The present invention will be described with reference to the drawings.

[0038] The detailed description and specific examples show exemplary embodiments of the apparatus, system and method, but are for illustrative purposes only and are not intended to limit the scope of the present invention. It should be understood that these and other features, aspects and advantages of the apparatus, system and method of the present invention will become better understood from the following description, the appended claims and the accompanying drawings. It should be understood that the figures are merely schematic and not drawn to scale. It should also be understood that the same reference numerals are used throughout the figures to indicate the same or similar parts.

[0039] The present invention provides an inverter circuit that receives an AC input signal and performs an electrical inversion function using at least two bidirectional switches between an input terminal and a junction node, wherein a resonant circuit is formed by a primary inductor between the junction node and a second node, and a capacitor arrangement between the second node and the input terminal.

[0040] FIG. 1 shows the front end of a power factor correction circuit comprising a resonant LLC converter and an inverter.

[0041] The circuit has an inverter circuit on the input side and a resonant circuit on the output side.

[0042] The inverter circuit has an input for receiving an AC input signal V_ac after filtering by LC filter circuits C_filt1, C_filt2, L_filt1, L_filt2. The AC input is an unrectified mains input signal. The input to the inverter circuit has a first terminal T1 and a second terminal T2 for receiving power from the input after the filtering stage. In the example shown, T1 is designated live (l) and T2 is designated neutral (n).

[0043] The first bidirectional switch BD1 is located between the first terminal T1 and the junction node x, and the second bidirectional switch BD2 is located between the second terminal T2 and the junction node x.

[0044] A primary inductor L1 is provided between the junction node x and a second node N2. A first capacitor C_res1 is provided between the second node N2 and a first terminal T1, and a second capacitor C_res2 is provided between the second node N2 and a second terminal T2. These capacitors can be used to form a resonant tank in a resonant power factor correction circuit or a resonant converter.

[0045] The filtering stage has an LC filter element and no mains rectifier.

[0046] The power factor correction circuit has an output stage represented as a DC voltage sink V_out. The output voltage is defined between output nodes N3 and N4. Between N3 and N4 there are two parallel branches, each consisting of an inductor (magnetically coupled to inductor L1) and a diode. One of the branches is L2 and D1, the other is L3 and D2.

[0047] There may be an additional mains storage capacitor (not shown), which may be considered part of V_out.

[0048] Inductors L1, L2 and L3 form a transformer, and capacitors C_res1 and C_res2 form a resonant tank together with the inductor of the transformer in some circuit embodiments.

[0049] The bidirectional switches BD1 and BD2 each include a pair of transistor switches. The first, high-side bidirectional switch BD1 includes two anti-series transistors QH1 and QH0. The second, low-side bidirectional switch BD2 includes two anti-series transistors QL1 and QL0. Both the high-side pair GH0, QH1 and the low-side pair GL0, QL1 can be considered to be formed by two individual switches (bottom and top) as shown. Each switch pair may be constructed by a monolithically integrated device or by two individual chips that are integrated into a multi-chip module or simply packaged separately. In either case, there are two gate contacts for each bidirectional switch.

[0050] Figure 1 shows a common-source version where the junction between each transistor pair is the source terminal.

[0051] Figure 2 shows an alternative common-drain version in which the contact point between each transistor pair is the drain terminal, which can be left floating.

[0052] The advantage of the common-source configuration of FIG. 1 is that both the pair of top gates and bottom gates have the same reference voltage, i.e., the common-source voltage, so that less design effort is required for the gate driver.

[0053] The gate drive circuit is not shown. It is supplied by an auxiliary power supply that uses, for example, a bridge rectifier.

[0054] The two gates of each bidirectional switch each receive their respective gate signals (gH1, gH0, gL1, gL0). One is the master signal and the other is the auxiliary (or slave) signal.

[0055] During the positive inverter polarity (i.e., between v(l)>v(n), e.g., through the first half of the main power cycle), the master signal drives the top gates (gH1, gL1). During the negative inverter polarity, the master signal drives the bottom gates (gH0, gL0).

[0056] The slave gates can be switched or can be left on all the time, as will be explained in more detail below. The advantage of switching all four gate signals is that Manchester encoding can be supported in the case of an inductive gate drive / gate drive transformer.

[0057] FIG. 3 shows the input AC voltage on the left and the shape of the voltage v(x) at node x on the right for the part where the polarity of the input voltage changes (from v(l)>v(n) to v(l)<v(n)).

[0058] The inverter generates a high frequency switched version of the input voltage based on the control signal applied to the transistor.

[0059] Figure 4 shows on the left the shape of one of the high-frequency pulses when v(l) > v(n), that is, in the left part of Figure 3, and on the right the shape of one of the high-frequency pulses when v(l) < v(n), that is, in the right part of Figure 3.

[0060] Note that in these graphs, v(n) is defined as 0. In the flat part of the graph in Figure 4, that is, when ignoring the transient phenomenon, v(x) = v(l), or v(x) = v(n) = 0.

[0061] Figure 5 shows an example of a circuit diagram of a bidirectional switch and a table of operating modes. When both switches are turned on or off simultaneously, the bidirectional mode is defined. When one switch is turned on at a time, the diode mode is defined as shown. Figure 5 shows a common drain connection.

[0062] Each transistor serves as a switch for a positive drain-source voltage and as a diode for a negative drain-source voltage. The transistor is, for example, a GaN transistor such as a GaN e-mode HEMT. These have a larger forward bias voltage of about 2V during reverse conduction compared to the 0.7V of the pn junction diode present in Si-MOSFETs. Although there is no diode in the HEMT, the transistor can conduct even in the third quadrant only when the reverse bias voltage exceeds the gate threshold (at a gate-source voltage of 0V), so the HEMT behaves like this when a reverse bias is applied to the drain-source terminals.

[0063] Figure 6 shows a control sequence for the operation of four transistors.

[0064] In Figure 6, v(a,b) indicates the voltage of a with respect to b. For example, v(gH1,sH) indicates the voltage applied to the gate gH1 of transistor QH1 with respect to the source voltage sH.

[0065] In the case of a transistor, a gate voltage of V1 indicates an on (conducting) state, and a voltage of V0 indicates an off state.

[0066] Note that the control can be based on voltage or current, depending on the type of transistor. Therefore, V0 should generally be considered to be associated with an off command, and V1 should generally be considered to be associated with an on command.

[0067] Each bidirectional switch has an on mode in which the first transistor and the second transistor are turned on (V1 and V1), a first transition mode in which the first transistor is turned on and the second transistor is turned off (V1 and V0), and a second transition mode in which the second transistor is turned on and the first transistor is turned off (V0 and V1).

[0068] The upper part of FIG. 6 shows the switching sequence for the positive phase of the AC input, i.e., when v(l)>v(n), and thus v(l)>0.

[0069] As also shown on the left side of FIG. 4, there are four intervals.

[0070] Interval 0 is the transition when v(x) increases from 0 to v(l) at the start of the positive v(x) pulse.

[0071] Interval 1 is the period when v(x)=v(l).

[0072] Interval 2 is the transition when v(x) decreases from v(l) to 0 at the end of the v(x) pulse.

[0073] Interval 3 is the period when v(x)=0 between v(x) pulses.

[0074] The lower part of FIG. 6 shows the switching sequence for the negative phase of the AC input, i.e., when v(l)<v(n), and thus v(l)<0.

[0075] As shown on the right side of Figure 4, there are again four intervals.

[0076] Section 4 is the transition at the beginning of the negative v(x) pulse as v(x) decreases from 0 to negative v(l).

[0077] Section 5 is the period v(x)=v(l).

[0078] Section 6 is the transition at the end of the v(x) pulse when v(x) increases from v(l) to 0.

[0079] Section 7 is the period between v(x) pulses where v(x)=0.

[0080] During the positive phase of the live voltage, in sections 1 and 3, the junction node x is connected to live or neutral by the pair in which both transistors are turned on. This is also true for sections 5 and 7 in the opposite phase with a negative live voltage.

[0081] For opposing transistor pairs, the transistors are individually controlled.

[0082] In the positive phase, only the upper transistors of the opposite pair (hence QL1 and QH1) are in the complementary state, i.e., off, in sections 1 and 3. Thus, during section 1, QL1 is off, and during section 3, QH1 is off.

[0083] This means that they are subjected to the full blocking voltage. The lower transistor of each pair (QL0, QH0) is kept on during the entire positive phase.

[0084] The role of the slave transistors in each pair switches between phases.

[0085] Therefore, in the antiphase, in sections 5 and 7, only the lower transistors of each pair (hence QL0, QH0) are in the complementary state, i.e., off, meaning that they experience the full blocking voltage. The upper transistors of each pair (QL1, QH1) remain on throughout the antiphase.

[0086] Thus, when the voltage at the first terminal is higher than (or equal to) the voltage at the junction node and the voltage at the second terminal is lower than (or equal to) the voltage at the junction node (and thus is in positive phase), the control sequence for each bidirectional switch utilizes the on mode and the first transition mode.

[0087] When the voltage at the first terminal is lower than (or equal to) the voltage at the junction node and the voltage at the second terminal is higher than (or equal to) the voltage at the junction node (and therefore is in antiphase), the control sequence for each bidirectional switch utilizes an on mode and a second transition mode.

[0088] Using GaN transistors for the bidirectional switch allows the switch to be monolithically integrated as shown in FIG.

[0089] 7 includes a silicon substrate 60, a buffer layer 62, an i-GaN layer 64, an i-AlGaN layer 66, and a drain / source contact layer 68. The gate includes a gate stack of a p-AlGaN layer 70 and a gate electrode layer 72.

[0090] There are various gate structures used for GaN e-mode HEMTs. The structure shown in Figure 7 employs an additional gate injection transistor ("GIT," or "p-GaN gate"), which means that a current, rather than a voltage, needs to be applied to keep the device in on mode. Voltage driving is the case for alternative technologies that use simple (Schottky) gate structures.

[0091] Two transistors with separate gates are placed side by side. Bidirectional GaN switches benefit from the relatively low on-state resistance of GaN devices, the relatively low output capacitance of GaN devices, and the low gate charge of GaN devices.

[0092] For a GaN bidirectional switch based on a voltage-controlled Schottky gate structure, example values ​​for the two gate voltage levels are V1=5V and V0=0V.

[0093] In the case of the control scheme of Figure 6, if the two transistors of the pair are switched in opposite directions, turning off the transistor with the reverse drain-source voltage will not cause the device to block any voltage higher than 0.7V or 2V because it is in diode mode. Therefore, the control scheme of Figure 6 allows the transistor to be turned on throughout the phase (positive or negative) to keep the gate drive simple and efficient. The master device, controlled by the master signal, is switched to determine whether the bidirectional switch is in a blocking or conducting state, and the slave device remains on.

[0094] Alternative gate drive methods are discussed below in connection with more detailed gate timing schemes.

[0095] Figure 8 shows the waveforms of the junction node voltage v(x) and the individual gate drive voltages for this alternative drive scheme, specifically for a common-source configuration during the positive phase (hence the v(x) pulse is positive). It differs from the first scheme of Figure 6 in the control of the slave transistor, which is now also turned on and off periodically.

[0096] The master transistors (QH1 and QL1 during the positive phase) are turned on after a dead time Td that is longer than the transition time (longer by ΔTd). However, the slave devices must be turned on at the latest at the end of the transition, because then, in order to promote the diode mode of the master transistors, the diode mode of the slave devices must end and they must be conducting.

[0097] Such precise timing is impractical for the slave devices, which means they need to be switched earlier. Instead, the slave devices are switched just Td earlier, i.e., when each master device in each pair is switched (i.e., QH0 and QL0 are operated in a complementary manner to QL1 and QH1). This approach only requires generating two timing signals per half period.

[0098] Figure 9 shows the control sequence for the operation of the four transistors. The same sections as in Figure 6 are identified.

[0099] Here, the off mode of each bidirectional switch is also used since the slave transistor is also switched, in which the respective first and second transistors are both turned off.

[0100] In the positive phase, the control sequence for each bidirectional switch utilizes an on mode, an off mode, and a first transition mode (the upper transistor, eg, QH1, is off and the lower transistor, eg, GH0, is on).

[0101] In the reverse phase, the control sequence for each bidirectional switch utilizes an on mode, an off mode, and a second transition mode (where the upper transistor, eg, QH1, is on and the lower transistor, eg, GH0, is off).

[0102] This drive scheme allows for gate drive by a transformer pair, which can be beneficial at high switching frequencies. The gate drive transformer can replace a frequency-limited level-shift type gate driver. The resonant gate drive transformer for a half-bridge recovers energy from discharging the gate of one (e.g., the lower) device to charge the gate of the other (e.g., the upper) device. However, adjusting the dead time is cumbersome because charging and discharging cannot be untangled.

[0103] Figure 10 shows how the gate drive approaches shown in Figures 8 and 9 can employ pairs of gate drive transformers. In particular, the scheme of Figure 9 makes it possible to provide two pairs of gates that are switched simultaneously, one of which is turned on and the other off, which is suitable for a resonant gate driver transformer approach.

[0104] Gate drivers have to handle both signal transmission and sourcing or sinking the gate charge to turn the transistor's channel on or off. Standard level shifters make both difficult at frequencies in the MHz range due to the large (parasitic) capacitances they introduce. This is also true for bootstrap techniques used to supply gate drive power. For floating (high-side) transistors, non-galvanic signal transmission (e.g., optical transmission, signal transformers, or RF links) is used.

[0105] In connection with gate drives, transformers are used not only to transmit signals but also as part of the floating gate driver power supply. A transformer may be used for both of these functions simultaneously.

[0106] For floating gate driver power supplies, resonant gate drivers with two complementary outputs for driving the low-side and high-side transistors of a half-bridge have been described. The resonant gate drive transformer for the half-bridge recovers energy from discharging the gate of one (e.g., the lower) device to charge the gate of the other (e.g., the upper) device. However, adjusting the dead time is cumbersome because charging and discharging cannot be disentangled.

[0107] For high frequency operation, implementing the above timing pattern of FIG. 8 for two switches of a bidirectional half-bridge with three or four floating transistors (for common drain or common source configuration) may imply a relatively complex gate driver configuration employing four, e.g., separate floating gate drive circuits, using one of the known principles listed above.

[0108] Regarding the second drive scheme for the bidirectional half-bridge of FIG. 6, two gate pairs can be constructed that are switched simultaneously such that one of them is turned on and the other is turned off at the same time.

[0109] Figure 10 shows a schematic of such a gate driver for a common-drain configuration. At the same time, there are two gate driver pairs (A and B), each with two outputs switched with complementary signals (gH0, gL1 for the A gate driver pair, and gH1, gL1 for the B gate driver pair). The delay between the switching events of the first and second pairs is the dead time (Td) of the half-bridge inverter, i.e., the time when both (bidirectional) switches are off.

[0110] Each assembly consists of a transformer used for power and signal transmission. One gate driver has a primary winding LpA and secondary windings LL0 and LH1. The other gate driver has a primary winding LpB and secondary windings LH0 and LL1. The primary side of the transformer is supplied by a central drive circuit that generates gate drive patterns from set points and feedback information ("FB"), which can be supplied from the main power supply (l, n). The floating secondary side is connected to the gates and their respective sources via gate drive pulse adjustment circuits gH0, gL1, gH1, and gL0.

[0111] In the common drain configuration shown, both sources of the first gate drive pair (A) have the same potential and no unwanted oscillations between the outputs due to parasitic capacitance are excited. A similar situation exists for the second assembly (B), since the voltage difference between the two sources is the supply voltage, which contains only a small amount of high frequency ripple due to the filtering capacitance C_filt2.

[0112] Since the gate drive pulses of the two outputs of each gate drive circuit are complementary and no specific delay needs to be provided between them, the gate discharge energy of one output can be used to charge the other, and therefore only a small portion of the required drive energy needs to be supplied from the central supply circuit.

[0113] The use of inverter topologies is particularly interesting for implementing zero-voltage switching (ZVS) converters. ZVS is a soft-switching technique, meaning virtually lossless switching. For this purpose, resonant converters can be used, allowing high switching frequencies and therefore miniaturization of certain passive power components. ZVS means that the transistor is only turned on when the voltage between its drain and source terminals is (virtually) zero, since this prevents the occurrence of a short circuit of a charged capacitor, i.e., the output capacitance of the device. This is called hard switching. Therefore, the capacitor needs to be discharged by the current provided by the power conversion circuit.

[0114] For example, for section 0, where the junction node is increased from zero to the live voltage, initially the low-side switch BD2 is turned off (by turning off QL1). The current that was flowing into the junction node continues to flow, but now flows into both the low-side and high-side branches, thereby charging the output capacitance of QL1 (QL0 is still on) and simultaneously discharging the output capacitance of QH1.

[0115] Both the device current and output capacitance determine not only whether a final voltage level (here, the live voltage) is achieved, but also the duration and shape of the voltage transition at the junction node. Once this voltage is reached, the high-side master switch QH1 can be softly turned on since the voltage across its output capacitance is zero.

[0116] Device QH1 does not need to be turned on at that exact moment. If device QH1 is kept off for some longer, assuming current is still flowing into the junction node, this current will reverse bias QH1 and put it into diode mode. This provides some headroom for control of the gate drive signal, which is needed in the presence of adaptive dead-time control. The dead-time is the time during which both the lower and upper master switches are in the off state so that soft charging / discharging of the device's output capacitance can occur. This time may be fixed or adaptive, and in either case must be long enough to ensure a clean transition under all operating conditions.

[0117] During a mains overvoltage event (surge), all four transistors can be switched off so that the half-bridge with two bidirectional switches can withstand twice the maximum reverse drain-source blocking voltage.

[0118] The inverter may utilize two half-bridges with a resonant tank element (transformer, resonant capacitor) connected between two junction nodes.

[0119] Note that in the case of a common-drain configuration, the roles of the transistor pairs are reversed, so the common-source circuit example above can be routinely converted to a common-drain configuration by one skilled in the art.

[0120] FIG. 1 shows the front end of a power factor correction circuit with a resonant LLC converter and an inverter. A non-resonant PFC circuit may have the same configuration, but in that case the capacitor does not form part of the resonant circuit. Instead, it includes a DC blocking capacitor. While a relatively large capacitance is used for the DC blocking capacitor, resulting in a small voltage drop, the resonant capacitor experiences a large voltage drop because it is sized to operate somewhat near the resonant frequency formed with one of the inductors. The same circuit can also form a resonant converter circuit (without power factor correction) because the power factor correction function is performed by the converter control rather than the power circuit.

[0121] Those skilled in the art can understand and effect variations to the disclosed embodiments in practicing the claimed invention, from a study of the drawings, the specification and the appended claims. In the claims, the word "comprises" does not exclude other elements or steps, and the singular does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain means are recited in mutually different dependent claims does not indicate that a combination of these means cannot be used to advantage. It should be noted that where the term "adapted to" appears in the claims or the description, this term is intended to be equivalent to the term "configured to." Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. an input for receiving an unrectified AC input signal, the unrectified AC input signal including positive and negative polarities; a first terminal and a second terminal for receiving power from the input; a first bidirectional switch between the first terminal and the junction node, the first bidirectional switch including a first transistor and a second transistor coupled in anti-series; a second bidirectional switch between the second terminal and the junction node, the second bidirectional switch including a third transistor and a fourth transistor coupled in anti-series; a primary inductor between the junction node and a second node; a capacitor arrangement between the second node and the first terminal and / or the second terminal; a control circuit for controlling switching of the first transistor, the second transistor, the third transistor, and the fourth transistor; a first gate driver including a first primary winding, a first secondary winding coupled to the third transistor, and a second secondary winding coupled to the second transistor, wherein a gate drive pulse signal on the first secondary winding is complementary to a gate drive pulse signal on the second secondary winding; a second gate driver including a second primary winding, a third secondary winding coupled to the first transistor, and a fourth secondary winding coupled to the fourth transistor, wherein a gate drive pulse signal on the third secondary winding is complementary to a gate drive pulse signal on the fourth secondary winding; the first transistor and the second transistor have a common source at a junction node between the first transistor and the second transistor, and the third transistor and the fourth transistor have a common source at a junction node between the third transistor and the fourth transistor; The control circuit, for the first bidirectional switch, an on mode in which the first transistor and the second transistor are turned on; a first transition mode in which the first transistor is turned off and the second transistor is turned on; a second transition mode in which the second transistor is turned off and the first transistor is turned on; an off mode in which the first transistor and the second transistor are turned off; The control circuit, for the second bidirectional switch, an on mode in which the third transistor and the fourth transistor are turned on; a first transition mode in which the third transistor is turned off and the fourth transistor is turned on; a second transition mode in which the fourth transistor is turned off and the third transistor is turned on; an off mode in which the third transistor and the fourth transistor are turned off; The control circuit a control sequence for each bidirectional switch utilizing the on mode, the off mode, and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal; a control sequence for each bidirectional switch adapted to implement a control sequence utilizing the on mode, the off mode, and the second transition mode when a voltage at the first terminal is lower than a voltage at the second terminal.

2. 10. A power factor correction circuit comprising: the bridgeless inverter circuit of claim 1; and an output circuit including a secondary inductor coupled to the primary inductor.

3. 10. A bridgeless resonant converter comprising: the inverter circuit of claim 1; and an output circuit including a secondary inductor coupled to the primary inductor.

4. 1. A method for providing electrical reversal, comprising: receiving an unrectified AC input signal at a first terminal and a second terminal, the input signal having positive and negative polarities; controlling switching of a first bidirectional switch between the first terminal and a junction node and a second bidirectional switch between the second terminal and the junction node, wherein a primary-side inductor is between the junction node and a second node, a capacitor arrangement is between the second node and the first terminal and / or the second terminal, the first bidirectional switch includes a first transistor and a second transistor coupled in anti-series, and the second bidirectional switch includes a third transistor and a fourth transistor coupled in anti-series; the first transistor and the second transistor have a common source at a junction node between the first transistor and the second transistor, and the third transistor and the fourth transistor have a common source at a junction node between the third transistor and the fourth transistor; The method further comprises, for the first bidirectional switch: an on mode in which the first transistor and the second transistor are turned on; a first transition mode in which the first transistor is turned off and the second transistor is turned on; a second transition mode in which the second transistor is turned off and the first transistor is turned on; and implementing an off mode in which the first transistor and the second transistor are turned off; The method further comprises, for the second bidirectional switch: an on mode in which the third transistor and the fourth transistor are turned on; a first transition mode in which the third transistor is turned off and the fourth transistor is turned on; a second transition mode in which the fourth transistor is turned off and the third transistor is turned on; and implementing an off mode in which the third transistor and the fourth transistor are turned off; The method comprises a control sequence comprising: when the voltage at the first terminal is higher than the voltage at the second terminal, the control sequence for each bidirectional switch utilizes the on mode, the off mode, and the first transition mode; when the voltage at the first terminal is lower than the voltage at the second terminal, the control sequence for each bidirectional switch includes implementing a control sequence utilizing the on mode, the off mode, and the second transition mode; The method comprises: generating, by a first gate driver including a first primary winding, a first secondary winding coupled to the third transistor, and a second secondary winding coupled to the second transistor, a gate drive pulse signal at the first secondary winding and a gate drive pulse signal at the second secondary winding that is complementary to the gate drive pulse signal at the first secondary winding; generating, by a second gate driver including a second primary winding, a third secondary winding coupled to the first transistor, and a fourth secondary winding coupled to the fourth transistor, a gate drive pulse signal at the third secondary winding and a gate drive pulse signal at the fourth secondary winding that is complementary to the gate drive pulse signal at the third secondary winding.

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