Block-based adaptive resolution management

Abstract

The method includes receiving a reference frame, determining a scaling constant for a current block, scaling a block of the reference frame according to the scaling constant, the block of the reference frame corresponding to the current block, and reconstructing pixel data for the current block using the scaled block of the reference frame. Related apparatus, systems, techniques, and articles are also described.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 883,407, filed August 6, 2019, and entitled "BLOCK-BASED ADAPTIVE RESOLUTION MANAGEMENT," which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to the field of video compression, and more particularly to block-based adaptive resolution management. [Background technology]

[0003] A video codec can include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video into a compressed format, or vice versa. In the context of video compression, a device that compresses video (and / or performs some function thereof) can typically be called an encoder, and a device that decompresses video (and / or performs some function thereof) can be called a decoder.

[0004] The format of the compressed data can conform to standard video compression specifications. The compression can be lossy, in that the compressed video lacks some information present in the original video. The consequences of this can include the decompressed video having lower quality than the original uncompressed video because there is insufficient information to accurately reconstruct the original video.

[0005] There can be a complex relationship between video quality, the amount of data used to represent the video (e.g., determined by bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end delay (e.g., latency), and the like.

[0006] Motion compensation can include an approach for predicting a video frame or a portion thereof given a reference frame, such as an immediately preceding and / or future frame, by taking into account the motion of the camera and / or objects in the video. This can be employed in encoding and decoding video data for video compression, for example, in encoding and decoding using the Moving Picture Experts Group (MPEG) Advanced Video Coding (AVC) standard (also referred to as H.264). Motion compensation can describe a picture in terms of transforming a reference picture into a current picture. The reference picture can be temporally immediately preceding compared to the current picture or from the future compared to the current picture. Compression efficiency can be improved when images can be accurately synthesized from previously transmitted and / or stored images. Summary of the Invention [Means for solving the problem]

[0007] In one aspect, the decoder includes circuitry configured to receive a reference frame, determine a scaling constant for a current block, scale a block of the reference frame that corresponds to the current block according to the scaling constant, and reconstruct pixel data for the current block using the scaled block of the reference frame.

[0008] In another aspect, a method includes receiving a reference frame; determining a scaling constant for a current block; scaling a block of the reference frame according to the scaling constant, the block of the reference frame corresponding to the current block; and reconstructing pixel data for the current block using the scaled block of the reference frame.

[0009] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. The present invention provides, for example, the following. (Item 1) a decoder, the decoder comprising circuitry; The circuitry comprises: receiving a reference frame; determining a scaling constant for the current block; scaling a block of the reference frame according to the scaling constant, the block of the reference frame corresponding to the current block; reconstructing pixel data for the current block using the scaled block of the reference frame; and a decoder configured to: (Item 2) The decoder further comprises: receiving a bitstream; determining the scaling constant from the bitstream, the scaling constant being signaled within the bitstream; Item 1. The decoder of item 1, configured to: (Item 3) Item 3. The decoder of item 2, wherein the bitstream includes an index to a predetermined scaling constant. (Item 4) Item 1 . The decoder of item 1 , wherein the decoder is configured to receive the reference frame by accessing the reference frame from a memory. (Item 5) Item 1 , the decoder being configured to scale blocks of the reference frame by interpolating pixel values. (Item 6) 10. The decoder of claim 9, wherein the interpolating pixel values ​​is performed using a sub-pixel prediction interpolation filter. (Item 7) 2. The decoder of claim 1, wherein reconstructing the pixel data includes processing the current block using an inter-prediction mode, and the reconstructing includes determining the current block by combining at least a predicted block and a residual, the predicted block being determined using a scaled block of the reference frame. (Item 8) Item 1 , the decoder being configured to receive a bitstream, the bitstream including a field characterizing a skip adaptive resolution management mode. (Item 9) The decoder further comprises: processing a plurality of blocks according to an adaptive resolution management mode, said processing comprising: applying a first filter to a first current block of the plurality of current blocks; applying a second filter to a second current block of the plurality of current blocks, the plurality of blocks forming a portion of a frame; Including Item 1. The decoder of item 1, configured to: (Item 10) an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor configured to process the quantized coefficients including performing inverse discrete cosine; A deblocking filter; A frame buffer and an intra-prediction processor; Item 1. The decoder of item 1, further comprising: (Item 11) 1. A method, comprising: receiving a reference frame; determining a scaling constant for the current block; scaling the block of the reference frame according to the scaling constant, the block of the reference frame corresponding to the current block; reconstructing pixel data for the current block using the scaled block of the reference frame; A method comprising: (Item 12) receiving a bitstream; determining the scaling constant from the bitstream, the scaling constant being signaled within the bitstream; Item 12. The method of item 11, further comprising: (Item 13) Item 13. The method of item 12, wherein the bitstream includes an index to a predetermined scaling constant. (Item 14) Item 12. The method of item 11, wherein receiving the reference frame includes accessing the reference frame from a memory. (Item 15) Item 12. The method of item 11, wherein scaling the blocks of the reference frame includes interpolating pixel values. (Item 16) Item 21. The method of item 20, wherein the interpolating pixel values ​​is performed using a sub-pixel prediction interpolation filter. (Item 17) Item 12. The method of item 11, wherein reconstructing the pixel data includes processing the current block using an inter-prediction mode, and the processing further includes determining the current block by combining at least a predicted block and a residual, the predicted block being determined using a scaled block of the reference frame. (Item 18) Item 12. The method of item 11, further comprising receiving a bitstream, the bitstream including a field characterizing a skip adaptive resolution management mode. (Item 19) The method further includes processing the plurality of blocks according to an adaptive resolution management mode, the processing comprising: applying a first filter to a first current block of the plurality of current blocks; applying a second filter to a second current block of the plurality of current blocks, the plurality of blocks forming a portion of a frame; The method according to item 1, comprising: (Item 20) At least one of the receiving, determining, scaling, and reconstructing is performed by a decoder, the decoder comprising: an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor configured to process the quantized coefficients, the inverse quantization and inverse transform processor including performing inverse discrete cosine; A deblocking filter; A frame buffer and an intra-prediction processor; The method of item 1, comprising: [Brief explanation of the drawings]

[0010] For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention, it being understood, however, that this invention is not limited to the precise arrangements and instrumentalities shown in the drawings.

[0011] [Figure 1] FIG. 1 is a diagram of exemplary reference frames and exemplary predicted frames at various resolution scales.

[0012] [Figure 2] FIG. 2 is a diagram depicting an example reference frame, an example rescaled reference frame, and an example subsequent block prediction process.

[0013] [Figure 3] FIG. 3 is a process flow diagram illustrating an example process according to some implementations of the present subject matter.

[0014] [Figure 4] FIG. 4 is a system block diagram illustrating an example decoder capable of decoding a bitstream in accordance with some implementations of the present subject matter.

[0015] [Figure 5] FIG. 5 is a process flow diagram illustrating an exemplary process for encoding video according to some implementations of the present subject matter.

[0016] [Figure 6] FIG. 6 is a system block diagram illustrating an example video encoder in accordance with some implementations of the present subject matter.

[0017] [Figure 7]FIG. 7 is a block diagram of a computing system that may be used to implement any one or more of the methodologies disclosed herein and in any one or more portions thereof.

[0018] The drawings are not necessarily to scale and may be illustrated by phantom lines, schematic representations, and partial views. In some instances, details that are not necessary for an understanding of the embodiments or that make other details difficult to perceive may be omitted. Like reference symbols in various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0019] Detailed Description In many current state-of-the-art encoders, resolution is managed by recoding and retransmitting entire portions of video known as groups of pictures (GOPs). This requires transmitting intra-frames (I-frames), which can incur additional cost, since these frames contribute most of the bits within a GOP.

[0020]

[0003] Embodiments described in this disclosure relate to adaptive resolution management (ARM), a technique that enables additional flexibility for video encoders / decoders, enabling bitrate savings in various use cases. Generally, ARM involves performing prediction using reference frames of a different resolution than the current frame. In current coding standards, the reference frames have the same resolution as the predicted frame. In ARM, the reference frames can be of a lower or higher resolution than the frame being predicted. This approach can be used to downscale video resolution, thus reducing bitrate, or upscale video resolution, thus enhancing the display characteristics of video playback.

[0021] ARM may alternatively, or equivalently, be referred to as reference picture resampling (RPR) for purposes of this disclosure, and RPR and ARM may be used synonymously.

[0022] Some implementations of the present subject matter may include using ARM for any number of frames at any position within a GOP, thus eliminating the requirement for recoding I-frames.

[0023] FIG. 1 is a diagram of reference frames and predicted frames of various resolution scales. Frame 1 is smaller (lower resolution) than the reference frame, Frame 2 is the same size (same resolution), while Frame 3 is larger (higher resolution). "Resolution," as used in this disclosure, refers to the number of pixels in a picture, frame, subframe, and / or other displayed area or portion thereof used in video playback, compression, or the like, with a higher number of pixels corresponding to a higher resolution and a lower number of pixels corresponding to a lower resolution. Resolution may be measured in terms of area, for example, but not limited to, by using one or more dimensions, measured in pixels, that define an area. For example, a circular subframe or other region may have a resolution defined according to its radius. Alternatively, or in addition, resolution may be defined by the total number of pixels.

[0024] As an example, with continued reference to FIG. 1 , if the reference frame and / or subframes have a geometric form whose area can be completely defined in terms of two length parameters, such as, but not limited to, a triangle, parallelogram, and / or rectangular form, the reference frame and / or subframes may have a resolution W×H (W and H may indicate the number of pixels describing the width (or base) and height dimensions of the reference frame and / or subframe, respectively). Each predicted frame may also have a resolution that can be determined similarly to the resolution of the reference frame; for example, frame 1 may have a lower resolution WS×HS, frame 2 may have the same resolution as the reference frame W×H, and frame 3 may have a higher resolution WL×HL. The widths and heights of smaller and larger frames may be obtained by multiplying the reference width and height by an arbitrary rescaling constant (Rc), also referred to as a scaling ratio and / or constant. In the case of smaller frames, Rc may have a value between 0 and 1. In the case of larger frames, Rc may have a value greater than 1, for example, Rc may have a value between 1 and 4. Other values ​​are possible. The rescaling constants may differ from one another for one resolution dimension, for example, a rescaling constant Rch may be used to rescale the height, while another rescaling constant Rcw may be used to rescale the width.

[0025] Still referring to FIG. 1, ARM may be implemented as a mode. In the case of ARM mode activation at some point during decoding, the decoder may have already received reference frames at resolution W×H and may rescale predicted frames using a rescaling constant. In some implementations, the encoder may signal the rescaling constant to use to the decoder. The signaling may be performed within the sequence parameter set (SPS) corresponding to the GOP containing the current picture and / or the picture parameter set (PPS) corresponding to the current picture. For example, without limitation, the encoder may signal the rescaled parameters using fields such as pps_pic_width_in_luma_samples, pps_pic_height_in_luma_samples, pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, pps_scaling_win_bottom_offset, and / or sps_num_subpics_minus1.

[0026] 1 , the W and H parameters as described above may be represented using, but not limited to, the variables CurrPicScalWinWidthL and CurrPicScalWinHeightL, respectively, which may be derived from the signaled parameters as described above using one or more mathematical relationships between the signaled parameters and the variables. For example, but not limited to, CurrPicScalWinWidthL may be derived according to the following equation: CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset) As a further non-limiting example, CurrPicScalWinHeightL may be derived according to the following equation: CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset)

[0027] Those skilled in the art will recognize, upon review of this disclosure in its entirety, various alternative calculations that may be used to derive the variables described above. The encoder may alternatively or additionally signal one or more such variables Rc, Rch, and / or Rcw directly within the PPS and / or SPS, for example, but not by way of limitation.

[0028] Alternatively, or in addition, still referring to FIG. 1, a rescaling constant and / or set of rescaling constants as described above may be signaled in the bitstream using a reference to a stored scaling constant and / or multiple scaling constants and / or an index of a frame and / or block signaled using a previously signaled and / or utilized scaling constant and / or multiple scaling constants. The reference to the index of the stored scaling constant may be explicitly signaled and / or determined from one or more additional parameters signaled in the bitstream. For example, without limitation, the decoder may identify a group of pictures containing a reference frame and / or a current frame, and if a rescaling constant has been previously signaled and / or utilized within such group of pictures, with the reference frame signaled as applicable to the current frame and / or current group of pictures, or the like, the decoder may identify that rescaling constant for use as a rescaling constant with the current frame.

[0029] In some implementations, with continued reference to FIG. 1, ARM operations may be performed according to the block level of an encoded frame. For example, a reference frame may first be rescaled, followed by prediction as depicted in FIG. 2. FIG. 2 is a diagram depicting a reference frame, a rescaled reference frame, and a subsequent block prediction process. The block prediction process may be performed on the scaled reference frame (having a scaled resolution) rather than the original reference frame. Rescaling the reference frame may include rescaling according to any parameters signaled by the encoder, as described above; for example, but not limited to, if a reference frame to be used with the current picture is signaled via a reference to an index value associated with the reference frame or the like, the signaled reference frame may be rescaled according to any of the rescaling methods described above prior to prediction. The rescaled reference frames may be stored in memory and / or buffers, which may include, but are not limited to, a buffer that identifies the frame contained therein by an index, according to a frame retrieval that may be performed, and which may include a decoded picture buffer (DCB) and / or one or more additional buffers implemented by the decoder. The prediction process may include, for example, inter-picture prediction, including motion compensation.

[0030] Some implementations of block-based ARM may allow the flexibility of applying an optimal filter per block instead of applying the same filter across the entire frame. In some implementations, skip ARM mode may be considered a possibility, such that some blocks (e.g., based on uniformity of pixel and bitrate cost) may be in skip ARM mode (such that rescaling would not change the bitrate). Skip ARM mode may be signaled within the bitstream, for example, but not by way of limitation, skip ARM mode may be signaled within the PPS parameters. Alternatively, or in addition, the decoder may determine that skip ARM mode is active based on one or more parameters set by the decoder and / or signaled within the bitstream. Spatial filters used within the block-based ARM may include, but are not limited to, bicubic spatial filters that apply bicubic interpolation, bilinear spatial filters that apply bilinear interpolation, Lanczos filters that use Lanczos filtering, and / or sinc filters, Lanczos resampling that uses a combination of sinc function interpolation and / or signal reconstruction techniques, or the like; those skilled in the art will recognize a variety of filters that may be used consistently with this disclosure for interpolation upon review of the entirety of this disclosure.

[0031] FIG. 3 is a process flow diagram illustrating one example embodiment of a process 300 of block-based adaptive resolution management that may enable additional flexibility for video encoders / decoders, enabling bitrate savings in various use cases.

[0032] At step 305, still referring to FIG. 3, a reference frame is received. The reference frame may be received by (e.g., accessed from) a memory; for example, without limitation, the reference frame may be accessed from a frame buffer. The reference frame may have been previously decoded from a bitstream. The bitstream may have been received by a decoder. The bitstream may include the current block. The current block may be contained within a bitstream received by the decoder. The bitstream may include data found in a stream of bits that is input to the decoder when using data compression, for example, as described in further detail below. The bitstream may include information necessary to decode the video. Receiving may include extracting and / or parsing the block and associated signaling information from the bitstream. In some implementations, the current block may include a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU).

[0033] 3, at step 310, a scaling constant may be determined for the current block. In some implementations, the scaling constant may be determined from the bitstream. For example, the scaling constant may be signaled, such as directly within the bitstream, and / or the bitstream may include an index to a predetermined scaling constant.

[0034] At step 315, still referring to FIG. 3, a block of a reference frame may be scaled according to a scaling constant. The block of the reference frame may correspond to the current block. Scaling the block of the reference frame may include interpolating pixel values ​​to determine pixel values ​​for the scaled block. In some implementations, interpolating pixel values ​​may be performed using a sub-pixel prediction interpolation filter. The interpolation filter may include, by way of non-limiting example and not limitation, a low-pass filter that may be used with an upsampling process whereby pixels between pixels of the block and / or frame immediately prior to scaling are initialized to zero and then the output of the low-pass filter may be taken. Alternatively, or in addition, any luma sample interpolation filtering process may be used. Luma sample interpolation may include calculating an interpolated value at a half-sample interpolation filter index that falls between two consecutive sample values ​​of the unscaled sample array. Calculation of the interpolated values ​​may be performed, without limitation, by reading coefficients and / or weights from a lookup table, with the selection of the lookup table being performed as a function of the coding unit and / or motion model of the scaling ratio, for example, as determined using the scaling constants as described above. The calculation may include, without limitation, performing a weighted sum of adjacent pixel values, where the weights are read from a lookup table. Alternatively or additionally, the calculated values ​​may be shifted, for example, without limitation, by a minimum value (4, i.e., bit depth minus 8), 6, a maximum value (2, i.e., 14-bit depth), or the like. Those skilled in the art will recognize various alternative or additional implementations that may be used for the interpolation filters upon review of the entirety of this disclosure.

[0035] At step 320, and still referring to FIG. 3, pixel data for the current block may be reconstructed using a scaled block of the reference frame. Reconstructing the pixel data may include processing the current block using an inter-prediction mode, which may include determining the current block by combining at least a predicted block and a residual. The predicted block may be determined using a scaled block of the reference frame.

[0036] In some implementations, multiple blocks may be processed according to an adaptive resolution management mode. The processing may include applying a first filter to a first current block of the multiple current blocks and applying a second filter to a second current block of the multiple current blocks. The multiple blocks may form a portion of a frame. The decoder may use a predefined, ordered list of filters by default, or the encoder may calculate an optimal filter for a given frame and / or portion thereof and signal the optimal filter to the decoder.

[0037] In some implementations, the bitstream may include a field that characterizes the skip adaptive resolution management mode.

[0038] 4 is a system block diagram illustrating an example decoder 400 capable of block-based adaptive resolution management. The decoder 400 may include an entropy decoder processor 404, an inverse quantization and inverse transform processor 408, a deblocking filter 412, a frame buffer 416, a motion compensation processor 420, and / or an intra-prediction processor 424.

[0039] In operation, still referring to FIG. 4, a bitstream 428 may be received by the decoder 400 and input to the entropy decoder processor 404, which may entropy decode a portion of the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 408, which may perform inverse quantization and inverse transform and generate a residual signal, which may be added to the output of the motion compensation processor 420 or the intra-prediction processor 424, depending on the processing mode. The output of the motion compensation processor 420 and the intra-prediction processor 424 may include a block prediction based on the previously decoded block. The prediction and residual sum may be processed by the deblocking filter 412 and stored in the frame buffer 416.

[0040] 5 is a process flow diagram illustrating an example process 500 for encoding video according to block-based adaptive resolution management, which may allow additional flexibility for video encoders / decoders, enabling bitrate savings in various use cases. In step 505, a video frame may undergo initial block segmentation using, for example, a tree-structured macroblock partitioning scheme, which may include partitioning the picture frame into CTUs and CUs.

[0041] At step 510, still referring to FIG. 5, block-based adaptive resolution management may be performed, including resolution scaling of a frame or portion thereof.

[0042] At step 515, and continuing with reference to Figure 5, the block may be encoded and included in the bitstream. Encoding may include, for example, utilizing inter-prediction and intra-prediction modes.

[0043] 6 is a system block diagram illustrating an example video encoder 600 capable of encoding video using a reordering of fusion candidates based on global motion vectors. The example video encoder 600 may receive an input video 604, which may first be segmented or divided according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree + binary tree). An example of a tree-structured macroblock partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks, called coding units (CUs). The final result of this partitioning may include a group of sub-blocks, which may be called a prediction unit (PU). Transform units (TUs) may also be utilized.

[0044] 6, the exemplary video encoder 600 may include an intra-prediction processor 608, a motion estimation / compensation processor 612, which may also be referred to as an inter-prediction processor, which may build a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, a transform / quantization processor 616, an inverse quantization / inverse transform processor 620, an in-loop filter 624, a decoded picture buffer 628, and / or an entropy coding processor 632. Bitstream parameters may be input to the entropy coding processor 632 for inclusion in an output bitstream 636.

[0045] 6, for each block of a frame of the input video 604, it may be determined whether to process the block via intra-picture prediction or using motion estimation / compensation. The block may be provided to the intra-prediction processor 608 or the motion estimation / compensation processor 612. If the block is to be processed via intra-prediction, the intra-prediction processor 608 may perform processing and output a predictor. If the block is to be processed via motion estimation / compensation, the motion estimation / compensation processor 612 may perform processing, including building a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, if applicable.

[0046] Continuing with reference to FIG. 6, a residual may be formed by subtracting the predictor from the input video. The residual may be received by a transform / quantization processor 616, which may perform a transform operation (e.g., a discrete cosine transform (DCT)) to produce coefficients, which may be quantized. The quantized coefficients and any associated signaling information may be provided to an entropy coding processor 632 for entropy encoding and inclusion in an output bitstream 636. The entropy encoding processor 632 may assist in encoding signaling information related to encoding the current block. Additionally, the quantized coefficients may be combined with the predictor and provided to an inverse quantization / inverse transform processor 620, which may reconstruct pixels that may be processed by an in-loop filter 624, the output of which may be stored in a decoded picture buffer 628 for use by a motion estimation / compensation processor 612, which may build a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list.

[0047] 6, while several variations have been described in detail above, other modifications or additions are possible. For example, in some implementations, the current block may include any symmetric block (8x8, 16x16, 32x32, 64x64, 128x128, and the like) as well as any asymmetric block (8x4, 16x8, and the like).

[0048] In some implementations, still referring to FIG. 6, a quadtree plus binary decision tree (QTBT) may be implemented. In QTBT, at the coding tree unit level, partition parameters of the QTBT may be dynamically derived to adapt to local characteristics without transmitting any overhead. Subsequently, at the coding unit level, a joint classifier decision tree structure may eliminate unnecessary iterations and control the risk of erroneous predictions. In some implementations, an LTR frame block update mode may be available as an additional option available per leaf node of the QTBT.

[0049] In some implementations, still referring to Figure 6, additional syntax elements may be signaled at different hierarchical levels of the bitstream. For example, a flag may be enabled throughout a sequence by including an enabled flag coded in a sequence parameter set (SPS). Furthermore, a CTU flag may be coded at the coding tree unit (CTU) level.

[0050] Some embodiments may include a non-transitory computer program product (i.e., a physically embodied computer program product) storing instructions that, when executed by one or more data processors of one or more computing systems, cause at least one data processor to perform the operations herein.

[0051] Embodiments disclosed herein include a decoder that includes circuitry configured to receive a reference frame, determine a scaling constant for a current block, scale a block of the reference frame that corresponds to the current block according to the scaling constant, and reconstruct pixel data for the current block using the scaled block of the reference frame.

[0052] The decoder may be further configured to receive a bitstream and determine a scaling constant from the bitstream, the scaling constant being signaled within the bitstream. The bitstream may include an index to a predetermined scaling constant. The decoder may be configured to receive a reference frame by accessing the reference frame from a memory. The decoder may be configured to scale blocks of the reference frame by interpolating pixel values. Interpolating the pixel values ​​may be performed using a sub-pixel prediction interpolation filter. Reconstructing pixel data may include processing the current block using an inter-prediction mode, where the reconstructing includes determining the current block by combining a residual with at least a predicted block, the predicted block being determined using a scaled block of the reference frame. The decoder may be configured to receive a bitstream, the bitstream including a field characterizing a skip adaptive resolution management mode. The decoder may be further configured to process a plurality of blocks according to the adaptive resolution management mode, the processing including applying a first filter to a first current block of the plurality of current blocks and applying a second filter to a second current block of the plurality of current blocks, the plurality of blocks forming part of a frame. The decoder may include an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

[0053] Embodiments disclosed herein may include a method that may include receiving a reference frame, determining a scaling constant for a current block, scaling a block of the reference frame according to the scaling constant, where the block of the reference frame corresponds to the current block, and reconstructing pixel data for the current block using the scaled block of the reference frame.

[0054] The method may additionally include receiving a bitstream and determining a scaling constant from the bitstream, the scaling constant being signaled within the bitstream. The bitstream may include an index to a predetermined scaling constant. Receiving a reference frame may include accessing the reference frame from a memory. Scaling the blocks of the reference frame may include interpolating pixel values. Interpolating the pixel values ​​may be performed using a sub-pixel prediction interpolation filter. Reconstructing pixel data includes processing a current block using an inter-prediction mode, the processing further including determining the current block by combining a residual with at least a predicted block, the predicted block being determined using the scaled block of the reference frame. The method may include receiving a bitstream, the bitstream including a field characterizing a skip adaptive resolution management mode. The method may include processing a plurality of blocks according to the adaptive resolution management mode, the processing including applying a first filter to a first current block of the plurality of current blocks and applying a second filter to a second current block of the plurality of current blocks, the plurality of blocks forming part of a frame. At least one of receiving, determining, scaling, and reconstructing may be performed by a decoder including an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

[0055] It should be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic circuitry, integrated circuit networking, specially designed application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof, as embodied and / or implemented in one or more machines (e.g., one or more computing devices utilized as user computing devices for electronic documents, one or more server devices, such as document servers, etc.) programmed according to the teachings herein, as would be apparent to those skilled in the computer arts. These various aspects or features may include implementation in one or more computer programs and / or software executable and / or interpretable on a programmable system including at least one programmable processor, which may be special-purpose or general-purpose, coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Appropriate software coding can be readily prepared by skilled programmers based on the teachings of the present disclosure, as would be apparent to those skilled in the software arts. The above-discussed aspects and implementations employing software and / or software modules may also include appropriate hardware to assist in implementing the machine-executable instructions of the software and / or software modules.

[0056] Such software may be a computer program product employing a machine-readable storage medium. A machine-readable storage medium may be any medium capable of storing and / or encoding sequences of instructions for execution by a machine (e.g., a computing device), causing the machine to perform any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random-access memory "RAM" devices, magnetic cards, optical cards, solid-state memory devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and / or any combination thereof. As used herein, machine-readable medium is intended to include a single medium as well as a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with computer memory. As used herein, machine-readable storage medium does not include a transitory form of signal transmission.

[0057] Such software may also include information (e.g., data) carried in a data signal on a data carrier, such as a carrier wave. For example, machine-executable information may be included as a data carrier signal embodied in a data carrier, which signal encodes a sequence of instructions, or portions thereof, for execution by a machine (e.g., a computing device), and any associated information (e.g., data structures and data) that causes the machine to perform any one of the methodologies and / or embodiments described herein.

[0058] Examples of computing devices include, but are not limited to, e-book reading devices, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smartphones, etc.), web appliances, network routers, network switches, network bridges, any machine capable of executing a sequence of instructions that define actions to be taken by the machine, and any combination thereof. In one example, the computing device may include and / or be included within a kiosk.

[0059] 7 shows a diagrammatic representation of one embodiment of a computing device in the exemplary form of a computer system 700 upon which a set of instructions for causing a control system to implement any one or more of the aspects and / or methodologies of the present disclosure may be executed. It is also contemplated that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more of the devices to implement any one or more of the aspects and / or methodologies of the present disclosure. Computer system 700 includes a processor 704 and a memory 708, which communicate with each other and with other components via a bus 712. Bus 712 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of a variety of bus architectures.

[0060] Memory 708 may include a variety of components (e.g., machine-readable media), including, but not limited to, random-access memory components, read-only components, and any combination thereof. In one example, a basic input / output system 716 (BIOS), containing the basic routines that help to transfer information between elements within computer system 700, such as during start-up, may be stored in memory 708. Memory 708 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 720 that embody any one or more aspects and / or methodologies of the present disclosure. In another example, memory 708 may further include any number of program modules, including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0061] Computer system 700 may also include a storage device 724. Examples of a storage device (e.g., storage device 724) include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disk drive in combination with optical media, a solid-state memory device, and any combination thereof. Storage device 724 may be connected to bus 712 by an appropriate interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE®), and any combination thereof. In one embodiment, storage device 724 (or one or more components thereof) may removably interface with computer system 700 (e.g., via an external port connector (not shown)). In particular, storage device 724 and associated machine-readable media 728 may provide nonvolatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for computer system 700. In one embodiment, software 720 may reside, completely or partially, within machine-readable medium 728. In another embodiment, software 720 may reside, completely or partially, within processor 704.

[0062] Computer system 700 may also include input devices 732. In one embodiment, a user of computer system 700 may type commands and / or other information into computer system 700 via input devices 732. Examples of input devices 732 include, but are not limited to, an alphanumeric input device (e.g., a keyboard), a pointing device, a joystick, a gamepad, an audio input device (e.g., a microphone, a voice response system, etc.), a cursor control device (e.g., a mouse), a touchpad, an optical scanner, a video capture device (e.g., a still camera, a video camera), a touch screen, and any combination thereof. Input devices 732 may interface to bus 712 via any of a variety of interfaces (not shown), including, but not limited to, a serial interface, a parallel interface, a gameport, a USB interface, a FIREWIRE® interface, an interface directly to bus 712, and any combination thereof. Input devices 732 may include a touch screen interface, which may be part of or separate from display 736, discussed further below. The input device 732 may be utilized as a user selection device for selecting one or more graphical representations within a graphical interface such as those described above.

[0063] A user may also input commands and / or other information into computer system 700 via storage device 724 (e.g., a removable disk drive, flash drive, etc.) and / or network interface device 740. A network interface device such as network interface device 740 may be utilized to connect computer system 700 to one or more of various networks, such as network 744, and one or more remote devices 748 connected thereto. Examples of network interface devices include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of networks include, but are not limited to, a wide area network (e.g., the Internet, an enterprise network), a local area network (e.g., a network associated with an office, building, campus, or other relatively small geographic space), a telephone network, a data network associated with a telephone / voice provider (e.g., a mobile communications provider's data and / or voice network), a direct connection between two computing devices, and any combination thereof. A network such as network 744 may employ wired and / or wireless modes of communication. In general, any network topology may be used. Information (e.g., data, software 720, etc.) may be communicated to and / or from computer system 700 via network interface device 740.

[0064] Computer system 700 may further include a video display adapter 752 for communicating images displayable on a display device, such as display device 736. Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combination thereof. Display adapter 752 and display device 736 may be utilized in combination with processor 704 to provide graphical representations of aspects of the present disclosure. In addition to a display device, computer system 700 may include one or more other peripheral output devices, including, but not limited to, audio speakers, a printer, and any combination thereof. Such peripheral output devices may be connected to bus 712 via a peripheral interface 756. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a FIREWIRE® connection, a parallel connection, and any combination thereof.

[0065] The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions may be made without departing from the spirit and scope of the present invention. Features of each of the various embodiments described above may be combined, as appropriate, with features of other described embodiments to provide combinations of features in related new embodiments. Moreover, while the foregoing describes several separate embodiments, what has been described herein merely illustrates the application of the principles of the present invention. In addition, although certain methods herein may be illustrated and / or described as being performed in a particular order, the order may be highly variable among those skilled in the art to achieve the embodiments as disclosed herein. Therefore, the present description is intended to be exemplary only and is not intended to otherwise limit the scope of the present invention.

[0066] In the above description and in the claims, phrases such as "at least one of" or "one or more of" may appear and be followed by a conjunctive listing of elements or features. The term "and / or" may also appear within a listing of two or more elements or features. Unless otherwise implicitly or explicitly contradicted by the context in which such a phrase is used, this is intended to mean any of the listed elements or features individually or any of the recited elements or features in combination with any of the other recited elements or features. For example, the phrases "at least one of A and B," "one or more of A and B," and "A and / or B" are intended to mean "A alone, B alone, or A and B together," respectively. A similar interpretation is also intended with respect to listings containing three or more items. For example, the phrases "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, and / or C" are intended to mean "A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together," respectively. Additionally, use of the term "based on" above and in the claims is intended to mean "based at least on," so that unrecited features or elements also qualify as permissible.

[0067] The subject matter described herein can be embodied in systems, devices, methods, and / or articles, depending on the desired configuration. The implementations described in the foregoing description do not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. While some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations can be provided in addition to those described herein. For example, the implementations described above can be directed to various combinations and subcombinations of the disclosed features and / or combinations and subcombinations of some additional features disclosed above. In addition, the logic flow depicted in the accompanying figures and / or described herein does not necessarily require the particular order shown or sequential order to achieve desirable results. Other implementations may be within the scope of the following claims.

Claims

1. a decoder, the decoder comprising circuitry; The circuitry comprises: receiving a bitstream including a current picture including a coded current block and a reference picture, said bitstream also including an index useful for determining a scaling factor; determining that a mode is enabled when the reference picture and the current picture have different resolutions; Using the above mode, determining a scaling factor using information in the bitstream including the index; determining a scaled prediction block by scaling a block of the reference picture using the scaling factor and by applying a pixel interpolation filter, the pixel interpolation filter being determined specifically for the prediction block; and combining the scaled prediction block with a residual; and reconstructing the coded current block by a decoder configured to:

2. 2. The decoder of claim 1, wherein the current picture includes a second coded current block, the mode is skipped for the second coded current block, and the decoder reconstructs the second coded current block without using scaled predictive blocks of a reference picture.

Images