Reference voltage source circuit

Abstract

To provide a highly reliable and stable reference voltage source circuit that suppresses and reduces fluctuations in output voltage caused by leakage current generated in bipolar transistors at high temperatures.SOLUTION: In a reference voltage source circuit, a collector of a first transistor 3 for suppression, which uses an NPN bipolar transistor, is connected to a collector of a first transistor 1 for generation, a collector of a second transistor 4 for suppression, which uses the NPN bipolar transistor, is connected to a drain of a first transistor 16 for output, and a base and an emitter of each of the first transistor for suppression and the second transistor for suppression are opened. By setting a normalized emitter area ratio of the first transistor 1 for generation as 1, normalized emitter area ratios of both a second transistor for generation and the second transistor for suppression as m, and an emitter area ratio of the first transistor for suppression as m-1, fluctuations in reference voltage VBG due to temperature changes are suppressed and reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a reference voltage source circuit that enables a highly accurate voltage output, and more particularly to a circuit that aims to stabilize output voltage characteristics at high temperatures and improve reliability. [Background technology]

[0002] As a reference voltage source circuit, which is one of the voltage sources used in analog circuits, a circuit that utilizes a so-called dead gap voltage to enable a constant voltage output without being affected by fluctuations in temperature or power supply voltage is well known. Also, various circuits have been disclosed as reference voltage source circuits that utilize such dead gap voltage (see, for example, Patent Document 1, Non-Patent Document 1, Non-Patent Document 2, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 3,617,859 [Non-patent literature]

[0004] [Non-Patent Document 1] Kunihiro Asada, Yutaka Nagata, and PR Gray, co-authors, "Analog Integrated Circuit Design Technology for System LSI (Basics) (Applications)," Baifukan Publishing, 2004 [Non-patent document 2] Banba, Shiga, Umezawa, Miyaba, Tanzawa, Atsumi, Sakui, "A CMOS bandgap reference circuit with sub-1-V operation", IEEE Journal of Solid-State Circuits, May 1999, Vol.34, pp.670-674 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a reference voltage source circuit configured to use the bandgap voltage of a bipolar transistor, a PN junction formed between the collector of the bipolar transistor and the circuit board causes leakage current from the collector to the circuit board in a high-temperature environment. This current increases exponentially with increasing temperature, and depending on the circuit configuration, this current may flow to the output side, causing fluctuations in the output voltage.

[0006] The present invention has been made in view of the above circumstances, and provides a highly reliable and stable reference voltage source circuit that suppresses and reduces fluctuations in output voltage caused by leakage current that occurs in bipolar transistors at high temperatures. [Means for solving the problem]

[0007] In order to achieve the above object of the present invention, a reference voltage source circuit according to the present invention comprises: a bandgap voltage generating circuit is provided, which has first and second generating transistors that are NPN bipolar transistors and is configured to be able to generate a bandgap voltage; the bases of the first and second generating transistors are connected to each other, while the emitter of the first generating transistor is connected to ground and the emitter of the second generating transistor is connected to ground via a first resistor; the collectors of the first and second generating transistors are connected to a first negative feedback circuit, and the collector of the second generating transistor is connected to a second negative feedback circuit; the first negative feedback circuit includes first to third transistors for first negative feedback using P-channel MOSFETs, and a fourth transistor for first negative feedback using an N-channel MOSFET; a positive power supply voltage can be applied to the sources of the first to third negative feedback transistors, and gates thereof are connected to each other and to the drain of the first negative feedback first transistor, the drain of the first negative feedback fourth transistor, and an output circuit; the drain of the first negative feedback second transistor is connected to the collector of the generating first transistor, and the drain of the first negative feedback third transistor is connected to the collector of the generating second transistor; the collector of the first generating transistor is connected to the gate of the first negative feedback fourth transistor, and the source of the first negative feedback fourth transistor is connected to ground; the second negative feedback circuit includes first and second transistors for second negative feedback using P-channel MOSFETs, and a third transistor for second negative feedback using N-channel MOSFETs; a positive power supply voltage can be applied to the sources of the second negative feedback first and second transistors, and gates thereof are connected to each other and to the drain of the second negative feedback first transistor, the drain of the second negative feedback third transistor, and the output circuit; a source of the second negative feedback third transistor is connected to ground, and a gate of the second negative feedback third transistor is connected to the collector of the generating second transistor; and a drain of the second negative feedback second transistor is connected to the bases of the first and second generating transistors and to ground via a second resistor; the output circuit includes first and second output transistors using P-channel MOSFETs, and a positive power supply voltage can be applied to the sources of the first and second output transistors, while the gates of the first to third first negative feedback transistors are connected to the gate of the first output transistor, and the gate of the second output transistor is connected to the gates of the first and second second negative feedback transistors, and the drains of the first output transistor and the second output transistor are connected to each other and to ground via a third resistor; a collector of a first suppression transistor, which is an NPN bipolar transistor, is connected to a collector of the first generation transistor, and a base and an emitter of the first suppression transistor are in an open state; the drains of the first and second output transistors are connected to the collector of a second suppression transistor, which is an NPN bipolar transistor, and the base and emitter of the second suppression transistor are open; The circuit is configured so as to be able to suppress temperature-dependent fluctuations in the reference voltages output to the drains of the first and second output transistors. [Effects of the Invention]

[0008] According to the present invention, by providing first and second suppression transistors whose bases and emitters are open, it is possible to cancel out leakage currents, thereby suppressing and reducing fluctuations in output voltage caused by leakage currents that occur in bipolar transistors at high temperatures, and providing a highly reliable and stable reference voltage source circuit. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing an example of the configuration of a reference voltage source circuit according to an embodiment of the present invention; [Figure 2] 1 is a characteristic diagram showing an example of the change characteristics of the output voltage with respect to the change in the environmental temperature of the reference voltage source circuit according to the embodiment of the present invention, together with a similar characteristic example of a conventional circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, an example of the configuration of a reference voltage source circuit according to an embodiment of the present invention will be described with reference to FIG. This reference voltage source circuit is roughly divided into a bandgap voltage generating circuit 101, first and second negative feedback circuits 102 and 103, and an output circuit 104.

[0011] The bandgap voltage generating circuit 101 is configured with first and second generating transistors 1 and 2 (represented as "Qn1" and "Qn2" in FIG. 1, respectively) that use NPN bipolar transistors as main components. The bases of the first and second generating transistors 1 and 2 are connected to each other, and the connection point is connected to a second negative feedback circuit 103, which will be described later. The collectors of the first and second generating transistors 1 and 2 are connected to the output stages of a first negative feedback circuit 102, which will be described later. On the other hand, the emitter of the first generating transistor 1 is directly connected to ground, and the emitter of the second generating transistor 2 is connected to ground via a first resistor 31 (denoted as "R1" in FIG. 1).

[0012] The first negative feedback circuit 102 is configured as a current mirror using first to third negative feedback transistors 11 to 13 and a first negative feedback fourth transistor 21, as will be described below. First, in the first negative feedback circuit 102 according to the embodiment of the present invention, PMOS (P-channel Metal-Oxide Semiconductor) transistors (hereinafter referred to as "PMOS") are used for the first negative feedback first to third transistors 11 to 13 (represented as "Mp1," "Mp2," and "Mp3," respectively, in FIG. 1). Furthermore, the first negative feedback fourth transistor (denoted as "Mn1" in FIG. 1) 21 is an NMOS (N-channel Metal-Oxide Semiconductor) transistor (hereinafter referred to as "NMOS").

[0013] Specific circuit connections will be explained below. First, the gates of the first and second first negative feedback transistors 11 and 12 are connected to each other and to the drain of the first first negative feedback transistor 11, the gate of the third first negative feedback transistor 13, and the drain of the fourth first negative feedback transistor 21, and the connection point is further connected to the input stage of the output circuit 104, which will be described later. The sources of the first and second negative feedback transistors 11 and 12, as well as the source of the third negative feedback transistor 13, are supplied with the positive power supply voltage VDD.

[0014] The drain of the first negative feedback second transistor 12 is connected to the collector of the first generating transistor 1, as well as to the gate of the first negative feedback fourth transistor 21. The source of the first negative feedback fourth transistor 21 is connected to ground. The drain of the first negative feedback third transistor 13 is connected to the collector of the second generating transistor 2 and to the input stage of a second negative feedback circuit 103, which will be described next.

[0015] Next, the second negative feedback circuit 103 has as its main components the first and second transistors 14 and 15 for second negative feedback and the third transistor 22 for second negative feedback, and is configured as a current mirror as described below. In the second negative feedback circuit 103 according to the embodiment of the present invention, the first and second transistors 14, 15 for second negative feedback (represented as "Mp4" and "Mp5" in FIG. 1, respectively) are PMOS, and the third transistor 22 for second negative feedback (represented as "Mn2" in FIG. 1) is an NMOS.

[0016] Specific circuit connections will be described below. First, the gates of the second negative feedback first and second transistors 14, 15 are connected to each other and to the drain of the second negative feedback first transistor 14, the drain of the second negative feedback third transistor 22, and the input stage of the output circuit 104 (described later). The positive power supply voltage VDD is applied to the sources of both the second negative feedback first and second transistors 14, 15. The gate of the second negative feedback third transistor 22 is connected to the collector of the second generation transistor 2 and the drain of the first negative feedback third transistor 13. On the other hand, the source of the second negative feedback third transistor 22 is connected to ground. In addition, the drain of the second negative feedback transistor 15 is connected to the bases of the first and second generation transistors 1 and 2, and is also connected to ground via a second resistor (denoted as "R2" in Figure 1) 32.

[0017] The output circuit 104 has first and second output transistors 16 and 17 (represented as "Mp6" and "Mp7" respectively in FIG. 1) as its main components, and is configured as described below. First, in the output circuit 104 according to the embodiment of the present invention, PMOS transistors are used for the first and second output transistors 16 and 17. The positive power supply voltage VDD is applied to the source of the first output transistor 16 as well as to the source of the second output transistor 17. The gate of the first output transistor 16 is connected to the gates of the first negative feedback first to third transistors 11 to 13, the drain of the first negative feedback first transistor 11, and the drain of the first negative feedback fourth transistor 21.

[0018] The gate of the second output transistor 17 is connected to the gates of the first and second second negative feedback transistors 14 and 15 and the drains of the first and third second negative feedback transistors 14 and 22 . The drain of the first output transistor 16 and the drain of the second output transistor 17 are connected to each other and to the output terminal 40, and a third resistor (denoted as "R3" in Figure 1) 33 is connected between the output terminal 40 and ground.

[0019] The collector of the first generating transistor 1 is connected to the collector of a first suppressing transistor 3 which is an NPN bipolar transistor, and both the base and emitter of the first suppressing transistor 3 are open. The drain of the first output transistor 16 is connected to the collector of the second suppression transistor 4, which is an NPN bipolar transistor, and both the base and emitter of the second suppression transistor 4 are open. The first and second suppression transistors 3 and 4 cancel out leakage currents that occur on the collector sides of the first and second generation transistors 1 and 2, as will be described later.

[0020] Next, the operation of this configuration will be described. First, in an NPN bipolar transistor, the relationships expressed by the following equations 1 to 3 usually hold between the collector current Ic and the base-emitter voltage VBE, between the collector current Ic and the base current IB, and between the collector current Ic and the emitter current IE.

[0021] Ic=χ×Is×exp(VBE / VT)...Formula 1

[0022] Ic=βIB...Equation 2

[0023] Ic + IB = I Equation 3

[0024] Here, χ is the normalized emitter area ratio, Is is the saturation current, and β is the current amplification factor. Also, VT is the thermal voltage, which is expressed as VT=k×T÷q, where k is Boltzmann's constant, T is absolute temperature, and q is elementary charge.

[0025] When this relational expression is applied to the first and second generating transistors 1 and 2, the respective collector currents IcQn1 and IcQn2 can be obtained as shown in the following expressions 4 and 5.

[0026] IcQn1=Is×exp(VBEQn1p / VT)...Formula 4

[0027] IcQn2=m×Is×exp(VBEQn2 / VT)...Equation 5

[0028] Here, VBEQn1 is the base-emitter voltage of the first generating transistor 1, VBEQn2 is the base-emitter voltage of the second generating transistor 2, m is the normalized emitter area ratio of the second generating transistor 2 and is a real number greater than 1, and the normalized emitter area ratio of the first generating transistor 1 is 1.

[0029] When Equation 4 and Equation 5 are transformed into equations expressing base-emitter voltages VBEQn1 and VBEQn2, respectively, the following Equations 6 and 7 are obtained.

[0030] VBEQn1=VT×ln(IcQn1 / Is)...Equation 6

[0031] VBEQn2=VT×ln(IcQn2 / Is)...Formula 7

[0032] On the other hand, due to the action of the first negative feedback circuit 102, the collector current IcQn1 of the first generating transistor 1 becomes equal to the drain current IDSp2 of the first negative feedback second transistor 12. Similarly, the collector current IcQn2 of the second generating transistor 1 becomes equal to the drain current IDSp3 of the first negative feedback third transistor 13.

[0033] In this case, if the shape ratio (W / L) of the first negative feedback second transistor 12 and the first negative feedback third transistor 13 is set to 1:1 and the voltage difference between the base-emitter voltage VBEQn1 of the first generating transistor 1 and the base-emitter voltage VBEQn2 of the second generating transistor 2 is calculated using the above-mentioned equations 6 and 7, it is obtained as shown in the following equation 8. Here, "W" is the channel width of the MOS transistor, and "L" is the channel length.

[0034] VBEQn1-VBEQn2=VT×lnm...Formula 8

[0035] Since the voltage expressed by this equation 8 is applied to the first resistor 31, the current flowing through the first resistor 31, i.e., the emitter current IEQn2 of the second generating transistor 2, is expressed by the following equation 9.

[0036] IEQn2=(VBEQn1-VBEQn2) / R1=(VT / R1)×lnm...Equation 9

[0037] Here, R1 is the resistance value of the first resistor 31. Next, the base current IBQn1 of the first generating transistor 1, the base current IBQn2 of the second generating transistor 2, and the current IR2 flowing through the second resistor 32 are each supplied by the action of the second negative feedback circuit 103, and if the drain current of the second negative feedback second transistor 15 is IDSp5, the relationships expressed in the following equations 10 and 11 hold.

[0038] IDSp5=IBQn1+IBQn2+IR2...Formula 10

[0039] IBQn1=IBQn2...Formula 11

[0040] Since a voltage VBEQn1 is generated across the second resistor 32, the current IR2 flowing through the second resistor 32 is expressed by the following equation 12.

[0041] IR2=VBEQn1 / R2...Equation 12

[0042] Here, R2 is the resistance value of the second resistor 32. Furthermore, by setting the (W / L) shape ratio of the first negative feedback second and third transistors 12, 13 and the first output transistor 16 to 1:1:1, and by setting the (W / L) shape ratio of the second negative feedback second transistor 15 and the second output transistor 17 to 2:1, the relationship expressed by the following equation 13 is established between the drain current IDSp7 of the second output transistor 17 and the current IR3 flowing through the third resistor 33.

[0043] IR3=IDSp6+IDSp7=IDSp6+IDSp5 / 2...Equation 13

[0044] Here, IDSp6 is the drain current of the first output transistor 16. Thus, the voltage VBG (output voltage) generated across the third resistor 33 is expressed as the following equation 14 using the above equations 3, 9 to 13.

[0045] VBG=R3×IR3=R3(IDSp6+IDSp5 / 2)=R3{IDSp3+(IBQn1+IBQn2+IR2) / 2}=R3{IcQn2+(2×IBQn2+IR2) / 2}=R3{IcQn2+IBQn2+IR2 / 2}=R3{IEQn2+VBEQn1 / (2×R2)}=R3{(VT / R1)×lnm+VBEQn1 / (2×R2)}...Equation 14

[0046] As is generally known, the base-emitter voltage of an NPN bipolar transistor has a negative temperature characteristic, while the thermal voltage has a positive temperature characteristic. Therefore, by adjusting the resistance values ​​of the first to third resistors 31 to 33 and m, which is used as the value of the normalized emitter area ratio, the negative and positive temperature characteristics can be offset, and the voltage VBG shown in Equation 14 can be made a constant voltage that is independent of temperature.

[0047] However, when the circuit is exposed to a high-temperature environment, a leakage current, as shown by the dotted line in Figure 1, occurs between the collectors of the first and second generating transistors 1 and 2, which are NPN bipolar transistors, and ground, and it is known that this current increases exponentially with increasing temperature. This leakage current flows into the third resistor 33 via the current mirror circuit consisting of the first negative feedback second and third transistors 12 and 13 and the first output transistor 16, causing an increase in the voltage VBG, which should be constant.

[0048] In contrast, in the reference voltage source circuit according to the embodiment of the present invention, the normalized emitter area ratio of the first suppression transistor 3 is set to m-1, so that the magnitude of the leakage current of the first generation transistor 1 and the magnitude of the leakage current of the second generation transistor 2 are equal. On the other hand, due to the action of the current mirror formed by the first negative feedback second and third transistors 12 and 13 and the first output transistor 16, the leakage current of the first generating transistor 1 and the leakage current of the second generating transistor 2 are mirrored and tend to flow in the third resistor 33, but the leakage current is cancelled out by the second suppression transistor 4, whose normalized emitter area ratio is set to m as described above, and the voltage VBG is maintained at a constant voltage independent of temperature. It should be noted that m is the same value as the normalized emitter area ratio of the second generation transistor 2 described above.

[0049] FIG. 2 shows the results of a simulation of the change characteristics of the output voltage with respect to temperature changes of the reference voltage source circuit according to the embodiment of the present invention, and this figure will be described below. In FIG. 2, the horizontal axis represents the ambient temperature in the vicinity of the reference voltage source circuit, and the vertical axis represents the output voltage at the output terminal 40. In the same figure, the change characteristic of the output voltage in response to temperature changes in the reference voltage source circuit in the embodiment of the present invention is shown by the solid characteristic line, and it can be seen that there is almost no change in the output voltage regardless of temperature changes, and that the characteristic is almost flat. In contrast, the dotted characteristic line in Figure 2 shows the similar characteristics of the conventional circuit, which shows that in a temperature environment exceeding 100°C, the output voltage increases with the rise in temperature, and the output characteristics deteriorate. [Industrial Applicability]

[0050] The present invention can be applied to a reference voltage source circuit in which it is desired to suppress or reduce fluctuations in output voltage caused by leakage currents that occur in bipolar transistors at high temperatures. [Explanation of symbols]

[0051] 1...First generating transistor 2... Second generating transistor 3...First suppression transistor 4...Second suppression transistor 101...Bandgap voltage generator circuit 102...First negative feedback circuit 103...Second negative feedback circuit 104...Output circuit

Claims

[Claim 1] a bandgap voltage generating circuit is provided, which has first and second generating transistors that are NPN bipolar transistors and is configured to be able to generate a bandgap voltage; the bases of the first and second generating transistors are connected to each other, while the emitter of the first generating transistor is connected to ground and the emitter of the second generating transistor is connected to ground via a first resistor; the collectors of the first and second generating transistors are connected to a first negative feedback circuit, and the collector of the second generating transistor is connected to a second negative feedback circuit; the first negative feedback circuit includes first to third transistors for first negative feedback using P-channel MOSFETs, and a fourth transistor for first negative feedback using an N-channel MOSFET; a positive power supply voltage can be applied to the sources of the first to third first negative feedback transistors, and gates thereof are connected to each other and to the drain of the first first negative feedback transistor, the drain of the first fourth first negative feedback transistor, and an output circuit; the drain of the first second negative feedback transistor is connected to the collector of the first generating transistor, and the drain of the third first negative feedback transistor is connected to the collector of the second generating transistor; the collector of the first generating transistor is connected to the gate of the fourth first negative feedback transistor, and the source of the fourth first negative feedback transistor is connected to ground; the second negative feedback circuit includes first and second transistors for second negative feedback using P-channel MOSFETs, and a third transistor for second negative feedback using an N-channel MOSFET; a positive power supply voltage can be applied to the sources of the second negative feedback first and second transistors, and gates thereof are connected to each other and to the drain of the second negative feedback first transistor, the drain of the second negative feedback third transistor, and the output circuit; a source of the second negative feedback third transistor is connected to ground, and a gate of the second negative feedback third transistor is connected to the collector of the generating second transistor; and a drain of the second negative feedback second transistor is connected to the bases of the first and second generating transistors and to ground via a second resistor; the output circuit includes first and second output transistors using P-channel MOSFETs, and a positive power supply voltage can be applied to the sources of the first and second output transistors, while the gates of the first to third first negative feedback transistors are connected to the gate of the first output transistor, and the gate of the second output transistor is connected to the gates of the first and second second negative feedback transistors, and the drains of the first output transistor and the second output transistor are connected to each other and to ground via a third resistor; a collector of a first suppression transistor, which is an NPN bipolar transistor, is connected to a collector of the first generation transistor, and a base and an emitter of the first suppression transistor are in an open state; the drains of the first and second output transistors are connected to the collector of a second suppression transistor which is an NPN bipolar transistor, and the base and emitter of the second suppression transistor are open; 1. A reference voltage source circuit comprising: a first output transistor and a second output transistor; a first output transistor and a second output transistor;

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