Display device and manufacturing method thereof

Abstract

To provide a display device capable of preventing or reducing lateral moisture penetration due to the presence of a light-emitting stack.SOLUTION: An embodiment disclosed herein relates to a display device, more specifically a display device comprising: a substrate having a non-display area with a through-hole and a display area adjacent to the non-display area; an insulating layer disposed on the substrate; a light-emitting stack disposed on the insulating layer; a second electrode disposed on the light-emitting stack, the second electrode extending from the display area to the non-display area; and an electrode patterning material layer arranged to be in contact with one end of the second electrode and disposed on the light-emitting stack. One end of the light-emitting stack and one end of the electrode patterning material layer coincide.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] SUMMARY An embodiment of the present disclosure relates to a display device and a manufacturing method thereof. [Background technology]

[0002] With the development of technology, the applications of display devices have become more diverse, and the range of applications has expanded as display devices have become thinner and lighter.

[0003] The area of ​​a display device that is occupied by a display region for displaying an image is expanding, and various functions that are linked to or incorporated into the display device are being added.

[0004] Bezel-less or bezel-free designs, in which the display area appears filled, are gradually becoming more common, and there is a demand for research into display devices that have areas inside the display area that can be used to add various functions rather than just displaying images.

[0005] Accordingly, a display device called a Hole-in Display (HID) or Hole-in Active Area (HiAA) has been proposed, in which at least a part of the substrate is removed from the display area of ​​the display panel.

[0006] However, there are problems such as cracks occurring during the process of removing a portion of the substrate, or moisture or the like penetrating into the area where the substrate has been removed, resulting in a deterioration in display quality, and solutions to these problems are being sought. Summary of the Invention [Problem to be solved by the invention]

[0007] The problem is that moisture or the like penetrates into the area where the substrate is removed in the display area, deteriorating the display quality. To address this problem, the inventors of this specification have invented a display device that prevents or reduces side moisture penetration through the light-emitting stack.

[0008] The embodiments of the present disclosure can provide a display device and a manufacturing method thereof that can block lateral moisture permeation paths through the light emitting stack by patterning the light emitting stack.

[0009] The embodiments of the present disclosure may provide a display device and a manufacturing method thereof that can prevent or reduce lateral moisture permeation paths and microcracks caused by the light emitting stack by patterning the light emitting stack and arranging a dam structure.

[0010] The embodiments of the present disclosure can provide a display device capable of reducing power consumption by preventing or reducing side moisture permeation and improving the lifespan, and a method for manufacturing the same. [Means for solving the problem]

[0011] An embodiment of the present disclosure may provide a display device including a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a light-emitting stack disposed on the insulating layer, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, and an electrode patterning material layer disposed on the light-emitting stack in contact with one end of the second electrode, wherein one end of the light-emitting stack and one end of the electrode patterning material layer are aligned.

[0012] An embodiment of the present disclosure may provide a display device including a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a plurality of dams located between the display area and the through hole and disposed on the insulating layer, a light-emitting stack disposed on the insulating layer and the plurality of dams, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, an electrode patterning material layer contacting one end of the second electrode and disposed on the light-emitting stack, and a groove in which the light-emitting stack and the electrode patterning material layer are each interrupted.

[0013] An embodiment of the present disclosure may provide a method for manufacturing a display device, including the steps of forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack to cover the sacrificial layer and the dam, forming an electrode patterning material layer located in the non-display area on the light-emitting stack, forming a second electrode on the light-emitting stack in contact with the electrode patterning material layer, forming a capping layer on the second electrode and the electrode patterning material layer, and irradiating laser light on the sacrificial layer to form a groove. [Effects of the Invention]

[0014] According to the embodiments of the present disclosure, it is possible to provide a display device and a manufacturing method thereof that can block lateral moisture permeation paths through the light emitting stack by patterning the light emitting stack.

[0015] According to an embodiment of the present disclosure, a display device and a manufacturing method thereof can be provided that can prevent or reduce side moisture permeation paths and microcracks caused by the light emitting stack by patterning the light emitting stack and arranging a dam structure.

[0016] According to the embodiments of the present disclosure, it is possible to provide a display device that can consume less power by preventing or reducing side moisture permeation and improving the lifespan, and a method for manufacturing the same. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] 1 is an equivalent circuit of a subpixel in a display panel according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a plan view illustrating a structure of an optical region of a display panel according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is an example of a cross-sectional view taken along line II' in FIG. 3; [Figure 5] 4 is an example of a cross-sectional view taken along line II-II' in FIG. 3. [Figure 6]2 is another cross-sectional view taken along line II-II' of FIG. 3; [Figure 7] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 8] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 9] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 10] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 11] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 12a] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. [Figure 12b] 1A-1C illustrate a process for forming an optical region of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] Some embodiments of the present disclosure will be described in detail below with reference to the illustrative drawings. When adding reference numerals to components in each drawing, the same reference numerals may be used to the same components as long as they appear in different drawings. When describing the present disclosure, if a detailed description of related publicly known structures or functions is deemed to obscure the gist of the present disclosure, such a detailed description may be omitted. When terms such as "include," "have," and "perform" are used in this specification, other parts may be added unless "only" is used. When a component is expressed as a singular element, the plural may also be included unless otherwise explicitly stated.

[0019] Furthermore, when describing components of the present disclosure, terms such as first, second, A, B, (a), B, etc. are used to distinguish the components from other components, and the terms do not limit the essence, order, procedure, number, etc. of the components.

[0020] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" through an "intervening" component. Here, the other component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0021] In describing the temporal sequence of elements, methods of operation, methods of production, etc., when the temporal or chronological sequence is described using, for example, "after," "following," "after," or "before," non-consecutive sequences may also be included, unless "immediately" or "directly" is used.

[0022] On the other hand, when referring to a numerical value or its corresponding information (e.g., level, etc.) for a component, even if there is no explicit statement otherwise, the numerical value or its corresponding information can be interpreted as including an error range that may arise due to various factors (e.g., process factors, internal or external impact, noise, etc.).

[0023] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0024] 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure. All components of the display device according to an embodiment of the present disclosure are operatively coupled and configured.

[0025] Referring to FIG. 1, a display device 100 is a component for displaying an image and may include a display panel 110 and a display driving circuit.

[0026] The display driving circuit is a circuit for driving the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, a display controller 140, and the like.

[0027] The display panel 110 may include a display area AA where an image is displayed and a non-display area NA where an image is not displayed. The non-display area NA may be an outer periphery of the display area AA and may also be called a bezel area. The entire or a part of the non-display area NA may be visible from the front surface of the display device 100, or may be curved so that it is not visible from the front surface of the display device 100.

[0028] The display panel 110 may include a substrate SUB and a number of sub-pixels SP disposed on the substrate SUB, and may further include several types of signal lines to drive the number of sub-pixels SP.

[0029] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device or an emissive display device in which the display panel 110 emits light by itself. When the display device 100 according to the embodiment of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element. However, the embodiment of the present disclosure is not limited thereto.

[0030] For example, the display device 100 according to the embodiment of the present disclosure may be an organic light emitting display device in which light emitting elements are configured with organic light emitting diodes (OLEDs). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light emitting display device in which light emitting elements are configured with inorganic-based light emitting diodes. As yet another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which light emitting elements are configured with quantum dots, which are semiconductor crystals that emit light themselves.

[0031] The structures of the subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emitting display device in which the subpixels SP emit light themselves, each subpixel SP may include a self-emitting light-emitting element, one or more transistors, and one or more capacitors. However, the embodiments of the present disclosure are not limited thereto.

[0032] For example, some types of signal lines may include a number of data lines DL that transmit data signals (also called data voltages or video signals) and a number of gate lines GL that transmit gate signals (also called scan signals).

[0033] The data lines DL and the gate lines GL may cross each other. Each of the data lines DL may extend in a first direction. Each of the gate lines GL may extend in a second direction.

[0034] Here, the first direction may be the column direction and the second direction may be the row direction, or the first direction may be the row direction and the second direction may be the column direction.

[0035] The data driving circuit 120 is a circuit configured to drive a number of data lines DL and can output data signals to the number of data lines DL. The gate driving circuit 130 is a circuit configured to drive a number of gate lines GL and can output gate signals to the number of gate lines GL.

[0036] The display controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130. The display controller 140 can control the driving timing for a number of data lines DL and the driving timing for a number of gate lines GL.

[0037] The display controller 140 can provide data drive control signals DCS to the data drive circuit 120 to control the data drive circuit 120. The display controller 140 can provide gate drive circuit control signals GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0038] The display controller 140 can receive input video data from the host system 150 and provide video data (Data) to the data driving circuit 120 based on the input video data.

[0039] The data driving circuit 120 can supply data signals to a large number of data lines DL under the drive timing control of the display controller 140 .

[0040] The data driving circuit 120 receives digital image data Data from the display controller 140, converts the received image data Data into analog data signals, and outputs the analog data signals to a number of data lines DL.

[0041] The gate driving circuit 130 can supply gate signals to a large number of gate lines GL under timing control of the display controller 140. The gate driving circuit 130 is supplied with a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage along with various gate driving circuit control signals GCS, and can generate gate signals and supply the generated gate signals to a large number of gate lines GL.

[0042] For example, the data driving circuit 120 may be connected to the display panel 110 using a tape automated bonding (TAB) method, connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or configured using a chip on film (COF) method to be connected to the display panel 110. However, the embodiments of the present disclosure are not limited thereto.

[0043] The gate driving circuit 130 may be connected to the display panel 110 using a tape automated bonding (TAB) method, a chip-on-glass (COG) or chip-on-panel (COP) method, or a chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be formed in the non-display area NA of the display panel 110 in a gate-in-panel (GIP) type. The gate driving circuit 130 may be disposed on or connected to the substrate SUB. For example, in the case of a gate-in-panel (GIP) type, the gate driving circuit 130 may be disposed in the non-display area NA of the substrate SUB. In the case of a chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate driving circuit 130 may be connected to the substrate.

[0044] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area AA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed so as not to overlap the sub-pixels SP, or may be disposed so as to overlap the sub-pixels SP partially or completely. However, the embodiments of the present disclosure are not limited thereto.

[0045] The data driving circuit 120 may be connected to one side (e.g., the top or bottom) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the top and bottom) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0046] The gate driving circuit 130 may be connected to one side (e.g., the left or right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., the left and right sides) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0047] The display controller 140 may be configured as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 into an integrated circuit.

[0048] The display controller 140 may be a timing controller used in common display technology, a control device that includes a timing controller and performs other control functions, a control device different from the timing controller, or a circuit within the control device. The display controller 140 may be configured with various circuits and electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0049] The display controller 140 may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 via a printed circuit board (PCB), a flexible printed circuit board (FPCB), etc. However, the embodiments of the present disclosure are not limited thereto.

[0050] The display controller 140 can transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces, for example, the interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a Serial Peripheral Interface (SPI), etc.

[0051] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include one or more optical areas (OA) in which at least a portion of a substrate SUB is removed.

[0052] One or more components (not shown) for providing various functions may be disposed in an area that at least partially overlaps with the optical area OA. The one or more components may be, for example, an optical / electronic device, clock hands, etc. However, embodiments of the present disclosure are not limited thereto.

[0053] The optical electronic device may include, for example, one or more of a photographing device such as a camera (image sensor), a sensing sensor such as a proximity sensor and an illuminance sensor, etc. However, the embodiments of the present disclosure are not limited thereto.

[0054] For example, a photographing device such as a camera may be located under the first optical area OA1, and a sensing sensor may be located under the second optical area OA2, but the embodiments of the present disclosure are not limited thereto.

[0055] The component may be located below the substrate SUB, and the component may be located at least partially overlapping with the optical area OA.

[0056] The first optical area OA1 and the second optical area OA2 may have various shapes, such as a circle, an ellipse, a rectangle, a hexagon, or an octagon. The shapes of the first optical area OA1 and the second optical area OA2 may be the same or different. The area of ​​the first optical area OA1 may be the same as or different from the area of ​​the second optical area OA2.

[0057] In the following description, for convenience of explanation, it is assumed that the first optical area OA1 and the second optical area OA2 are circular and have the same area, but the present invention is not limited to this.

[0058] On the other hand, one or more optical areas OA are located in an area where the substrate SUB has been removed, and such optical areas OA may be non-display areas NA where sub-pixels SP are not arranged.

[0059] The optical area OA located within the display area AA is also called a "HID (Hole in Display)" or "HiAA (Hole in Active Area)" area.

[0060] Signal lines (for example, data lines DL, gate lines GL, etc.) arranged on the substrate SUB can be arranged around (or detouring around) the periphery of the optical area OA.

[0061] The display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, and detects the touch position, in order to provide not only an image display function but also a touch sensing function.

[0062] The touch sensing circuit may include a touch driving circuit 160 that drives and senses a touch sensor to generate and output touch sensing data, and a touch controller 170 that can sense the occurrence of a touch and detect the touch position using the touch sensing data.

[0063] The touch sensor may include multiple touch electrodes, and may further include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driving circuit 160.

[0064] The touch sensor may be provided outside the display panel 110 in the form of a touch panel, or may be provided inside the display panel 110 .

[0065] When the touch sensor is in the form of a panel and is located outside the display panel 110, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be manufactured separately and combined during the assembly process. The external type touch panel may include a touch panel substrate and a number of touch electrodes on the touch panel substrate.

[0066] If the touch sensor is present inside the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0067] The touch drive circuit 160 may provide a touch drive signal to at least one of the plurality of touch electrodes, and sense the at least one of the plurality of touch electrodes to generate touch sensing data.

[0068] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0069] When the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0070] According to the self-capacitance sensing method, each of the plurality of touch electrodes can function as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 160 can drive all or a portion of the plurality of touch electrodes and sense all or a portion of the plurality of touch electrodes.

[0071] When the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0072] According to the mutual capacitance sensing method, the touch electrodes are divided into driving touch electrodes and sensing touch electrodes, and the touch driving circuit 160 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0073] The touch driving circuit 160 and the touch controller 170 included in the touch sensing circuit may be configured as separate devices or as a single device, and the touch driving circuit 160 and the data driving circuit 120 may be configured as separate devices or as a single device.

[0074] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0075] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display device of various types and sizes capable of displaying information or images.

[0076] 2 is an equivalent circuit diagram of a subpixel SP in a display panel 110 according to an embodiment of the present disclosure. In the following description, content that is the same as or similar to the content described with reference to FIG. 1 will be omitted or briefly described.

[0077] Referring to FIG. 2, each of the sub-pixels SP arranged in the display area AA of the display panel 110 may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scan transistor SCT for transmitting a data voltage Vdata to a first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0078] The driving transistor DRT may include a first node N1 to which a data voltage Vdata is applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which a high potential common voltage ELVDD is applied from a driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be either a source node or a drain node, and the third node N3 may be the other of the source node or the drain node.

[0079] The light emitting element ED may include an anode electrode AE ​​as a first electrode, an emitting layer EL, and a cathode electrode CE as a second electrode. The anode electrode AE ​​may be a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP. The cathode electrode CE may be a common electrode disposed in common to a plurality of sub-pixels SP and may be applied with a low potential common voltage ELVSS.

[0080] For example, the anode electrode AE ​​may be a pixel electrode, and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE ​​may be a common electrode, and the cathode electrode CE may be a pixel electrode. Hereinafter, for convenience of explanation, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode. However, embodiments of the present disclosure are not limited thereto.

[0081] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode, or a quantum dot light emitting element, etc. In this case, when the light emitting element ED is an organic light emitting diode, the light emitting layer EL in the light emitting element ED may include an organic light emitting layer containing an organic material.

[0082] The scan transistor SCT is turned on and off by a scan signal SCAN, which is a gate signal applied via a gate line GL, and can switch the electrical connection between the first node N1 of the drive transistor DRT and the data line DL.

[0083] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0084] Each subpixel SP may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DRT, SCT and one capacitor Cst, as shown in FIG. 2, and may further include one or more transistors or one or more capacitors in some cases.

[0085] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DRT, rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node N1 and the second node N2 of the drive transistor DRT.

[0086] Each of the drive transistor DRT and the scan transistor SCT may be an n-type transistor or a p-type transistor.

[0087] Since the circuit elements (particularly, the light-emitting elements ED) in each subpixel SP are vulnerable to external moisture and oxygen, an encapsulation layer ENCAP for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light-emitting elements ED) may be disposed on the display panel 110. The encapsulation layer ENCAP may be disposed in a form that covers the light-emitting elements ED.

[0088] 3 is a plan view showing the structure of an optical area OA of a display panel 110 according to an embodiment of the present disclosure. In the following description, content that is the same as or similar to the content described with reference to FIGS. 1 and 2 will be omitted or will be briefly described.

[0089] 3, an optical area OA is disposed within the display area AA. Pixels SP may be disposed around the optical area OA. The optical area OA may be either the first optical area OA1 or the second optical area OA2 described above. However, the embodiments of the present disclosure are not limited thereto.

[0090] 3, the optical area OA may include a through-hole TH and a bezel area surrounding the through-hole TH. Such a bezel area located between the through-hole TH and the display area AA is also called a "HiAA bezel area HBA."

[0091] The HiAA bezel area HBA is an area surrounding the outer periphery of the through hole TH. The HiAA bezel area HBA can prevent damage to the wiring when irradiating the laser to form the through hole TH. The HiAA bezel area HBA has a minimum width, which can be kept constant.

[0092] The HiAA bezel area HBA may be provided with a dam area 200 having a dam structure for preventing moisture penetration from the outside through the trimming line and preventing microcracks. At least one dam may be provided in the dam area 200. Subpixels for displaying images may not be provided in the optical area OA. That is, the optical area OA including the HiAA bezel area HBA may be a non-display area NA where no images are displayed.

[0093] The through holes TH may be formed by removing the substrate along a trimming line. The through holes TH may have a circular shape as shown in FIG. 3, but may also have various other shapes such as an oval, a square, a hexagon, or an octagon. However, the embodiments of the present disclosure are not limited thereto.

[0094] The dam region 200 may include at least one dam. For example, the dam region 200 may include a first dam 230, a second dam 220, and a third dam 210 arranged between the display region AA and the through-hole TH in order of proximity to the display region AA.

[0095] The shapes of the dams 210, 220, and 230 correspond to the shapes of the through-holes TH and have a closed curve shape surrounding the through-holes TH. The dams 210, 220, and 230 and the through-holes TH may have different closed curve shapes or may have the same closed curve shape but different sizes. For example, the dams 210, 220, and 230 and the through-holes TH may have concentric circles or may be continuously overlapping and spaced apart. However, the embodiments of the present disclosure are not limited thereto.

[0096] Meanwhile, the subpixels SP arranged in the display area AA may include a light-emitting element. A light-emitting stack (not shown) including a light-emitting layer may be located in the display area AA. When the light-emitting element is an organic light-emitting element, the light-emitting stack may be an organic light-emitting stack including an organic material. However, the embodiments of the present disclosure are not limited thereto.

[0097] The organic light-emitting stack may be disposed over at least a portion of the optical area OA.

[0098] On the other hand, if moisture penetrates into the organic light-emitting stack, defects such as darkening of subpixels may occur. From various viewpoints, moisture may penetrate into the region where the through-hole TH is located.

[0099] An inorganic sealing layer may be located on the dam region 200. Moisture can penetrate through the inorganic sealing layer, but the dam region 200 has the effect of lengthening the path along which moisture penetrates in the inorganic sealing layer. As a result, the dam region 200 can prevent moisture that has entered through the through-holes TH from reaching the light-emitting layer located in the display region AA.

[0100] Fig. 4 is an example of a cross-sectional view taken along line II' in Fig. 3. For example, Fig. 4 is an example view showing a cross-sectional structure of the subpixel SP in Fig. 3. In the following description, content that is the same as or similar to the content described with reference to Figs. 1 to 3 will be omitted or will be briefly described.

[0101] 4, a display device 100 according to an embodiment of the present disclosure may include a substrate 301. The substrate 301 may be a glass substrate or a plastic substrate. The plastic substrate may be made of, for example, polyimide (PI), polymethyl methacrylate (PMMA), polyethylene (PE), or the like, and may have flexible properties. However, the embodiment of the present disclosure is not limited thereto.

[0102] A plurality of insulating layers may be provided on the substrate 301. A buffer layer 302 may be provided on the substrate 301. The buffer layer 302 may include a multi-buffer layer 302a and a lower buffer layer 302b. A first transistor 320 may be disposed on the lower buffer layer 302b. A first semiconductor layer 323 constituting the first transistor 320, a first gate electrode 322, and a lower gate insulating layer 304 for insulation may be disposed on the first semiconductor layer 323. A lower interlayer insulating layer 305 may be disposed on the first gate electrode 322. The lower interlayer insulating layer 305 may include a first lower interlayer insulating layer 305a and a second lower interlayer insulating layer 305b disposed in sequence. An upper buffer layer 307 may be disposed on the lower interlayer insulating layer 305. However, the embodiments of the present disclosure are not limited thereto.

[0103] The multi-buffer layer 302a can retard the diffusion of moisture or oxygen that has penetrated into the substrate 301, and may be formed by alternately stacking at least one layer of silicon nitride (SiNx) and silicon oxide (SiOx), although the embodiments of the present disclosure are not limited thereto.

[0104] The lower buffer layer 302b may protect the first semiconductor layer 323 and block various types of defects from entering from the substrate. The lower buffer layer 302b may be formed of amorphous silicon (a-Si), silicon nitride (SiNx), silicon oxide (SiOx), or the like. However, the embodiments of the present disclosure are not limited thereto.

[0105] The first semiconductor layer 323 of the first thin film transistor 320 may be a polycrystalline semiconductor layer, but embodiments of the present disclosure are not limited thereto. The first semiconductor layer 323 may include a channel region, a source region, and a drain region.

[0106] A polycrystalline semiconductor layer has higher mobility, lower energy consumption, and superior reliability than an amorphous semiconductor layer and an oxide semiconductor layer. Due to these advantages, a polycrystalline semiconductor layer can be used for the driving transistor. However, the embodiments of the present disclosure are not limited thereto.

[0107] The first gate electrode 322 may be disposed on the lower gate insulating film 304 and may be disposed so as to overlap the first semiconductor layer 323 .

[0108] A second transistor 330 may be disposed on the upper buffer layer 307 , and a light-shielding layer 336 may be disposed below the region corresponding to the second transistor 330 .

[0109] 4, a light-shielding layer 336 may be disposed on the first lower interlayer insulating film 305a in a region corresponding to the second transistor 330, and a second semiconductor layer 333 of the second transistor 330 may be disposed on the second lower interlayer insulating film 305a and the upper buffer layer 307 so as to overlap the light-shielding layer 336. An upper gate insulating film 337 for insulating the second gate electrode 332 from the second semiconductor layer 333 may be disposed on the second semiconductor layer 333, and then an upper interlayer insulating film 308 may be disposed on the second gate electrode 332. The first gate electrode 322 and the second gate electrode 332 may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but are not limited thereto.

[0110] The first and second lower interlayer insulating films 305a and 305b may be formed of an inorganic film having a higher content of hydrogen particles than the upper interlayer insulating film 308. For example, the first and second lower interlayer insulating films 305a and 305b may be made of silicon nitride (SiNx) formed by a deposition process using NH3 gas, and the upper interlayer insulating film 308 may be made of silicon oxide (SiOx). However, the embodiments of the present disclosure are not limited thereto. The hydrogen particles contained in the first and second lower interlayer insulating films 305a and 305b diffuse into the polycrystalline semiconductor layer during the hydrogenation process, filling voids in the polycrystalline semiconductor layer with hydrogen. This stabilizes the polycrystalline semiconductor layer and prevents degradation of the characteristics of the first transistor 320.

[0111] After the activation and hydrogenation processes of the first semiconductor layer 323 of the first transistor 320, the second semiconductor layer 333 of the second transistor 330 may be formed, and in this case, the second semiconductor layer 333 may be formed of an oxide semiconductor. Since the second semiconductor layer 333 is not exposed to the high-temperature atmosphere of the activation and hydrogenation processes of the first semiconductor layer 323, damage to the second semiconductor layer 333 may be prevented, and reliability may be improved.

[0112] After the upper interlayer insulating film 308 is disposed, a first source contact hole 325S and a first drain contact hole 325D may be formed to correspond to the source and drain regions of the first transistor, and a second source contact hole 335S and a second drain contact hole 335D may be formed to correspond to the source and drain regions of the second transistor 330, respectively.

[0113] 4, the first source contact hole 325S and the first drain contact hole 325D may be formed continuously from the upper interlayer insulating film 308 to the lower gate insulating film 304, and a second source contact hole 335S and a second drain contact hole 335D may also be formed in the second transistor 330. The first source electrode 321 and the first drain electrode 324 corresponding to the first transistor 320 and the second source electrode 331 and the second drain electrode 334 corresponding to the second transistor 330 may be formed simultaneously, thereby reducing the number of processes for forming the source and drain electrodes of the first transistor 320 and the second transistor 330.

[0114] The first source and drain electrodes 321, 324 and the second source and drain electrodes 331, 334 may be a single layer or multiple layers made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, although embodiments of the present disclosure are not limited thereto.

[0115] The first source and drain electrodes 321, 324 and the second source and drain electrodes 331, 334 may have a triple-layer structure. The first source electrode 321 may be composed of a first electrode layer 321a, a second electrode layer 321b, and a third electrode layer 321c, in that order.

[0116] The first electrode layer 321a, the second electrode layer 321b, and the third electrode layer 321c may include materials with relatively different etching rates. The second electrode layer 321b may include a material with a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c may include a material with a relatively slow etching rate. For example, the second electrode layer 321b may include aluminum (Al), which has a relatively fast etching rate, and the first electrode layer 321a and the third electrode layer 321c may include titanium (Ti), which has a relatively slow etching rate. The first source electrode 321 may have a triple-layer structure of Ti / Al / Ti. However, embodiments of the present disclosure are not limited thereto.

[0117] The other source and drain electrodes may have the same structure as the first source electrode 321 .

[0118] A storage capacitor 340 may be disposed between the first transistor 320 and the second transistor 330. The storage capacitor 340 may be formed by overlapping a storage lower electrode 341 and a storage upper electrode 342 with a first lower interlayer insulating film 305a interposed therebetween, as shown in FIG.

[0119] The lower storage electrode 341 is located on the lower gate insulating film 304 and may be formed in the same layer and made of the same material as the first gate electrode 322. The upper storage electrode 342 may be electrically connected to the pixel circuit via a storage supply line 343. The upper storage electrode 342 may be formed in the same layer and made of the same material as the light-shielding layer 336. The upper storage electrode 342 is exposed through a storage contact hole 344 that penetrates the second lower interlayer insulating film 305b, the upper buffer layer 307, the upper gate insulating layer 337, and the upper interlayer insulating film 308, and is connected to the storage supply line 343. Meanwhile, the upper storage electrode 342 is separated from the light-shielding layer 336 as shown in FIG. 4, but may also be formed as an integrated structure in which they are connected to each other. The storage supply line 343 can be formed on the same plane as the first source and drain electrodes 321, 324 through the second source and drain electrodes 331, 334 and from the same material. Therefore, the storage supply line 343 can be formed simultaneously with the first source and drain electrodes 321, 324 through the second source and drain electrodes 331, 334 using the same mask process.

[0120] A passivation layer 309 may be formed by depositing an inorganic insulating material such as SiNx or SiOx on the entire surface of the substrate 301 on which the first source and drain electrodes 321 and 324, the second source and drain electrodes 331 and 334, and the storage supply line 343 are formed. A first planarization layer 310 may be formed on the substrate 301 on which the passivation layer 309 is formed. Specifically, the first planarization layer 310 may be disposed by coating an organic insulating material such as an acrylic resin on the entire surface of the substrate 301 on which the passivation layer 309 is formed.

[0121] A protective layer 309 and a first planarization layer 310 may be disposed, and a contact hole exposing the first source electrode 321 or the first drain electrode 324 of the first transistor 320 may be formed through a photolithography process. A connection electrode 345 may be disposed in the contact hole region exposing the first drain electrode 324. However, the embodiments of the present disclosure are not limited thereto.

[0122] The connecting electrode 345 may be a single layer or multiple layers made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, although embodiments of the present disclosure are not limited thereto.

[0123] The connection electrode 345 may have a triple-layer structure, which may be composed of a first connection electrode layer 345a, a second connection electrode layer 345b, and a third connection electrode layer 345c, in that order.

[0124] The first connection electrode layer 345a, the second connection electrode layer 345b, and the third connection electrode layer 345c may include materials with relatively different etching rates. The second connection electrode layer 345b may include a material with a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c may include a material with a relatively slow etching rate. For example, the second connection electrode layer 345b may include aluminum (Al), which has a relatively fast etching rate, and the first connection electrode layer 345a and the third connection electrode layer 345c may include titanium (Ti), which has a relatively slow etching rate. The connection electrode 345 may have a triple-layer structure of Ti / Al / Ti. However, embodiments of the present disclosure are not limited thereto.

[0125] A second planarization layer 311 may be disposed on the connection electrode 345, and a contact hole exposing the connection electrode 345 may be formed in the second planarization layer 311, so that a light emitting element 350 connected to the first transistor 320 may be disposed therein.

[0126] The light-emitting element 350 may include a first electrode 351 connected to the first drain electrode 324 of the first transistor 320, at least one light-emitting stack 352 formed on the first electrode 351, and a second electrode 353 formed on the light-emitting stack 352.

[0127] The light-emitting stack 352 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. However, embodiments of the present disclosure are not limited thereto. In a tandem structure in which multiple light-emitting layers are stacked, a charge generation layer may be further disposed between the light-emitting layers. The light-emitting layer may emit different colors for each subpixel. For example, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer may be formed separately for each subpixel. However, a common light-emitting layer may be formed for each pixel to emit white light without color differentiation, and a color filter for color differentiation may be provided separately. This type of differentiation can be classified into an RGB type (real RGB type) and a WOLED (white OLED). While the light-emitting layers can be formed individually, the injection layer or transport layer may be provided as a common layer and may be disposed in the same manner for each subpixel.

[0128] The first electrode 351 can be connected to the exposed connection electrode 345 through a contact hole penetrating the second planarization layer 311. The first electrode 351 can be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed as a single layer or a multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. For example, the first electrode 351 can be formed as a structure in which a transparent conductive film, an opaque conductive film, and another transparent conductive film are sequentially stacked, or as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked. The first electrode 351 may be disposed on the second planarization layer 311 so as to overlap not only the light-emitting region defined by the bank 354 but also the pixel circuit region in which the first and second transistors 320 and 330 and the storage capacitor 340 are disposed, thereby increasing the light-emitting area. The first electrode 351 may be an anode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0129] The light-emitting stack 352 may be formed by stacking a hole transport layer, an organic light-emitting layer, and an electron transport layer on the first electrode 351 in this order, or in the reverse order. Alternatively, the light-emitting stack 352 may further include a charge generation layer and first and second light-emitting stacks facing each other. However, the embodiments of the present disclosure are not limited thereto.

[0130] The bank 354 may be formed to expose the first electrode 351. The bank 354 may be formed of an organic material such as photoacrylic and may be a translucent material, but the embodiment of the present disclosure is not limited thereto. The bank 354 may also be formed of an opaque material to prevent light interference between subpixels. A spacer (not shown) may be formed on the bank 354. The spacer (not shown) may include an organic insulator. The spacer (not shown) may include the same material as the bank 354. The bank 354 and the spacer (not shown) may be formed together in a mask process using a halftone mask or the like. In another example, the spacer (not shown) may include a different material from the bank 354.

[0131] The second electrode 353 may be formed on an upper surface of the light emitting stack 352 to face the first electrode 351 across the light emitting stack 352. When the second electrode 353 is applied to a top-emitting organic light emitting display device, the second electrode 353 may be formed as a transparent conductive film by forming a thin film of indium tin oxide (ITO), indium zinc oxide (IZO), or magnesium-silver (Mg-Ag). However, the embodiments of the present disclosure are not limited thereto.

[0132] A capping layer 355 may be disposed on the second electrode 353 .

[0133] The capping layer 355 may protect the light emitting element 350 and help the light generated in the light emitting stack 352 to be efficiently emitted to the outside. For example, the capping layer 355 may be made of an inorganic or organic material to prevent the light emitted from the light emitting stack 352 from being lost due to total internal reflection. The capping layer 355 may be made of an organic or inorganic material to prevent the inflow of moisture, oxygen, and the like.

[0134] The capping layer 355 may include a single layer or multiple layers. For example, the capping layer 355 may be formed as a single layer of an organic capping layer containing an organic material or an inorganic capping layer containing an inorganic material, or may be formed as multiple layers by alternately depositing an organic capping layer and an inorganic capping layer. When the capping layer 355 is formed as multiple layers, the organic capping layer and the inorganic capping layer may be sequentially formed on the second electrode 353. However, the embodiments of the present disclosure are not limited thereto.

[0135] The organic capping layer may include any one of the materials constituting the light-emitting stack 352. For example, the organic capping layer may be formed using a material selected from the host material of the light-emitting layer, the materials constituting the hole transport layer, or the electron transport layer, or may be formed using a separate organic material.

[0136] The inorganic capping layer can be formed using materials such as LiF, LiO, MgF, NaF, CaO, KF, BiS, NaAlF, and SiO to enhance light transmittance from the light-emitting stack 352. However, embodiments of the present disclosure are not limited thereto.

[0137] An encapsulation layer 360 for protecting the light emitting element 350 may be formed on the capping layer 355. The light emitting element 350 may react with external moisture or oxygen due to the organic properties of the light emitting stack 352, which may cause dark spots or pixel shrinkage. To prevent this, the encapsulation layer 360 may be disposed on the capping layer 355.

[0138] The sealing layer 360 may have a single-layer structure or a multi-layer structure. For example, as shown in FIG. 4, the sealing layer 360 may include a first sealing layer 361, a second sealing layer 362, and a third sealing layer 363. However, the embodiments of the present disclosure are not limited thereto.

[0139] The encapsulation layer 360 may include an inorganic film containing an inorganic insulating material, an organic film containing an organic material, or both an inorganic film and an organic film.

[0140] For example, the first encapsulation layer 361 and the third encapsulation layer 363 may be inorganic films, and the second encapsulation layer 362 may be an organic film. Among the first encapsulation layer 361, the second encapsulation layer 362, and the third encapsulation layer 363, the second encapsulation layer 362 may be the thickest. Accordingly, the second encapsulation layer 362 may serve as a planarization layer. The first encapsulation layer 361 may also be a first inorganic encapsulation layer, the second encapsulation layer 362 may also be an organic encapsulation layer, and the third encapsulation layer 363 may also be a second inorganic encapsulation layer. However, the embodiments of the present disclosure are not limited thereto.

[0141] The first encapsulation layer 361 may be disposed on the capping layer 355 and may be disposed closest to the light emitting element 350. The first encapsulation layer 361 may be formed of an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulation layer 361 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, embodiments of the present disclosure are not limited thereto. Because the first encapsulation layer 361 is deposited in a low-temperature atmosphere, the first encapsulation layer 361 may prevent damage to the light emitting stack 352, which includes organic materials that are vulnerable to high-temperature atmospheres, during the deposition process.

[0142] The second encapsulation layer 362 may be formed with an area smaller than that of the first encapsulation layer 361. In this case, the second encapsulation layer 362 may be formed to expose both ends of the first encapsulation layer 361. The second encapsulation layer 362 may serve as a buffer to relieve stress between layers due to warping of the display device 100 and to enhance planarization performance. The second encapsulation layer 362 may also serve as a foreign matter compensation layer. For example, the second encapsulation layer 362 may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). However, the embodiments of the present disclosure are not limited thereto. For example, the second encapsulation layer 362 may be formed by an inkjet method.

[0143] The third encapsulation layer 363 may be formed on the substrate 301 on which the second encapsulation layer 362 is formed, to cover the top and side surfaces of the second encapsulation layer 362 and the first encapsulation layer 361. The third encapsulation layer 363 may minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 361 and the second encapsulation layer 362. For example, the third encapsulation layer 363 may be formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, embodiments of the present disclosure are not limited thereto.

[0144] The materials of the first encapsulation layer 361 and the third encapsulation layer 363 may be different from each other. The thicknesses of the first encapsulation layer 361 and the third encapsulation layer 363 may be different from each other. The thickness of the first encapsulation layer 361 may be greater than the thickness of the third encapsulation layer 363. Alternatively, the thickness of the third encapsulation layer 363 may be greater than the thickness of the first encapsulation layer 361, or the thicknesses of the first encapsulation layer 361 and the third encapsulation layer 363 may be the same.

[0145] Fig. 5 is an example of a cross-sectional view taken along line II-II' in Fig. 3. For example, Fig. 5 is an example view showing the cross-sectional structure of the optical region OA in Fig. 3. In the following description, content that is the same as or similar to the content described with reference to Figs. 1 to 4 will be omitted or will be described briefly.

[0146] 3 and 5, in the display device 100 according to the embodiment of the present disclosure, the optical area OA includes a through-hole TH and a HiAA bezel area HBA, and the display area AA may be located on the outer periphery of the HiAA bezel area HBA. The HiAA bezel area HBA may be a non-display area NA.

[0147] When viewing the cross section of the HiAA bezel area HBA, various insulating films present in the display area AA and the HiAA bezel area HBA may be arranged. For example, a buffer layer 302, a lower interlayer insulating film 305, an upper buffer layer 307, and an upper interlayer insulating film 308 may be stacked in this order on top of the substrate 301. However, the embodiments of the present disclosure are not limited thereto.

[0148] 3 and 5, a dam area 200 including a "dam structure" such as a dam may be located between the display area AA and the through-hole TH.

[0149] The dam structure may have a layer structure of two or more layers formed perpendicular to the substrate 301. For example, the dam structure may include a first layer formed of a planarization layer 310 and a second layer formed of a bank 354. Specifically, the dam structure may include a first layer formed of a second planarization layer 311 and a second layer formed of a bank 354. The dam structure may include a first layer formed of the second planarization layer 311, a second layer formed of a bank 354, and a third layer formed of a spacer (not shown). The dam structure may further include the first planarization layer 310 below the second planarization layer 311, or may have a stacked structure including other layers. However, the embodiments of the present disclosure are not limited thereto.

[0150] The dam region 200 may include at least one dam. For example, the dam region 200 may include a first dam 230, a second dam 220, and a third dam 210 arranged between the display region AA and the through-hole TH in the order of their proximity to the display region AA.

[0151] 5 , in the HiAA bezel area HBA, which is a non-display area, a light emitting stack 352 may be disposed on the upper interlayer insulating layer 308, which is an insulating layer. The light emitting stack 352 may also be disposed on the dams 210, 220, and 230 disposed in the dam area 200. The light emitting stack 352 may be an organic light emitting stack. However, the embodiments of the present disclosure are not limited thereto.

[0152] A second electrode 353 may be disposed on the light-emitting stack 352, extending from the display area AA to the non-display area HiAA bezel area HBA. The second electrode 353 may be a cathode electrode. However, the embodiments of the present disclosure are not limited thereto.

[0153] An electrode patterning material layer 420 that can improve light transmittance may be disposed in the HiAA bezel area HBA. The electrode patterning material layer 420 may be disposed on the light emitting stack 352 and may extend from one end of the second electrode 353 to the through-hole TH. One end of the electrode patterning material layer 420 may be aligned with one end of the light emitting stack 352. However, the embodiments of the present disclosure are not limited thereto.

[0154] The electrode patterning material layer 420 may be formed using an electrode patterning material (EPM) containing an organic material. For example, the electrode patterning material layer 420 may be formed by depositing the electrode patterning material (EPM) using a fine metal mask (FMM) to cover at least a portion of the HiAA bezel area (HBA). As an example, the electrode patterning material may be Ir(ppy)3 (Tris(2-phenylpyridine)iridium(III)), which is an organic material. However, the embodiments of the present disclosure are not limited thereto.

[0155] The electrode patterning material (EPM) can be used to improve the light transmittance of the optical area OA and to effectively pattern the second electrode 353 formed on the entire surface of the display area AA and part of the non-display area NA.

[0156] After forming the electrode patterning material (EPM) in the optical area OA using the FMM, the second electrode 353 is deposited on the entire surface of the display area AA and a portion of the non-display area NA using an OMM (Open Metal Mask), thereby effectively forming the second electrode 353 on the entire surface of the display area AA and a portion of the non-display area NA except for the electrode patterning material (EPM). As a result, the electrode patterning material layer 420 and the second electrode 353 can be positioned on the same plane.

[0157] The thickness of the second electrode 353 does not have to be less than the thickness of the electrode patterning material layer 420. For example, the thickness of the second electrode 353 may be the same as or greater than the thickness of the electrode patterning material layer 420.

[0158] For example, when an electrode patterning material (EPM) is deposited on the light emitting stack 352 in the optical area OA using FMM to form the electrode patterning material layer 420, and then a metal material serving as the second electrode 353 is deposited over the entire surface, the metal material may not be deposited on the electrode patterning material layer 420, and the second electrode 353 may be selectively formed only over the entire surface of the display area AA and part of the light emitting stack 352 in the non-display area NA, excluding the electrode patterning material layer 420. However, the embodiments of the present disclosure are not limited thereto.

[0159] The electrode patterning material (EPM) has low surface energy or low adhesion characteristics with high interfacial energy between the metal and the electrode patterning material layer 420. This significantly increases the probability of metal desorption from the surface of the electrode patterning material layer 420 during metal deposition, and also prevents metal nucleation. Therefore, the metal is selectively deposited only in areas with relatively low interfacial energy and high adhesion, making it possible to form self-aligned patterned metal.

[0160] 5, the light emitting stack 352 and the electrode patterning material layer 420 may be sequentially stacked and disposed in the HiAA bezel area HBA. For example, the light emitting stack 352 and the electrode patterning material layer 420 may be sequentially stacked and disposed on the dams 210, 220, and 230 located in the dam area 200. The light emitting stack 352 and the electrode patterning material layer 420 may be sequentially stacked and disposed between the display area AA and the first dam 230. The light emitting stack 352 and the electrode patterning material layer 420 may be sequentially stacked and disposed between the dams 210, 220, and 230 in the dam area 200. The light emitting stack 352 and the electrode patterning material layer 420 may be sequentially stacked and disposed between the third dam 210 and the through-hole TH.

[0161] At least one groove may be disposed between the display area AA and the through-hole TH. The groove may be formed by cutting the light emitting stack 352 and the electrode patterning material layer 420, respectively.

[0162] The groove 434 may be located between the display area AA and the dam area 200. For example, the groove 434 may be located between the display area AA and the first dam 230.

[0163] Alternatively, a groove may be located between the dams. For example, groove 433 may be located between first dam 230 and second dam 220, and groove 432 may be located between second dam 220 and third dam 210.

[0164] Also, the groove 431 may be located between the dam region 200 and the through-hole TH. For example, the groove 431 may be located between the third dam 210 and the through-hole TH.

[0165] The light emitting stack 352 and the electrode patterning material layer 420 may be cut off in the grooves 431, 432, 433, and 434, respectively.

[0166] 5, if the grooves 431, 432, 433, and 434 are not formed, the light-emitting stack 352 may be disposed so as to extend to the through-hole TH. Therefore, the light-emitting stack 352 may become a moisture permeation path to the side at the cut surface of the through-hole TH, and the moisture permeation may cause the film to lift up.

[0167] Referring to FIG. 5, the light emitting stack 352 is cut off at the grooves 431, 432, 433, and 434, blocking the moisture permeation path through the light emitting stack 352 and preventing or reducing side moisture permeation due to lifting of the film.

[0168] In the grooves 431, 432, 433, and 434, one end of the electrode patterning material layer 420 may be aligned with one end of the light-emitting stack 352. However, the embodiments of the present disclosure are not limited thereto.

[0169] 5, a capping layer 355 may be disposed on the second electrode 353 and the electrode patterning material layer 420. The capping layer 355 may be disposed so as to be interrupted at grooves 431, 432, 433, and 434.

[0170] That is, the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 may be disposed so as to be disconnected in the grooves 431, 432, 433, and 434. Also, in the grooves 431, 432, 433, and 434, one end of the light emitting stack 352, one end of the electrode patterning material layer 420, and one end of the capping layer 355 may be disposed so as to be aligned.

[0171] An encapsulation layer 360 may be disposed over the capping layer 355 .

[0172] The sealing layer 360 is not interrupted at the grooves 431, 432, 433, and 434 and can be in contact with the upper interlayer insulating film 308, which is an insulating layer.

[0173] The encapsulation layer 360 may be single or multi-layered.

[0174] For example, the sealing layer 360 may include a first sealing layer, a second sealing layer, and a third sealing layer. The first and third sealing layers may be inorganic films, and the second sealing layer may be an organic film. That is, the first sealing layer may be a first inorganic sealing layer 361, the second sealing layer may be an organic sealing layer 362, and the third sealing layer may be a second inorganic sealing layer 363.

[0175] The first inorganic sealing layer 361 is not interrupted at the grooves 431, 432, 433, and 434, and can be in contact with the upper interlayer insulating film 308, which is an insulating layer.

[0176] The organic sealing layer 362 may be disposed between the first inorganic sealing layer 361 and the second inorganic sealing layer 363. The organic sealing layer 362 may be disposed between the display area AA and the first dam 230.

[0177] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 may be disposed in contact with each other around the first dam 230 and extend into the through-hole TH.

[0178] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 may be disposed so as to be exposed to the through-holes TH.

[0179] Referring to FIG. 5, a lower shield metal 410 may be disposed between the substrate 301 and the buffer layer 302, which is an insulating layer.

[0180] One end of the lower shield metal 410 may overlap the electrode patterning material layer 420, and the other end of the lower shield metal 410 may overlap the second electrode 353. For example, one end of the lower shield metal 410 may be located between one end of the second electrode 353 and the groove 434.

[0181] Fig. 6 is another exemplary cross-sectional view taken along line II-II' in Fig. 3. For example, Fig. 6 is another exemplary view showing the cross-sectional structure of the optical region OA in Fig. 3. In the following description, content that is the same as or similar to the content described with reference to Figs. 1 to 5 will be omitted or will be explained briefly.

[0182] 6, the only difference compared to the cross-sectional example shown in FIG. 5 is the arrangement of the first inorganic sealing layer 361 and the second inorganic sealing layer 363 in the through-hole TH region, and therefore, a description of the other configurations will be omitted.

[0183] 6, the organic sealing layer 362 may be disposed between the first inorganic sealing layer 361 and the second inorganic sealing layer 363. The organic sealing layer 362 may be disposed between the display area AA and the first dam 230.

[0184] The first inorganic sealing layer 361 and the second inorganic sealing layer 363 may be disposed in contact with each other around the periphery of the first dam 230 and extend to the through-hole TH. The second inorganic sealing layer 363 may cover one end of the first inorganic sealing layer 361 at the through-hole TH. That is, one end 363a of the second inorganic sealing layer 363 may cover one end of the first inorganic sealing layer 361 at the through-hole TH.

[0185] In various embodiments of the present disclosure, the number, size, arrangement, and shape of the grooves 431, 432, 433, and 434 may vary. For example, referring to FIGS. 5 and 6, the number of grooves may be four as shown, but embodiments of the present disclosure are not limited thereto. For example, the number of grooves may be more or less than four. In the embodiments shown in FIGS. 5 and 6, the number of grooves 431, 432, 433, and 434 may be one more than the number of dams 210, 220, and 230, but in other embodiments, the number of grooves may be the same as, more than, or less than the number of dams.

[0186] Additionally, the size of one or more of the grooves 431, 432, 433, and 434 may vary. For example, referring to FIGS. 5 and 6, the size of each of the grooves 431, 432, 433, and 434 may be illustrated as being smaller than the width of the gap between adjacent dams. For example, the groove 433 may be illustrated as being narrower than the gap or groove between the first dam 230 and the second dam 220. In this regard, the other grooves 434, 432, and 431 may be illustrated as having the same or similar width or size. However, embodiments of the present disclosure are not limited thereto. For example, the width or size of one or more of the grooves 431, 432, 433, and 434 may be the same as the gap or groove between adjacent dams, such as the first dam 230 and the second dam 220. In this case, the groove 433 may extend from the planarization layer 310 of the first dam 230 to the planarization layer 310 of the second dam 220. One or more of the other grooves 434 , 432 , 431 can have the same or similar width or size as groove 433 .

[0187] Furthermore, the arrangement of one or more grooves 431, 432, 433, and 434 may vary. Referring to FIGS. 5 and 6, one groove is shown between adjacent dams. For example, there is one groove 433 between adjacent first dam 230 and second dam 220. However, embodiments of the present disclosure are not limited thereto. For example, two or more grooves may be located between first dam 230 and second dam 220 and between other dams. In other embodiments, any of grooves 431, 432, 433, and 434 may be formed as multiple grooves, while the remaining may be formed as a single groove. In embodiments of the present disclosure, there may be multiple grooves between a pair of dams, such as first dam 230 and second dam 220, but there may be no groove between second dam 220 and third dam 210. In other embodiments of the present disclosure, grooves 434 and 431 may each be multiple grooves.

[0188] Furthermore, the shapes of the grooves 431, 432, 433, and 434 may vary. Referring to Figures 3, 5, and 6, the grooves 431, 432, 433, and 434 may be circular in plan view or may correspond to the shape of the through-holes, but the embodiments of the present disclosure are not limited thereto. For example, the shape of one or more of the grooves 431, 432, 433, and 434 in plan view does not necessarily have to be a smooth curve, but may be wavy, or one of the outer and inner walls of the grooves 431, 432, 433, and 434 may have a V-shape, square wave shape, semicircular shape, or other shape, but the embodiments of the present disclosure are not limited thereto.

[0189] 5, 6 and 7, the number, size, arrangement and shape of the sacrificial layer 440 may correspond to the number, size, arrangement and shape of the grooves 431, 432, 433, 434.

[0190] 7 to 12b are diagrams illustrating steps of forming the optical region of a display panel according to an embodiment of the present disclosure.

[0191] Referring to FIG. 7, a sacrificial layer 440 and dams 210 ′, 220 ′, and 230 ′ may be formed on a substrate 301 .

[0192] For example, a lower shield metal 410 can be disposed on the substrate 301 .

[0193] A plurality of insulating layers can be disposed on the substrate 301 and the lower shield metal 410. For example, a buffer layer 302, a lower interlayer insulating film 305, an upper buffer layer 307, and an upper interlayer insulating film 308 can be disposed. A planarizing layer 310 can be formed by patterning on the upper interlayer insulating film 308.

[0194] A metal material is patterned on the upper interlayer insulating film 308 to form a sacrificial layer 440. The sacrificial layer 440 may be formed of the same material as the first electrode material, although embodiments of the present disclosure are not limited thereto.

[0195] The banks 354 may be patterned on the planarization layer 310 to form the dams 210', 220', and 230'. The light-emitting stack 352 may be formed on the banks 354, the upper interlayer insulating film 308, the sacrificial layer 440, and the dams 210', 220', and 230'.

[0196] 8, an electrode patterning material layer 420 may be formed in the HiAA bezel area HBA, which is the non-display area NA, using an electrode patterning material (EPM). The electrode patterning material (EPM) may be deposited using FMM to cover at least a portion of the HiAA bezel area HBA. In this case, the electrode patterning material layer 420 may be formed to overlap the lower shield metal 410.

[0197] 9, metal can be deposited on the entire surface of the display area AA and a portion of the non-display area NA using the OMM to form the second electrode 353. In this case, the second electrode 353 can be effectively formed on the entire surface of the display area AA and a portion of the non-display area NA, excluding the electrode patterning material layer 420. As a result, the electrode patterning material layer 420 and the second electrode 353 can be positioned on the same plane.

[0198] 10, a capping layer 355 may be formed by blanket depositing on the second electrode 353 and the electrode patterning material layer 420. However, the embodiment of the present disclosure is not limited thereto.

[0199] 11 , grooves 431′, 432′, 433′, and 434′ may be formed by irradiating laser light 500 onto the sacrificial layer 440 below the substrate 301. The laser light 500 may travel in the thickness direction of the substrate 301 from the lower surface of the substrate 301 and be irradiated onto the lower surface of the sacrificial layer 440. The laser light 500 may have an infrared wavelength. However, the embodiments of the present disclosure are not limited thereto. When the laser light 500 is infrared, the transmittance of the substrate 301 and the insulating layers 302, 305, 307, and 308 is high, and the laser light 500 may efficiently reach the sacrificial layer 440.

[0200] The sacrificial layer 440 can absorb the laser light 500, causing thermal expansion of the sacrificial layer 440, and the sacrificial layer 440 irradiated with the laser light 500 can be lifted off from the insulating layers 302, 305, 307, and 308.

[0201] As the sacrificial layer 440 is peeled off, the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 disposed on the peeled sacrificial layer 440 may also be removed together with the sacrificial layer 440. As a result, grooves 431′, 432′, 433′, and 434′ formed by openings in the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 may be formed.

[0202] Meanwhile, the lower shield metal 410 may be positioned between one end of the second electrode 353 and one end of the sacrificial layer 440. Since one end of the lower shield metal 410 is positioned between one end of the second electrode 353 and one end of the sacrificial layer 440, even if a laser beam 500 is irradiated onto the lower surface of the substrate 301, the lower shield metal 410 can prevent the laser beam 500 from irradiating onto the second electrode 353. Therefore, the distance between the second electrode 353 and the grooves 431′, 432′, 433′, and 434′ can be reduced, and the width of the HiAA bezel area HBA can be reduced.

[0203] 12a, after forming grooves 431', 432', 433', and 434', a first inorganic encapsulating layer 361, an organic encapsulating layer 362, and a second inorganic encapsulating layer 363 are sequentially stacked. In this case, the first inorganic encapsulating layer 361 and the second inorganic encapsulating layer 363 may be formed to extend to the through-hole TH region. Then, the through-hole TH may be formed using a laser along a trimming line. In this case, the first inorganic encapsulating layer 361 and the second inorganic encapsulating layer 363 may be disposed so as to be exposed to the through-hole TH.

[0204] 12b, after forming grooves 431', 432', 433', and 434', a first inorganic encapsulating layer 361, an organic encapsulating layer 362, and a second inorganic encapsulating layer 363 are sequentially stacked. In this case, the first inorganic encapsulating layer 361 may be formed so as not to extend to the through-hole TH region, and the second inorganic encapsulating layer 363 may extend to the through-hole TH region to form a region 363a that surrounds the first inorganic encapsulating layer 361. Then, the through-hole TH may be formed using a laser along a trimming line. One end 363a of the second inorganic encapsulating layer 363 may be formed to cover one end of the first inorganic encapsulating layer 361 at the through-hole TH.

[0205] 5 to 12b, when the sacrificial layer 440 is peeled off to remove the light emitting stack 352, the electrode patterning material layer 420, and the capping layer 355, portions of the upper interlayer insulating film 308 may be exposed in groups 431, 432, 433, and 434. Then, when the first encapsulating layer 361 and the third encapsulating layer 363 are formed in groups 431, 432, 433, and 434, a encapsulating structure of multiple stacked inorganic layers may be formed. The encapsulating structure may include two or more upper interlayer insulating films 308, first encapsulating layers 361, and third encapsulating layers 363 that are in direct contact with each other.

[0206] Two or more of the upper interlayer insulating film 308, the first encapsulation layer 361, and the third encapsulation layer 363 may include or be formed of the same material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but embodiments of the present disclosure are not limited thereto.

[0207] In various embodiments of the present disclosure, when two or more of groups 431, 432, 433, 434 are sealed with the first sealing layer 361 and the third sealing layer 363, each portion of the light-emitting stack 352, the electrode patterning material layer 420, and the capping layer 355 can be sealed between the upper interlayer insulating film 308 and the first sealing layer 361.

[0208] The above-described embodiment of the present disclosure can be briefly described as follows.

[0209] According to an embodiment of the present disclosure, a display device can be provided that includes a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a light-emitting stack disposed on the insulating layer, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, and an electrode patterning material layer disposed on the light-emitting stack in contact with one end of the second electrode, wherein one end of the light-emitting stack and one end of the electrode patterning material layer are aligned.

[0210] The display device according to the embodiment of the present disclosure may include a dam disposed between the display area and the through-hole.

[0211] In the display device according to the embodiment of the present disclosure, a light-emitting stack and an electrode patterning material layer may be sequentially disposed on the dam.

[0212] In the display device according to the embodiment of the present disclosure, the light emitting stack and the electrode patterning material layer may each include a groove disposed between the display area and the dam.

[0213] The display device according to the embodiment of the present disclosure may include a capping layer disposed on the second electrode and the electrode patterning material layer.

[0214] In a display device according to an embodiment of the present disclosure, the capping layer may be interrupted at the grooves.

[0215] In a display device according to an embodiment of the present disclosure, the dam may include a plurality of dams spaced apart from one another.

[0216] In a display device according to an embodiment of the present disclosure, the plurality of dams may include a first dam and a second dam, and may include a groove located between the first dam and the second dam, in which the light-emitting stack and the electrode patterning material layer are each cut off.

[0217] In the display device according to the embodiment of the present disclosure, the light emitting stack and the electrode patterning material layer may each include a recessed groove located between the display area and the first dam.

[0218] A display device according to an embodiment of the present disclosure may include a lower shield metal disposed between the substrate and the insulating layer, one end of the lower shield metal overlapping the electrode patterning material layer and the other end of the lower shield metal overlapping the second electrode.

[0219] In the display device according to the embodiment of the present disclosure, one end of the lower shield metal may be located between one end of the second electrode and one end of the electrode patterning material layer.

[0220] The display device according to the embodiment of the present disclosure includes a sealing layer disposed on the capping layer, and the sealing layer can be in contact with the insulating layer without being interrupted at the groove.

[0221] In the display device according to the embodiment of the present disclosure, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and the first inorganic encapsulation layer can be in contact with the insulating layer without being interrupted by the groove.

[0222] In the display device according to the embodiment of the present disclosure, the first inorganic sealing layer and the second inorganic sealing layer may be exposed to the through-holes.

[0223] In the display device according to the embodiment of the present disclosure, the second inorganic sealing layer can cover one end of the first inorganic sealing layer at the through-hole.

[0224] In the display device according to the embodiment of the present disclosure, the thickness of the second electrode may not be smaller than the thickness of the electrode patterning material layer.

[0225] According to an embodiment of the present disclosure, a display device can be provided that includes a substrate including a non-display area including a through hole and a display area surrounding the non-display area, an insulating layer disposed on the substrate, a plurality of dams located between the display area and the through hole and disposed on the insulating layer, a light-emitting stack disposed on the insulating layer and the plurality of dams, a second electrode extending from the display area to the non-display area and disposed on the light-emitting stack, an electrode patterning material layer contacting one end of the second electrode and disposed on the light-emitting stack, and a groove in which the light-emitting stack and the electrode patterning material layer are each cut off.

[0226] In a display device according to an embodiment of the present disclosure, the grooves can be arranged in at least one of the areas between the display area and the plurality of dams, the areas between the plurality of dams, and the areas between the plurality of dams and the through holes.

[0227] The display device according to the embodiment of the present disclosure may include a capping layer disposed on the second electrode and the electrode patterning material layer, and the capping layer may be interrupted at the groove.

[0228] A display device according to an embodiment of the present disclosure may include a lower shield metal disposed between the substrate and the insulating layer, and one end of the lower shield metal may be located between one end of the second electrode and one end of the electrode patterning material layer.

[0229] In a display device according to an embodiment of the present disclosure, a sealing layer is disposed on the capping layer, and the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, and the first inorganic sealing layer can contact the insulating layer without being interrupted at the groove.

[0230] In the display device according to the embodiment of the present disclosure, the thickness of the second electrode may not be smaller than the thickness of the electrode patterning material layer.

[0231] According to an embodiment of the present disclosure, a method for manufacturing a display device can be provided, including the steps of forming a substrate including a display area and a non-display area, forming a sacrificial layer and a dam in the non-display area, forming a light-emitting stack to cover the sacrificial layer and the dam, forming an electrode patterning material layer located in the non-display area on the light-emitting stack, forming a second electrode on the light-emitting stack in contact with the electrode patterning material layer, forming a capping layer on the second electrode and the electrode patterning material layer, and irradiating laser light on the sacrificial layer to form a groove.

[0232] In the manufacturing method of the display device according to the embodiment of the present disclosure, in the step of forming the groove, the light-emitting stack may be interrupted by the groove.

[0233] In the method for manufacturing a display device according to the embodiment of the present disclosure, in the step of forming the second electrode, the second electrode may be formed in the same layer as the electrode patterning material layer.

[0234] A method for manufacturing a display device according to an embodiment of the present disclosure may include forming a sealing layer to cover the capping layer and the groove.

[0235] In the manufacturing method of a display device according to an embodiment of the present disclosure, the step of forming a sealing layer may be formed so that the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer, and the second inorganic sealing layer covers the organic sealing layer and is in contact with the first inorganic sealing layer.

[0236] In the method for manufacturing a display device according to the embodiment of the present disclosure, the second inorganic sealing layer may be formed to cover one end of the first inorganic sealing layer.

[0237] The display device and the manufacturing method thereof according to the embodiments of the present disclosure can block the lateral moisture permeation path through the light emitting stack by patterning the light emitting stack.

[0238] The display device and manufacturing method thereof according to the embodiments of the present disclosure can prevent or reduce lateral moisture permeation paths and microcracks due to the light emitting stack by patterning the light emitting stack and disposing a dam structure.

[0239] A display device and a manufacturing method thereof according to an embodiment of the present disclosure can reduce power consumption by preventing or reducing side moisture permeation to improve lifespan.

[0240] The above description merely exemplifies the technical idea of ​​the present disclosure, and various modifications and variations are possible by a person having ordinary skill in the art to which the present disclosure pertains without departing from the essential characteristics of the present disclosure. Furthermore, the examples disclosed in the present disclosure are intended to illustrate rather than limit the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by such examples.

Claims

1. a substrate including a non-display area including a through-hole and a display area surrounding the non-display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light-emitting stack and contacting one end of the electrode; a dam disposed between the display area and the through-hole; a groove located between the display area and the dam; a capping layer disposed on the electrode and the electrode patterning material layer; Including, the capping layer is interrupted at the groove; Display device.

2. The display device of claim 1 , wherein the light-emitting stack and the electrode patterning material layer are disposed sequentially on the dam.

3. A display device as described in Claim 2, wherein the light-emitting stack and the electrode patterning material layer are each cut off in the groove.

4. The display device according to claim 3 , wherein one end of the light-emitting stack and one end of the electrode patterning material layer are arranged to coincide with each other.

5. The display device according to claim 1 , wherein the dam includes a plurality of dams spaced apart from one another.

6. the plurality of dams further includes a first dam and a second dam; The display device of claim 5 , further comprising a first groove located between the first dam and the second dam, the first groove being cut off from the light emitting stack and the second groove being cut off from the electrode patterning material layer.

7. The display device of claim 6 , further comprising a second groove located between the display area and the first dam, the second groove being cut off from the light emitting stack and the electrode patterning material layer.

8. A substrate including a non-display area including a through-hole and a display area surrounding the non-display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light-emitting stack and contacting one end of the electrode; a lower shield metal disposed between the substrate and the insulating layer; Including, One end of the light emitting stack is aligned with one end of the electrode patterning material layer; one end of the lower shield metal overlaps the electrode patterning material layer, and the other end of the lower shield metal overlaps the electrode; Display device.

9. The display device of claim 8 , wherein one end of the lower shield metal is located between one end of the electrode and one end of the electrode patterning material layer.

10. a sealing layer disposed on the capping layer; The display device according to claim 1 , wherein the sealing layer is not interrupted at the groove and is in contact with the insulating layer.

11. the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer; The display device according to claim 10 , wherein the first inorganic sealing layer is not interrupted at the groove and is in contact with the insulating layer.

12. A substrate including a non-display area including a through-hole and a display area surrounding the non-display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light-emitting stack and contacting one end of the electrode; a dam disposed between the display area and the through-hole; a groove located between the display area and the dam, the groove being formed by cutting the light emitting stack and the electrode patterning material layer; a capping layer disposed on the electrode and the electrode patterning material layer; a sealing layer disposed on the capping layer; Including, One end of the light emitting stack is aligned with one end of the electrode patterning material layer; the light-emitting stack and the electrode patterning material layer are sequentially disposed on the dam; the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer; the first inorganic sealing layer is not interrupted at the groove and is in contact with the insulating layer; the first inorganic sealing layer and the second inorganic sealing layer are exposed to the through-hole; Display device.

13. A substrate including a non-display area including a through-hole and a display area surrounding the non-display area; an insulating layer disposed on the substrate; a light emitting stack disposed on the insulating layer; an electrode extending from the display area to the non-display area and disposed on the light-emitting stack; an electrode patterning material layer disposed on the light-emitting stack and contacting one end of the electrode; a dam disposed between the display area and the through-hole; a groove located between the display area and the dam, the groove being formed by cutting the light emitting stack and the electrode patterning material layer; a capping layer disposed on the electrode and the electrode patterning material layer; a sealing layer disposed on the capping layer; Including, One end of the light emitting stack is aligned with one end of the electrode patterning material layer; the light-emitting stack and the electrode patterning material layer are sequentially disposed on the dam; the sealing layer includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer; the first inorganic sealing layer is not interrupted at the groove and is in contact with the insulating layer; the second inorganic sealing layer covers one end of the first inorganic sealing layer at the through-hole; Display device.

14. The display device of claim 1 , wherein the thickness of the electrode is not less than the thickness of the electrode patterning material layer.

15. a substrate including a non-display area including a through-hole and a display area adjacent to the non-display area; an inorganic insulating layer disposed on the substrate; a light-emitting stack disposed on the inorganic insulating layer; a common electrode extending from the display area to the non-display area and disposed on the light-emitting stack; a dam disposed between the display area and the through-hole; an electrode patterning material layer contacting one end of the common electrode and disposed on the light emitting stack; at least one groove formed in the light emitting stack and surrounding the through hole; a capping layer disposed on the common electrode and the electrode patterning material layer; an inorganic sealing layer formed on the common electrode, the inorganic sealing layer being disposed within the at least one groove; Including, the capping layer is interrupted at the at least one groove; Display device.

16. The display device according to claim 15 , wherein the inorganic insulating layer and the inorganic sealing layer are in direct contact with each other within the at least one groove.

17. forming a substrate including a display area and a non-display area; forming a sacrificial layer and a dam in the non-display area; forming a light emitting stack overlying the sacrificial layer and the dam; forming an electrode patterning material layer located in the non-display area on the light-emitting stack; forming a second electrode on the light-emitting stack in contact with the electrode-patterning material layer; forming a capping layer on the second electrode and the electrode patterning material layer; irradiating the sacrificial layer with laser light to form grooves; forming a sealing layer to cover the capping layer and the groove; Including, the sealing layer includes at least a first inorganic sealing layer and a second inorganic sealing layer; the second inorganic sealing layer is formed so as to cover one end of the first inorganic sealing layer; A method for manufacturing a display device.

18. In the step of forming the groove, The method of claim 17 , wherein the light-emitting stack is interrupted by the groove.

19. In the step of forming the second electrode, The method of claim 17, wherein the second electrode is formed in the same layer as the electrode patterning material layer.

20. the sealing layer includes an organic sealing layer between the first inorganic sealing layer and the second inorganic sealing layer, The method for manufacturing a display device according to claim 17 , wherein the second inorganic sealing layer is formed to cover the organic sealing layer and to be in contact with the first inorganic sealing layer.

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