Semiconductor Devices

Abstract

To provide a semiconductor device capable of high speed operation.SOLUTION: The semiconductor device comprises: a first transistor to one of whose source and drain a first signal is input; a second transistor to one of whose source and drain a first potential is supplied and to whose gate a second signal is input; and a capacitance element whose first electrode is electrically connected to the other of source and drain of the first transistor, and whose second electrode is connected to the other of source and drain of the second transistor. The semiconductor device has a first period during which the first signal is at a low level and the second signal is at a high level, and a second period during which the first signal is at a high level and the second signal is at a low level or high level.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, or the like. [Background technology]

[0002] As display devices such as liquid crystal display devices and EL display devices become larger, more value-added display devices are required. In particular, the development of display device drive circuits that use only transistors of one conductivity type is underway. The development of technology for configuring such a device is being actively promoted (see Patent Document 1).

[0003] FIG. 16 shows a driving circuit disclosed in Patent Document 1. The driving circuit of Patent Document 1 The signal GOUT[N-1] is at a high level. When this happens, transistor M3 turns on. Then, the voltage VON is applied to the gate of transistor M1. As a result, the potential at the gate of transistor M1 begins to rise. The potential at the gate of transistor M1 gradually rises, so the voltage between the gate and source of transistor M3 The potential difference (hereinafter also referred to as Vgs) of transistor M3 gradually decreases. becomes the threshold voltage of transistor M3, turning transistor M3 off. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-103226 Summary of the Invention [Problem to be solved by the invention]

[0005] In the driving circuit of Patent Document 1, as the potential of the gate of transistor M1 rises, The Vgs of transistor M3 gradually decreased. Therefore, after the signal GOUT[N-1] becomes high level, The time it takes for transistor M3 to turn off is longer. Meanwhile, the signal CKV is high. Before the voltage reaches the threshold, transistor M3 is turned off, and the gate of transistor M1 is left floating. Therefore, in the drive circuit of Patent Document 1, it is necessary to increase the drive frequency. It was difficult to do so.

[0006] In addition, in the drive circuit of Patent Document 1, in order to quickly increase the potential of the gate of the transistor M1, To achieve this, the W (W: channel width) / L (L: channel length) ratio of transistor M3 is increased. Therefore, the size of transistor M3 becomes large, and the layout area becomes large. It had become like this.

[0007] Furthermore, in the drive circuit of Patent Document 1, the gate of the transistor M1 must be in a floating state. On the other hand, the transistors whose source or drain is connected to the gate of the transistor M1 The off-state current of the transistor causes charge to leak from the gate of the transistor M1. It was difficult to extend the period during which the gate of the driving transistor M1 was in a floating state. It was difficult to lower the operating frequency.

[0008] As mentioned above, the driving circuit of Patent Document 1 can neither increase nor decrease the driving frequency. This makes it difficult to achieve the required operating frequency range, narrowing the operating frequency range.

[0009] In view of the above, one aspect of the present invention provides a drive circuit that can operate even at a high drive frequency. Another object of the present invention is to provide a driving circuit that can operate even at a low driving frequency. Another object of the present invention is to provide a driver circuit that can operate over a wide range of drive frequencies. Another objective is to reduce the W / L ratio of the transistor. Another objective is to provide a circuit with a new configuration. When describing an effect in this specification, etc., it is necessary to understand that there is a problem corresponding to the effect. On the other hand, when a problem is stated in this specification, etc., It is self-evident that this will have the desired effect. [Means for solving the problem]

[0010] One aspect of the present invention is a first transistor having a first signal input to one of a source and a drain. A first potential is applied to one of the source and drain, and a second signal is input to the gate. a second transistor connected to the first electrode and a source and drain of the first transistor; the second electrode is electrically connected to the other of the source and drain of the second transistor. and a capacitance element electrically connected to the semiconductor device. The first period is when the first signal is at a low level and the second signal is at a high level, and the second period is when the first signal is at a low level and the second signal is at a high level. a second period in which the first signal is at a high level and the second signal is at a low level or a high level; , has.

[0011] One aspect of the present invention is a first transistor having a first signal input to one of a source and a drain. A first potential is applied to one of the source and drain, and a second signal is input to the gate. a second transistor connected to the gate of the first transistor, and a first signal is input to one of the source and the drain of the second transistor; a third transistor whose gate is electrically connected to the gate of the first transistor; The electrode is electrically connected to the other of the source and drain of the first transistor, and the second electrode is a capacitor element electrically connected to the other of the source and the drain of the second transistor; The semiconductor device is a semiconductor device in which the first signal is at a low level and the second signal is at a low level. A first period in which the second signal is at a high level, and a second period in which the first signal is at a high level and the second signal is at a low level. and a second period in which the signal is at a low level or a high level.

[0012] In the above-described embodiment of the present invention, the semiconductor device has a first A potential is supplied, and the other of the source and drain is connected to the source and drain of the first transistor. the gate is electrically connected to the other of the source and drain of the second transistor. a fourth transistor electrically connected to the first transistor and a second transistor having a first potential applied to one of a source and a drain; the other of the source and the drain is electrically connected to the gate of the first transistor; a fifth transistor whose gate is electrically connected to the other of the source and drain of the second transistor; A second potential is applied to one of the source and drain of the transistor, and the source and drain The other of the two is electrically connected to the other of the source and drain of the second transistor, and the other is connected to the gate of the second transistor. and a sixth transistor to which the third signal is input.

[0013] In the above embodiment of the present invention, W (W is a channel width) / L ( The W / L ratio (L is the channel length) may be greater than the W / L ratio of the second transistor. [Effects of the Invention]

[0014] One embodiment of the present invention can provide a driver circuit that can operate even at a high drive frequency. It is also possible to provide a drive circuit that can operate even at a low drive frequency. It is possible to provide a driving circuit that can operate in a wide range of driving frequencies. The / L ratio can be reduced. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 illustrates a basic circuit according to one embodiment of the present invention. [Figure 2] FIG. 1 illustrates a basic circuit according to one embodiment of the present invention. [Figure 3] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 5] FIG. 10 is a diagram illustrating a shift register circuit according to one embodiment of the present invention. [Figure 6] 1A and 1B are diagrams illustrating a basic circuit and a sequential circuit according to one embodiment of the present invention. [Figure 7] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 8] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 9] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 10] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 11] FIG. 10 is a diagram illustrating a sequential circuit according to one embodiment of the present invention. [Figure 12] 1A and 1B are diagrams illustrating a display device according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating transistors according to one embodiment of the present invention. [Figure 14] 1A and 1B are diagrams illustrating a display device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 16] FIG. 1 is a diagram for explaining a conventional driving circuit. DETAILED DESCRIPTION OF THE INVENTION

[0016] An example of an embodiment for explaining the present invention will be described below with reference to the drawings. The contents of the embodiments may be changed without departing from the spirit and scope of the present invention. It is easy for a person skilled in the art to understand the present invention. Therefore, the present invention is not limited to the description of the following embodiments. It will not be done.

[0017] The present invention can be applied to any semiconductor device using transistors, such as integrated circuits, RF tags, and display devices. The category includes semiconductor devices. Note that integrated circuits include microprocessors and image processing circuits. , DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit) including FPGA (Field Programmable Gate Array) and CPLD Programmable logic circuits (PLDs) such as complex PLDs The display device includes: Liquid crystal display devices, light-emitting devices with light-emitting elements, such as organic light-emitting diodes (OLEDs), in each pixel Display, electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi This category includes devices such as a 3D display.

[0018] In this specification, the term "display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are formed into pixels. The panel is a module in which ICs including a controller are mounted on the panel. This category includes both.

[0019] In this specification, connection means electrical connection, and the current, voltage, or potential Therefore, the connected state corresponds to the state in which the signal is directly connected. It does not necessarily refer to the state of being connected, but rather to the state in which a current, voltage, or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes the state in which components are indirectly connected through other means. Even when elements are connected to each other, in reality, for example, part of the wiring functions as an electrode. In some cases, a single conductive film may have the functions of multiple components. In the specification, connection means that one conductive film has the functions of multiple components. If so, include it in that category.

[0020] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The source electrode of a transistor is a region or a semiconductor film connected to the source electrode. The drain is a drain region that is a part of the semiconductor film, or a region connected to the semiconductor film. The term "gate" refers to a gate electrode.

[0021] The source and drain of a transistor are determined by the polarity of the transistor and the characteristics given to each terminal. The name changes depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel transistor, the terminal to which a low potential is applied is called The terminal to which a high potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. However, in reality, the names of source and drain are changed according to the above potential relationship. Replace.

[0022] (Embodiment 1) In this embodiment, a basic circuit, a sequential circuit using the basic circuit, and A shift register circuit using this sequential circuit will be described.

[0023] First, the configuration of a basic circuit of this embodiment will be described with reference to FIG.

[0024] The basic circuit of FIG. 1A includes a transistor 101, a transistor 102, and a capacitor 11. 0.

[0025] The first terminal of the transistor 101 is connected to the wiring 11, and the second terminal of the transistor 101 is connected to the wiring 11. The terminal is connected to wiring 12.

[0026] A first terminal of the transistor 102 is connected to the wiring 13, and a gate of the transistor 102 is connected to the It is connected to wiring 14.

[0027] A first electrode (also referred to as one electrode) of the capacitor 110 is connected to the wiring 12. A second electrode (also referred to as the other electrode) of the transistor 10 is connected to a second terminal of the transistor 102. do.

[0028] Note that the second terminal of the transistor 102 or the second electrode of the capacitor 110 is connected to a node N1. The gate of the transistor 101 is indicated as a node N2.

[0029] Note that the transistors 101 and 102 preferably have the same conductivity type. In this embodiment, the case where these transistors are N-channel transistors will be described. .

[0030] In this specification, connection means electrical connection, and does not include current, voltage, potential, signal Therefore, "connected" means that the device is in a state where it can supply or transmit a signal or charge. In addition to direct connections, other connections such as wiring, conductive films, resistors, diodes, and transistors This also includes indirect connections via elements such as inverters and switching elements. .

[0031] The first terminal of the transistor is connected to one of the source and drain of the transistor, or The second terminal of a transistor is also called the source electrode of the transistor. The other electrode of the transistor is also called the other of the source and drain, or the second electrode of the transistor.

[0032] A signal CK is input to the wiring 11 (also called a signal line), and the wiring 11 transmits the signal CK. The signal CK is a signal that has a high level and a low level. The signal CK corresponds to one of a plurality of clock signals input to the shift register circuit. This is the corresponding signal.

[0033] A signal OUT is output from the wiring 12 (also called a signal line), and the wiring 12 transmits the signal OUT. The signal OUT has a high level and a low level. The signal OUT is the output signal of the basic circuit shown in FIG. Any one of a plurality of output signals output from the soft register circuit, or an output signal of the sequential circuit is the signal corresponding to

[0034] A potential VSS (also referred to as a first potential) is supplied to the wiring 13 (also referred to as a power supply line), and The potential VSS is a constant potential.

[0035] A signal SP is input to the wiring 14 (also called a signal line), and the wiring 14 transmits or supplies the signal SP. The signal SP has a high level and a low level. The signal SP is a signal that controls the on / off of the transistor 102. The signal SP is The start pulse input to the shift register circuit, or the sequential pulse one or more stages before This signal corresponds to the output signal of the path.

[0036] The transistor 101 has a function of controlling conduction or non-conduction between the wiring 11 and the wiring 12 . The transistor 101 also has a function of supplying a signal CK from the wiring 11 to the wiring 12. In addition, the transistor 101 has a function of holding the potential difference between the wiring 12 and the node N2.

[0037] The transistor 102 has a function of controlling conduction or non-conduction between the wiring 13 and the node N1. The transistor 102 has a function of supplying the potential VSS of the wiring 13 to the node N1. do.

[0038] The capacitor 110 has a function of holding the potential difference between the wiring 12 and the node N1.

[0039] Next, the driving method of the basic circuit of FIG. 1(A) will be explained with reference to the timing chart shown in FIG. 1(B). , and FIG. 2.

[0040] The high-level potential of the signal CK and the signal SP is the potential VDD (also called the second potential). The low level potential is VSS. It has a higher potential than SS.

[0041] The initial potential of the node N1 is the potential VDD, and the initial potential of the node N2 is the potential VS The following description will be given on the assumption that the initial potential of the wiring 12 is VSS. If the initial potential of N2 is the potential VSS, then initially transistor 101 is off. are.

[0042] For convenience, the period required for operation will be explained by dividing it into a period Ta and a period Tb.

[0043] First, during a period Ta, the signal SP goes high and the signal CK goes low. When the signal SP goes high, the transistor 102 turns on. When the potential VSS of the wiring 13 is turned on, the potential VSS of the node N1 is supplied to the node N1. At this time, the potential of the capacitor 110 is connected between the node N1 and the wiring 12. Since the transistor 101 is turned off, the wiring 12 Therefore, as the potential of the node N1 drops, the potential of the wiring 12 Then, the potential of the wiring 12 falls from the potential of the node N2 (for example, the potential VSS ) minus the threshold voltage of the transistor 101, the transistor 101 It turns on (see Figure 2(A)).

[0044] When the transistor 101 is turned on, the signal CK on the wiring 11 is supplied to the wiring 12. Since CK is at a low level, the potential of the wiring 12 rises to the potential VSS. The transistor 101 maintains the potential difference between the node N2 and the wiring 12, and the node N2 Therefore, as the potential of the wiring 12 increases, the potential of the node N2 also increases. The potential of the node N2 rises. If the potential exceeds the sum of the threshold voltage of Therefore, the potential of the wiring 12 rises to the potential VSS. This results in a bell (see Figure 2(B)).

[0045] Next, during a period Tb, the signal SP goes low and the signal CK goes high. When the signal SP goes low, the transistor 102 is turned off. Therefore, the signal CK on the line 11 is connected to the line 1. 2. Since the signal CK is at a high level, the potential of the wiring 12 remains at the potential V At this time, the transistor 101 reduces the potential difference between the node N2 and the wiring 12. The potential of the wiring 12 is maintained at 1 V, and the node N2 is kept floating. As the potential of the node N2 rises, the potential of the node N2 also rises. For example, if the potential exceeds the sum of the potential VDD and the threshold voltage of the transistor 101, Therefore, the potential of the wiring 12 rises to the potential VDD. That is, the signal OUT becomes high level (see FIG. 2(C)).

[0046] In the basic circuit of FIG. 1A, during the period Ta, Vgs of the transistor 102 is set to a large voltage. Therefore, the drain current of the transistor 102 can be maintained at a large value. Therefore, the potential of the node N1 can be rapidly decreased, and This allows the time Ta to be shortened, which means that the drive frequency can be increased.

[0047] Also, if the Vgs of the transistor 102 can be maintained at a large voltage, the transistor Therefore, the layout area can be reduced and the input capacity can be reduced. It is possible to reduce the amount, etc.

[0048] Note that a capacitor may be connected between the gate and the second terminal of the transistor 101. In this way, the capacitance between the node N2 and the wiring 12 can be increased. The potential of N2 can be made higher.

[0049] Incidentally, the signal SP may remain at a high level even during the period Tb. During the period Tb, the transistor 102 remains on, and therefore the potential VSS of the wiring 13 Therefore, the potential of the node N1 due to the change in the potential of the wiring 12 Fluctuations in the temperature can be prevented.

[0050] During the period Tb, the signal SP is maintained at a high level from the period Ta and then goes to a low level. In this way, the transistor 102 remains on during the period Tb. Therefore, during the period Tb during which the potential of the wiring 12 is fluctuating, The potential VSS of the wiring 13 is continuously supplied to the node N1. This can prevent the accompanying fluctuation in the potential of the node N1.

[0051] When a load is connected to the wiring 12, the load is driven by the transistor 101. Therefore, the W / L ratio of the transistor 101 is larger than the W / L ratio of the transistor 102. It is preferable that

[0052] Note that a transistor may be used as the capacitor 110. In this case, The gate is connected to the node N1, and the first terminal and / or the second terminal of the transistor is connected to the wiring 1. 2. That is, the capacitance element 110 is preferably connected to the semiconductor a semiconductor layer, a gate electrode connected to the node N1, and a gate insulator between the semiconductor layer and the gate electrode; In this way, the potential of the node N1 decreases during the period Ta. When this is done, the capacitance value between the node N1 and the wiring 12 can be increased.

[0053] The first terminal of the transistor 102 is connected to the wiring 13, and the second terminal is connected to the node N 1 may be replaced with a switching element connected to the

[0054] The high level potential of the signal SP may be lower than the potential VDD. Since the amplitude voltage of the SP can be reduced, power consumption can be reduced.

[0055] The low level potential of the signal SP may be lower than the potential VSS. To reliably turn off the transistor 102 even if the transistor 102 is normally on. can be done.

[0056] Next, a sequential circuit using the basic circuit of FIG. 1(A) will be described.

[0057] First, the configuration of the sequential circuit of this embodiment will be described with reference to FIG. The circuit is configured by adding transistors 103 to 105 to the basic circuit of FIG. is.

[0058] Note that the transistors 101 to 105 preferably have the same conductivity type. In this embodiment, the case where these transistors are N-channel transistors will be described. .

[0059] The first terminal of the transistor 103 is connected to the wiring 13, and the second terminal of the transistor 103 is connected to the wiring 13. The terminal of the transistor 103 is connected to a wiring 12, and the gate of the transistor 103 is connected to a node N1.

[0060] The first terminal of the transistor 104 is connected to the wiring 13, and the second terminal of the transistor 104 is connected to the wiring 13. The gate of transistor 104 is connected to node N1.

[0061] The first terminal of the transistor 105 is connected to the wiring 15, and the second terminal of the transistor 105 is connected to the wiring 15. The transistor 105 has a gate connected to a node N1, and a gate connected to a wiring 16.

[0062] The potential VDD is supplied to the wiring 15 (also called a power supply line). has the function of supplying

[0063] A signal RE is input to the wiring 16 (also called a signal line), and the wiring 16 transmits the signal RE. The signal RE is a signal that has a high level and a low level. The signal RE is a signal that controls the on / off of the transistor 105. RE is a reset pulse input to the shift register circuit, or a reset pulse input to the shift register circuit one or more stages later. This signal corresponds to the output signal of a sequential circuit.

[0064] The transistor 103 has a function of controlling conduction or non-conduction between the wiring 13 and the wiring 12 . The transistor 103 has a function of supplying the potential VSS of the wiring 13 to the wiring 12 .

[0065] The transistor 104 has a function of controlling conduction or non-conduction between the wiring 13 and the node N2. The transistor 104 has a function of supplying the potential VSS of the wiring 13 to the node N2. do.

[0066] The transistor 105 has a function of controlling conduction or non-conduction between the wiring 15 and the node N1. The transistor 105 has a function of supplying the potential VDD of the wiring 15 to the node N1. do.

[0067] Next, the operation of the sequential circuit of FIG. 3 will be described with reference to the timing chart of FIG.

[0068] The high level potentials of the signals CK, SP, and RE are the potential VDD, and the low level The explanation will be given assuming that the potential of the bell is the potential VSS.

[0069] The initial potential of the node N1 is the potential VDD, and the initial potential of the node N2 is the potential VS The following description will be given assuming that the potential of the node N2 is S and the initial potential of the wiring 12 is VSS. Since the initial potential of the transistor 101 is the potential VSS, the transistor 101 is initially off. There are.

[0070] For convenience, the period required for operation is divided into periods Ta, Tb, Tc, and Td. explain.

[0071] First, during a period Ta, the signal SP goes high and the signal RE goes low. When the signal CK goes low, the transistor 105 is turned on. When the signal SP goes high, the transistor 102 turns on. When the transistor 102 is turned on, the potential VSS of the wiring 13 is supplied to the node N1. As a result, the potential of the node N1 drops to the potential VSS. The transistor 103 and the transistor 104 are turned off. Therefore, the potential of the node N2 is maintained at the potential VSS. Therefore, transistor 101 remains off.

[0072] When the potential of the node N1 is decreasing, the capacitor 110 is connected to the node N1 and the wiring 12. The potential difference between the transistor 101 and the transistor 103 is maintained. Therefore, the wiring 12 is in a floating state. As a result, the potential of the wiring 12 drops from the potential VSS. For example, if the potential becomes lower than the potential obtained by subtracting the threshold voltage of the transistor 101 from the potential VSS, the transistor When the transistor 101 is turned on, the signal CK on the wiring 11 is is supplied to the wiring 12. Since the signal CK is at a low level, the potential of the wiring 12 rises. At this time, the transistor 101 holds the potential difference between the node N2 and the wiring 12. Since the transistor 104 is turned off, the node N2 is in a floating state. Therefore, the potential of the node N2 rises as the potential of the wiring 12 rises. is the sum of the potential of the wiring 11 (for example, the potential VSS) and the threshold voltage of the transistor 101. If the potential of the wiring 12 exceeds The potential rises to the potential VSS, that is, the signal OUT becomes low level.

[0073] Next, during a period Tb, the signal SP goes low, and the signal RE remains low. The signal RE remains low, so the transistor 105 remains off. Also, since the signal SP is at a low level, the transistor 10 2 is turned off. Therefore, the node N1 is in a floating state, and the potential of the node N1 is Since the potential is maintained at becomes.

[0074] Here, since the transistor 101 remains on, the signal CK on the wiring 11 Since the signal CK is at a high level, the potential of the wiring 11 remains At this time, the transistor 101 maintains the potential difference between the node N2 and the wiring 12. Since the transistor 104 is off, the node N2 is floating. Therefore, as the potential of the wiring 12 rises, the potential of the node N2 rises. The potential of the wiring 11 (for example, the potential VDD) and the threshold voltage of the transistor 101 are equal to each other. If the potential exceeds the potential at which the wiring The potential of the terminal 12 rises to the potential VDD, that is, the signal OUT goes high.

[0075] Next, during a period Tc, the signal SP remains at a low level, and the signal RE goes to a high level. The signal SP remains at a low level, so the transistor The transistor 102 remains off. Also, the signal RE goes high. When the transistor 105 is turned on, the potential VDD of the wiring 15 is changed to As a result, the potential at node N1 rises. The potential of the gate of the transistor 105 (for example, the potential VDD) is changed to the threshold voltage of the transistor 105. When the potential at node N1 rises to the voltage lower than the voltage at node N1, transistor 105 is turned off. The potential of the node N1 is kept at a high potential. When rises, transistor 103 and transistor 104 turn on. When the node N104 is turned on, the potential VSS of the wiring 13 is supplied to the node N2. When the potential of the node N2 drops to the potential VSS, When the transistor 103 is turned on, the wiring 1 The potential VSS of the line 12 is supplied to the line 12. Therefore, the potential of the line 12 drops to the potential VSS. In other words, the signal OUT becomes low level.

[0076] Next, during a period Td, the signal SP remains at a low level, and the signal RE goes low. The signal CK alternates between high and low levels, and the signal SP remains at low level. Therefore, the transistor 102 remains off. Also, the signal RE becomes low level. Therefore, transistor 105 remains off. Since node N1 remains in a floating state, node N1 voltage Since the potential is maintained at the potential in the period Tc, the transistor 103 and the transistor 10 4 remains on. When the transistor 104 remains on, the potential VS of the wiring 13 Therefore, the potential of the node N2 remains at the potential VSS. This causes transistor 101 to remain off, and transistor 103 to remain on. When the potential VSS of the wiring 13 is applied to the wiring 12, the potential VSS of the wiring 13 remains applied to the wiring 12. 2 remains at the potential VSS, that is, the signal OUT remains at the low level.

[0077] In the sequential circuit of FIG. 3, the potential of the wiring 12 is lower than the potential VSS during the period Ta. The source and drain of the transistor 103 can be reversed. This can suppress the deterioration of the capacitor 103.

[0078] Moreover, the sequential circuit of FIG. 3 can achieve the same effects as the basic circuit described above.

[0079] When a load is connected to the wiring 12, the load is connected to the transistor 101 and the transistor 103. Therefore, the W / L ratio of transistor 101 is 2. It is preferable that the W / L ratio is larger than that of the transistors 104 and 105. The W / L ratio of the transistor 103 is the same as that of the transistors 102, 104, and It is preferable that the W / L ratio is larger than that of the transistor 105 .

[0080] Note that both the transistor 101 and the transistor 103 supply charge to the wiring 12. However, the Vgs of the transistor 101 during the period Tb is Therefore, the W / L ratio of the transistor 101 is It is preferable that the W / L ratio is larger than that of the resistor 103.

[0081] Note that both the transistor 102 and the transistor 105 supply charge to the node N1. However, while the Vgs of the transistor 102 during the period Ta is maintained at a large value, During the period Tc, the Vgs of the transistor 105 gradually decreases. The W / L ratio of transistor 105 is preferably greater than the W / L ratio of transistor 102 .

[0082] The W / L ratio of the transistor 102 is greater than the W / L ratio of the transistor 104. is preferred.

[0083] The high level potential of the signal RE may be higher than the potential VDD. At Tc, the transistor 105 can be prevented from turning off. The potential of the node N1 can be raised to the potential VDD.

[0084] The low level potential of the signal RE may be lower than the potential VSS. To reliably turn off the transistor 105 even if the transistor 105 is normally on. can be done.

[0085] Note that a potential lower than the potential VDD may be supplied to the wiring 15.

[0086] The first terminal of the transistor 103 is connected to the wiring 13, and the second terminal of the transistor 103 is connected to the wiring 12. may be replaced with a switching element connected to

[0087] The transistor 104 has a first terminal connected to the wiring 13 and a second terminal connected to the node N 2 may be replaced with a switching element connected to

[0088] The transistor 105 has a first terminal connected to the wiring 15 and a second terminal connected to the node N 1 may be replaced with a switching element connected to the

[0089] Next, a shift register circuit using the sequential circuit of FIG. 3 will be described.

[0090] First, the configuration of the shift register circuit of this embodiment will be described with reference to FIG. The shift register circuit of FIG. 5 has a sequential circuit 100 with N stages (N is a natural number). 5, for convenience, the sequential circuits 100 of the first to third stages (sequential Only sequential circuits 100[1] to 100[3] are shown.

[0091] The shift register circuit includes N wirings 21 (shown as wirings 21[1] to 21[N]), The wiring 22, the wiring 23, and the wiring 24 are connected. Specifically, i (i is any of 2 to N-1) In the sequential circuit 100 of the first stage, the first terminal of the transistor 101 is connected to the wiring 22 or is connected to the wiring 23, the second terminal of the transistor 101 is connected to the wiring 21[i], The gate of the transistor 102 is connected to the wiring 21[i-1], and the gate of the transistor 105 is connected to the wiring 21[i-2]. The port is connected to the wiring 21[i+1].

[0092] The connection relationship of the first stage sequential circuit 100 is the same as the connection relationship of the i-th stage sequential circuit 100. However, since the sequential circuit 100 is not provided in the previous stage, the gate of the transistor 102 Therefore, in the first stage sequential circuit 100, the gate of the transistor 102 is It is connected to line 24.

[0093] The connection relationship of the Nth stage sequential circuit 100 is the same as the connection relationship of the ith stage sequential circuit 100. However, since the sequential circuit 100 is not provided in the subsequent stage, the gate of the transistor 105 Therefore, in the Nth stage sequential circuit 100, the gate of the transistor 105 is In the N-th stage sequential circuit 100, the transistor 105 is connected to the line 24. The gate is connected to the wiring to which the reset pulse is input, and the gate is connected to the wiring provided in the subsequent stage of the Nth stage sequential circuit 100. It may also be connected to the output of a Mie circuit.

[0094] In the odd-numbered sequential circuit 100, the first terminal of the transistor 101 is connected to the wiring 22. When the first and second wirings 23 are connected to each other, the transistors 101, 102, 103 in the even-numbered sequential circuits 100 A first terminal of the sir 101 is connected to the other of the wiring 22 and the wiring 23 .

[0095] The signal SOUT is output from the wiring 21 (also called a signal line), and the signal SO In the sequential circuit 100 at the i-th stage, the i-th The (i-1)th wire 21 corresponds to the wire 12, and the (i-1)th wire 21 corresponds to the wire 14. The (i+1)th wire 21 corresponds to the wire 16. The signal SOUT output from the wiring 21 is a signal corresponding to the signal OUT, and the (i-1)th wiring The signal SOUT output from the wiring 21 is a signal corresponding to the signal SP, and The signal SOUT output from the wiring 21 is a signal corresponding to the signal RE.

[0096] A signal SCK is input to the wiring 22 (also called a signal line). In addition, the sequential circuit 100 in either the odd-numbered stage or the even-numbered stage has a function of transmitting or supplying. In this example, the wiring 22 corresponds to the wiring 11, and the signal SCK corresponds to the signal CK. It's a signal.

[0097] The signal SCKB is input to the wiring 23 (also called a signal line), and the wiring 23 is connected to the signal SCK The other sequential circuit 10 in the odd-numbered stage and the other sequential circuit 10 in the even-numbered stage has a function of transmitting or supplying B. In the example shown in FIG. 1, the line 23 corresponds to the line 11, and the signal SCKB corresponds to the signal CK. The signal SCKB is an inverted signal of the signal SCK, or an inverted signal of the signal SCK. The signals are out of phase.

[0098] A signal SSP is input to the wiring 24 (also called a signal line). In the first stage sequential circuit 100, the wiring 24 This is a wiring corresponding to the wiring 14, and the signal SSP is a wiring corresponding to the signal SP.

[0099] The shift register circuit of FIG. 5 has the same effect as the basic circuit or sequential circuit described above. can be done.

[0100] In the sequential circuit 100 at the i-th stage, the gate of the transistor 102 is connected to the (i-2)th transistor. It may be connected to the wire 21 or the i-3rd wire 21.

[0101] In the sequential circuit 100 at the i-th stage, the gate of the transistor 105 is connected to the (i+2)th transistor. It may be connected to the line 21 or the (i+3)th line 21.

[0102] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0103] (Embodiment 2) In this embodiment, a basic circuit provided with a buffer circuit and a sequential circuit using the basic circuit are We will explain about this.

[0104] First, the configuration of the basic circuit of this embodiment will be described with reference to FIG. The basic circuit of A) has a configuration in which a transistor 201 is provided in the basic circuit of FIG.

[0105] Note that the transistor 201 preferably has the same conductivity type as the transistor 101 . In this embodiment, a case where these transistors are N-channel transistors will be described.

[0106] The first terminal of the transistor 201 is connected to the wiring 11, and the second terminal of the transistor 201 is connected to the wiring 11. The gate of the transistor 201 is connected to the wiring 31, and the gate of the transistor 201 is connected to the gate of the transistor 101. Connected.

[0107] The transistor 201 has a function of controlling conduction or non-conduction between the wiring 11 and the wiring 31 . The transistor 201 also has a function of supplying a signal CK from the wiring 11 to the wiring 31. In addition, the transistor 201 has a function of holding the potential difference between the wiring 31 and the node N2.

[0108] A signal BOUT is output from the wiring 31 (also called a signal line). The signal BOUT has a high level and a low level. The signal BOUT is the output signal of the basic circuit shown in FIG. OUT is one of the multiple output signals output from the shift register circuit, or a sequential circuit This signal corresponds to the output signal of

[0109] Next, a method for driving the basic circuit of FIG. 6(A) will be described.

[0110] Note that the description of the driving method common to that of the basic circuit of FIG. 1(A) will be omitted.

[0111] Further, the description will be given assuming that the initial potential of the wiring 31 is the potential VSS.

[0112] For convenience, if the potential of the node N2 becomes a potential at which the transistor 101 is turned on, The following description will be given assuming that the transistor 201 is also turned on.

[0113] First, during the period Ta, the potential of the node N2 is equal to the potential of the wiring 11 (for example, the potential VSS). The potential exceeds the sum of the threshold voltage of the transistor 20 and the potential of the transistor 101. 1 is turned on, the signal CK on the wiring 11 is supplied to the wiring 31. The signal CK is low level. Therefore, the potential of the wiring 31 remains at the potential VSS. It becomes a high level.

[0114] Next, during the period Tb, the potential of the node N2 becomes equal to the potential of the wiring 11 (for example, the potential VDD). The potential exceeds the sum of the threshold voltage of the transistor 20 and the potential of the transistor 101. Since the signal CK on the wiring 11 remains on, the signal CK on the wiring 11 remains supplied to the wiring 31. Since the signal CK is at a high level, the potential of the wiring 31 rises to the potential VDD. The signal BOUT goes high.

[0115] In the basic circuit of FIG. 6A, the potential of the wiring 31 is Therefore, the basic circuit of FIG. can output a more stable signal.

[0116] Moreover, the basic circuit of FIG. 6(A) can achieve the same effect as the basic circuit of the first embodiment. Cut.

[0117] When a load is connected to the wiring 31, the load is driven by the transistor 201. In addition, the load connected to the wiring 31 is often larger than the load connected to the wiring 12. Therefore, the W / L ratio of transistor 201 is larger than the W / L ratio of transistor 101. It is preferable that

[0118] The first terminal of the transistor 101 and the first terminal of the transistor 201 are connected to different terminals. It may be connected to a line.

[0119] Next, a sequential circuit using the basic circuit of FIG. 6(A) will be described.

[0120] First, the configuration of the sequential circuit of this embodiment will be described with reference to FIG. The sequential circuit of B) is the sequential circuit of FIG. 3, except that a transistor 201 and a transistor 202 are added. This is the configuration.

[0121] The transistors 201 and 202 have the same conductivity type as the transistor 101. In this embodiment, when these transistors are N-channel type, This section explains the case.

[0122] The first terminal of the transistor 201 is connected to the wiring 11, and the second terminal of the transistor 201 is connected to the wiring 11. The gate of the transistor 201 is connected to the wiring 31, and the gate of the transistor 201 is connected to the gate of the transistor 101. Connected.

[0123] The first terminal of the transistor 202 is connected to the wiring 13, and the second terminal of the transistor 202 is connected to the wiring 13. The terminal of the transistor 202 is connected to the wiring 31, and the gate of the transistor 202 is connected to the node N1.

[0124] The transistor 202 has a function of controlling conduction or non-conduction between the wiring 13 and the wiring 31 . The transistor 202 has a function of supplying the potential VSS of the wiring 13 to the wiring 31 .

[0125] Next, a method for driving the sequential circuit of FIG. 6(B) will be described.

[0126] Note that explanations of the driving method common to that of the sequential circuit of FIG. 3 will be omitted.

[0127] Further, the initial potential of the wiring 31 is VSS.

[0128] For convenience, if the potential of the node N2 becomes a potential at which the transistor 101 is turned on, The following description will be given assuming that the transistor 201 is also turned on.

[0129] For convenience, if the potential of the node N1 becomes a potential at which the transistor 103 is turned on, The following description will be given assuming that the transistor 202 is also turned on.

[0130] First, during the period Ta, the potential of the node N1 becomes the potential VSS, and the transistor 20 2 is turned off. Also, the potential of the node N2 is transferred to the potential of the wiring 11 (for example, the potential VSS). The potential exceeds the sum of the threshold voltage of transistor 101 and the potential of transistor 102. Since O1 is turned on, the signal CK on the wiring 11 is supplied to the wiring 31. Therefore, the potential of the wiring 31 remains at the potential VSS. It becomes low level.

[0131] Next, during the period Tb, the potential of the node N1 is maintained at the potential during the period Ta, so that The transistor 202 remains off. In addition, the potential of the node N2 is equal to the potential of the wiring 11 (e.g., For example, the potential exceeds the potential obtained by adding the potential VDD and the threshold voltage of the transistor 101. Therefore, the transistor 201 is turned on, and the signal CK on the wiring 11 is supplied to the wiring 31. Since the signal CK is at a high level, the potential of the wiring 31 rises to the potential VDD. That is, the signal BOUT becomes high level.

[0132] Next, in the period Tc, the potential of the node N2 becomes the potential VSS, and the transistor 20 1 is turned off. In addition, the potential of the node N1 rises, and the potential of the gate of the transistor 105 (for example, potential VDD) minus the threshold voltage of the transistor 105. Since the transistor 202 is turned on, the potential of the wiring 13 is supplied to the wiring 31. The potential of the wiring 31 drops to the potential VSS. In other words, the signal BOUT becomes low level. .

[0133] Next, during the period Td, the potential of the node N2 remains at the potential VSS, The potential of the node N1 is maintained at the potential during the period Tc. Therefore, the transistor 202 remains on, and the potential of the wiring 13 is Therefore, the potential of the wiring 31 remains at the potential VSS. , the signal BOUT remains at a low level.

[0134] The sequential circuit of FIG. 6B is the same as the basic circuit described above, the basic circuit of the first embodiment, and the sequential circuit. It can have a variety of effects.

[0135] When a load is connected to the wiring 31, the load is driven by the transistor 201. In addition, the load connected to the wiring 31 is often larger than the load connected to the wiring 12. Therefore, the W / L ratio of transistor 202 is larger than the W / L ratio of transistor 103. It is preferable that

[0136] Note that both the transistor 201 and the transistor 202 supply charge to the wiring 31. However, the Vgs of the transistor 201 during the period Tb is Therefore, the W / L ratio of transistor 201 is It is preferable that the W / L ratio is larger than that of resistor 202.

[0137] The first terminal of the transistor 202 is connected to the wiring 13, and the second terminal of the transistor 202 is connected to the wiring 31. may be replaced with a switching element connected to

[0138] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0139] (Embodiment 3) In this embodiment, a sequential circuit different from that in Embodiments 1 and 2 will be described. .

[0140] First, the sequential circuit of FIG. 7A is the sequential circuit of FIG. 3, except that the second transistor 105 The terminals are connected to wiring 16 .

[0141] In the sequential circuit of FIG. 7A, the wiring 15 and the potential VDD can be omitted.

[0142] In addition, the sequential circuits and shift register circuits described in the first and second embodiments also include The second terminal of the resistor 105 may be connected to the wiring 16 .

[0143] Next, the sequential circuit of FIG. 7B is the sequential circuit of FIG. 3, except that the second transistor 105 The terminals are connected to wiring 17 .

[0144] The signal CKB is input to the wiring 17 (also called a signal line). The signal CKB has a high level and a low level. The signal CKB is one of the multiple clock signals input to the shift register circuit. The signal CKB is an inverted signal of the signal CK, or a signal corresponding to the signal CK. It is a signal that is out of phase with the

[0145] In the sequential circuit of FIG. 7B, the wiring 15 and the potential VDD can be omitted.

[0146] In addition, the sequential circuits and shift register circuits described in the first and second embodiments also include The second terminal of the resistor 105 may be connected to the wiring 17 .

[0147] Next, the sequential circuit of FIG. 8A has a configuration in which a capacitor 301 is provided in the sequential circuit of FIG. .

[0148] A first electrode of the capacitor 301 is connected to the wiring 13, and a second electrode of the capacitor 301 is connected to the node 14. It is connected to node N1.

[0149] The capacitor 301 has a function of holding a potential difference between the wiring 13 and the node N1. The element 301 has a function of maintaining the potential of the node N1.

[0150] During the period Ta, the capacitor 301 is connected to the node N1 when the potential VSS of the wiring 13 is supplied to the node N1. The potential difference between the wiring 13 and the node N1 at this time is maintained.

[0151] During the period Tb, the capacitive element 301 holds the voltage during the period Ta.

[0152] During the period Tc, the capacitor 301 is connected to the node N1 when the potential VDD of the wiring 15 is supplied to the node N1. The potential difference between the wiring 13 and the node N1 at this time is maintained.

[0153] During the period Td, the capacitive element 301 holds the voltage during the period Tc.

[0154] In the sequential circuit of FIG. 8A, the capacitor 301 is connected to the wiring 13 and the node N1 during the period Tb. Since the potential difference between the wiring 12 and the node N1 is maintained, the potential rise of the node N1 due to the rise of the potential of the wiring 12 is suppressed. It can be suppressed.

[0155] During the period Td, the capacitor 301 holds the potential difference between the wiring 13 and the node N1. Therefore, fluctuations in the potential of the node N1 can be suppressed.

[0156] Note that the connection destination of the first electrode of the capacitor 301 is not limited to the wiring 13. The first electrode of the terminal 301 may be connected to the wiring 11, the wiring 14, the wiring 15, the wiring 16, or the like. stomach.

[0157] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are A capacitor 301 may also be provided in a capacitor circuit or the like.

[0158] Next, the sequential circuit of FIG. 8B has a configuration in which a transistor 302 is provided in the sequential circuit of FIG. be.

[0159] It is preferable that the transistor 302 has the same conductivity type as the transistor 101. In the embodiment, a case where these transistors are N-channel type will be described.

[0160] The first terminal of the transistor 302 is connected to the wiring 13, and the second terminal of the transistor 302 is connected to the wiring 13. The node N2 is connected to the node N3, and the gate of the transistor 302 is connected to the wiring 16.

[0161] The transistor 302 has a function of controlling conduction or non-conduction between the wiring 13 and the node N2. The transistor 302 has a function of supplying the potential VSS of the wiring 13 to the node N2. do.

[0162] During the periods Ta, Tb, and Td, the signal RE is at a low level. Transistor 302 is turned off.

[0163] During the period Tc, the signal RE goes high. The transistor 302 is turned on, and the potential VSS of the wiring 13 is supplied to the node N2.

[0164] In the sequential circuit of FIG. 8B, the transistor 302 is included, and therefore, This allows the timing at which the potential VSS of the wiring 13 is supplied to the node N2 to be advanced. This allows the timing at which the potential of the node N2 drops to be accelerated, This allows the timing at which the motor 101 turns off to be advanced.

[0165] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are The transistor 302 may also be provided in a transistor circuit or the like.

[0166] The first terminal of the transistor 302 is connected to the wiring 13, and the second terminal is connected to the node N2. may be replaced with a switching element connected to

[0167] Next, the sequential circuit of FIG. 9A has a configuration in which a transistor 303 is provided in the sequential circuit of FIG. be.

[0168] The first terminal of the transistor 303 is connected to the wiring 13, and the second terminal of the transistor 303 is connected to the wiring 13. The terminal of the transistor 301 is connected to a wiring 12, and the gate of the transistor 303 is connected to a wiring 16.

[0169] It is preferable that the transistor 303 has the same conductivity type as the transistor 101. In the embodiment, a case where these transistors are N-channel type will be described.

[0170] The transistor 303 has a function of controlling conduction or non-conduction between the wiring 13 and the wiring 12 . The transistor 303 has a function of supplying the potential VSS of the wiring 13 to the wiring 12 .

[0171] During the periods Ta, Tb, and Td, the signal RE is at a low level. Transistor 303 is turned off.

[0172] During the period Tc, the signal RE goes high. The transistor 303 is turned on, and the potential VSS of the wiring 13 is supplied to the wiring 12 .

[0173] In the sequential circuit of FIG. 9A, the transistor 303 is included, and therefore, This allows the timing at which the potential VSS of the wiring 13 is supplied to the wiring 12 to be advanced. This makes it possible to shorten the fall time of the signal OUT.

[0174] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are The transistor 303 may also be provided in a transistor circuit or the like.

[0175] In particular, in the basic circuit and the sequential circuit described in the second embodiment, the transistor 303 is provided. In this case, the second terminal of the transistor 303 may be connected to the wiring 31. A transistor 303 is provided, and a first terminal thereof is connected to the wiring 13, and a second terminal thereof is connected to the wiring 14. 31 and a transistor whose gate is connected to the wiring 16. For example, the fall time of the signal BOUT can be shortened.

[0176] A first terminal of the transistor 303 is connected to the wiring 13, and a second terminal of the transistor 303 is connected to the wiring 12 or may be replaced with a switching element connected to the wiring 31.

[0177] Next, the sequential circuit of FIG. 9B is configured by adding a transistor 304 to the sequential circuit of FIG. be.

[0178] It is preferable that the transistor 304 has the same conductivity type as the transistor 101. In the embodiment, a case where these transistors are N-channel type will be described.

[0179] The first terminal of the transistor 304 is connected to the wiring 15, and the second terminal of the transistor 304 is connected to the wiring 15. The node N2 is connected to the node N3, and the gate of the transistor 304 is connected to the wiring 14.

[0180] The transistor 304 has a function of controlling conduction or non-conduction between the wiring 15 and the node N2. The transistor 304 has a function of supplying the potential VDD of the wiring 15 to the node N2. After the transistor 304 raises the potential of the node N2, the voltage to the node N2 is It has the function of stopping the supply of load, potential, signal, etc.

[0181] During the period Ta, the signal SP goes to a high level. When the transistor 304 is turned on, the potential VD D is supplied to the node N2. Therefore, the potential of the node N2 rises. The potential of the gate of the transistor 304 (for example, the potential VDD) is changed to the potential of the gate of the transistor 304. When the potential is lower than the threshold voltage, the transistor 304 is turned off. When 4 is turned off, node N2 is left floating.

[0182] During periods Tb, Tc, and Td, the signal SP is at a low level. When it goes low, transistor 304 turns off.

[0183] The sequential circuit in FIG. 9B includes the transistor 304, and therefore, during the period Ta, The potential of the node N2 can be reliably increased. can be turned on automatically.

[0184] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are The transistor 304 may also be provided in a transistor circuit or the like.

[0185] The first terminal of the transistor 304 is connected to the wiring 11, the wiring 14, the wiring 17, or the like. Good too.

[0186] Note that a first terminal of the transistor 304 is connected to the wiring 15 or the wiring 11, and a second terminal may be replaced with a switching element connected to node N2.

[0187] Next, the sequential circuit of FIG. 10A is configured by adding a transistor 305 to the sequential circuit of FIG. is.

[0188] It is preferable that the transistor 305 has the same conductivity type as the transistor 101. In the embodiment, a case where these transistors are N-channel type will be described.

[0189] The first terminal of the transistor 305 is connected to the wiring 16, and the second terminal of the transistor 305 is connected to the wiring 16. The gate of the transistor 305 is connected to the wiring 15. Connected.

[0190] The transistor 305 controls conduction or non-conduction between the wiring 16 and the gate of the transistor 105. The transistor 305 also has a function of transmitting a signal RE from the wiring 16 to the transistor 10. The transistor 305 has a function of supplying a voltage to the gate of the transistor 105. After the potential of the gate is increased, a charge, a signal, a potential, etc. is applied to the gate of the transistor 105. It has the function of stopping the supply of

[0191] During periods Ta, Tb, and Td, the transistor 305 is turned on. When the transistor 305 is turned on, the signal RE on the wiring 16 is supplied to the gate of the transistor 105. Since the signal RE is at a low level, the potential of the gate of the transistor 305 is equal to the potential VS It becomes S.

[0192] During the period Tc, the transistor 305 is turned on. The transistor 305 is turned on. Then, the signal RE on the wiring 16 is supplied to the gate of the transistor 105. Since the transistor 105 is turned off, the potential of the gate of the transistor 105 rises. When the potential at the gate rises, transistor 105 turns on. When the potential Vdd of the wiring 15 is turned on, the potential of the node N1 is supplied to the node N1, and the potential of the node N1 rises. In addition, the potential of the gate of the transistor 105 is equal to the potential of the gate of the transistor 305 (for example, For example, when the potential is a potential obtained by subtracting the threshold voltage of the transistor 305 from the potential VDD, the transistor Therefore, the gate of the transistor 105 is in a floating state. At this time, the gate of the transistor 105 is connected between the gate and the second terminal. Therefore, as the potential at node N1 rises, Therefore, the potential of the gate of the transistor 105 also rises. When the potential exceeds the sum of the potential VDD of the wiring 15 and the threshold voltage of the transistor 105, Therefore, the potential of the node N1 becomes the potential It becomes VDD.

[0193] In the sequential circuit of FIG. 10A, the transistor 305 is included, and therefore, Therefore, the potential of the node N1 can be raised to the potential VDD. The Vgs of the transistor 103 and the transistor 104 can be increased. If the Vgs of the transistor 104 can be increased, the transistors 103 and This allows the transistor 104 to be turned on more reliably.

[0194] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are The transistor 305 may also be provided in a transistor circuit or the like.

[0195] The first terminal of the transistor 305 is connected to the wiring 16, and the second terminal of the transistor 305 is connected to the wiring 16. The gate of the inverter 105 may be replaced with a switching element connected to the gate of the inverter 105 .

[0196] The first electrode is connected to the gate of the transistor 105, and the second electrode is connected to the gate of the transistor 106. A capacitor may be provided connected to the second terminal of the transistor 105. Since the capacitance between the gate and the second terminal of the transistor 05 can be increased, The potential of the gate of 105 can be made higher.

[0197] Note that the gate of the transistor 305 may be connected to the wiring 17.

[0198] Next, the sequential circuit of FIG. 10B is the sequential circuit of FIG. 3 with the transistor 306 and the transistor This configuration includes a star 307.

[0199] The transistors 306 and 307 have the same conductivity type as the transistor 101. In this embodiment, when these transistors are N-channel type, This section explains the case.

[0200] The first terminal of the transistor 306 is connected to the wiring 15, and the second terminal of the transistor 306 is connected to the wiring 15. The gate of the transistor 306 is connected to the wiring 16. Connected.

[0201] The first terminal of the transistor 307 is connected to the wiring 13, and the second terminal of the transistor 307 is connected to the wiring 13. The gate of the transistor 307 is connected to the wiring 14. Connected.

[0202] The transistor 306 controls conduction or non-conduction between the wiring 15 and the gate of the transistor 105. The transistor 306 has a function of supplying the potential VDD of the wiring 15 to the transistor 1. The transistor 306 has a function of supplying a voltage to the gate of the transistor 105. After raising the potential of the gate of the transistor 105, a charge, potential or signal It has the function of stopping the supply of

[0203] The transistor 307 controls conduction or non-conduction between the wiring 13 and the gate of the transistor 105. The transistor 307 has a function of supplying the potential VSS of the wiring 13 to the transistor 1. It has the function of supplying to gate 05.

[0204] During the period Ta, the signal SP goes high and the signal RE goes low. When E goes low, the transistor 306 is turned off. When transistor 307 is turned on, the The potential VSS of the line 13 is supplied to the gate of the transistor 105. The potential of the gate of the transistor 105 becomes the potential VSS, and the transistor 105 is turned off.

[0205] During the period Tb, the signal SP goes low and the signal RE remains low. When the signal SP goes low, the transistor 306 is turned off. If the transistor 307 remains at a low level, it will remain off. When both transistor 306 and transistor 307 are turned off, the gate of transistor 105 Therefore, the potential of the gate of the transistor 105 is maintained at the potential VSS. Therefore, transistor 105 remains off.

[0206] During the period Tc, the signal SP remains at a low level, and the signal RE goes to a high level. When the signal SP remains low, the transistor 307 remains off. When the signal RE goes high, the transistor 306 turns on. When the transistor 105 is turned on, the potential VDD of the wiring 15 is supplied to the gate of the transistor 105. The potential at the gate of transistor 105 rises. When the transistor 105 is turned on, the wiring 15 The potential VDD of the transistor N1 is supplied to the node N1, and the potential of the node N1 rises. The potential of the gate of the transistor 105 is changed from the potential of the gate of the transistor 306 (for example, the potential VDD) When the potential is lower than the threshold voltage of the transistor 306, the transistor 306 is turned off. Therefore, the gate of the transistor 105 is in a floating state. Between the gate of the transistor 105 and the second terminal, there is a transistor between the gate of the transistor 105 and the node N1. Therefore, as the potential at node N1 rises, the transistor 10 The potential of the gate of the transistor 105 also rises. If the potential exceeds the sum of D and the threshold voltage of the transistor 105, Therefore, the potential of the node N1 becomes the potential VDD.

[0207] During the period Td, the signal SP remains at the low level, and the signal RE goes low. When signal SP remains low, transistor 306 remains off. When the signal RE goes low, the transistor 307 is turned off. When both transistor 306 and transistor 307 are turned off, the gate of transistor 105 Therefore, the potential of the gate of the transistor 105 is in a floating state. , so that transistor 105 remains on.

[0208] The sequential circuit of FIG. 10B includes a transistor 306 and a transistor 307. As a result, the potential of the node N1 can be increased to the potential VDD during the period Tc. Therefore, the Vgs of the transistors 103 and 104 can be increased. If the Vgs of the transistors 103 and 104 can be increased, This makes it possible to turn on the transistor 103 and the transistor 104 more reliably.

[0209] Also, during the period Td, the transistor 105 can be kept on. Since the potential VDD of the wiring 15 can be continuously supplied to the node N1, the potential of the node N1 It is possible to maintain a stable position.

[0210] The basic circuits, sequential circuits, and shift registers described in the first and second embodiments and this embodiment are The transistor 306 and the transistor 307 may also be provided in a transistor circuit or the like.

[0211] The first terminal of the transistor 306 is connected to the wiring 15, and the second terminal of the transistor 306 is connected to the wiring 15. The gate of the inverter 105 may be replaced with a switching element connected to the gate of the inverter 105 .

[0212] The first terminal of the transistor 307 is connected to the wiring 13, and the second terminal of the transistor 307 is connected to the wiring 13. The gate of the inverter 105 may be replaced with a switching element connected to the gate of the inverter 105 .

[0213] Note that the first terminal of the transistor 306 may be connected to the wiring 16, the wiring 17, or the like.

[0214] Next, the sequential circuit of FIG. 11A has a configuration in which a circuit 308 is provided in addition to the sequential circuit of FIG.

[0215] A first terminal of the circuit 308 is connected to the node N1, and a second terminal of the circuit 308 is connected to the transistor The gate of the inverter 104 is connected to the inverter 104 .

[0216] The circuit 308 has a function of outputting the potential or signal of the first terminal from the second terminal. The circuit 308 also controls the potential of the first terminal or the rise time of the signal and / or The circuit 3 has the function of outputting a signal with a longer fall time from the second terminal. 08 has the function of outputting the delayed potential or signal of the first terminal from the second terminal. do.

[0217] During the period Ta, the potential of the wiring 12 drops as the potential of the node N1 drops. At this time, the potential of the gate of the transistor 104 lags behind or is slower than the potential of the node N1. Therefore, the potential VSS of the wiring 13 decreases. is supplied to the gate of transistor 101. Then, the gate of transistor 104 The potential at node 104 drops, turning transistor 104 off.

[0218] During the period Tc, the potential of the node N1 rises. The potential at node N1 rises later or more slowly than the potential at node N2. Then, the potential of the gate of transistor 104 rises, and transistor Therefore, the potential VSS of the wiring 13 is applied to the gate of the transistor 101. , turning transistor 101 off.

[0219] During the periods Tb and Td, the potential of the node N1 does not rise or fall significantly. The sequential circuit of FIG. 11(A) operates in the same manner as the sequential circuit of FIG.

[0220] In the sequential circuit of FIG. 11A, when the potential of the wiring 12 is decreasing in the period Ta, Therefore, the potential VSS of the wiring 13 can be supplied to the node N2. This can prevent the potential at node N2 from dropping as the potential at node N2 drops. If the drop in the potential of node N1 can be prevented, the potential of node N2 can be made higher. Therefore, the Vgs of the transistor 101 can be made larger.

[0221] In addition, during the period Tc, the timing at which the transistor 101 is turned off can be delayed. Therefore, the signal CK of the wiring 11 can be supplied to the wiring 12. Since it is a bell, the fall time of the signal OUT can be shortened. Since the W / L ratio of the 101 is often large, the fall time of the signal OUT can be significantly shortened. It can be made easier.

[0222] Here, a specific example of the circuit 308 will be described.

[0223] The circuit 308 in FIG. 11B includes a transistor 308a. The first terminal of the transistor 308a is connected to the first terminal of the circuit 308, and the second terminal of the transistor 308a is connected to the The gate of the transistor 308a is connected to the wiring 11. can be.

[0224] The circuit 308 in FIG. 11C is the same as the circuit 308 in FIG. 11B except that a transistor 308b is provided. The first terminal of the transistor 308b is connected to the first terminal of the circuit 308. The second terminal of the transistor 308b is connected to the second terminal of the circuit 308. The gate of the transistor 308b is connected to the second terminal of the circuit 308.

[0225] The circuit 308 in FIG. 11D is the same as the circuit 308 in FIG. 11B except that a transistor 308c is provided. The first terminal of the transistor 308c is connected to the wiring 11. The second terminal of the transistor 308c is connected to the second terminal of the circuit 308, and the gate of the transistor 308c is The port is connected to a first terminal of the circuit 308 .

[0226] The circuit 308 in FIG. 11E is the circuit 308 in FIG. 11B, except that a transistor 308d and a transistor 308e are added. The first terminal of the transistor 308d is connected to the wiring 11. and the second terminal of the transistor 308d is connected to the second terminal of the circuit 308. The first terminal of the transistor 308e is connected to the first terminal of the circuit 308. The second terminal of transistor 308e is connected to the gate of transistor 308d. The gate of 8e is connected to wiring 11.

[0227] In the circuit 308 of FIG. 11E, the potential of the gate of the transistor 308d is set higher than the potential VDD. Therefore, the potential of the second terminal of the circuit 308 can be raised to the potential VDD. It can be raised.

[0228] Note that the transistors 308a to 308e have the same conductivity as the transistor 101. Preferably, it is of the electrolytic type.

[0229] The gate of the transistor 308a, the first terminal of the transistor 308c, The first terminal of the transistor 308d and / or the gate of the transistor 308e are connected to the wiring 17, etc. You may do so.

[0230] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0231] (Fourth embodiment) Taking an EL display device as an example, the cross-sectional structure of a pixel and a driving circuit of a display device according to one embodiment of the present invention will be described. The structure will be described with reference to FIG. 12. FIG. 12 shows a cross-sectional view of a pixel 840 and a driving circuit 841. is shown as an example.

[0232] The pixel 840 includes a light emitting element 832 and a transistor that has a function of supplying current to the light emitting element 832. The pixel 840 includes a light-emitting element 832 and a transistor 831. In addition, a transistor for controlling the input of an image signal to the pixel 840 and a transistor for controlling the potential of the image signal It may also have various semiconductor elements such as a capacitor element for holding the signal.

[0233] The driving circuit 841 controls the transistor 830 and maintains the gate voltage of the transistor 830. The driver circuit 841 includes the basic circuit of the first to third embodiments, Specifically, the transistor 830 corresponds to a transistor The driver circuit 841 corresponds to the transistor 101 or the transistor 201. In addition to the resistor 830 and the capacitor 833, various semiconductors such as transistors and capacitors are The semiconductor device may have an element.

[0234] The transistor 831 is formed on a substrate 800 having an insulating surface, and a conductive film serving as a gate is formed on the substrate 800. 816, the gate insulating film 802 on the conductive film 816, and the conductive film 816 at a position overlapping the gate insulating film 802. A semiconductor film 817 located on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 are located over the semiconductor film 817. The film 816 also functions as a scan line.

[0235] The transistor 830 is formed on a substrate 800 having an insulating surface, and a conductive film serving as a gate is formed on the substrate 800. 812, the gate insulating film 802 on the conductive film 812, and the conductive film 812 at a position overlapping the gate insulating film 802. A semiconductor film 813 located on the gate insulating film 802 and a source terminal or a drain terminal The semiconductor film 813 functions as a conductive film 814 and a conductive film 819 .

[0236] The capacitor 833 is formed by forming a conductive film 812 over a substrate 800 having an insulating surface. The gate insulating film 802 and the conductive film 812 are overlapped with each other. The conductive film 819 is placed on the substrate 811.

[0237] An insulating film 820 is formed over the conductive film 814, the conductive film 815, the conductive film 818, and the conductive film 819. and an insulating film 821 are stacked in this order. A conductive film 822 that functions as an anode is provided on the insulating film 820. and is connected to the conductive film 818 through a contact hole 823 formed in the insulating film 821. It is being done.

[0238] In addition, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 82 An EL layer 825 and a conductive layer 826 are provided on a part of the conductive film 822 and the insulating film 824. A conductive film 826 that functions as a cathode is provided so as to be stacked in this order. The region where the EL layer 825 and the conductive film 826 overlap corresponds to the light emitting element 832. do.

[0239] Note that in one embodiment of the present invention, the transistors 830 and 831 are amorphous, Semiconductors such as silicon or germanium, which may be crystalline, polycrystalline, or single crystalline, are used for the semiconductor film. Alternatively, a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. It may be possible.

[0240] The semiconductor films of the transistors 830 and 831 may be amorphous, microcrystalline, polycrystalline, or When a semiconductor such as silicon or germanium is used, it is necessary to add one conductivity. The semiconductor film is doped with an impurity element that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, An impurity region having n-type conductivity can be formed. By adding it to a semiconductor film, an impurity region having p-type conductivity can be formed.

[0241] When an oxide semiconductor is used for the semiconductor films of the transistors 830 and 831, In this case, a dopant is added to the semiconductor film to function as a source terminal or a drain terminal. The dopant may be added by ion implantation. Dopants include rare gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 elements such as arsenic and antimony can be used. For example, nitrogen can be used as a dopant. When used as a substrate, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 1x or more 10 22 / cm 3 It is desirable that the following:

[0242] Silicon semiconductors are grown by vapor deposition methods such as plasma CVD or sputtering. Amorphous silicon produced by the laser annealing method, and amorphous silicon The surface layer is formed by implanting hydrogen ions into polycrystalline silicon and single crystal silicon wafers. For example, single crystal silicon from which a portion has been peeled off can be used.

[0243] The oxide semiconductor film is made of at least one material selected from the group consisting of In, Ga, Sn, and Zn. For example, the oxide of a quaternary metal, In-Sn-Ga-Zn-O, is In-Ga-Zn-O oxide semiconductors, which are oxides of ternary metals, and In-S n-Zn-O based oxide semiconductor, In-Al-Zn-O based oxide semiconductor, Sn-Ga-Zn -O-based oxide semiconductors, Al-Ga-Zn-O-based oxide semiconductors, Sn-Al-Zn-O-based oxide semiconductors oxide semiconductors, binary metal oxides such as In-Zn-O oxide semiconductors, Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O based oxide semiconductors, In-Mg-O based oxide semiconductors, and In-Ga-O based oxide Compound semiconductors, In-O-based oxide semiconductors and Sn-O-based oxide semiconductors, which are oxides of single-component metals In addition, a Zn—O-based oxide semiconductor or the like can be used. Elements other than Ga, Sn, and Zn, such as SiO2, may also be included.

[0244] For example, an In-Ga-Zn-O oxide semiconductor is a semiconductor containing indium (In), gallium (G a) It means an oxide semiconductor containing zinc (Zn), and its composition is not important.

[0245] The oxide semiconductor film has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Zn, Ga, Al, Mn and Co. For example, M may represent Ga, Ga and Al, Ga and Mn, or Examples of the elements include Ga and Co.

[0246] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, The atomic ratio of metal elements is In:Zn=50:1 to 1:2 (converted to molar ratio, InO In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn= 15:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn is within the above range. By keeping the above range, it is possible to improve the mobility.

[0247] In addition, impurities such as water or hydrogen, which act as electron donors (donors), are reduced, and the acid The oxide semiconductor (purified Oxide) is highly purified by reducing the electron vacancies. An i-type semiconductor is an intrinsic semiconductor or is very close to an i-type semiconductor. Therefore, the transistor including the oxide semiconductor has a characteristic of having an extremely low off-state current. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. The concentration of impurities such as moisture and hydrogen is sufficiently reduced. and a highly purified oxide semiconductor film having reduced oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0248] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e., 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current density, which corresponds to the off-state current divided by the transistor channel width, is 100 zA. It can be seen that the capacitance is less than / μm. A circuit that controls the charge flowing into or out of a capacitance element using the transistor is used. The current density was measured using a highly purified oxide semiconductor. A conductive film is used in the channel formation region, and the amount of charge per unit time of the capacitance element is measured. The off-state current density of the transistor was measured. As a result, the source terminal and drain terminal of the transistor When the voltage between the terminals is 3 V, an even lower off-state current density of several tens of yA / μm is obtained. Therefore, it was found that the high-purity oxide semiconductor film was used for the channel formation region. The off-state current of the transistor is significantly lower than that of a transistor using crystalline silicon. Very low.

[0249] Unless otherwise specified, the off-state current in this specification refers to the off-state current in an n-channel transistor. In this case, when the drain terminal is at a higher potential than the source terminal and gate, When the potential of the gate is 0 or less relative to the potential of the transistor, the source terminal and drain The off-state current in this specification refers to the current that flows between the terminals of a p-channel In a transistor with a drain terminal at a lower potential than the source terminal and gate, In this state, when the potential of the gate is 0 or more with respect to the potential of the source terminal, It refers to the current that flows between the source and drain terminals.

[0250] For example, the oxide semiconductor film may contain In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When the Zn-based oxide semiconductor film is formed by sputtering, it is preferable that the atomic ratio of In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or An In-Ga-Zn oxide target with an atomic ratio of 3:1:4 is used. an oxide semiconductor film is formed using an In-Ga-Zn oxide target having This makes it easier for polycrystals or CAAC, which will be described later, to form.

[0251] The filling rate of the target containing In, Ga, and Zn is preferably 90% or more and 100% or less. The filling rate is 95% or more and less than 100%. The deposited oxide semiconductor film becomes a dense film.

[0252] Specifically, the oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state. The remaining moisture in the processing chamber is removed, and the sputtering gas from which hydrogen and moisture have been removed is introduced. During film formation, the substrate temperature is preferably 100°C or higher and 600°C or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. This allows the concentration of impurities contained in the formed oxide semiconductor film to be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a displacement pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the vacuum chamber. Then, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon Since the exhaust gas contains oxygen (including compounds containing hydrogen atoms), the oxide semiconductor film formed in the treatment chamber is The concentration of impurities contained in the material can be reduced.

[0253] Note that the oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen ( The water or hydrogen atoms form donor levels. Therefore, in one embodiment of the present invention, To reduce impurities such as water or hydrogen in semiconductor films (dehydration or dehydrogenation) , an oxide semiconductor film is heated under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an acid atmosphere. under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The heat treatment is carried out in an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less. To administer.

[0254] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen in the oxide semiconductor film is released. Specifically, the substrate temperature is 250° C. or higher and 750° C. or lower, preferably 400° C. or higher. For example, the heat treatment may be performed at 500°C for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be carried out in a short time. Therefore, processing can be performed at temperatures exceeding the strain point of the glass substrate.

[0255] Note that the heat treatment causes oxygen to be released from the oxide semiconductor film and oxygen to be left in the oxide semiconductor film. Therefore, in one embodiment of the present invention, a gate electrode in contact with the oxide semiconductor film is An insulating film containing oxygen is used as an insulating film such as a gate insulating film. After the insulating film is formed, heat treatment is performed, whereby oxygen is supplied from the insulating film to the oxide semiconductor film. With the above structure, oxygen vacancies that serve as donors are reduced, and oxygen atoms contained in the oxide semiconductor film are The oxide semiconductor film can have a stoichiometric composition. It is preferable that the oxide semiconductor film contains oxygen in an amount exceeding the stoichiometric composition. This reduces variations in the electrical characteristics of transistors due to oxygen vacancies. This reduces the capacitance and improves the electrical characteristics.

[0256] Note that the heat treatment for supplying oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or dilute In a gas (argon, helium, etc.) atmosphere, preferably at 200°C to 400°C The temperature is, for example, 250°C or higher and 350°C or lower. It is desirable that the concentration is not more than 1 ppm, and more preferably not more than 10 ppb.

[0257] Note that the oxide semiconductor film may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0258] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0259] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0260] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 5° or more and 5° or less.

[0261] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0262] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0263] Transistors using CAAC-OS films show fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0264] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0265] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b Peels off as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0266] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0267] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal from collapsing due to impurities. For example, reducing the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at 0° C. or below, preferably −100° C. or below, is used.

[0268] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0269] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0270] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0271] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. After that, it is heat-treated at a temperature between 1000℃ and 1500℃ to form polycrystalline In-G The target is a-Zn-O compound, where X, Y, and Z are any positive numbers. The predetermined mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 The type of powder and the molar ratio of the powder to be mixed depend on the sputtering temperature to be prepared. You can change it as needed depending on the target.

[0272] Next, an example of a specific structure of a transistor included in a semiconductor device of the present invention will be described. do.

[0273] The transistor shown in FIG. 13A is a bottom-gate transistor with a channel-etched structure.

[0274] The transistor shown in FIG. 13(A) has a gate electrode (gate 1602, a gate insulating film 1603 on the gate electrode 1602, and a gate insulating film 160 3, a semiconductor film 1604 overlapping the gate electrode 1602, and a semiconductor film 1604 The transistor has a conductive film 1605 and a conductive film 1606 formed thereon. The insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606 is , may be included in its components.

[0275] Note that the transistor shown in FIG. 13A has an insulating layer at a position overlapping with the semiconductor film 1604. It may further include a back gate electrode formed on the insulating film 1607.

[0276] The transistor shown in FIG. 13B is a bottom-gate transistor with a channel protection structure.

[0277] The transistor shown in FIG. 13B has a gate electrode 161 formed on an insulating surface. 2, a gate insulating film 1613 on the gate electrode 1612, and a The semiconductor film 1614 overlaps the gate electrode 1612, and the semiconductor film 1614 is formed on the semiconductor film 1614. a channel protective film 1618 formed on the semiconductor film 1614; a conductive film 1615 formed on the semiconductor film 1614; The transistor further includes a channel protection film 1618 and a conductive film 1616. The insulating film 1617 formed on the conductive film 1616 may be included in the components. .

[0278] Note that the transistor shown in FIG. 13B has an insulating layer at a position overlapping with the semiconductor film 1614. It may further include a back gate electrode formed on the insulating film 1617.

[0279] By providing the channel protective film 1618, the channel forming region of the semiconductor film 1614 and In the subsequent process, the film is formed by plasma or etching agent during etching on the part that will be This prevents damage such as wear, thereby improving the reliability of the transistor. can be done.

[0280] The transistor shown in FIG. 13C is a bottom-gate transistor with a bottom-contact structure.

[0281] The transistor shown in FIG. 13C has a gate electrode 162 formed on an insulating surface. 2, a gate insulating film 1623 on the gate electrode 1622, and a conductive film on the gate insulating film 1623. A gate electrode 1622 is formed on the gate insulating film 1623. The semiconductor film 162 overlaps the conductive film 1625 and the conductive film 1626. 4. The transistor further includes a conductive film 1625, a conductive film 1626, and a semiconductor The components may include an insulating film 1627 formed on the film 1624.

[0282] Note that the transistor shown in FIG. 13C has an insulating layer at a position overlapping with the semiconductor film 1624. It may further include a back gate electrode formed on the insulating film 1627.

[0283] The transistor shown in FIG. 13D is a top-gate transistor with a bottom-contact structure.

[0284] The transistor shown in FIG. 13D includes a conductive film 1645 formed on an insulating surface, A conductive film 1646, a semiconductor formed on the insulating surface, the conductive film 1645, and the conductive film 1646 The semiconductor film 1644, the conductive film 1645, and the conductive film 1646 are formed on the semiconductor film 1644. A gate insulating film 1643 and a semiconductor film 1644 overlapping the gate insulating film 1643. The transistor further comprises a gate electrode 1642 formed on the gate electrode 1642. The insulating film 1647 formed on the insulating film 1647 may be included in the components.

[0285] The transistor of this embodiment is used in the basic circuits, sequential circuits, and shift registers of the first to third embodiments. The present invention can be applied to transistors constituting a transistor circuit or the like. A transistor using an oxide semiconductor has a small off-state current. By using it in the basic circuits, sequential circuits, shift register circuits, etc. of the first to third embodiments, This can reduce the charge leaking from the nodes N1 and N2. If the charge leaking from nodes such as N2 can be reduced, the drive frequency can be reduced. can.

[0286] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0287] (Embodiment 5) An example of a panel, which corresponds to one form of a display device, will be described with reference to FIG. The panel includes a substrate 700, a pixel portion 701 on the substrate 700, a signal line driving circuit 702, a scanning line It includes a driving circuit 703 and a terminal 704 .

[0288] The pixel portion 701 has a plurality of pixels, and each pixel has a display element and a control circuit for controlling the operation of the display element. The scanning line driver circuit 703 is provided with one or more transistors for driving each pixel. By controlling the supply of a potential to a scanning line connected to the pixel, the pixel of the pixel portion 701 can be selected. The signal line driver circuit 702 selects an image to be sent to the pixel selected by the scanning line driver circuit 703. Controls the supply of signals.

[0289] One or both of the signal line driver circuit 702 and the scanning line driver circuit 703 may be the same as those in the first to third embodiments. It can include a basic circuit, a sequential circuit, a shift register circuit, etc. The effects described in the first to third embodiments can be achieved, and the pixel portion 701 can be enlarged. In addition, the pixel portion 701 can be provided with many pixels.

[0290] As the display element, a liquid crystal element, a light emitting element, or the like can be used.

[0291] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0292] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras and digital cameras Cameras such as digital still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound reproduction devices (car audio, digital audio players) Years, etc.), copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0293] FIG. 15A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The semiconductor according to one embodiment of the present invention is used in a driver circuit of a portable game machine. By using this device, it is possible to provide a portable game machine with low power consumption and stable operation. The portable game machine shown in FIG. 15A has two display units 5003 and 5004, but the number of display units that the portable game machine has is not limited to this. .

[0294] FIG. 15B shows a display device, which includes a housing 5201, a display portion 5202, a support base 5203, and the like. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a display device, power consumption can be reduced. It is possible to provide a display device with low force and stable operation. All information display devices, such as for personal computers, TV broadcast reception, and advertising displays, Included.

[0295] FIG. 15C shows a notebook personal computer, which includes a housing 5401 and a display portion 5402. , a keyboard 5403, a pointing device 5404, etc. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile computer, power consumption can be reduced. It is possible to provide a notebook-type personal computer that requires less force and operates stably.

[0296] FIG. 15D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 56 5605, and the angle between the first housing 5601 and the second housing 5602 is The first display unit 5603 is connected to the The switching is performed according to the angle between the first housing 5601 and the second housing 5602 at the section 5605. The semiconductor device according to one embodiment of the present invention may be included in a driver circuit of a portable information terminal. By using this, it is possible to provide a portable information terminal with low power consumption and stable operation.

[0297] FIG. 15E shows a mobile phone, which includes a housing 5801, a display portion 5802, an audio input portion 5803, It has an audio output unit 5804, operation keys 5805, a light receiving unit 5806, etc. By converting the light received in the camera into an electrical signal, it is possible to capture an external image. By using a semiconductor device according to one embodiment of the present invention in a driver circuit of a mobile phone, power consumption can be reduced. Therefore, a mobile phone with stable operation can be provided.

[0298] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0299] M1 transistor M3 transistor M7 transistor N1 node N2 node 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 21[i] Wiring 21[i-1] Wiring 21[N] Wiring 21[1] Wiring 22 Wiring 23 Wiring 24 Wiring 31 Wiring 100 sequential circuits 100[1] Sequential circuit 100[3] Sequential circuit 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 110 Capacitor element 201 Transistor 202 Transistor 301 Capacitor element 302 Transistor 303 Transistor 304 Transistor 305 Transistor 306 Transistor 307 Transistor 308 circuits 308a transistor 308b transistor 308c transistor 308d transistor 308e transistor 700 boards 701 Pixel section 702 Signal line driver circuit 703 Scanning line driving circuit 704 terminal 800 boards 802 Gate insulating film 812 Conductive film 813 Semiconductor film 814 Conductive film 815 Conductive film 816 Conductive film 817 Semiconductor film 818 Conductive film 819 Conductive film 820 insulating film 821 insulating film 822 Conductive film 823 Contact Hole 824 insulating film 825 EL layer 826 Conductive film 830 transistors 831 Transistor 832 Light-emitting element 833 Capacitor 840 pixels 841 Drive Circuit 1602 gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 insulating film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display section 5604 Display section 5605 Connection 5606 Operation Key 5801 Housing 5802 Display section 5803 Audio input unit 5804 Audio output unit 5805 Operation key 5806 Light receiving section

Claims

1. a driver circuit including first to sixth transistors and a capacitor; and a pixel portion including a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor element; the other of the source and the drain of the first transistor is electrically connected to a first wiring having a function of supplying a clock signal; a gate of the first transistor electrically connected to one of a source and a drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, one of the source and the drain of the fifth transistor, and one of the source and the drain of the sixth transistor; a gate of the second transistor electrically connected to a gate of the third transistor; one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor and the other electrode of the capacitor element; a gate of the fourth transistor electrically connected to a gate of the sixth transistor; a first conductive layer that functions as a gate electrode of the seventh transistor; a second conductive layer having the same material as the first conductive layer and functioning as the other electrode of the capacitor element; a first insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region overlapping with the second conductive layer with the first insulating layer interposed therebetween and functioning as one electrode of the capacitor element; the third conductive layer functions as one of a source electrode and a drain electrode of the first transistor, a W / L ratio (W is a channel width, L is a channel length) of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the third transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fourth transistor; A semiconductor device, wherein the W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor.

2. a driver circuit including first to sixth transistors and a capacitor; and a pixel portion including a seventh transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one electrode of the capacitor element; the other of the source and the drain of the first transistor is electrically connected to a first wiring having a function of supplying a clock signal; a gate of the first transistor electrically connected to one of a source and a drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, one of the source and the drain of the fifth transistor, and one of the source and the drain of the sixth transistor; a gate of the second transistor electrically connected to a gate of the third transistor; one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor and the other electrode of the capacitor element; a gate of the fourth transistor electrically connected to a gate of the sixth transistor; a first conductive layer that functions as a gate electrode of the seventh transistor; a second conductive layer having the same material as the first conductive layer and functioning as the other electrode of the capacitor element; a first insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; a third conductive layer having a region overlapping with the second conductive layer with the first insulating layer interposed therebetween and functioning as one electrode of the capacitor element; the third conductive layer functions as one of a source electrode and a drain electrode of the first transistor, the first transistor includes an oxide semiconductor layer having a channel formation region, a W / L ratio (W is a channel width, L is a channel length) of the first transistor is greater than a W / L ratio of the second transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the third transistor; a W / L ratio of the first transistor is greater than a W / L ratio of the fourth transistor; A semiconductor device, wherein the W / L ratio of the first transistor is greater than the W / L ratio of the fifth transistor.

3. A semiconductor device according to claim 1 or 2, wherein the W / L ratio of the fourth transistor is greater than the W / L ratio of the fifth transistor.

Images