Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing a parasitic capacitance.SOLUTION: A transistor 10 includes: a first insulation layer 110; a semiconductor layer 120 on the first insulation layer; a source electrode layer 130 and a drain electrode layer 140 on the semiconductor layer; a second insulation layer 173 on the first insulation layer; a second insulation layer; a third insulation layer 175 on the source electrode layer and the drain electrode layer; a gate insulation layer 150 on the semiconductor layer; a gate electrode layer 160 on the gate insulation layer; and a fourth insulation layer 170 on the third insulation layer, the gate insulation layer, and the gate electrode layer. The second insulation layer includes a region contacted to the semiconductor layer, the source electrode layer, and the drain electrode layer on a side surface. An upper surface of the second insulation layer is on a flat surface that is similar to the source electrode layer and the drain electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 11-505377 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements continue to be miniaturized, parasitic capacitance near transistors becomes a major problem.

[0007] During transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, slowing the transistor response. This reduces the performance and, ultimately, the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) are becoming more and more difficult with each advance in miniaturization. It is becoming increasingly difficult to control this, and variations in the manufacturing process affect transistor characteristics, and has a significant impact on reliability.

[0009] Furthermore, with miniaturization, the precision required for processing is becoming stricter, and the difficulty of processing is increasing. It's getting more and more popular.

[0010] Therefore, one embodiment of the present invention aims to reduce parasitic capacitance near a transistor. Another object is to provide a semiconductor device with good electrical characteristics. Another object is to provide a highly reliable semiconductor device. One of the purposes of the present invention is to reduce the variation in characteristics of a capacitor or semiconductor device due to the manufacturing process. Another object is to stabilize the manufacturing process of a transistor. One object of the present invention is to provide a semiconductor device including an oxide semiconductor layer with few oxygen vacancies. Another object of the present invention is to provide a semiconductor device that can be formed through a simple process. Alternatively, a semiconductor having a structure capable of reducing an interface state density in the vicinity of an oxide semiconductor layer may be used. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device or the like. Another object is to provide a method for manufacturing the semiconductor device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device comprising a first insulating layer, a first oxide layer on the first insulating layer, and a first oxide layer. a semiconductor layer on the first insulating layer; a source electrode layer and a drain electrode layer on the semiconductor layer; a second insulating layer, and a third insulating layer on the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer on the semiconductor layer; a gate insulating layer on the second oxide layer; and a gate insulating layer. a gate electrode layer on the layer, a third insulating layer, a second oxide layer, a gate insulating layer, and a gate and a fourth insulating layer on the electrode layer. The second insulating layer is a layer including the first oxide layer, the semiconductor layer, and the silicon dioxide layer. The second insulating layer has a region in contact with the side surfaces of the source electrode layer and the drain electrode layer. , the source electrode layer, and the drain electrode layer, and the second oxide layer is coplanar with the first the oxide layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer; The semiconductor device has a region in contact with the

[0013] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A first mask is formed on the conductive film, and a part of the first conductive film is etched using the first mask. The first conductive layer is formed in an island shape, and a first mask and a second conductive layer are used as a mask. and etching a portion of the first oxide film and the semiconductor film using a A second insulating layer is formed on the first insulating layer and the first conductive layer. and performing chemical mechanical polishing on the second insulating film until the first conductive layer is exposed. A second insulating layer is formed by this, and a third insulating film is formed on the first conductive layer and the second insulating layer. forming a second mask on the third insulating film; and forming a second mask on the third insulating film using the second mask. By partially etching, the source electrode layer, the drain electrode layer, and the third insulating layer are removed. forming an insulating layer and a second oxide film on the semiconductor layer; A fourth insulating film is formed on the first insulating film, a second conductive film is formed on the fourth insulating film, and the second conductive film and the first insulating film are formed on the second insulating film. The insulating film of 4 and the second oxide film are subjected to a chemical mechanical polishing process to form the second oxide layer. a gate insulating layer and a gate electrode layer; .

[0014] In addition, after forming the semiconductor film, a first heat treatment is performed to form the third insulating layer, the second oxide layer, and the gate A fourth insulating layer containing oxygen is formed over the insulating layer and the gate electrode layer, and during the formation of the fourth insulating layer, A mixed layer of the third insulating layer and the fourth insulating layer is formed, and at the same time, the mixed layer or the first insulating layer is formed. It is preferable to add oxygen to the semiconductor layer and then perform a second heat treatment to diffuse the oxygen into the semiconductor layer. stomach.

[0015] The third insulating film is an insulating film containing oxygen, and the fourth insulating layer is an insulating film containing oxygen gas. It is preferable to form the film by sputtering.

[0016] The third insulating film is a silicon oxide film, and the fourth insulating layer is formed by absorbing 50 volumes of oxygen gas. % or more and formed by sputtering using an aluminum oxide target. It is preferable to do so.

[0017] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0018] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A second insulating film is formed on the conductive film, a first mask is formed on the second insulating film, and the first mask is The second insulating film and a part of the first conductive film are etched using a etchant. and a second insulating layer is formed, a second mask is formed on the second insulating layer and the semiconductor film, and a first The second insulating layer, the first conductive layer, the first oxide film, and the semiconductor film are then formed using the second mask. By partially etching, the first oxide layer, the semiconductor layer, the source electrode layer, the drain electrode layer, and the like are removed. An electrode layer and a third insulating layer are formed on the first insulating layer, the third insulating layer, and the semiconductor layer. a second oxide film is formed on the second oxide film, a third insulating film is formed on the second oxide film, and the third insulating film is formed on the third insulating film. A second conductive film is formed on the first conductive film, a third mask is formed on the second conductive film, and a third mask is used to form a second conductive film. and etching a part of the second oxide film, the third insulating film, and the second conductive film. A semiconductor device characterized in that a second oxide layer, a gate insulating layer, and a gate electrode layer are formed by A method for manufacturing a body device.

[0019] After the semiconductor film is formed, a first heat treatment is performed to form the first insulating layer, the third insulating layer, and the gate electrode. A fourth insulating layer containing oxygen is formed on the electrode layer, and when the fourth insulating layer is formed, the first insulating layer and the fourth insulating layer are separated. a first mixed layer made of the first insulating layer and the fourth insulating layer, and a second mixed layer made of the third insulating layer and the fourth insulating layer. At the same time, an oxide is formed in the first mixed layer, the second mixed layer, the first insulating layer, or the second insulating layer. It is preferable to add oxygen and then perform a second heat treatment to diffuse oxygen into the semiconductor layer.

[0020] The first insulating film and the second insulating film are insulating films containing oxygen, and the fourth insulating layer It is preferable that the film is formed by sputtering using oxygen gas.

[0021] The first insulating film and the second insulating film are silicon oxide films, and the fourth insulating layer is an oxide film. Sputtering is performed using 50% or more of nitrogen gas and an aluminum oxide target. It is preferable to form the film by a coating method.

[0022] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0023] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising forming a first insulating layer and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A second insulating film is formed on the conductive film, a third insulating film is formed on the second insulating film, and the third insulating film is formed on the conductive film. A first mask is formed on the film, and a third insulating film and a second insulating film are formed using the first mask. a first conductive film, a semiconductor film, and a first oxide film; The first oxide layer, the semiconductor layer, the second insulating layer, and the third insulating layer are formed in an island shape by the above steps. A fourth insulating film is formed on the first insulating layer and the third insulating layer until the third insulating layer is exposed. The fourth insulating film is subjected to a chemical mechanical polishing process to form a fourth insulating layer, and A second mask is formed on the first insulating layer and the third insulating layer, and a source electrode layer, a drain electrode layer, and a gate electrode layer are formed using the second mask. A rain electrode layer, a fifth insulating layer, and a sixth insulating layer are formed, and the fourth insulating layer and the sixth insulating layer are formed. forming a second oxide film on the edge layer and the semiconductor layer; and forming a fifth insulating film on the second oxide film. a second conductive film is formed on the fifth insulating film; and a second conductive film is formed on the fifth insulating film. The oxide film of 2 is subjected to chemical mechanical polishing treatment to form the second oxide layer, the gate insulating layer, and the gate insulating layer. The present invention relates to a method for manufacturing a semiconductor device, and a method for manufacturing the same, characterized in that a gate electrode layer is formed.

[0024] In addition, the first heat treatment is performed after the semiconductor film is formed, and when the third insulating film is formed, the second insulating film and the A mixed layer with the third insulating film is formed, and oxygen is simultaneously added to the mixed layer or the second insulating film. Then, a fourth insulating layer, a sixth insulating layer, a second oxide layer, a gate insulating layer, and a gate electrode layer are formed on the fourth insulating layer, the sixth insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer. When forming the seventh insulating layer, a mixed layer of the fourth insulating layer and the seventh insulating layer is formed. At the same time, oxygen is added to the mixed layer or the fourth insulating layer, and a second heat treatment is performed. It is preferable to diffuse oxygen into the semiconductor layer.

[0025] The second insulating film and the fourth insulating film are insulating films containing oxygen, and the third insulating film and The seventh insulating layer is preferably formed by sputtering using oxygen gas.

[0026] The second insulating film and the fourth insulating film are silicon oxide films, and the third insulating film and the fourth insulating film are silicon oxide films. The insulating layer 7 is formed by using 50% or more by volume of oxygen gas and an aluminum oxide target. In particular, it is preferable to form the insulating film by sputtering.

[0027] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0028] Moreover, a structure using a semiconductor device, a microphone, a speaker, and a housing can be used. [Effects of the Invention]

[0029] By using one embodiment of the present invention, parasitic capacitance near a transistor can be reduced. Alternatively, a semiconductor device having good electrical characteristics can be provided. Alternatively, a semiconductor device can be manufactured using the same method as in the case of a transistor or a semiconductor device. It is possible to reduce variations in characteristics due to the manufacturing process. Alternatively, a semiconductor having an oxide semiconductor layer with few oxygen vacancies can be obtained. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, the interface state density in the vicinity of the oxide semiconductor layer can be reduced. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. A method for fabricating a semiconductor device can be provided.

[0030] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 2] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 3] Enlarged cross-sectional view and band diagram of a transistor. [Figure 4] Schematic diagram showing the principle of ALD film formation. [Figure 5] Schematic diagram of the ALD equipment. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 15]1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 28] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 32] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 33] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 34]Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 35] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 36] Electron diffraction pattern of CAAC-OS. [Figure 37] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 38] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 39] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 40] FIG. [Figure 41] FIG. 2 is a plan view showing pixels of the imaging device. [Figure 42] FIG. [Figure 43] FIG. [Figure 44] FIG. 2 is a diagram illustrating an example of the configuration of an RF tag. [Figure 45] FIG. 2 is a diagram illustrating an example of the configuration of a CPU. [Figure 46] Circuit diagram of a memory element. [Figure 47] 1A and 1B are diagrams illustrating a structural example of a display device and a circuit diagram of a pixel. [Figure 48] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 49] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 50] FIG. 2 is a diagram illustrating a display module. [Figure 51] 1A and 1B are a perspective view showing a cross-sectional structure of a package using a lead frame type interposer and a diagram showing the configuration of a module. [Figure 52] 1A to 1C illustrate electronic devices. [Figure 53] 1A to 1C illustrate electronic devices. [Figure 54] 1A to 1C illustrate electronic devices. [Figure 55] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0033] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0034] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0035] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0036] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0037] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0038] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0039] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0040] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0041] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , does not have a second connection path, and the second connection path is connected to the source (or the first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. The first connection path is a path via Z1, and is connected to the drain (or second The terminal of the third terminal (such as the terminal of the first terminal) is electrically connected to Y through at least a third connection path, and the third terminal The connection path does not have the second connection path, and the third connection path is via Z2. Or, it can be expressed as "the source of the transistor (or the first terminal) is electrically connected to X through Z1 by at least the first connection path. The first connection path does not have a second connection path, and the second connection path is A connection path through the transistor, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 by at least a third connection path, The third connection path does not have the second connection path. "The source (or first terminal, etc.) of the transistor is connected to at least a first electrical path. Therefore, the first electrical path is electrically connected to X through Z1, and the second electrical path is The second electrical path is connected to the source (or first terminal) of the transistor. (e.g., the first terminal) to the drain (or second terminal) of the transistor, The drain (or second terminal, etc.) of the transistor is connected to the drain (or second terminal, etc.) by at least a third electrical path. The third electrical path is electrically connected to Y via Z2, and the fourth electrical path is The fourth electrical path is connected to the drain (or second terminal, etc.) of the transistor. The electrical path from the source (or first terminal, etc.) of the transistor. Using the same representation as these examples, we can express the connection paths in the circuit configuration. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0042] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0043] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0044] <Notes regarding the description of the drawings> In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. , are used for convenience in explanation with reference to the drawings. The meaning of the wording in the specification changes depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0045] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below, and directly adjacent to each other. For example, if the expression is "electrode B on insulating layer A," Electrode B does not need to be formed directly on insulating layer A, but between insulating layer A and electrode B This does not exclude the inclusion of other components.

[0046] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0048] In addition, in the drawings, the size, thickness of a layer, or area is shown arbitrarily for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of illustration, and are not limited to the shapes or values ​​shown in the drawings.

[0049] In addition, in the drawings, top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0050] Moreover, "the same" may mean having the same area or the same shape. The same height in the vertical direction from the plate surface can also be said to be on the same plane. Also, due to the manufacturing process, the shapes, planes and heights may not be completely the same. Therefore, even if they are substantially the same, they can be said to be the same.

[0051] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc. depending on the situation. It can be done.

[0052] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0053] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain A channel is formed between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode). The transistor has a channel region and allows current to flow through the drain, channel region, and source. It is possible.

[0054] Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be written.

[0055] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0056] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Switched Circuits) or TCP (Tape Carrier Packet ge) or COG (Chip On Glass) on the board A display device is sometimes called a display device when an IC (integrated circuit) is directly mounted on it.

[0057] Also, the words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0058] <Notes on definitions of terms> The definitions of each term used in this specification will be explained below.

[0059] In this specification, the term "trench" or "groove" refers to a thin, band-like depression. It refers to the

[0060] In this specification, when a film is referred to as silicon oxynitride, it is referred to as SiOxNy. In this case, x and y may be natural numbers or numbers with decimal points. Good too.

[0061] <About connection> In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Connected means that there is an object between A and B that has some electrical effect. , which enables the transmission and reception of electrical signals between A and B.

[0062] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the context, and / or one or more other embodiments The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. You can do things like drawing.

[0063] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0064] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0065] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. explain.

[0066] 1A, 1B, and 1C are top views and diagrams of a transistor 10 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the device shown in FIG. 1(A). FIG. 1(A) is a cross-sectional view between A1 and A2, and FIG. 1(C) is a cross-sectional view between A3 and A4. For clarity, some elements are shown enlarged, reduced, or omitted. The A1-A2 direction is called the channel length direction, and the dashed line A3-A4 direction is called the channel width direction. There are cases where this happens.

[0067] The transistor 10 includes a substrate 100, an insulating layer 110, an insulator 121, and a semiconductor layer 122. , an insulator 123, a source electrode layer 130, a drain electrode layer 140, and a gate insulating layer 1 50, a gate electrode layer 160, an insulating layer 175, an insulating layer 173, and an insulating layer 170. The transistor 10 has an insulating layer 110 on a substrate 100. The transistor 10 has an insulator 121 on the insulating layer 110. The transistor 10 has a semiconductor layer on the insulator 121. The transistor 10 has a semiconductor layer 122 on the semiconductor layer 122, a source electrode layer 130, and The transistor 1 has a drain electrode layer 140 and is electrically connected to the semiconductor layer 122. 0 has an insulating layer 173, which is made up of an insulator 121, a semiconductor layer 122, an insulator 12 3, the source electrode layer 130 and the drain electrode layer 140 have a region in contact with their side surfaces. The gate electrode 10 has an insulating layer 173, a source electrode layer 130, and a drain electrode layer 140 on which an insulating layer 17 is formed. 5, and the insulating layer 175 has a region in contact with the side surface of the insulator 123. The semiconductor layer 122 has an insulator 123 over it. 21, and has an area in contact with the side surfaces of the insulating layer 173 and the insulating layer 175. 1(B), the lower surface of the insulating layer 170, the insulating layer 175, the source electrode layer 130, and The transistor 10 has an insulator 12 and a region in contact with the side of the drain electrode layer 140. The transistor 10 has a gate insulating layer 150 on the gate insulating layer 150. It has a top electrode layer 160.

[0068] <About insulators> In addition, the insulators (for example, the insulators 121 and 123) basically have insulating properties and are When the inlet or drain electric field becomes strong, current flows near the interface with the semiconductor layer. This refers to a layer that can

[0069] In addition, the above-described structure is such that the semiconductor layer 122 is connected to the source electrode layer 130 and the drain electrode The insulator 123 is in contact with the source electrode layer 130 and the drain electrode layer 140. Since the insulator 121 and the electrode layer 140 are in contact with each other during operation of the transistor 10, The semiconductor layer 122 and the insulator 123 have a high heat dissipation effect. do.

[0070] In addition, when the insulating layer 170 is formed, the transistor 10 has an insulating layer at the interface with the insulating layer 175. The material of the insulating layer 175 and the material of the insulating layer 170, or the gas used in forming the insulating layer 170, etc. A mixed layer is formed, and oxygen (referred to as excess oxygen, exO) is added to the mixed layer or insulating layer 175. Further heat treatment is performed to diffuse the oxygen into the semiconductor layer 122, and the insulating The oxygen vacancies present in the body 121 and the semiconductor layer 122 can be compensated for by the oxygen. This makes it possible to improve transistor characteristics (e.g., threshold voltage, reliability, etc.). Cut.

[0071] The excess oxygen added during the formation of the insulating layer 170 can be obtained by, for example, sputtering. The oxygen radiance is affected by the voltage, power, plasma, or substrate temperature applied during film formation. The excess oxygen exists in various forms, such as oxygen atoms, oxygen ions, or oxygen atoms. is a state that has more energy than the stable state and penetrates into the insulating layer 175. It is possible.

[0072] The method for adding oxygen is not limited to the above method. It may contain oxygen or may be deposited by other methods (e.g., ion implantation, ion plasma immersion) after deposition. Methods such as the above may also be used.

[0073] As shown in the cross section of the dashed line A3-A4 in FIG. 1(C), the transistor 10 has a channel In the width direction of the gate electrode layer 160, the gate insulating layer 150 is interposed between the insulator 121 and the semiconductor The conductor layer 122 faces the side surface of the insulator 123. That is, when a voltage is applied to the gate electrode layer 160, Then, the insulator 121, the semiconductor layer 122, and the insulator 123 are gate-type in the channel width direction. The semiconductor layer 122 is surrounded by the electric field of the gate electrode layer 160. The structure of the transistor is called the surrounded channel (s-channel) The transistor 10 is also called a self-aligned gate electrode layer using a trench. Since the source electrode layer and the drain electrode layer can be formed on the insulating film, the alignment accuracy is relaxed. This makes it possible to easily manufacture a miniaturized transistor. This structure is called a self-aligned s-channel FET (Self Aligned S-channel FET). s-channel FET, SA s-channel FET) structure, or Trench gate s-channel FET FET) structure, or TGSA s-channel FET (Trench Gate e Self Align FET) structure, or GLSA s-channel FE This is called the T (Gate Last Self Align FET) structure.

[0074] Here, the insulator 121, the semiconductor layer 122, and the insulator 123 are combined to form the semiconductor layer 120. In this case, in a transistor with a TGSA structure, the entire semiconductor layer 120 ( On the other hand, in the off state, the semiconductor Since the entire channel region formed in the conductor layer 120 can be depleted, The flow can be further reduced.

[0075] Furthermore, since the transistor 10 has a TGSA structure, the gate electrode and the source electrode or reducing the parasitic capacitance occurring between the gate electrode and the drain electrode, thereby reducing the cutoff frequency of the transistor 10. This allows the transistor 10 to have a high-speed response, for example, by improving the wave number characteristics.

[0076] In this embodiment, the second insulating film that will become the insulating layer 175 is formed on the source electrode layer as will be described later. 130, a planarization process is performed until the drain electrode layer 140 is exposed, and then an insulating layer 173 and When forming the third insulating film, the upper surface of the insulating layer 173, the source electrode layer 130, and the drain electrode layer 130 are It is preferable that the upper surface of the drain electrode layer 140 is flush with the substrate surface. The insulating layer 173 on the source electrode layer 130 and the drain electrode layer 140 is formed uniformly within the substrate surface. This allows the process of forming the groove 174 (for example, etching time) to be stable. As a result, the transistor 10 can be manufactured stably. This stabilizes the shape of the transistor and reduces variations in transistor characteristics. It can be suppressed.

[0077] The position of the top surface of the source electrode layer 130 or the drain electrode layer 140 is the same as that of the gate electrode layer It may be lower than the position of the bottom surface of 160, may be the same as, or may be higher.

[0078] In addition, the upper surface of the gate electrode layer 160 of the transistor 10 is located below the upper surface of the insulating layer 175. The transistor 10 may also include a source electrode layer 130 and a drain electrode layer 14. 0 may have a shape shorter than the semiconductor layer 122 in the channel length direction, or a shape longer than the semiconductor layer 122. may have

[0079] <Channel length> Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (drain region or drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is one of the values, the maximum value, and the minimum value in the region where the channel is formed. Or the average value.

[0080] <About channel width> The channel width is the width of the semiconductor (or transistor) when it is in the on state. This refers to the length of the area where the gate electrode overlaps with the current-carrying part of a transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one value, maximum value, minimum value or the like in the region where the channel is formed. or the average value.

[0081] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors containing minute, three-dimensional channels, In some cases, the proportion of the channel region formed on the surface may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width shown by the The width will be larger.

[0082] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0083] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the "surrounding channel width (SCW)." In this specification, it is sometimes referred to as "Dedicated Channel Width." When we refer to channel width, it refers to enclosed channel width or apparent channel width. In this specification, when simply referring to the channel width, it may refer to the effective channel width. It may refer to the channel width. The upper channel width, the enclosed channel width, etc. are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0084] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0085] <Improved characteristics through miniaturization> To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the value is reduced, the on-state current decreases.

[0086] However, in the transistor according to one embodiment of the present invention shown in FIG. 1, as described above, An insulator 123 is formed to cover the semiconductor layer 122 where the channel is formed. Therefore, the channel formation layer and the gate insulating layer are not in contact with each other. This suppresses the scattering of carriers at the interface with the insulating layer, thereby increasing the on-current of the transistor. It can be heard.

[0087] In the transistor of one embodiment of the present invention, the channel width of the semiconductor layer 122 serving as the channel is Since the gate electrode layer 160 is formed so as to electrically surround the semiconductor layer 12 In addition to the gate electric field applied vertically to 2, a gate electric field is also applied laterally. That is, a gate electric field is applied to the entire semiconductor layer 122, and the current flows through the semiconductor layer 122. Since the current flows through the entire layer 122, the on-current can be further increased.

[0088] In the transistor of one embodiment of the present invention, the insulator 123 is formed between the insulator 121 and the semiconductor layer 122. By forming the semiconductor layer 122 on the upper surface, it is difficult to form an interface state. By using this layer, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor mentioned above, the threshold voltage is stabilized and the S Therefore, the Icut (gate This reduces the current when the output voltage VG is 0V, thereby reducing power consumption. Furthermore, the threshold voltage of the transistor is stabilized, improving the long-term reliability of the semiconductor device. It can be raised.

[0089] In this embodiment, the semiconductor layer 120 (semiconductor layer 122) ) is used as an example, but one aspect of the embodiment of the present invention is not limited to this. For example, the channel and its vicinity, the source region, the drain region, etc., may be Or, depending on the situation, silicon (including strained silicon), germanium, silicon germanium Silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride The insulating layer 10 may be formed of a material having sodium, an organic semiconductor, or the like.

[0090] <Transistor configuration> The structure of a transistor in this embodiment will be described below.

[0091] <<Substrate 100>> The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal crystalline semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Silicon on Insulator) It is also possible to use a silicon-on-insulator (Si-on-insulator) substrate, and on these substrates The substrate 100 may be a substrate on which a semiconductor element is provided. It may be a substrate on which other devices such as transistors are formed. At least one of the gate electrode layer 160, the source electrode layer 130, and the drain electrode layer 140 of the transistor At least one of the devices may be electrically connected to the other devices mentioned above.

[0092] A flexible substrate may be used as the substrate 100. As a method for providing a transistor, a transistor is formed on a non-flexible substrate, and then a transistor is formed on the substrate. There is also a method of peeling off the substrate and transferring it to the substrate 100, which is a flexible substrate. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil containing the material may be used. In addition, the substrate 100 has the property of returning to its original shape when the bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and The thickness of the substrate 100 is preferably 15 μm or more and 300 μm or less. Furthermore, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate 100 when using glass or the like. It has the property of being stretchable even when bent or pulled, and of returning to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0093] The substrate 100, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100, which is a flexible substrate.

[0094] Insulating layer 110 The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to prevent the semiconductor layer 120 (semiconductor layer 122). The layer 110 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. For example, the oxygen emission converted into oxygen atoms by the TDS method is Output is 1.0 x 10 19 The film is defined as having a density of at least atoms / cm3. The surface temperature of the film at this time is 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. As described above, the substrate 100 may be a substrate on which other devices are formed. In the case of a plate, the insulating layer 110 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) It is preferable to perform a flattening treatment by the method g) or the like.

[0095] Insulators 121 and 123, semiconductor layer 122 Oxides that can be used as the insulator 121, the semiconductor layer 122, and the insulator 123 are It is preferable that the alloy contains at least indium (In) or zinc (Zn). It is preferable that the oxide contains both In and Zn. To reduce the variation in the electrical properties of the stators, it is preferable to include a stabilizer therewith. Representative examples include In-Ga oxide, In-Zn oxide, In-Mg oxide, and Zn- Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, C e, Mg, or Nd).

[0096] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0097] When the insulator 123 is an In-M-Zn oxide, the sum of In and M is 100 at When expressed as omic%, the ratio of In and M atoms is preferably 25 atomic %. c% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % In the above, M is less than 66 atomic %.

[0098] The indium and gallium contents in the insulator 123 were determined using time-of-flight secondary ion mass spectrometry. (TOF-SIMS), X-ray electron spectroscopy (XPS), ICP mass spectrometry (ICP-MS) ) can be compared.

[0099] The semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Preferably, the potential is 3 eV or more, so that the off-state current of the transistor 10 can be reduced. .

[0100] The thickness of the semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less. Further, it is more preferably 3 nm or more and 50 nm or less.

[0101] The insulators 121 and 123 are composed of one or more elements that constitute the semiconductor layer 122. Therefore, the semiconductor layer 122, the insulator 121, and the insulator 12 At the interface with 3, interfacial scattering is unlikely to occur. Since the electron transport is not impeded, the field effect mobility of the transistor 10 is increased.

[0102] The insulators 121 and 123 are typically made of In—Ga oxide, In—Zn oxide, or I n-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn oxide (M is A l, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) and a semiconductor The energy level of the bottom of the conduction band is closer to the vacuum level than the layer 122, and is typically an insulator 12 1. The energy level of the lower end of the conduction band of the insulator 123 and the energy level of the lower end of the conduction band of the semiconductor layer 122 The difference between the energy level and the 0.2eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less That is, the electron affinity of the insulator 121 and the insulator 123 and the electron affinity of the semiconductor layer 122 are The difference between the two forces is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Electron affinity indicates the difference between the vacuum level and the energy level at the bottom of the conduction band.

[0103] Insulators 121 and 123 include Al, Ti, Ga, Y, Zr, Sn, La, and Ce. By having Mg or Nd in a higher atomic ratio than In, the following effects may be obtained: (1) The energy gap of the insulator 121, the semiconductor layer 122, and the insulator 123 is (2) The electron affinity of the insulators 121 and 123 is decreased. (3) The external (4) It has higher insulating properties than the semiconductor layer 122. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd has a bonding strength with oxygen. Because they are metallic elements with strong properties, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, By having Nd at a higher atomic ratio than In, oxygen vacancies are less likely to occur.

[0104] The insulators 121 and 123 have higher insulating properties than the semiconductor layer 122. It has the same function as the gate insulating layer.

[0105] When the insulators 121 and 123 are In-M-Zn oxides, excluding Zn and O, The atomic ratio of In and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. atomic % or more, more preferably, In is less than 25 atomic % and M is 75 atomic % or more. omic% or more.

[0106] The insulators 121 and 123 are made of In-M-Zn oxide (M is Al, Ti, Ga, Y , Zr, Sn, La, Ce, Mg, or Nd), the insulating layer 122 is M (Al, Ti, Ga, Y, Zr, Sn, La, C) contained in the insulator 121 and the insulator 123 The atomic ratio of the above-mentioned elements (e, Mg, or Nd) contained in the semiconductor layer 122 is high. The atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher than that of the atomic ratio. The element represented by M above bonds more strongly with oxygen than indium, so oxygen It has a function of suppressing the occurrence of defects in the insulators 121 and 123. The insulating layer 121 and the insulating layer 123 are oxide films in which oxygen vacancies are less likely to occur than in the semiconductor layer 122 .

[0107] The semiconductor layer 122 contains more indium than the insulators 121 and 123. In semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, By increasing the In content, more s orbitals overlap, so that In is more abundant than M. The oxides with a higher In content have a higher mobility than the oxides with a composition with an equal or lower In content than M. Therefore, by using an oxide with a high indium content for the semiconductor layer 122, Therefore, a transistor with high field effect mobility can be realized.

[0108] The semiconductor layer 122 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, S In the case of n, La, Ce, Mg, or Nd), the temperature used to deposit the semiconductor layer 122 In the target, if the atomic ratio of metal elements is In:M:Zn=x1:y1:z1, x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 / It is preferable that z1 / y1 is 3 or more and 6 or less, and more preferably 1 or more and 6 or less. 6 or less, the semiconductor layer 122 can be formed by CAAC-OS (C Axis Alignment A crystalline oxide semiconductor (Crystalline Oxide Semiconductor) film is formed. A typical example of the atomic ratio of the target metal elements is In:M:Zn=1. :1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2 , 4:2:3, 4:2:4.1, etc.

[0109] The insulators 121 and 123 are made of In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), insulator 121, insulator 123 In the target used to deposit the film, the atomic ratio of the metal elements is In:M:Zn=x Assuming 2:y2:z2, x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more 6 or less, more preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less it becomes easier to form the CAAC-OS film as the insulator 121 and the insulator 123. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4: 7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1: 6:4, 1:9:6, etc. The atomic ratio of the insulator 121 and the insulator 123 includes fluctuations of plus or minus 40% of the above atomic ratio as an error, respectively.

[0110] In addition, the insulator (123) can be replaced with a metal oxide, for example, aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the metal oxide can be provided on the insulator 123. [[ID=>

[0111] The atomic ratio is not limited to these, and appropriate atomic ratios can be used according to the required semiconductor characteristics.

[0112] [[ID=2>>The insulator 121 and the insulator 123 may have the same composition. For example, as the insulator 121 and the insulator 123, an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, 1:3:4, or 1:4:5 used in the sputtering method may be used.

[0113] <00>

[0114] ​​​​​​​​​ Alternatively, the insulators 121 and 123 may have different compositions. The atomic ratio of the metal elements in the target used in the sputtering method is In:Ga:Zn= Using 1:3:4 In-Ga-Zn oxide, the target metal element was used as the insulator 123. Alternatively, an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2 may be used.

[0115] The thickness of the insulator 121, the semiconductor layer 122, and the insulator 123 is 3 nm or more and 100 nm or less. It is preferable that the thickness is 3 nm or less and 50 nm or less.

[0116] Here, the thickness of the semiconductor layer 122 can be formed thinner than at least the insulator 121. For example, the semiconductor layer 122 may be thickened. In this case, the on-state current of the transistor can be increased. The thickness may be such that the effect of suppressing the generation of interface states of the layer 122 is not lost. The thickness of the semiconductor layer 122 is greater than or equal to the thickness of the insulator 121. The transistor on-resistance can be 100 times or more, 4 times or more, or 6 times or more. When it is not necessary to increase the on-current, the thickness of the insulator 121 is set to be equal to or greater than the thickness of the semiconductor layer 122. For example, the insulating layer 110, the insulating layer 170, the insulating layer 173, or the insulating layer 175 may be When the semiconductor layer 122 contains excess oxygen, the oxygen diffuses and is contained in the semiconductor layer 122 by heat treatment. This can reduce the amount of oxygen vacancies and stabilize the electrical characteristics of the semiconductor device.

[0117] Similarly to the insulator 121, the insulator 123 also serves to suppress the generation of interface states in the semiconductor layer 122. For example, the thickness may be equal to or greater than that of the insulator 121. If the insulator 123 is thick, the electric field generated by the gate electrode layer 160 is It is preferable to form the insulator 123 thinly, since it may be difficult to reach the layer 122. In addition, oxygen contained in the insulator 123 diffuses into the source electrode layer 130 and the drain electrode layer 140. In order to prevent the source electrode layer 130 and the drain electrode layer 140 from being oxidized, the insulator 12 For example, the thickness of the insulator 123 is thinner than the thickness of the semiconductor layer 122. However, the thickness of the insulator 123 is not limited to this, and may be determined based on the withstand voltage of the gate insulating layer 150. Taking this into consideration, it may be set appropriately according to the voltage at which the transistor is driven.

[0118] When the insulator 121, the semiconductor layer 122, and the insulator 123 have different compositions, The surface was observed using a scanning transmission electron microscope (STEM). It may be possible to observe the morphology using a Electron Microscope.

[0119] <About hydrogen concentration> The hydrogen contained in the insulator 121, the semiconductor layer 122, and the insulator 123 bonds with the metal atoms. The lattice (or the part where oxygen is released) reacts with the oxygen to form water. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, resulting in the formation of carriers. Therefore, oxides containing hydrogen can be used as semiconductors. The transistor used tends to have normally-on characteristics.

[0120] Therefore, in the insulator 121, the semiconductor layer 122, the insulator 123, and their interfaces, It is preferable that the amount of oxygen vacancies and hydrogen be reduced as much as possible. 121, the semiconductor layer 122, the insulator 123, and the secondary ion mass at their respective interfaces. Analysis method (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration obtained by 16 atoms / cm 3 Over 2×10 20 ato ms / cm 3 Less than 1 × 10 16 atoms / cm 3 5x10 or more 19 ato ms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 More than 1×10 19 a toms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 As a result, the transistor 10 It has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). Cut.

[0121] <Carbon and silicon concentrations> In addition, in the insulator 121, the semiconductor layer 122, the insulator 123, and their interfaces, When silicon or carbon, which is one of the group 14 elements, is included, the insulator 121 and the semiconductor layer 122 In addition, oxygen vacancies increase in the insulator 123, resulting in the formation of an n-type region. Therefore, the insulator 121, the semiconductor layer 122, the insulator 123, and the silicon at their interfaces are For example, the insulator 121, the semiconductor layer 1, and the carbon concentration are preferably reduced. 22, insulator 123, and silicon and The concentration of carbon is 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below Below, preferably 1 x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 Below or less, more preferably 1 × 10 16 atoms / cm 3 Over 2×10 18 atoms / c m 3 As a result, the threshold voltage of the transistor 10 is preferably set to a value equal to or less than the threshold voltage of the transistor 10. The device has electrical characteristics (also called normally-off characteristics) such that

[0122] <About the concentration of alkali metals or alkaline earth metals> In addition, alkali metals and alkaline earth metals generate carriers when combined with oxides. This may increase the off-state current of the transistor. 21, the semiconductor layer 122, the insulator 123, and the alkali metal or For example, the insulator 121, the semiconductor, and the like preferably have a reduced concentration of alkaline earth metals. The Al obtained by SIMS at the layer 122, the insulator 123, and their respective interfaces. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 As a result, the transistor The transistor 10 has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). Has.

[0123] <Regarding nitrogen concentration> Nitrogen is contained in the insulator 121, the semiconductor layer 122, the insulator 123, and their interfaces. When the electrons are surrounded by the n-type region, the carrier density increases and the n-type region is formed. As a result, transistors using oxides containing nitrogen are normally on. Therefore, the insulator 121, the semiconductor layer 122, the insulator 123, and At the interface, it is preferable that nitrogen is reduced as much as possible. For example, 21, the semiconductor layer 122, the insulator 123, and the respective interfaces obtained by SIMS. The nitrogen concentration is 1×10 15 atoms / cm 3 5x10 or more 19 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 5x10 or more 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 or less, more preferably 1 × 10 15 atoms / cm 3 5x10 or more 17 ato ms / cm 3 As a result, the transistor 10 has a threshold voltage of It has electrical characteristics in which the load is positive (also called normally-off characteristics).

[0124] <About carrier density> By reducing impurities in the insulator 121, the semiconductor layer 122, and the insulator 123, the insulator The carrier density of the insulating layer 121, the semiconductor layer 122, and the insulator 123 can be reduced. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have a carrier density of 1× 10 15 pieces / cm 3 Less than 1 × 10 13 pieces / cm 3 More preferably, 8 x10 11 pieces / cm 3 less than 1×10 11 pieces / cm 3 Less than, most preferably is 1 x 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 That's all.

[0125] The insulator 121, the semiconductor layer 122, and the insulator 123 have a low impurity concentration and a defect level. By using an oxide film with a low potential density, it is possible to create a transistor with even better electrical characteristics. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic. Intrinsic oxides have fewer carrier sources, so they can reduce carrier density. Therefore, a transistor in which a channel region is formed in the oxide film may be The threshold voltage tends to be a positive electrical characteristic (also called a normally-off characteristic). In addition, a highly pure intrinsic or substantially highly pure intrinsic oxide film has a low defect level density. In addition, the trap level density may also be lower. The transistor using the oxide film has a significantly small off-state current and When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current is below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 A characteristic of A or less Therefore, a transistor in which a channel region is formed in the oxide film can The variation in electrical characteristics may be small, resulting in a highly reliable transistor.

[0126] In addition, as described above, a transistor using a highly purified oxide film in a channel formation region The off-state current is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V, or When the voltage is set to about 10 V, the off-state current normalized by the channel width of the transistor is several y It is possible to reduce the resistance to A / μm to several zA / μm.

[0127] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, a non-single crystal structure. The non-single crystal structure may be, for example, a CAAC-OS, a polycrystalline structure, a microcrystalline structure, or a non-single crystal structure, which will be described later. Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0128] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, a microcrystalline structure. The crystalline insulator 121, the semiconductor layer 122, and the insulator 123 are, for example, 1 nm or more. The oxide film contains crystallites of less than 10 nm in size. Alternatively, the oxide film having a crystallite structure is, for example, It has a mixed phase structure with crystalline parts of 1 nm or more and less than 10 nm in the amorphous phase.

[0129] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, an amorphous structure. The insulator 121, the semiconductor layer 122, and the insulator 123, which have an amorphous structure, are, for example, The oxide film is disordered and has no crystalline components. Alternatively, the oxide film with an amorphous structure is, for example, completely It has an amorphous structure and does not have any crystalline parts.

[0130] The insulator 121, the semiconductor layer 122, and the insulator 123 are made of CAAC-OS, microcrystalline The film may be a mixed film having regions of two or more structures, namely, an amorphous structure and an amorphous structure. For example, an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region are Alternatively, a mixed film may have a single layer structure with an amorphous structure and a microcrystalline structure. The structure is a layered structure consisting of a region of SiO2 and a region of CAAC-OS.

[0131] The insulator 121, the semiconductor layer 122, and the insulator 123 have, for example, a single crystal structure. You may do so.

[0132] The oxide film, which is less likely to cause oxygen deficiency than the semiconductor layer 122, is in contact with the upper and lower sides of the semiconductor layer 122. By providing the oxygen vacancies in the semiconductor layer 122, oxygen vacancies in the semiconductor layer 122 can be reduced. The semiconductor layer 122 is made of an insulator 121 having one or more metal elements constituting the semiconductor layer 122, an insulating Since the semiconductor layer 122 is in contact with the insulator 121, the interface between the insulator 121 and the semiconductor layer 122 and the semiconductor layer 122 are For example, when oxygen is added to the insulating layer 110, the interface state density at the interface with the insulating layer 123 is extremely low. After the heating, the oxygen is transferred to the semiconductor layer 122 via the insulator 121. However, oxygen is not easily captured at the interface state, and the insulator 12 The oxygen contained in the semiconductor layer 122 can be transferred to the semiconductor layer 122. It is possible to reduce oxygen vacancies contained in the insulator 122. Since the insulator 121 is doped with Zn, it is possible to reduce oxygen vacancies in the insulator 121. The localized state density of the semiconductor layer 122 can also be reduced.

[0133] In addition, the semiconductor layer 122 may be an insulating film having a different constituent element (for example, a gate insulating film containing a silicon oxide film). When the semiconductor comes into contact with a silicon dioxide film (a silicon dioxide insulating layer), an interface state is formed, and the interface state may form a channel. In such a case, a second transistor with a different threshold voltage appears, and the transistor However, the apparent threshold voltage of the semiconductor layer 122 may fluctuate. The insulator 121 and the insulator 123 each containing one or more metal elements are in contact with the semiconductor layer 122. Therefore, the interface between the insulator 121 and the semiconductor layer 122 and the interface between the insulator 123 and the semiconductor layer 122 are Interface states are less likely to form at the interface.

[0134] The insulators 121 and 123 are the components of the insulating layer 110 and the gate insulating layer 150, respectively. In order to prevent the formation of levels due to impurities caused by the incorporation of elements into the semiconductor layer 122, It also functions as a barrier film.

[0135] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 The carbon that can be mixed into the insulator 121 or the insulator 123 penetrates to a depth of several nanometers from the interface. When impurities such as silicon and carbon enter the semiconductor layer 122, the impurity level increases. The impurity level acts as a donor and generates electrons, making the material n-type.

[0136] However, if the film thickness of the insulators 121 and 123 is greater than several nm, the mixed Since impurities such as silicon and carbon do not reach the semiconductor layer 122, the influence of the impurity level is small. is reduced.

[0137] Therefore, by providing the insulators 121 and 123, the threshold voltage of the transistor It is possible to reduce variations in electrical characteristics such as the above.

[0138] Furthermore, the gate insulating layer 150 and the semiconductor layer 122 come into contact with each other, and a channel is formed at the interface. In this case, interface scattering occurs at the interface, resulting in a decrease in the field-effect mobility of the transistor. However, the insulators 121 and 123, which contain one or more metal elements constituting the semiconductor layer 122, Since the insulating film 121 is provided in contact with the semiconductor layer 122, the insulating film 121 and the insulating film 123 At the interface with the semiconductor, carrier scattering is less likely to occur, increasing the field-effect mobility of the transistor. It is possible.

[0139] In this embodiment, the amount of oxygen vacancies in the semiconductor layer 122 and the amount of oxygen vacancies in the semiconductor layer 122 It is possible to reduce the amount of oxygen vacancies in the insulators 121 and 123 formed in the semiconductor layer 12. The density of localized states of the transistor 2 can be reduced. 10 has a small fluctuation in threshold voltage and has high reliability. The transistor 10 described in this embodiment has excellent electrical characteristics.

[0140] Note that an insulating film containing silicon is often used as a gate insulating layer of a transistor. For the above reasons, the region of the oxide layer that serves as a channel of the transistor of one embodiment of the present invention In this way, it can be said that a structure that does not come into contact with the gate insulating layer is preferable. When a channel is formed at the interface between the silicon dioxide layer and the oxide layer, scattering of carriers occurs at the interface, and From this viewpoint, the oxide layer It is preferable to separate the region that will become the channel from the gate insulating layer.

[0141] Therefore, the semiconductor layer 120 is a laminated structure of the insulator 121, the semiconductor layer 122, and the insulator 123. By doing so, a channel can be formed in the semiconductor layer 122, and high field-effect mobility and Furthermore, a transistor having stable electrical characteristics can be formed.

[0142] The semiconductor layer does not necessarily have to be three layers, but can be a single layer, two layers, four layers, or even five or more layers. In the case of a single layer, the semiconductor layer 122 shown in this embodiment may have a structure as follows. A layer may be used.

[0143] <Band diagram> Here, a band diagram will be described. For ease of understanding, the band diagram is shown with the insulating layer 110, The conduction band minimums of the insulator 121, the semiconductor layer 122, the insulator 123, and the gate insulating layer 150 The energy (Ec) of

[0144] As shown in FIG. 3(A) and FIG. 3(B), the insulator 121, the semiconductor layer 122, and the insulator 123 are In this case, the energy of the conduction band minimum changes continuously. The elements that make up the insulator 122 and the insulator 123 are the same, so oxygen easily diffuses between them. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have the following composition: Although it is a laminate of films with different properties, it can also be said to be physically continuous.

[0145] The oxide films that are laminated with the same main component are not simply laminated but are joined together continuously (this In particular, the energy of the conduction band edge changes continuously between layers in a U-shaped well (US The structure is fabricated so that a thin film (a thin film well) is formed at the interface of each layer. The stacking is done so that there are no impurities that form defect levels such as drop centers or recombination centers. If impurities exist between the layers of the laminated multilayer film, the energy The band continuity is lost, and carriers are trapped or disappear at the interface due to recombination. cormorant.

[0146] In FIG. 3B, the insulators 121 and 123 have the same Ec. However, they may be different.

[0147] As shown in FIG. 3B, the semiconductor layer 122 serves as a well, and in the transistor 10, It can be seen that a channel is formed in the semiconductor layer 122. Note that the semiconductor layer 122 is the bottom. The buried channel is a U-shaped well structure in which the energy of the conduction band edge changes continuously. It can also be called Nell.

[0148] In addition, in the vicinity of the interface between the insulator 121 and the insulator 123 and an insulating film such as a silicon oxide film, Insulators 121 and 123 may have trap levels due to impurities or defects. By virtue of this, the semiconductor layer 122 can be kept away from the trap level. The energy difference between Ec of the insulator 121 or the insulator 123 and Ec of the semiconductor layer 122 is When the difference is small, electrons in the semiconductor layer 122 exceed the energy difference and reach the trap level. When negatively charged electrons are captured in the trap level, A negative fixed charge is generated in the transistor, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in long-term storage tests of transistors, the traps were not fixed and did not affect the characteristics. There is a concern that this will cause fluctuations in the

[0149] Therefore, to reduce the variation in the threshold voltage of the transistor, the insulator 121, and It is necessary to provide an energy difference between Ec of the insulator 123 and Ec of the semiconductor layer 122. The respective energy differences are preferably 0.1 eV or more, and 0.2 eV or more. More preferable.

[0150] It is preferable that the insulator 121, the semiconductor layer 122, and the insulator 123 contain a crystalline portion. In particular, the use of crystals oriented along the c-axis provides stable electrical characteristics to transistors. It is possible.

[0151] In the band diagram shown in FIG. 3B, the insulator 123 is not provided and the semiconductor layer 12 2 and the gate insulating layer 150, an In-Ga oxide (for example, an atomic ratio of In:Ga=7 Alternatively, gallium oxide (In-Ga oxide: 93) may be provided. In addition, in the state where the insulator 123 is present, an In-Ga An oxide may be provided, or gallium oxide may be provided.

[0152] The semiconductor layer 122 is an oxide having a higher electron affinity than the insulators 121 and 123. For example, the semiconductor layer 122 has a higher electron density than the insulators 121 and 123. The affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, More preferably, an oxide having a larger valence of 0.2 eV or more and 0.4 eV or less can be used.

[0153] The transistor described in this embodiment contains one or more metal elements forming the semiconductor layer 122. Since the insulator 121 and the semiconductor layer 122 are and the interface between the insulator 123 and the semiconductor layer 122. Therefore, by providing the insulators 121 and 123, the threshold voltage of the transistor and the like can be reduced. This can reduce variations and fluctuations in electrical characteristics.

[0154] <<Source Electrode Layer 130, Drain Electrode Layer 140>> The source electrode layer 130 and the drain electrode layer 140 are made of copper (Cu), tungsten (W), molybdenum (Mo), and the like. Ribdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (T i), Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn) , iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (I r), strontium (Sr), or alloys, or A single layer or multilayer of conductive layers containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. as the main components For example, when stacking, the lower conductive layer that contacts the semiconductor layer 122 is preferably a conductive layer. The conductive layer has a material that easily bonds with oxygen, and the upper conductive layer has a material that is highly resistant to oxidation. In addition, high-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a low-resistance conductive material such as aluminum or copper. Furthermore, when a Cu-Mn alloy is used, oxidation occurs at the interface with an insulator containing oxygen. This is preferable because manganese oxide forms manganese and has the function of suppressing the diffusion of Cu. When tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen (barrier properties), and Tantalum nitride itself is preferred because it is resistant to oxidation.

[0155] In addition, when a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, The oxygen in the oxide semiconductor layer diffuses to the conductive material, which is more likely to bond with oxygen. Oxygen vacancies occur in the area near the contact with the source electrode layer or the drain electrode layer, and a small amount of oxygen is released into the film. The hydrogen contained in the region enters the oxygen vacancy, causing the region to become significantly n-type. Therefore, the n-type region can be used as the source or drain of a transistor. This can be done.

[0156] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer may be used. By doing so, the oxide semiconductor in contact becomes n-type, and the conductive layer in contact with the insulating layer 175 This can prevent oxidation of the conductive layer.

[0157] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( The gate insulating layer 150 may be an insulating film containing one or more of TaOx. The gate insulating layer 150 may be a laminate of the above materials. It may contain zirconium (Zr) or the like as an impurity.

[0158] Next, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0159] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the thickness of the gate insulating layer 150 can be increased compared to when silicon oxide is used. Therefore, the leakage current due to the tunnel current can be reduced. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous transistor. It has a higher dielectric constant than hafnium oxide, which has a porous structure. To make a small transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0160] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed close to the channel region of a transistor, the interface states This may cause deterioration of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating layer 150, or may be an oxide semiconductor. The film may be a film included in the conductive film. That is, the film having a buffer function may be silicon oxide. , silicon oxynitride, oxide semiconductor, or the like can be used. The film may contain, for example, a semiconductor having a larger energy gap than the semiconductor that will be the channel region. Alternatively, an insulator is used. Alternatively, the film having a buffer function may be, for example, a film that serves as a channel region. Use a semiconductor or insulator that has a smaller electron affinity than the semiconductor that is used. The film to be formed may contain, for example, a semiconductor having a higher ionization energy than the semiconductor that will be the channel region. Conductors or insulators are used.

[0161] On the other hand, the interface states (trap By trapping charge in the charge center, the threshold voltage of the transistor can be controlled. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, a film with a buffer function may be made of hafnium oxide with a larger ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0162] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges in the interface state in the gate insulating layer 150, the gate potential is Electrons can be moved toward the polar layer 160. , 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower), The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the temperature for at least one second, typically at least one minute.

[0163] In this way, a transistor in which a desired number of electrons are trapped in the interface states of the gate insulating layer 150 or the like is formed. The threshold voltage of the gate electrode layer 160 is shifted to the positive side. By adjusting the time for capturing electrons, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If charges can be trapped, they can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for other insulating layers.

[0164] Gate electrode layer 160 The gate electrode layer 160 may include, for example, aluminum (Al), titanium (Ti), chromium (C r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (T Conductive films such as tungsten (W) and tungsten (A) can be used. The electrode layer 160 can be a laminate. It can also be made of a conductive material containing nitrogen, such as a nitride of the above materials. In addition, when tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen. This is preferable because it has barrier properties and the tantalum nitride itself is resistant to oxidation.

[0165] Insulating layer 170 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Ox), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 170 can be formed of a laminate of the above materials. may be.

[0166] The insulating layer 170 may also be made of an oxide containing In or Zn. In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) is available.

[0167] The insulating layer 170 preferably includes an aluminum oxide film. It has a blocking effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film can be used during the manufacturing process of the transistor. After manufacturing, the insulation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the semiconductor layer 122 with oxygen, which is the main component material, The protective layer 122 has the effect of preventing unnecessary release of oxygen from the insulating layer 110. It is suitable for use as a protective film.

[0168] The insulating layer 170 is preferably a film having an oxygen supplying ability. When the insulating film 170a is formed, a mixed layer of the insulating layer 170 and the insulating layer 175 is formed. The mixed layer or insulating layer 175 is doped with oxygen, and the oxygen is then converted into The oxygen diffuses into the oxide semiconductor and can compensate for oxygen vacancies in the oxide semiconductor. This makes it possible to improve transistor characteristics (for example, threshold value, reliability, etc.).

[0169] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H For example, aluminum oxide can be used. Aluminum (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), acid Silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttria YOx, Zirconium oxide (ZrOx), Lanthanum oxide (LaOx), Neo oxide NdOx, hafnium oxide (HfOx) and tantalum oxide (TaOx) The insulating layer may be a laminate of the above materials. The insulating layer preferably contains more oxygen than the stoichiometric composition. The released oxygen diffuses through the gate insulating layer 150 into the channel forming region of the semiconductor layer 120. Since oxygen can be dispersed, oxygen is compensated for the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained.

[0170] Insulating Layer 173 and Insulating Layer 175 The insulating layer 173 and the insulating layer 175 contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Al, Mg, Si, Ga, and Germanium Ge, Yttrium, Zirconium, Lanthanum, Neo It contains Nd, Hf, Ta, Ti, etc. For example, magnesium oxide (MgOx), silicon oxide (SiOx), Silicon nitride (SiOxNx), silicon nitride oxide (SiNxOx), silicon nitride (S iNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Aluminum (YOx), Zirconium oxide (ZrOx), Lanthanum oxide (LaOx), Neodymium oxide NdOx, hafnium oxide (HfOx) and tantalum oxide (TaOx), tantalum oxide An insulating film containing one or more kinds of aluminum (AlOx) can be used. The insulating layer 175 may be a laminate of the above materials. It is preferred that the hydroxyl group has more oxygen than the hydroxyl group.

[0171] Alternatively, the insulating layer 173 and the insulating layer 175 may be made of a low-dielectric-constant material (low-k material). For example, silicon oxide (SiOF) containing a few percent of fluorine (F), Carbon (C)-doped silicon oxide (SiOC), fluorinated silicate glass (FSG) , organic silicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsil Sesquioxane (MSQ), organic polymer, polyimide, fluororesin (polytetrafluoroethylene) It can be formed using amorphous carbon with fluorine added, etc. By using a low-k material for the insulating layer 173 and the insulating layer 175, The capacitance associated with the motor 10 can be further reduced.

[0172] <Conductive layer 165> As shown in FIG. 2, the transistor 10 has a conductive layer 165 under the insulating layer 110. The conductive layer 165 can function as a bottom gate. 2(B), the same potential as the gate electrode layer 160 can be applied. The conductive layer 165 can be made of, for example, copper (C u), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), Manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (C r), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), Elements made of materials such as platinum (Pt), iridium (Ir), and strontium (Sr), or alloys, or compounds with oxygen, nitrogen, fluorine, silicon, etc. as their main components For example, the conductive layer 166 may be a single layer or a multilayer of conductive layers containing a resistant material. The conductive layer 167 can have a material that is highly oxidizable. It is preferable to use a high melting point material such as tungsten or molybdenum. It is preferable to form the insulating layer from a low resistance conductive material such as aluminum or copper.

[0173] <Transistor manufacturing method> Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. Note that the parts that overlap with those explained in the above transistor configuration will be omitted. The A1-A2 direction shown in FIGS. 6 to 14 corresponds to the channel shown in FIGS. 1(A) and 1(B). 6 to 14 is also referred to as the direction of the length of the cable. ) and the channel width direction shown in FIG. 1(C).

[0174] In this embodiment, each layer constituting a transistor (an insulating layer, an oxide semiconductor layer, a conductive layer The methods used for deposition include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. Alternatively, it can be formed by a coating method or a printing method. The film formation method includes sputtering and plasma-enhanced chemical vapor deposition (PECVD). ) The CVD method is representative, but the thermal CVD method may also be used. As an example of the thermal CVD method, MOCVD (metal-organic chemical vapor deposition) method or ALD (atomic layer deposition) method may be used.

[0175] <Thermal CVD method> Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0176] Also, in the thermal CVD method, a source gas and an oxidant are simultaneously fed into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate, <00工业设备1626> and film formation may be performed.

[0177] Also, thermal CVD methods such as MOCVD method and ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3 . The chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited thereto, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc. )2) can also be used.

[0178] <00016工业设备40><ALD method> A film forming apparatus using a conventional CVD method feeds a source gas (precursor) for the reaction during film formation. One or more of the above are simultaneously supplied to the chamber. Precursors for the reaction are introduced into the chamber in sequence, and the gas introduction sequence is repeated. For example, by switching each switching valve (also called high-speed valve), Two or more precursors are supplied to the chamber in sequence by switching between them, and multiple precursors are mixed. To avoid this, an inert gas (such as argon or nitrogen) is added after the first precursor. In addition, instead of introducing an inert gas, a vacuum pump is used. Thus, after the first precursor is evacuated, the second precursor can be introduced.

[0179] Figures 4(A), (B), (C), and (D) show the film formation process by the ALD method. O1 is adsorbed onto the surface of the substrate (see FIG. 4(A)), and a first monolayer is formed (see FIG. 4(B)). In this case, metal atoms contained in the precursor bond with hydroxyl groups present on the substrate surface. The metal atom is bonded to an alkyl group such as a methyl group or an ethyl group. The first precursor 601 is evacuated and then reacted with the second precursor 602 introduced. In response (see FIG. 4(C)), a second monolayer is deposited on the first monolayer to form a thin film. (See FIG. 4(D)). For example, if an oxidizing agent is included as the second precursor, A metal atom or an alkyl group bonded to the metal atom present in the first precursor and an acid A chemical reaction occurs between the first precursor and the second precursor, forming an oxide film. If a gas containing hydrogen is used as the catalyst, a metal film can be formed by a reduction reaction. do.

[0180] The ALD method is a film formation method based on surface chemical reactions, in which precursors are adsorbed onto the surface to be filmed, A self-limiting mechanism acts, and the resulting layer is formed. For example, trimethylaluminum Such precursors react with the hydroxyl groups (OH groups) present on the surface of the film to be formed. Since only surface reactions occur due to the precursor coming into contact with the surface to be coated, the thermal energy Metal atoms in the precursor can be adsorbed onto the surface to be film-formed through the precursor. Casa has a high vapor pressure, is thermally stable before film formation, and does not self-decompose. It has the characteristics of rapid chemical adsorption. In addition, the precursor is introduced as a gas, so the exchange If the precursors introduced into each other have enough time to diffuse, high aspect ratios can be achieved. Even in areas with irregularities, a film can be formed with good coverage.

[0181] In addition, in the ALD method, the gas introduction order is controlled and repeated multiple times until the desired thickness is achieved. By repeating this process, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the nozzle is turned on. By increasing the pressure, the film formation speed can be increased and the impurity concentration in the film can be reduced. can be done.

[0182] In addition, the ALD method includes ALD using heat (thermal ALD method), ALD using plasma ( In thermal ALD, thermal energy is used to induce the reaction of precursors. The plasma ALD method involves reacting precursors in a radical state. do.

[0183] The ALD method can deposit extremely thin films with high precision. Surface coating is possible even on uneven surfaces. The rate is high and the film density is high.

[0184] <Plasma ALD> In addition, by forming a film using the plasma ALD method, compared with the ALD method using heat (thermal ALD method) it is possible to form a film at a lower temperature. The plasma ALD method can, for example, form a film even at 100 °C or lower without reducing the film formation rate. Also, in the plasma ALD method, N2 can be radicalized by plasma, so it is possible to form not only oxides but also nitrides.

[0185] Also, in plasma ALD, the oxidizing power of the oxidant can be enhanced. As a result, when forming a film by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0186] Also, when performing plasma ALD, radical species can be generated, and plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), etc., and plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0187] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, and the surface coverage rate can be increased, and the film can be formed. As a result, the intrusion of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

[0188] <Explanation of the ALD apparatus> An example of a film formation apparatus using the ALD method is shown in FIG. a film forming chamber (chamber 1701), a raw material supply unit 1711a, a raw material supply unit 1711b, High-speed valves 1712a and 1712b, which are flow rate controllers, and a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b installed in the chamber 1701 are connected to the feed pipes and valves. The raw material supply units 1711a and 1711b are connected to the raw material discharge port 1714. is connected to an exhaust device 1715 via an exhaust pipe, a valve, and a pressure regulator.

[0189] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the substrate to be formed is placed on the substrate holder. A membrane substrate 1700 is placed.

[0190] In the raw material supply units 1711a and 1711b, solid A raw material gas is formed from a raw material of a liquid or a raw material. The unit 1711b may be configured to supply a source gas.

[0191] In addition, although an example in which two raw material supply units 1711a and 1711b are provided is shown, There is no particular limitation, and three or more valves may be provided. 12b can be precisely controlled by time, and either the source gas or the inert gas can be supplied. The high-speed valves 1712a and 1712b are flow rate controllers for the source gas. It can also be said to be a flow rate controller for inert gas.

[0192] In the film formation apparatus shown in FIG. 5(A), a film formation substrate 1700 is carried onto a substrate holder 1716. After the chamber 1701 is sealed, the substrate holder 1716 is heated by a heater to form a film. The substrate 1700 is heated to a desired temperature (for example, 100° C. or higher or 150° C. or higher), and the source gas supply of inert gas, exhaust by exhaust device 1715, and exhaust by exhaust device 1715. By repeating this process, a thin film is formed on the substrate surface.

[0193] In the film forming apparatus shown in FIG. 5(A), the raw material supply units 1711a and 1711b are provided with By appropriately selecting the raw materials (volatile organometallic compounds, etc.), One selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. Depositing an insulating layer containing an oxide (including a composite oxide) containing the above elements. Specifically, an insulating layer containing hafnium oxide and an insulating layer containing aluminum oxide can be formed. an insulating layer comprising hafnium silicate; or an insulating layer comprising aluminum It is possible to form an insulating layer containing ammonium silicate. The raw materials (volatile organometallic compounds, etc.) are supplied to the raw material supply unit 1711a and the raw material supply unit 1711b. By appropriately selecting the layer, a metal layer such as a tungsten layer or a titanium layer, or a titanium nitride layer, etc. It is also possible to deposit thin films such as nitride layers.

[0194] For example, when a hafnium oxide layer is formed using a film forming apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid In this case, two kinds of gases are used: The first source gas supplied from the source supply unit 1711b is TDMAH, and the second source gas supplied from the source supply unit 1711c is TDMAH. The raw material gas becomes ozone. The chemical formula of tetrakisdimethylamidohafnium is Hf [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Nitrogen has the function of eliminating charge trapping levels. Therefore, when the source gas contains nitrogen, a hafnium oxide film with a low charge trap level density can be formed. It is possible.

[0195] For example, when forming an aluminum oxide layer using a film forming apparatus that uses the ALD method, A raw material gas containing a catalyst and a liquid containing an aluminum precursor compound (such as TMA) is vaporized, and an oxidizing agent is added. In this case, two kinds of gases are used, one of which is a gas containing HCl and the other is H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0196] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0197] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. Alternatively, SiH4 gas may be used.

[0198] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- After that, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a GaO Then, Zn(CH3)2 gas and O3 gas are introduced repeatedly to form a ZnO layer. The order of these layers is not limited to this example. mixed compound layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed. It is also possible to use H2O obtained by bubbling an inert gas such as Ar instead of O3 gas. Although gas may be used, it is preferable to use O3 gas that does not contain H. In(CH 3) Instead of gas In(C2H5)3, gas Ga(CH3)3 may be used. Instead of the gas, Ga(C2H5)3 gas may be used. You can use it.

[0199] <<Multi-chamber film deposition equipment>> Also, a multi-chamber manufacturing apparatus having at least one film forming apparatus shown in FIG. An example is shown in Figure 5(B).

[0200] The manufacturing equipment shown in Figure 5(B) can continuously form laminated films without exposing them to the atmosphere. We aim to prevent impurities from being mixed in and improve throughput.

[0201] The manufacturing apparatus shown in FIG. 5(B) includes a load chamber 1702, a transfer chamber 1720, a pre-treatment chamber 1703, The system has at least a chamber 1701, which is a film-forming chamber, and an unloading chamber 1706. The chambers of the manufacturing equipment (including the load chamber, processing chamber, transfer chamber, deposition chamber, unload chamber, etc.) In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep the pressure reduced, and it is desirable to maintain the pressure reduced.

[0202] In addition, chambers 1704 and 1705 use the same ALD method as chamber 1701. It may be a film forming apparatus, a film forming apparatus using a plasma CVD method, or a sputtering apparatus. The deposition apparatus may be a deposition apparatus using a deposition method, or a metal organic chemical vapor deposition (MOCVD) method. Organic Chemical Vapor Deposition (OCCVD) method The film forming apparatus may be used.

[0203] For example, the chamber 1704 is a film forming device that uses a plasma CVD method. The following is an example of a film deposition system using the MOCVD method as the 1705. show.

[0204] In FIG. 5B, the top view of the transfer chamber 1720 is shown as an example of a hexagonal shape, but it may be changed depending on the number of layers of the laminated film. If necessary, a manufacturing device having a polygonal shape or more and connected to more chambers may be used. In addition, although the top surface shape of the substrate is shown as a rectangle in FIG. 5(B), it is not particularly limited. Although FIG. 5(B) shows an example of a single-wafer type, a batch type film formation in which a film is formed on multiple substrates at once is also possible. It may also be a device.

[0205] <Formation of Insulating Layer 110> First, an insulating layer 110 is formed on a substrate 100. The insulating layer 110 is formed by a plasma CVD method, a thermal For example, aluminum oxide is deposited by CVD (MOCVD, ALD) or sputtering. Nitride, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Oxide insulating films such as tantalum oxide and tantalum oxide, silicon nitride, silicon nitride oxide, and nitride nitride insulating film such as aluminum nitride, aluminum oxide nitride, or a mixture of these materials Alternatively, the insulating layer 121 may be formed by laminating the above materials. The upper layer of the stack in contact with the first insulating film can be a source of oxygen to the semiconductor layer 122. It is preferably formed from a material containing excess oxygen.

[0206] For example, the insulating layer 110 is formed by plasma CVD using silicon oxynitride having a thickness of 100 nm. A membrane can be used.

[0207] Next, a first heat treatment may be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, The heat treatment reduces the amount of water, hydrogen, and the like that diffuses into the first oxide semiconductor film that will be formed later. It is possible.

[0208] <Formation of the first insulating film and semiconductor film> Next, a first insulating film, which will later become an insulator 121, and a semiconductor layer 122 are formed on the insulating layer 110. The first insulating film and the semiconductor film are formed by a sputtering method, an MOCVD method, It can be formed by a PLD method or the like, and is more preferably formed by a sputtering method. The sputtering method used may be RF sputtering, DC sputtering, AC sputtering, etc. In addition, in the sputtering method, the facing target method (facing electrode method, gas phase sputtering method) Sputtering method, VDSP (Vapor Deposition Spattering) method By forming the film by the method (also called the "method"), plasma damage during film formation can be reduced. Cut.

[0209] For example, when the first insulating film is formed by sputtering, each channel in the sputtering device The members use cryopreservation to remove as much water as possible, which is an impurity for oxide semiconductors. A high vacuum (5 x 10) was achieved using an adsorption type vacuum exhaust pump such as -7 Pa~1×10 -4 and the substrate on which the film is to be formed can be heated to 100°C or higher, preferably 40 It is preferable to be able to heat the system to 0°C or higher. Alternatively, a turbomolecular pump and a cold trap can be used. This prevents gases containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is also preferable to use a combination of a turbomolecular pump and a cryopump. A system may also be used.

[0210] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also preferable to use highly purified sputtering gases. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas that has been purified to a level of 1000 ppm, moisture and the like can be taken into the oxide semiconductor film. It can be prevented as much as possible.

[0211] The sputtering gas is a rare gas (typically argon), oxygen gas, or a rare gas and oxygen gas. In the case of a mixture of rare gas and oxygen gas, the rare gas It is preferable to increase the gas ratio of oxygen.

[0212] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, the substrate temperature The temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200°C or higher and 420°C or lower. A film can be formed.

[0213] The material of the first insulating film can be selected so that it has a smaller electron affinity than the semiconductor film. can.

[0214] The semiconductor film has a higher indium content than the first and second insulator films. In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, By increasing the In content, more s orbitals overlap, so In is more dense than Ga. Oxides with a high In content move more easily than oxides with a composition equal to or less than Ga. Therefore, by using an oxide with a high indium content for the semiconductor layer 122, This makes it possible to realize a transistor with high mobility.

[0215] In addition, when the first insulating film and the semiconductor film are formed by, for example, a sputtering method, By using a chamber-type sputtering device, the first insulating film and the semiconductor film are not exposed to the atmosphere. In this case, the interface between the first insulating film and the semiconductor film is This can prevent unnecessary impurities from entering the interface, reducing the interface state density. As a result, the electrical characteristics of the transistor can be stably verified, especially in reliability tests. It can be stabilized.

[0216] In addition, if damage occurs in the semiconductor film, the presence of the first insulating film prevents damage from occurring. This allows the semiconductor film, which acts as an important conductive path, to be kept away from the damaged area, resulting in a transistor. This stabilizes the electrical characteristics of the capacitor, especially the characteristics in reliability tests.

[0217] For example, the first insulating film is formed by sputtering a composition of In:Ga:Zn=1:3: An oxide semiconductor film with a thickness of 20 nm was used, which was formed using a target with an atomic ratio of 4. In addition, a semiconductor film can be formed by sputtering In:Ga:Zn=1:1. An oxide semiconductor film with a thickness of 15 nm was formed using a target with an atomic ratio of 1:1. This can be done.

[0218] It is also preferable to perform a second heat treatment after forming the first insulating film and the semiconductor film. By performing the heat treatment, the amount of oxygen vacancies in the semiconductor film can be reduced.

[0219] The temperature of the second heat treatment is 250°C or higher and lower than the substrate strain point, preferably 300°C or higher and 650°C or lower. °C or less, and more preferably 350°C or more and 550°C or less.

[0220] The second heat treatment is carried out using a rare gas such as helium, neon, argon, xenon, or krypton, or or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point is -80°C or less, preferably -100°C or less, preferably - Heating may be carried out in an air atmosphere at a temperature of 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment time ranges from 3 minutes to 24 hours.

[0221] In the second heating process, heat transfer from a heating element such as a resistance heating element is used instead of an electric furnace. A device that heats the object to be treated by induction or heat radiation may be used. For example, a GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device uses a halogen lamp, a metal Halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The object to be treated is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a high-pressure mercury lamp. The GRTA device is a device that performs a second heat treatment using high-temperature gas. The hot gas is a noble gas such as argon, or an inert gas such as nitrogen. .

[0222] The second heat treatment is performed after etching to form the insulator 121 and the semiconductor layer 122, which will be described later. It may be done after.

[0223] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, The heat treatment can be carried out at 450°C for 1 hour.

[0224] The above steps reduce oxygen vacancies in the semiconductor film and also reduce impurities such as hydrogen and water. Furthermore, a semiconductor film with a reduced localized level density can be formed.

[0225] <Formation of the first conductive film> Next, a first conductive film that will become a source electrode layer 130 and a drain electrode layer 140 is formed on the semiconductor film. The first conductive film is formed by sputtering, chemical vapor deposition (CVD) (organometallic chemical vapor deposition), deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD) or plasma Chemical vapor deposition (PECVD), evaporation, pulsed laser deposition (PLD) It can be formed using the above.

[0226] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r) or alloys, or compounds with these as the main components. It is preferable to use a single layer or a stack of conductive films. For example, when using a stack of conductive films, the semiconductor layer 12 The lower conductive layer in contact with 2 has a material that easily bonds with oxygen, and the upper conductive layer has an oxidation-resistant It is possible to have a material with strong resistance to heat. It is preferable to use a high melting point material such as aluminum ( It is preferable to form the wiring layer from a low-resistance conductive material such as Al (Al) or copper (Cu). When a manganese alloy is used, a film containing manganese oxide is formed at the interface with the insulator containing oxygen, and oxidation Manganese is preferable because it has the function of suppressing the diffusion of Cu.

[0227] For example, a tungsten film having a thickness of 20 to 100 nm is formed on the first conductive layer by sputtering. It can be formed as a film.

[0228] The conductive layer 130b formed by processing the first conductive film in a later step will be In this case, it has a function as a hard mask and a function as a source electrode layer and a drain electrode layer. This eliminates the need for an additional film formation process, thereby shortening the semiconductor manufacturing process. .

[0229] <Formation of insulator 121 and semiconductor layer 122> Next, a resist mask is formed by a lithography process. The first conductive film is selectively partially etched to form the conductive layer 130b. After removing the resist on the layer 130b, the conductive layer 130b is used as a hard mask to form the semiconductor film, The oxide semiconductor film 1 is selectively etched to remove the semiconductor layer 122 and the insulator 121. It can be formed in an island shape (see Figure 6). The etching method is dry etching. The conductive layer 130b can be used as a hard mask to form a semiconductor layer. By etching the first insulating film and the second insulating film, the In comparison, the edge roughness of the oxide semiconductor layer after etching can be reduced.

[0230] For example, methane gas and argon gas are used as etching gases, and the resist mask and The first oxide semiconductor film and the semiconductor film are selectively etched using the hard mask. In this way, the insulator 121 and the semiconductor layer 122 can be formed. 10 may be partially etched.

[0231] <Insulating film formation> Next, an insulating film 173a that will become the insulating layer 173 is formed on the insulating layer 110 and the conductive layer 130b. (See FIG. 7.) The insulating film 173a is formed by a plasma CVD method, a thermal CVD method (MOCVD method, AL D), sputtering, or spin coating, for example, (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride Silicon (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx ), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (Ta Oxide insulating films such as silicon nitride (SiNx) and silicon oxynitride (SiNxO Nitrogen oxides such as aluminum nitride (AlNx), aluminum oxide nitride (AlNxOy) The insulating film can be formed using a compound insulating film of the above material or a mixture of these materials. It may be a laminate.

[0232] Alternatively, the insulating film 173a may be made of a material with a low dielectric constant (low-k material). For example, silicon oxide (SiOF) containing a few percent of fluorine (F) and silicon dioxide containing a few percent of carbon (C) are Silicon dioxide (SiOC), fluorinated silicate glass (FSG), organic silicates Glass (OSG), Hydrogenated Silsesquioxane (HSQ), Methylsilsesquioxane ( MSQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimides, It can be formed by using amorphous carbon to which fluorine is added.

[0233] Note that the second heat treatment may be performed after the insulating film 173a is formed.

[0234] <Planarization of the second insulating film> Next, the insulating film 173a is planarized until the conductive layer 130b is exposed. (See Figure 8.) The planarization process is performed by CMP (Chemical Mechanical Polishing). This can be done by using the Al Polishing method, etc. The thickness of the insulating film 175a on the conductive layer 130b within the plate surface can be made uniform.

[0235] Note that the second heat treatment may be performed after the insulating film 173a is planarized.

[0236] <Insulating film formation> Next, a third insulating film 175a that will become the insulating layer 175 is formed on the insulating layer 173 and the conductive layer 130b. (See Figure 9.)

[0237] The insulating film 175a can be formed using the same material and method as the insulating film 173a.

[0238] <Groove formation> Next, a resist mask 176 is formed on the insulating film 175a by a lithography process (FIG. 10). After applying an organic film onto the insulating film 175a, or after applying a resist The lithography process may be performed after applying an organic film. It contains cholesteryl methyl ether, ethyl lactate, etc., and is an anti-reflective coating (BA) RC (Bottom Anti-Reflective Coating) function In addition, it is possible to improve the adhesion between the resist and the film and improve the resolution.

[0239] When a transistor having an extremely short channel length is formed, at least the source electrode layer 130, in the region dividing the conductive layer 130b which becomes the drain electrode layer 140, an electron beam exposure, immersion exposure, and EUV (Extreme Ultra-violet) exposure. A resist mask is processed using a method suitable for fine line processing such as optical processing, and then the resist is removed by the etching process. The area can be etched by using the electron beam exposure. In this case, if a positive resist is used as the resist mask, the exposed area can be minimized. This allows for improved throughput. To form transistors with channel lengths of 100 nm or less, and even 30 nm or less. Alternatively, microfabrication may be performed by exposure technology using X-rays or the like.

[0240] Using the resist mask, the insulating film 175a is partially etched by dry etching. As a result, the insulating layer 175 is formed and the groove 174 is formed. is formed.

[0241] Subsequently, the exposed conductive layer 130b is partially etched to separate the source electrode layer 13 0, the drain electrode layer 140 can be formed (see FIG. 11).

[0242] After the source electrode layer 130 and the drain electrode layer 140 are formed, etching residues are removed. By this cleaning process, the source electrode layer 130, This can prevent short circuits in the drain electrode layer 140. Alkaline solutions such as tetramethylammonium hydroxide This can be done using acidic solutions such as diluted hydrofluoric acid, oxalic acid, and phosphoric acid. Note that the cleaning process etches a part of the semiconductor layer 122, and the semiconductor layer 122 A recess is formed.

[0243] For example, after the silicon oxynitride film formed as the insulating film 173a is planarized, the silicon oxynitride film is A resist mask is formed on the silicon film by lithography, and the resist mask and the carbon The silicon oxynitride is formed by dry etching using a gas containing fluorine. An opening process is performed, and the conductive layer 130b is dry-etched using a chlorine or fluorine-based gas. In this way, the source electrode layer 130 and the drain electrode layer 140 can be formed.

[0244] <Formation of second insulating film 123a> Next, a second insulating film used as an insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulating film 123a is formed in the same manner as the first insulating film. The second insulating film 123a can be formed so as to have a smaller electron affinity than the semiconductor film. The material can be selected accordingly.

[0245] For example, the second insulating film 123a may be formed by sputtering In:Ga:Zn= Using a target with an atomic ratio of 1:3:2, a 5-nm-thick oxide semiconductor film was formed. It is possible.

[0246] <Formation of insulating film 150a> Next, an insulating film 150a that will become the gate insulating layer 150 is formed on the second insulating film 123a. The insulating film 150a is made of, for example, aluminum oxide (AlOx), magnesium oxide (M silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, silicon dioxide lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating film 150a may be a laminate of the above materials. 0a is a method using sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), M The insulating film 150a can be formed by using the BE method or the like. An insulating film can be formed by appropriately using a similar method.

[0247] For example, a silicon oxynitride film of 10 nm is formed as the insulating film 150a by the plasma CVD method. It is possible.

[0248] <Formation of Conductive Film 160a> Next, a conductive film 160a that will become a gate electrode layer 160 is formed on the insulating film 150a (see FIG. 1). 2). The conductive film 160a may be made of, for example, aluminum (Al), titanium (Ti), Chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y ), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or a material consisting primarily of these The conductive film 160a can be formed by a sputtering method or a CVD method (a method using a plasma CVD method). plasma CVD, MOCVD, ALD, etc.), MBE, vapor deposition, plating, etc. The conductive film 160a can be formed by using a conductive film containing nitrogen. Alternatively, a laminate of the above conductive film and a conductive film containing nitrogen may be used. It may be a single layer or a laminate.

[0249] For example, titanium nitride is formed to a thickness of 10 nm by the ALD method, and tungsten is deposited by metal CVD. A laminated structure formed to a thickness of 150 nm by a method can be used.

[0250] <Flattening process> Next, a planarization process is performed using a CMP method, dry etching method, etc. The planarization process may be completed when the insulating film 150a is exposed, or may be completed after the first The process may be terminated when the insulating film 123a of the second insulating film 123 is exposed, or when the insulating layer 175 is exposed. This may be completed by forming the gate electrode layer 160, the gate insulating layer 150, and the insulating layer 12. 3 can be formed (see Figure 13).

[0251] The second insulating film 123a or the insulating film 150a is formed on the planarized insulating layer 175. If the second insulating film 1 has a resist mask, it may be processed using a new resist mask. A resist mask is formed on the insulating film 23a or the insulating film 150a by a lithography process. The mask has an area larger than the upper surface of the gate electrode layer 160. The insulating film 150a and the second insulating film 123a are selectively etched to form the gate insulating layer. 150, an insulator 123 can be formed.

[0252] In the transistor 10, by providing the insulator 123 in which oxygen vacancies are unlikely to occur, Oxygen desorption from the side surface of the insulator 123 in the channel width direction is suppressed, and oxygen vacancies are prevented. As a result, electrical characteristics are improved and highly reliable transistors are produced. This can be realized.

[0253] <Deposition of insulating layer 170> Next, the insulating layer 173, the insulator 123, the gate insulating layer 150, and the gate electrode layer 160 are An insulating layer 170 is then deposited.

[0254] The insulating layer 170 is formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), or a silicon carbide (SiO2) method. For example, aluminum oxide (AlOx), magnesium oxide (MgO x), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide ( GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide Zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide oxide insulating films such as tantalum oxide (HfOx) and tantalum oxide (TaOx), silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum nitride (AlNx), The insulating film is made of nitride such as aluminum oxide (AlNxOy), or a mixture of these materials. The insulating layer 170 may be formed of a laminate of the above materials. For the insulating layer, an oxide containing In or Zn may be used. Representative examples include In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd).

[0255] The insulating layer 170 is formed by depositing an aluminum oxide film by sputtering. It is also desirable to use aluminum oxide as the sputtering target. It is also desirable that the gas used during film formation contains oxygen gas.

[0256] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 173. do.

[0257] For example, the oxygen gas used in forming the insulating layer 170 is applied when forming the film by sputtering. Due to the influence of the applied voltage, power, plasma, and substrate temperature, oxygen radicals, oxygen ions, Oxygen atoms exist in various states and have higher energy states than the stable state. At this time, oxygen (excess oxygen, exO) 172 forms an insulating layer 173 or a mixed layer. It is added in layer 171 .

[0258] <Oxygen addition> Furthermore, the method for manufacturing the transistor 10 is not limited to the above method. The oxygen addition treatment may be performed on the insulating layer 110 or on the first insulating layer 110. The oxygen addition may be performed on the oxide semiconductor film or the second insulating film 123a. as one or more of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The oxygen doping method includes ion doping, ion implantation, and proton injection. There are methods such as plasma immersion ion implantation.

[0259] When ion implantation is used as a method for adding oxygen, oxygen atomic ions can be used. Alternatively, oxygen molecular ions may be used. When oxygen molecular ions are used, the amount of oxygen added to the film increases. The oxygen molecular ions are released from the surface of the film to which the oxygen is added. The oxygen molecules are separated into oxygen atoms and added as oxygen atom ions. Since energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added, The energy per oxygen atom ion in This is lower than when oxygen is added to the film. Therefore, damage to the film to which the oxygen is added is reduced. It can be reduced.

[0260] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low, so it is possible to implant oxygen molecular ions. This allows for a higher acceleration voltage and therefore a higher throughput. In addition, by using oxygen molecular ions for implantation, compared to when oxygen atomic ions are used, It is possible to halve the dose to add the same amount of oxygen atomic ions. As a result, the throughput of the manufacturing process can be increased.

[0261] In addition, when oxygen is added to the film to which oxygen is added, oxygen atoms are added to the film to which oxygen is added. The oxygen is added under the conditions that the peak of the concentration profile of the molecular ions is located. It is preferable to add oxygen to the film to be formed. As a result, compared to the case of implanting oxygen atomic ions, In addition, the acceleration voltage during implantation can be lowered, reducing damage to the film to which the oxygen is added. That is, the amount of defects in the film to which oxygen is added can be reduced, As a result, the change in the electrical characteristics of the transistor can be suppressed. This reduces damage to the film that is being processed, and suppresses fluctuations in the electrical characteristics of the transistor. It can be controlled.

[0262] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible to increase the amount of added gas, which is preferable. An example of an apparatus for performing such plasma treatment is shown below. As an example, there is an ashing device.

[0263] For example, the acceleration voltage is 5 kV and the dose is 1 × 10 16 / cm 2 The oxygen molecule ions The first oxide semiconductor film can be doped by an on-implantation method.

[0264] By combining the above steps and the subsequent heat treatment, the oxygen deficiency of the semiconductor layer 122 is reduced. The film to which oxygen has been added is different from the film before oxygen is added. In comparison, the film density is low.

[0265] Next, a third heat treatment may be performed. The third heat treatment is typically performed at a temperature of 150° C. or higher. Less than the plate strain point, preferably 250°C or more and 500°C or less, more preferably 300°C or more and 45°C or less The temperature can be set to 0°C or lower. By this heat treatment, the added oxygen 172 diffuses and The oxygen migrates to the conductor layer 122 and compensates for the oxygen vacancies present in the semiconductor layer 122. This can be done (see Figure 14).

[0266] For example, by sputtering, using an aluminum oxide (AlOx) target, The insulating layer 170 is formed using a sputtering gas containing 50% by volume of oxygen gas. The thickness can be 20 nm to 40 nm. As a practical example, it can be heat-treated at 400°C for 1 hour in an oxygen atmosphere.

[0267] By the above process, the localized level density of the semiconductor film is reduced, and a transistor having excellent electrical properties is obtained. It is also possible to produce a transistor that can withstand changes in electrical characteristics due to aging or stress testing. Therefore, highly reliable transistors with fewer defects can be manufactured.

[0268] (Embodiment 2) In this embodiment, a transistor having a structure different from that of the transistor 10 described in the first embodiment is used. The manufacturing methods of the transistor 11 and the transistor 12 will be described.

[0269] <Modification 1 of Transistor 10: Transistor 11> Regarding the transistor 11, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 15 to explain.

[0270] 15(A), 15(B), and 15(C) are a top view and a cross-sectional view of the transistor 11. FIG. 15(A) is a top view of the transistor 11, and FIG. 15(B) is a top view of the transistor 11. 15(B) is a cross-sectional view taken along the dashed line A1-A2, and FIG. 15(C) is a cross-sectional view taken along the dashed line A3-A4.

[0271] The transistor 11 has an insulating layer 170 that is made up of an insulator 121, a semiconductor layer 122, and a source electrode layer 13. 0, the transistor has a region in contact with the side surfaces of the drain electrode layer 140 and the insulating layer 175. Different from Sta. 10.

[0272] The transistor 11 includes an insulator 121, a semiconductor layer 122, a source electrode, and a The layer 130, the drain electrode layer 140, and the insulating layer 175 are formed in the same process. This method differs from the method for manufacturing the transistor 10 in that no planarization process is performed during this step.

[0273] <Method for manufacturing transistor 11> A manufacturing method of the transistor 11 will be described with reference to FIGS. For steps similar to those for the transistor 10 described above, the same description is used.

[0274] As shown in FIGS. 16A and 16B, the insulating layer 110 and the first insulating layer 121 are The insulating film 121a, the semiconductor film 122a that becomes the semiconductor layer 122, the source electrode layer 130, and the drain electrode layer 130 are The conductive film 130a that will become the rain electrode layer 140 and the insulating film 175a that will become the insulating layer 175 are formed. A resist mask 176 is formed on the insulating film 175a by lithography.

[0275] Next, the insulating film 175a and the conductive film 130a are partly etched using a resist mask 176. Then, grooves 174, an insulating layer 175b, and a conductive layer 130b are formed (see FIG. 17).

[0276] Next, the insulating layer 175b, the conductive layer 130b, the semiconductor film 122a, and the The insulating film 121a of the first insulating film 121 is partially etched, and the insulating film 121, the semiconductor layer 122, and the source electrode The layer 130, the drain electrode layer 140, and the insulating layer 175 are formed (see FIG. 18).

[0277] Next, a second insulating film 123a that will become the insulator 123 and an insulating film 123b that will become the gate insulating layer 150 are formed. 50a, and a conductive film 160a that will become the gate electrode layer 160 are sequentially formed (see FIG. 19).

[0278] Next, a resist mask formed by lithography is used to form the conductive film 160a and the insulating film 160b. The insulating film 150a and the second insulating film 123a are partially etched, and the insulating film 123 and the A gate insulating layer 150 and a gate electrode layer 160 are formed (see FIG. 20).

[0279] The insulator 123, the gate insulating layer 150, and the gate electrode layer 160 do not have to be formed at the same time. As shown in FIGS. 21 and 22, the insulating film 150a may be formed by etching the insulator 123. 123 and the gate insulating layer 160 may be formed. The end portions of the gate electrode layer 50 and the gate electrode layer 160 may be formed so as not to overlap each other.

[0280] Next, an insulating layer 170 is formed and heat treatment is performed to diffuse oxygen 172 into the semiconductor layer 122. This can reduce oxygen vacancies in the semiconductor layer 122 (see FIG. 23).

[0281] Through the above steps, the transistor 11 can be manufactured.

[0282] In the method for manufacturing the transistor 11, the insulating film 175a that becomes the insulating layer 175 is formed on the source electrode layer 1 30, the conductive film 130a that will become the drain electrode layer 140 can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the etching during the formation of the groove portion 174 can be performed. This allows the transistor 11 to be stably turned on. Therefore, the transistor shape can be stabilized. The transistor characteristics can be stabilized.

[0283] <Modification 2 of Transistor 10: Transistor 12> Regarding the transistor 12, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 24 to explain.

[0284] 24(A), 24(B), and 24(C) are a top view and a cross-sectional view of the transistor 12. 24(A) is a top view of the transistor 12, and FIG. 24(B) is a top view of the transistor 12. 24(B) is a cross-sectional view taken along the dashed line A1-A2 of FIG. 24(B), and FIG. 24(C) is a cross-sectional view taken along the dashed line A3-A4 of FIG. 24(B).

[0285] Transistor 12 differs from transistor 10 in that it has an insulating layer 177 .

[0286] As will be described later, the first insulating film 121a that becomes the insulator 121, the semiconductor layer 122, and the conductive film 122a to be the source electrode layer 130 and the drain electrode layer 140; 30a, an insulating film 175a that will become the insulating layer 175, and an insulating film 177a that will become the insulating layer 177. This method differs from the method for manufacturing the transistor 10 in that the above films are formed before processing.

[0287] <Method for manufacturing transistor 12> A method for manufacturing the transistor 12 will be described with reference to FIGS. For steps similar to those for the transistor 10 described above, the same description is used.

[0288] On the insulating layer 110, a first insulating film 121a which becomes the insulator 121 and a semiconductor layer 122 are formed. The conductive film 122a, the conductive film 130a that will become the source electrode layer 130 and the drain electrode layer 140 , an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. Before processing, films are formed in sequence (see Figure 25).

[0289] The insulating layer 177 can be formed using the same material and method as the insulating layer 170. Cut.

[0290] Next, a resist mask is used to remove the insulating film 177a, the insulating film 175a, the conductive film 130a, and the semiconductor The insulating film 122a and the first insulating film 121a are partially etched to leave the insulating film 121 and the semiconductor layer 122, a conductive layer 130b, an insulating layer 175b, and an insulating layer 171b are formed (see FIG. 26). At this time, the insulating layer 110 may be partially etched.

[0291] Next, an insulating film 173a that will become the insulating layer 173 is formed (see FIG. 27). , plasma CVD method, thermal CVD method (MOCVD method, ALD method), sputtering method, or It can be formed by a coating method or the like.

[0292] Next, the insulating film 173a is planarized by CMP until the insulating layer 171b is exposed. The insulating layer 171b is formed by the above steps (see FIG. 28). The polishing rate is low under the same CMP processing conditions as the stopper. It is preferable that the compound has the ability to

[0293] Next, a resist mask is formed on the insulating layer 173 and the insulating layer 171b by lithography. Then, using the insulating layer 171b as a hard mask, the semiconductor layer 122 is exposed. The conductive layer 130b is selectively etched by etching. This leaves the source electrode layer 130 and The drain electrode layer 140 and the insulating layer 175 are formed (see FIG. 29).

[0294] Next, a second insulating film 123a, an insulating film 150a, and a conductive film 160a are formed in this order (FIG. 3). 0).

[0295] Next, the conductive film 160a, the insulating film 150a, and the second insulating film 123a are subjected to a planarization process. 31. see).

[0296] Next, an insulating layer 170 is formed, and heat treatment is performed to remove oxygen 172 up to the semiconductor layer 122. This allows the diffusion to reduce oxygen vacancies in the semiconductor layer 122 (see FIG. 32).

[0297] Through the above steps, the transistor 12 can be manufactured.

[0298] In the method for manufacturing the transistor 12, the insulating film 175a that will become the insulating layer 175 is formed on the source electrode layer 1 30, the conductive film 130a that will become the drain electrode layer 140 can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the etching during the formation of the groove portion 174 can be performed. This allows the transistor 12 to be stably turned on. Therefore, the transistor shape can be stabilized. The transistor characteristics (for example, threshold value, reliability, etc.) can also be stabilized.

[0299] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0300] (Embodiment 3) <Oxide semiconductor structure> In this embodiment, a structure of an oxide semiconductor will be described.

[0301] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0302] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, nc-OS, etc.

[0303] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. It can also be described as a structure that has order but does not have long-range order.

[0304] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is converted into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a device that can achieve periodicity in a microscopic area. Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0305] <caac-os> First, let me explain about CAAC-OS.

[0306] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0307] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0308] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0309] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 33(A) is shown in FIG. 33(B). From Figure 33(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0310] As shown in Figure 33(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 33(B) and Figure 33(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used for CANC (C-Axis Aligned Nanocry The oxide semiconductor may also be called an oxide semiconductor having a crystalline structure.

[0311] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See Figure 33(D)). The inclination between the pellets observed in Figure 33(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 33(D).

[0312] In addition, Figure 34(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 34(A). Enlarged Cs-corrected high-resolution TEM images are shown in Figure 34(B), Figure 34(C), and Figure 34(D), respectively. 34(D). From Fig. 34(B), Fig. 34(C) and Fig. 34(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0313] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 35(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0314] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0315] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 35(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 35(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0316] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 36(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 36(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 36(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 36(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0317] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so we take the opposite view. CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0318] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0319] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0320] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0321] <nc-os> Next, we will explain nc-OS.

[0322] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor with a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are It may not be possible to clearly identify the nanocrystals. Therefore, the crystalline part of nc-OS is referred to as the pellet below. There may be cases where this happens.

[0323] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. For example, for nc-OS, there are cases where it is difficult to distinguish between X particles with a diameter larger than that of the pellet. When using X-rays, peaks indicating crystal planes are not detected in the out-of-plane analysis. In addition, for nc-OS, a probe diameter larger than the pellet (for example, 50n When electron diffraction is performed using an electron beam (over 1000 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than the pellet. When nanobeam electron diffraction is performed using an electron beam with a diameter of n, spots are observed. When nanobeam electron diffraction is performed on c-OS, a circular (ring-shaped) bright spot appears. In some cases, a ring-shaped area is observed. In addition, multiple spots are observed within the ring-shaped area. There are cases where this happens.

[0324] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0325] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0326] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0327] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0328] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0329] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0331] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0332] Figure 37 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 37 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 37, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0333] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0334] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0335] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0336] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0337] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0338] (Fourth embodiment) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in a drawing. Please refer to the following for explanation.

[0339] <Cross-sectional structure> FIG. 38A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part, In FIG. 38(A), a transistor 2100 using a second semiconductor material is provided in the semiconductor layer. As the transistor 2100 using the second semiconductor material, the transistor exemplified in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The right side is a cross section in the longitudinal direction, and the left side is a cross section in the channel width direction.

[0340] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide the second semiconductor (e.g., gallium gallium, indium phosphide, gallium nitride, organic semiconductors, etc.); The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can easily operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0341] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either of these transistors may be used, and an appropriate transistor may be used depending on the circuit. The transistor of one embodiment of the present invention using a nitride semiconductor is used, and other materials and structures are not limited to these. However, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0342] In the structure shown in FIG. 38A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate allow wiring provided on the upper and lower layers to be The electrodes are electrically connected to the insulator 2204 covering the transistor 2100. , and a wiring 2205 is provided on the insulator 2204 .

[0343] In this way, stacking two types of transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0344] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is converted into silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that cause the reliability of the transistor 2100 to decrease. Therefore, the upper layer of the transistor 2200 made of silicon-based semiconductor material is oxidized. When the transistor 2100 using a compound semiconductor is stacked, hydrogen diffusion between them It is particularly effective to provide an insulator 2207 that has the function of preventing the 7 improves the reliability of the transistor 2200 by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, and thus the transistor 2100 At the same time, reliability can be improved.

[0345] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0346] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film on the surface of the substrate 2100, which has the function of preventing hydrogen diffusion. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to use an aluminum oxide film. The aluminum oxide film is resistant to hydrogen, moisture, etc. It has a high blocking effect, preventing both impurities and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film covering the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. At the same time, water and hydrogen can be prevented from entering the oxide semiconductor film. The blocking film may be used by laminating the insulator 2204 or by forming a blocking film under the insulator 2204. It may be provided on the side.

[0347] The transistor 2200 is not limited to a planar transistor, but may be any of various types. It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in FIG. 38(D). An insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at its tip. Note that an insulator may be provided on the convex portion. That insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not have to have a thin tip. For example, it may be a substantially rectangular parallelepiped convex portion or a convex portion with a thick tip. <00‎02807>A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. [[ID=2‎0]]For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. It does not matter.

[0348] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0349] <CMOS inverter circuit> The circuit diagram shown in FIG. 38(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. The configuration of the S inverter is shown.

[0350] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 38C shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0351] <Example of storage device> By using a transistor according to one embodiment of the present invention, it is possible to preserve stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0352] The semiconductor device shown in FIG. 39A includes a transistor 3200 using a first semiconductor material and a second semiconductor material. The semiconductor device includes a transistor 3300 and a capacitor 3400 made of two semiconductor materials. Note that the transistor described in Embodiments 1 and 2 is used as the transistor 3300. You can be there.

[0353] 39(B) shows a cross-sectional view of the semiconductor device shown in FIG. In the figure, a configuration in which a back gate is provided in the transistor 3300 is shown. It may be configured not to provide.

[0354] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that This means that the memory contents can be retained for a longer period of time without requiring a refresh operation. Alternatively, the semiconductor memory device may be one in which the frequency of refresh operations is extremely low. This makes it possible to sufficiently reduce power consumption.

[0355] In FIG. 39A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor 3200. The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0356] In the semiconductor device shown in FIG. 39A, the potential of the gate electrode of the transistor 3200 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0357] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, the charge that gives two different potential levels is (hereinafter referred to as Low level charge and High level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to the port electrode is retained (retention).

[0358] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long time.

[0359] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor The second wiring 3002 is at a different potential depending on the amount of charge held in the gate electrode of the capacitor 3200. In general, if the transistor 3200 is an n-channel type, then the transistor 3200 The apparent threshold voltage V when a high level charge is applied to the gate electrode of th_H is seen when a low level charge is applied to the gate electrode of transistor 3200. Threshold V th_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L Between By setting the potential V0, the charge given to the gate electrode of the transistor 3200 is determined. For example, if a high level charge is applied during writing, The potential of the wiring 3005 of 5 is V0 (>V th_H ), then transistor 3200 is "ON" When a low level charge is applied, the voltage of the fifth wiring 3005 is The digit is V0( <V th_L ), transistor 3200 remains in the "off state." Therefore, the stored data can be read by determining the potential of the second wiring 3002. You can put it out.

[0360] When memory cells are arranged in an array, only the information in the desired memory cell can be read. For example, in a memory cell from which information is not read, the gate voltage The potential at which transistor 3200 is in the "off state" regardless of the polarity state, i.e., V th_H By applying a smaller potential to the fifth wiring 3005, the information of the desired memory cell is Alternatively, in a memory cell from which information is not read, , a potential at which transistor 3200 is "on" regardless of the state of its gate electrode. , that is, V th_L By applying a larger potential to the fifth wiring 3005, a desired memory It is sufficient to have a configuration that allows only the information in the cells to be read out.

[0361] The semiconductor device shown in FIG. 39(C) is different from the semiconductor device shown in FIG. 39(A) in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible.

[0362] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed between the capacitors 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the potential of one of the electrodes of the capacitor 3400 ( Alternatively, it takes on different values ​​depending on the charge stored in the capacitor element 3400.

[0363] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the electrodes of the electrode 3400 takes two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+C×V0) / (CB+C)).

[0364] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0365] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be stacked on the driver circuit.

[0366] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0367] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the electrons. For example, unlike conventional non-volatile memory, there is no floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0368] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple If several cases are possible, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations for only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0369] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0370] In this specification, etc., in a drawing or text that describes one embodiment, It is possible to extract a part of it and use it to constitute an aspect of the invention. If a drawing or text describing a certain part is included, the drawing or text of that part is omitted. The above content is also disclosed as one aspect of the invention and constitutes one aspect of the invention. Therefore, for example, active elements (transistors, diodes) etc.), wiring, passive elements (capacitive elements, resistive elements etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings depicting materials, inorganic materials, parts, devices, methods of operation, manufacturing methods, etc. Or, in a sentence, a part of it can be taken out and used to constitute one aspect of the invention. It is assumed to be so. For example, having N (N is an integer) circuit elements (transistors, capacitor elements, etc.) From a circuit diagram constituted, it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) and constitute one aspect of the invention. As another example, From a cross-sectional view constituted of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers and constitute one aspect of the invention. As yet another example, from a flowchart constituted of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N ) elements and constitute one aspect of the invention.

[0371] <Imaging device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0372] FIG. 40(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 has a pixel portion 210, a peripheral circuit 260 for driving the pixel portion 210, and peripheral circuits 270, 280, and 290. The pixel portion 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 each have a function of connecting to a plurality of pixels 211 and supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit" in some cases. For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0373] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0374] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. , the peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290 One or more of these may be omitted.

[0375] As shown in FIG. 40B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0376] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0377] FIG. 41(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 41(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. A sub-pixel 212 is provided with a color filter that transmits light in the wavelength bands of blue (B) and blue (C). (hereinafter also referred to as "sub-pixel 212B"). It can be made to function.

[0378] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, in the nth line (n is an integer between 1 and p), The wiring 248 and the wiring 249 connected to the pixel 211 of and wiring 249[n]. For example, in the m-th column (m is an integer between 1 and q), The wiring 253 connected to the pixel 211 is referred to as wiring 253[m]. ), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is connected to the wiring 2 53[m]R, the wiring 253 connected to the sub-pixel 212G is the wiring 253[m]G, and the sub-pixel The wiring 253 connected to the subpixel 212B is described as wiring 253[m]B. , and are electrically connected to the peripheral circuits via the wiring.

[0379] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light in the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. FIG. 41B shows a pixel 211 arranged in n rows and m columns, and a sub-pixel 212 of the pixel 211. 11 shows an example of connection of a sub-pixel 212 included in a pixel 211 arranged in the n+1th row and mth column adjacent to the pixel 11. In FIG. 41(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the n+1th row and mth column are The sub-pixels 212R arranged in n rows and m columns are connected via the switches 201. The sub-pixel 212G arranged in the n+1th row and the mth column is connected to the switch 202. The sub-pixels 212B arranged in the nth row and the mth column are connected via the The sub-pixel 212B arranged at the center is connected via the switch 203.

[0380] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels for detecting light of three different wavelength bands. By providing 212, a full color image can be obtained.

[0381] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have sub-pixels 2 that detect light in four different wavelength bands. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0382] Also, for example, in FIG. 41A, the sub-pixel 212 for detecting the red wavelength band, the sub-pixel 213 for detecting the green wavelength band, The ratio of the number of sub-pixels 212 detecting the blue wavelength band to the number of sub-pixels 212 detecting the blue wavelength band ( For example, the pixel ratio (or light receiving area ratio) does not have to be 1:1:1. ) may be a Bayer array with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0383] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that there are two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0384] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0385] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0386] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 42(A), a lens 255 and a filter 25 are formed in the pixel 211. 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0387] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is reflected by the wiring 257. Therefore, as shown in Figure 42(B), A lens 255 and a filter 254 are arranged on the conversion element 220 side, and the photoelectric conversion element 220 It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. can be done.

[0388] The photoelectric conversion element 220 shown in FIG. 42 is formed with a pn-type junction or a pin-type junction. A photoelectric conversion element may also be used.

[0389] The photoelectric conversion element 220 is made of a material that has the function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be a ceramic. Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0390] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0391] Here, one pixel 211 included in the imaging device 200 has, in addition to the sub-pixel 212 shown in FIG. 2. The pixel 212 may have a first filter.

[0392] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of configuring a pixel using the above will be described.

[0393] 43(A) and 43(B) are cross-sectional views of elements that constitute the imaging device.

[0394] The imaging device shown in FIG. 43(A) is a silicon-based transistor provided on a silicon substrate 300. a transistor 351 using an oxide semiconductor and stacked over the transistor 351; The transistor 352 and the transistor 353 are provided on the silicon substrate 300. Each transistor includes a photodiode 360 ​​having an anode 361 and a cathode 362. The photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 ​​has a low resistance region 363. 370 and has an electrical connection therethrough.

[0395] The imaging device also includes a transistor 351 and a photodiode 352 provided on the silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and a layer 320, which are provided in contact with the layer 320 and have a transistor 352 and a transistor 353. and a layer 330 provided in contact with the layer 330 and having wiring 372 and wiring 373. It has 40.

[0396] In the example of the cross-sectional view of FIG. 43(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0397] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0398] In the cross-sectional view of FIG. 43(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0399] In addition, in FIG. 43(B), the imaging device has a photodiode 365 on the layer 340 side. In FIG. 43(B), for example, the layer 310 may have a structure in which: The layer 320 has a silicon transistor 351 and a silicon transistor 352. 71, and the layer 330 includes a transistor 352 using an oxide semiconductor, and a transistor 35 3, and the layer 340 has a photodiode 365, and the photodiode 365 It is composed of semiconductor layers 366, 367, and 368, and has wiring 373 and a protrusion 374. It is electrically connected to wiring 374 via lug 370 .

[0400] By using the element configuration shown in FIG. 43(B), the aperture ratio can be increased.

[0401] The photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. The photodiode 365 may be an n-type semiconductor. The layer 368, the i-type semiconductor layer 367, and the p-type semiconductor layer 366 are stacked in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are provided with dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a pentapent can be used. The photodiode 365, which uses silicon as a photoelectric conversion layer, has high sensitivity in the visible light wavelength range. High sensitivity and easy detection of weak visible light.

[0402] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0403] (Embodiment 5) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is used. The tag will be described with reference to FIG.

[0404] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems. High reliability is required.

[0405] The structure of an RF tag will be described with reference to Fig. 44. Fig. 44 is a block diagram showing an example of the structure of an RF tag. FIG.

[0406] As shown in FIG. 44, an RF tag 800 includes a communicator 801 (also known as an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 808. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor showing the rectification action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of achieving this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and communicating through mutual induction. electromagnetic coupling, electromagnetic induction, which communicates by induced electromagnetic fields; and radio wave communication. The RF tag 800 shown in this embodiment can be used with any of these methods. It can also be used for

[0407] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side or A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent power above a certain level from being input to the subsequent circuit. This is a circuit for controlling the

[0408] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0409] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the received signal.

[0410] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0411] The above-mentioned circuits can be selected or omitted as appropriate.

[0412] Here, the transistor described in the above embodiment can be used in the memory circuit 810. The transistor according to one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly lower than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance between when reading and writing data. Furthermore, it prevents malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0413] Furthermore, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data so that users cannot freely rewrite it. It is preferable that the manufacturer writes a unique number on the product before shipping it. Instead of assigning a unique number to all RF tags produced, we only assign a unique number to non-defective products that are shipped. It is now possible to assign unique numbers to products, preventing discontinuities in the unique numbers of products after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0414] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0415] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0416] FIG. 45 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0417] <cpu> The CPU shown in FIG. 45 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 45 is merely an example of a simplified configuration. There are various configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 45 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0418] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0419] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0420] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0421] In the CPU shown in FIG. 45, a memory cell is provided in the register 1196. The transistors described in any of Embodiments 1 to 3 can be used as the memory cells of 1196. can.

[0422] In the CPU shown in FIG. 45, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0423] <Recording circuit> FIG. 46 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0424] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the load such as a resistor. The circuit is configured to be grounded.

[0425] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The terminal corresponds to one of the source and drain electrodes of the transistor 1213, and the terminal corresponds to the switch 120. The second terminal of the transistor 1213 corresponds to the other of the source and drain electrodes of the transistor 1213. The first switch 1203 is turned on by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on state of transistor 1213) The first terminal of the switch 1204 is connected to the transistor 121. The second terminal of the switch 1204 corresponds to one of the source and drain electrodes of the transistor 4. The switch 1204 corresponds to the other of the source and drain electrodes of the transistor 1214. The control signal RD input to the gate of the resistor 1214 controls the first and second terminals. The conduction or non-conduction between the two (i.e., the on or off state of the transistor 1214) is selected. It is selected.

[0426] One of the source electrode and the drain electrode of the transistor 1209 is connected to the pair of capacitors 1208. The transistor 1210 is electrically connected to one of the electrodes and the gate of the transistor 1210. The connection point is a node M2. The other side is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line), The other terminal is connected to the first terminal of the switch 1203 (the source and drain electrodes of the transistor 1213). The second terminal of the switch 1203 (one of the electrodes of the transistor 12 The other of the source and drain electrodes of transistor 13 is connected to the first terminal of switch 1204 (transistor The switch 120 is electrically connected to the source electrode or the drain electrode of the switch 1214. The second terminal of the transistor 1214 (the other of the source and drain electrodes of the transistor 1214) is connected to the power supply potential. The second terminal of the switch 1203 is electrically connected to a wiring that can supply VDD. the other of the source electrode and drain electrode of the transistor 1213 and the a first terminal (one of the source electrode and the drain electrode of the transistor 1214) and a logic element 1 The input terminal of the capacitor 1206 is electrically connected to one of a pair of electrodes of the capacitor 1207. Here, the connection point is referred to as a node M1. For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 7 is connected to a wiring (for example, GND) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a For example, a low power supply potential (GND, etc.) or a high power supply potential can be input. A voltage (such as VDD) can be input to the pair of electrodes of the capacitor 1208. The other one is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). To be continued.

[0427] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0428] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0429] In the transistor 1209 in FIG. 46, the second gate (second gate electrode: back The first gate receives a control signal WE, and the second gate receives a control signal WE. The control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the solenoid voltage of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the potential of the source electrode. This is the potential signal for controlling the threshold voltage of the resistor 1209. The gate voltage VG is 0V. In addition, the control signal WE2 has the same voltage as the control signal WE. The transistor 1209 may be a transistor without a second gate. A transistor may also be used.

[0430] The other of the source electrode and the drain electrode of the transistor 1209 is connected to a In FIG. 46, the signal output from the circuit 1201 is In this example, the signal is input to the other of the source electrode and the drain electrode of the transistor 1209. The second terminal of the transistor 1203 (the other of the source and drain electrodes of the transistor 1213) ) is an inverted signal whose logical value is inverted by logic element 1206. This is input to the circuit 1201 via the circuit 1220.

[0431] In FIG. 46, the second terminal of the switch 1203 (the source electrode of the transistor 1213) The signal output from the drain electrode (the other of the drain electrodes) is transmitted to the logic element 1206 and the circuit 1220. However, the present invention is not limited to this example. The signal output from the terminal 2 (the other of the source electrode and drain electrode of the transistor 1213) The signal may be input to the circuit 1201 without being inverted. A node in which a signal whose logical value is the inverse of the signal input from the input terminal is held is provided in the circuit 1201. When a voltage is present, the second terminal of the switch 1203 (the source voltage of the transistor 1213) A signal output from the other of the gate electrode and drain electrode can be input to this node.

[0432] In addition, in FIG. 46, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may also include a transistor in which the channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is connected to the gate of the transistor.

[0433] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0434] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0435] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when the power supply voltage is not supplied to 200, the signal held in the capacitor element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0436] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0437] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0438] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0439] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R It can also be applied to F (Radio Frequency) tags.

[0440] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0441] (Embodiment 7) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0442] <Display device circuit configuration example> FIG. 47A is a top view of a display device of one embodiment of the present invention, and FIG. 47B is a top view of a display device of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. 47C is a circuit diagram showing a pixel of a display device according to one embodiment of the present invention. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0443] The transistors arranged in the pixel portion can be formed according to any of Embodiments 1 to 3. In addition, since the transistor can be easily made into an n-channel type, it is possible to use an n-channel transistor in the driver circuit. A part of the driver circuit that can be configured with a channel transistor is connected to the transistor of the pixel portion. In this way, the transistors shown in the above embodiment modes are formed in the pixel portion and the driver circuit. By using the photoresist, a highly reliable display device can be provided.

[0444] An example of a top view of an active matrix display device is shown in Figure 47(A). On the display panel 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 70 3, a signal line driver circuit 704. A plurality of signal lines are connected to the pixel portion 701 via the signal line driver circuit 704. 704, and a plurality of scanning lines are connected to the first scanning line driving circuit 702 and the second scanning line driving circuit 703. The scanning lines are arranged in a direction extending from the scanning line driving circuit 703. In each of the display devices, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection part such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via

[0445] In FIG. 47A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. This reduces the number of components, such as the drive circuit, that are required on the board 7, thereby reducing costs. If a driver circuit is provided outside the 00, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield. Any one of the circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is mounted on the substrate 70. 0 or may be provided outside the substrate 700.

[0446] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in Figure 47(B). 1 shows a pixel circuit that can be applied to a pixel of a display device.

[0447] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0448] The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 have different On the other hand, the signal line 714 is separated so that a gate signal can be applied. The transistor 716 and the transistor 717 share the same The transistor 717 can be any of the transistors described in any of Embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0449] The transistor 716 is electrically connected to a first pixel electrode layer. The second pixel electrode layer is electrically connected to the first pixel electrode layer 17. The first pixel electrode layer and the second pixel electrode layer are separated from each other. For example, the first pixel electrode layer may be V-shaped.

[0450] The gate electrode of the transistor 716 is connected to the scanning line 712, and the gate electrode of the transistor 717 is connected to the scanning line 712. The gate electrode is connected to the scanning line 713. Different gate signals are applied to the scanning lines 712 and 713. By giving a signal to the transistor 716 and the transistor 717, the operation timing is made different. The orientation of the molecules can be controlled.

[0451] Also, the capacitor wiring 710, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0452] In the multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0453] It should be noted that the pixel circuit shown in FIG. 47(B) is not limited to this. For example, The pixel circuit is newly equipped with switches, resistors, capacitors, transistors, sensors, or logic elements. Circuits etc. may be added.

[0454] 48A and 48B are a top view and a cross-sectional view of an example of a liquid crystal display device. In FIG. 48(A), a display device 20, a display area 21, a peripheral circuit 22, and an FPC (flexible printed circuit board) are shown. A representative configuration is shown having a flexible printed circuit board 42.

[0455] Figure 48(B) shows cross sections between dashed lines A-A', B-B', and C-C' in Figure 48(A). Between A-A' is the peripheral circuit area, between B-B' is the display area, and between C-C' is the FPC and The connection part is shown.

[0456] The display device 20 includes a transistor 11, a conductive layer 190, a conductive layer 195, an insulating layer 420, Liquid crystal layer 490, liquid crystal element 80, capacitance element 60, insulating layer 430, spacer 440, colored layer 4 60, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 473, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarizing plate 103, polarizing plate 403, protective substrate 105, The protective substrate 402 has an anisotropic conductive layer 510 .

[0457] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in Figure 47(C). 1 shows the pixel structure of the device.

[0458] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0459] FIG. 47(C) is a diagram showing an example of an applicable pixel circuit. This example shows how two transistors are used in one pixel. Adjustable driving can be applied.

[0460] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0461] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The source electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to the signal line 725. ) is connected to the gate electrode layer of the driving transistor 722. 22, the gate electrode layer is connected to a power supply line 727 via a capacitor element 723, and the first electrode is connected to a power supply line 727. The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. The second electrode of the light emitting element 724 corresponds to the common electrode 728. It is electrically connected to a common potential line formed on the substrate.

[0462] The switching transistor 721 and the driving transistor 722 are the same as those in the first embodiment. The transistors described in Sections 1 to 3 can be used appropriately. An EL display device can be provided.

[0463] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and is at least the forward threshold. Includes low voltages.

[0464] The capacitor 723 can be saved by substituting the gate capacitance of the driving transistor 722. It can be omitted.

[0465] Next, a signal input to the driving transistor 722 will be described. In this case, the driving transistor 722 is either fully on or fully off. A video signal such as this is input to the driving transistor 722. In order to operate the drive transistor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0466] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 4 plus the threshold voltage Vth of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region. The driving transistor 722 is operated in the saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 724. It is possible to perform analog gradation driving.

[0467] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) The pixel circuit shown in FIG. 1 includes a switch, a resistor, a capacitor, a sensor, a transistor, or a logic element. A logic circuit or the like may be added.

[0468] When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). The potentials exemplified above may be inputted by applying a voltage to the electrode.

[0469] 49(A) and 49(B) are an example of a top view and a cross-sectional view of a light-emitting device. In FIG. 49(A), a light emitting device 24, a display area 21, a peripheral circuit 22, and an FPC (flexible printed circuit board) are shown. A representative configuration is shown having a flexible printed circuit board (PCB) 42.

[0470] Figure 49(B) shows cross sections between dashed lines A-A', B-B', and C-C' in Figure 49(A). Between A-A' is the peripheral circuit area, between B-B' is the display area, and between C-C' is the FPC and The connection part is shown.

[0471] The light emitting device 24 includes a transistor 11, a conductive layer 190, a conductive layer 195, a conductive layer 410, Optical adjustment layer 530, EL layer 450, light emitting element 70, capacitance element 60, spacer 440, coloring layer 460, adhesive layer 470, conductive layer 480, light-shielding layer 418, substrate 400, anisotropic conductive layer 51 0.

[0472] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to the current), electron-emitting elements, liquid crystal elements , electronic ink, electrophoretic element, grating light valve (GLV), plasma display PDP, MEMS (Micro Electro Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), M IRASOL®, an IMOD (Interference Modulation) element , electrowetting element, piezoelectric ceramic display, carbon nanotube In addition to these, the device has at least one of an electric or magnetic display element. The display medium has contrast, brightness, reflectance, transmittance, etc. that change due to electrochemical effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display ( FED) or SED type flat panel display (SED: Surface-conductive tion Electron-emitter Display). An example of a display device using the liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display) is LCD display, reflective LCD display, direct view LCD display, projection LCD display Examples of display devices using electronic ink or electrophoretic elements include Examples include electronic paper.

[0473] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0474] (Embodiment 8) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. The explanation will be given using 50.

[0475] <Display module> The display module 6000 shown in FIG. 50 is made up of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC6003 and touch panel 6005 connected to FPC6005 Display panel 6006, backlight unit 6007, frame 6009, printed circuit board 6010 and a battery 6011. The reader 6011, the touch panel 6004, etc. may not be provided.

[0476] The semiconductor device of one embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. The present invention can be used for integrated circuits mounted on a substrate.

[0477] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed as appropriate to fit the size of the cable 6006.

[0478] The touch panel 6004 is a resistive or capacitive touch panel. 6006. In addition, the opposing substrate (sealing substrate) of the display panel 6006 It is also possible to provide the display panel 6 with a touch panel function. It is also possible to add an optical sensor to each pixel of the 006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance method is used. It is also possible to add a touch panel function.

[0479] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the unit 6007 and configured to use a light diffusion plate.

[0480] The frame 6009 has a function of protecting the display panel 6006 and also functions to prevent electrical shock from The frame 600 also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. 9 may also function as a heat sink.

[0481] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a separately provided battery 6011 may be used. In this case, the battery 6011 can be omitted.

[0482] In addition, the display module 6000 may include components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0483] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0484] (Embodiment 9) In this embodiment, an example of use of a semiconductor device according to one embodiment of the present invention will be described.

[0485] <Package using lead frame type interposer> Figure 51(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 51A is a perspective view of a semiconductor device according to one embodiment of the present invention. The corresponding chip 2751 is mounted on the interposer 2750 by wire bonding. The terminals 2752 are connected to the chip 27 of the interposer 2750. The chip 2751 is mounted on the surface on which the mold resin 51 is mounted. 2753, but the sealing is performed with a part of each terminal 2752 exposed. Make sure that this is done.

[0486] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Figure 1. The mobile phone module shown in FIG. 51(B) is a printed wiring board 28 2801, a package 2802 and a battery 2804 are mounted. A printed wiring board 2801 is connected to a panel 2800 on which a child is provided by an FPC 2803. It has been implemented.

[0487] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0488] (Embodiment 10) In this embodiment, electronic devices and lighting devices according to embodiments of the present invention will be described with reference to drawings. do.

[0489] <Electronic equipment> Electronic devices and lighting devices can be manufactured using the semiconductor device of one embodiment of the present invention. By using the semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device of one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. You can create devices.

[0490] Examples of electronic devices include television sets (also known as televisions or television receivers). (c), computer monitors, digital cameras, digital video cameras, and other cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. .

[0491] Furthermore, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be mounted on the inner wall of a house or a building. Or it can be incorporated into the exterior wall or along the curved surface of the interior or exterior of a car. do.

[0492] Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery and may be configured to use wireless power transmission. It is preferable that the secondary battery can be charged.

[0493] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic Examples include nickel-zinc batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries. .

[0494] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. If present, the antenna may be used for contactless power transfer.

[0495] FIG. 52A shows a portable game machine, which includes a housing 7101, a housing 7102, a display portion 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using a display device according to one embodiment of the present invention, the user experience is excellent and quality deterioration is reduced. It is possible to provide a portable game machine that is less likely to cause such a problem. The portable game machine has two display units 7103 and 7104. The number of display units that the device has is not limited to this.

[0496] FIG. 52B shows a smartwatch, which includes a housing 7302, a display unit 7304, and operation buttons. 7311, 7312, a connection terminal 7313, a band 7321, a clasp 7322, etc. The semiconductor device according to one embodiment of the present invention includes a memory, a CPU, and the like built in the housing 7302. It can be used for.

[0497] FIG. 52C shows a portable information terminal, which includes a display portion 7502 incorporated in a housing 7501. , operation button 7503, external connection port 7504, speaker 7505, microphone 7506 The semiconductor device according to one embodiment of the present invention is built in a housing 7501. It can be used for mobile memory, CPU, etc. It can be made to high definition, so it can be used in full HD, 4K, or 8K despite being small to medium size. It can display a variety of images, including 3D and 4D, and produces very clear images.

[0498] FIG. 52D shows a video camera, which includes a first housing 7701, a second housing 7702, and a display unit 77 03, operation keys 7704, a lens 7705, a connection part 7706, etc. The lens 7705 and the display unit 7703 are provided in the first housing 7701. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a portion 7706, and the angle between the first housing 7701 and the second housing 7702 is The image on the display unit 7703 can be changed by the connection unit 7706. 6, and a configuration in which the switching is performed according to the angle between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention may be provided at the focal point of the lens 7705. In the semiconductor device according to one embodiment of the present invention, the integrated circuit device built in the first housing 7701 can be It can be used in integrated circuits, CPUs, etc.

[0499] FIG. 52(E) shows a digital signage system, which is a display unit 7922 installed on a utility pole 7921. The semiconductor device according to one embodiment of the present invention is used in a control circuit of the display portion 7922. It is possible.

[0500] FIG. 53(A) shows a notebook personal computer, which includes a housing 8121 and a display unit 8122. , a keyboard 8123, a pointing device 8124, etc. Such a semiconductor device can be applied to a CPU or memory built into the housing 8121. The display portion 8122 can be made very high-definition, so it can be used in small and medium-sized It can display 8K images while still providing extremely clear images.

[0501] Fig. 53(B) shows the exterior of the car 9700. Fig. 53(C) shows the driver's seat of the car 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, a light fixture, and a The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display portion 9710 shown in FIG. The display device or the semiconductor device of one embodiment of the present invention can be provided in the display portion 9715. do.

[0502] The display portion 9710 and the display portion 9711 are display devices provided on a windshield of an automobile, The display device or the input / output device of one embodiment of the present invention is a display device or By forming the electrodes of the input / output device using a light-transmitting conductive material, A so-called see-through display device or input / output device that allows the opposite side to be seen through. If it is a see-through display device or an input / output device, the operation of the car 9700 can be Therefore, the display device or input / output device according to one embodiment of the present invention can be used without obstructing the view even when the display device is turned on. The power device can be installed on the windshield of the automobile 9700. or an input / output device, a display device, or a transistor for driving the input / output device, etc. In this case, organic transistors using organic semiconductor materials and transistors using oxide semiconductors are used. A light-transmitting transistor such as a light-transmitting transistor may be used.

[0503] The display unit 9712 is a display device provided in a pillar part. By displaying an image from the imaging means on the display unit 9712, the view blocked by the pillars can be compensated for. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This allows the driver to supplement the view obstructed by the dashboard. By projecting images from the camera, blind spots can be filled and safety can be improved. In addition, by projecting images that complement the invisible parts, it is possible to create a more natural and unnatural appearance. Safety checks can be carried out quickly.

[0504] Also, Figure 53(D) shows the interior of a car with bench seats for the driver and passenger seats. The display unit 9721 is a display device or an input / output device provided in the door. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9721, The display unit 9722 can complement the view blocked by the handle. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0505] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It is possible to provide various information. In addition, it is possible to change the display items and layout displayed on the display unit. The above information can be displayed on the display unit 9. 710 to 9713, 9721, and 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 and the display unit The display portions 9721 to 9723 can also be used as a heating device.

[0506] 54(A) shows the appearance of the camera 8000. The camera 8000 has a housing 8001 , a display unit 8002, operation buttons 8003, a shutter button 8004, a connection unit 8005, etc. In addition, a lens 8006 can be attached to the camera 8000.

[0507] The coupling section 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as a strobe device, etc. can be connected.

[0508] Here, the camera 8000 is used, and the lens 8006 is removed from the housing 8001 and replaced. However, the lens 8006 and the housing 8001 may be integrated.

[0509] An image can be taken by pressing the shutter button 8004. The display unit 8002 functions as a touch panel, and an image is captured by touching the display unit 8002. It is also possible to

[0510] The display device or semiconductor device of one embodiment of the present invention can be applied to the display portion 8002. do.

[0511] FIG. 54(B) shows an example in which a finder 8100 is attached to a camera 8000. are.

[0512] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0513] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000. The finder 8100 can be attached to the camera 8000. The display unit 8102 displays images received from the camera 8000 via the electrodes. It can be done.

[0514] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0515] The semiconductor device of one embodiment of the present invention is applied to an integrated circuit and an image sensor in the housing 8101. It can be used.

[0516] In addition, in Figures 54(A) and 54(B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is configured to have a detachable housing 8001. A finder equipped with a display device or an input / output device according to one embodiment may be built in.

[0517] FIG. 54(C) shows the appearance of the head mounted display 8200.

[0518] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820 3, a display unit 8204, a cable 8205, etc. The mounting unit 8201 also has a battery It has a built-in Teri 8206.

[0519] A cable 8205 supplies power from a battery 8206 to the main body 8203. 3 is equipped with a wireless receiver and the like, and displays video information such as received image data on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movements of the user's eyeballs and eyelids. Capture it and calculate the coordinates of the user's perspective based on the information, so that the user's perspective can be input It can be used as a power means.

[0520] In addition, the wearing part 8201 may be provided with a plurality of electrodes at positions where it touches the user. The main body 8203 may have a function of recognizing the user's perspective by detecting the current flowing through the electrodes as the user's eyeballs move. Also, by detecting the current flowing through the electrodes, it may have a function of monitoring the user's pulse. In addition, the wearing part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display part 8204. Also, by detecting the movement of the user's head etc., the video displayed on the display part 8204 may be changed according to the movement. The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203 .

[0521] Note that this embodiment can be appropriately combined with other embodiments shown in this specification

[0522]

[0523] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described while using FIG. 55.

[0524] <Usage Example of RF Tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates documents (driver's licenses, resident cards, etc., see FIG. 55(A)), vehicles (bicycles, etc., FIG. 55(B) See Figure 55(C), packaging containers (wrapping paper, bottles, etc., see Figure 55(C)), recording media (DVDs and videos) Deodorant tape, etc. (See Figure 55(D)), personal belongings (bags, glasses, etc.), food, plants, animals items, human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices (liquid crystal display devices) , EL display devices, television devices, or mobile phones) or It can be attached to luggage tags (see Figure 55(E) and Figure 55(F)) and used.

[0525] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, if it is a book, it is embedded in the paper, and if it is a package made of organic resin, it is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each product. The 4000 is small, thin, and lightweight, so even after being fixed to an item, it does not change the design of the item itself. In addition, banknotes, coins, securities, bearer bonds, or certificates By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to various items, such as items, recording media, personal belongings, food, clothing, household goods, or electronic devices. By attaching RF tags according to the above, the efficiency of systems such as inspection systems can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0526] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using it for each of the above applications, it is possible to reduce the operating power consumption, including the writing and reading of information. Therefore, it is possible to extend the maximum communication distance. It can also store information for an extremely long period of time, making it suitable for applications where writing and reading are infrequent. It can be suitably used.

[0527] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0528] 10 transistors 11 Transistor 12 transistors 20 Display device 21 Display area 22 Peripheral circuits 24 Light-emitting device 60 Capacitor element 70 Light-emitting element 80 Liquid crystal element 100 boards 103 Polarizing Plate 105 Protection Board 110 Insulating layer 120 Semiconductor layer 121 Insulator 121a Insulator film 122 Semiconductor layer 122a Semiconductor film 123 Insulator 123a Insulator film 130 Source electrode layer 130a Conductive film 130b conductive layer 140 Drain electrode layer 150 Gate insulating layer 150a insulating film 160 gate electrode layer 160a Conductive film 165 Conductive Layer 166 Conductive Layer 167 Conductive Layer 170 Insulating Layer 170a insulating film 171 Mixed layer 171b Insulating layer 172 Oxygen 173 Insulating Layer 173a insulating film 174 Groove 175 Insulating Layer 175a insulating film 175b insulating layer 176 Resist Mask 177 Insulating Layer 177a Insulating film 190 Conductive Layer 195 Conductive Layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 transistors 353 Transistor 360 photodiode 361 Anode 362 cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 400 boards 402 Protection Board 403 Polarizing Plate 410 Conductive layer 418 Light blocking layer 420 Insulation Layer 430 Insulating layer 440 spacer 450 EL layer 460 Colored layer 470 Adhesive layer 473 Adhesive layer 474 Adhesive layer 475 Adhesive layer 476 Adhesive layer 480 Conductive Layer 490 Liquid Crystal Layer 510 Anisotropic conductive layer 530 Optical adjustment layer 601 Precursor 602 Precursor 700 boards 701 Pixel section 702 Scanning line driving circuit 703 Scanning line driving circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 signal line 716 Transistor 717 Transistor 718 Liquid Crystal Devices 719 Liquid Crystal Devices 720 pixels 721 Switching Transistor 722 Drive transistor 723 Capacitor 724 Light-emitting element 725 signal line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-treatment room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High Speed ​​Valve 1712b High Speed ​​Valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB holder 1720 Transport Room 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulators 2211 Semiconductor substrate 2212 Insulator 2213 Gate electrode 2214 Gate insulator 2215 Source and Drain Regions 2750 Interposer 2751 chips 2752 terminal 2753 Molding resin 2800 panels 2801 Printed wiring board 2802 Package 2803 FPC 2804 battery 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 4000 RF tags 5100 pellets 5120 board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight Unit 6008 Light source 6009 Frame 6010 printed circuit board 6011 Battery 7101 Housing 7102 Housing 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Housing 7304 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Housing 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7921 Electric pole 7922 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8121 Housing 8122 Display section 8123 keyboard 8124 pointing device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section< / cpu>

Claims

[Claim 1] a first transistor and a second transistor; a gate electrode of the first transistor electrically connected to one of a source electrode and a drain electrode of the second transistor; a first conductive layer that functions as a gate electrode of the first transistor; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region above the first insulating layer and having a channel formation region of the second transistor; a second conductive layer having a region above the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode; a second insulating layer having a region in contact with a side surface of the first insulating layer and a region in contact with a side surface of the oxide semiconductor layer; a third insulating layer having a region above the first conductive layer and a region above the second conductive layer, the third insulating layer having a groove; a fourth insulating layer having a region above the third insulating layer and having a groove; a fifth insulating layer formed along an inner wall of the groove and functioning as a gate insulating layer; a third conductive layer having a region in contact with the fifth insulating layer inside the trench and functioning as a gate electrode; A semiconductor device in which an upper surface of the second insulating layer, an upper surface of the fourth insulating layer, an upper surface of the fifth insulating layer, and an upper surface of the third conductive layer are on the same plane.

Images