Audio Output Circuit

Abstract

To provide an audio output circuit capable of adjusting audio volume, and capable of providing audio in high quality even at low volume while adopting a full digital system.SOLUTION: An audio output circuit includes: a microcontroller (10) for generating a differential PWM signal (PWM0, PWM1) based on audio data; a driver circuit (60) for outputting a drive voltage to a speaker (SP) by causing an H-bridge circuit (40) to perform switching operation in response to the differential PWM signal; and a voltage variable power supply (20) for applying a variable voltage to the driver circuit and causing the driver circuit to output a drive voltage according to the variable voltage. The driver circuit includes a logic level voltage conversion circuit (30) for converting a voltage of the inputted PWM signal to a voltage level different therefrom according to a power supply of the microcontroller and the voltage of the voltage variable power supply and inputting the converted voltage to the gate terminal of a PMOSFET of the H-bridge circuit. Output volume from the speaker is made variable by controlling the output voltage of the H-bridge circuit by varying the output voltage of the voltage variable power supply.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an audio output circuit. [Background technology]

[0002] There are audio output devices that are installed in devices that output audio such as guide audio and sound effects. One known example of such an audio output device is one that converts audio data into a PWM signal (Pulse Width Modulation: PWM) and drives a speaker based on the PWM signal to output audio at a predetermined volume. For example, Patent Document 1 listed below discloses an audio playback device (audio output device) that includes an inexpensive microcomputer (hereinafter, microcomputer will be abbreviated as "microcomputer") and an H-bridge circuit (drive circuit) (see FIG. 1(B) of Patent Document 1).

[0003] In the above audio playback device, the microcomputer's memory stores a driver, which is middleware for driving the audio output devices (H-bridge circuit, speaker). The microcomputer (CPU) converts compressed audio data into a PCM format digital audio signal, and then converts the PCM format audio signal into a PWM signal whose pulse width is proportional to the signal level based on the driver stored in the memory.

[0004] In addition, in the above audio playback device, the H-bridge circuit is composed of four field effect transistors (FETs). This H-bridge circuit amplifies power by switching the four FETs based on a PWM signal from the microcontroller, and drives the speaker. This allows audio to be played at a set volume.

[0005] The above audio playback device employs a fully digital system, and all processes, from inputting the digital audio signal to generating the PWM signal that drives the speaker, are performed digitally. Compared to devices that first convert the signal to analog, this fully digital audio playback device generates less heat and consumes less power, avoids signal degradation due to noise contamination, and significantly reduces component costs. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6308705 (paragraphs 0021, 0022, Figure 1(B)) Summary of the Invention [Problem to be solved by the invention]

[0007] The above-mentioned audio playback device plays audio at a predetermined volume based on an input audio signal, so it is not expected that the volume will be adjusted after installation in a device. In this regard, if the above-mentioned audio playback device were configured to allow free control of the audio volume even after installation in an audio output device, each user would be able to adjust the volume to their desired level, thereby expanding its applications. Therefore, a configuration using a digital volume control for such a fully digital audio playback device is conceivable. For example, to reduce the volume of the audio, the amplitude of the digital data output by the PWM signal is reduced using a signed division process, thereby lowering the modulation degree of the PWM signal and thereby reducing the amplitude of the output audio signal.

[0008] However, in such a configuration, if the bit depth that can be reproduced by the audio reproduction device is relatively small (for example, 16 bits), when the volume is lowered using the volume control method described above, the number of effective bits of the signal component in the digital data decreases (for example, to 16 bits - 3 bits = 13 bits), which becomes quantization noise and pushes up the noise floor, resulting in a decrease in the sound quality of the audio (i.e., the sound becomes worse).

[0009] To avoid deterioration of sound quality when the volume is reduced using the digital volume, it is sufficient to ensure an effective bit number of about 16 bits in the output digital data. However, in this case, if the bit number for volume control is set to 4 to 8 bits, the reproducible bit depth (N D ) requires about 24 bits. Then, the sampling rate (f S ) is 48 kilohertz (kHz), the frequency of the timer clock signal that generates the PWM signal (2 N D power × f S ) would require a speed of 800 gigahertz (GHz) or more, which is extremely difficult to achieve with current technology.

[0010] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide an audio output circuit that can adjust the volume and output audio with good sound quality (i.e., good sound) even at low volume while adopting a full digital system. [Means for solving the problem]

[0011] In order to achieve the above object, the present invention provides an audio output circuit comprising a microcomputer that generates a differential PWM signal based on audio data, and a drive circuit that performs switching operations on an H-bridge circuit in accordance with the differential PWM signal to output a drive voltage to a speaker, the audio output circuit further comprising a voltage variable power supply that applies a variable voltage to the drive circuit and causes the drive circuit to output a drive voltage corresponding to the variable voltage, the drive circuit comprising a logic level voltage conversion circuit that converts the voltage of an input PWM signal to a voltage level different from this voltage in accordance with the voltages of the power supply of the microcomputer and the voltage variable power supply, and inputs the converted voltage to the gate terminals of PMOSFETs in the H-bridge circuit, the PMOSFET has a source terminal connected to a voltage variable power supply and a gate terminal connected to the voltage variable power supply via a resistor; the logic level voltage conversion circuit has a Schottky barrier diode connected between the gate terminal of the PMOSFET and the voltage variable power supply, and a capacitor connected between an anode terminal of the Schottky barrier diode and a PWM signal input terminal; The output voltage of the H-bridge circuit is controlled by changing the voltage of the variable voltage power supply, thereby making it possible to vary the output volume of the speaker.

[0012] Furthermore, in the above configuration 、H The FETs constituting the bridge circuit may be two PMOSFETs and two NMOSFETs, the drain terminals of the two NMOSFETs may be connected to the drain terminals of different PMOSFETs, the gate terminals of the NMOSFETs may be connected to the PWM signal input terminal and also to ground via a resistor, and the source terminals of the NMOSFETs may be connected to ground. To, In the above configuration, the logic level voltage conversion circuit applies a voltage of a level equal to the signal voltage of the PWM signal to the gate terminal of the NMOSFET, and in certain cases may apply a voltage of a level obtained by subtracting the voltage value of the voltage variable power supply from the voltage value of the power supply voltage of the microcomputer to the gate terminal of the PMOSFET. [Effects of the Invention]

[0013] According to the present invention, the volume can be adjusted by changing the voltage of the variable voltage power supply, and good quality sound can be output even at low volume while employing a full digital system. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a block diagram showing an example of a schematic configuration of an audio output circuit. [Figure 2] FIG. 2 is a schematic diagram illustrating an example of a main part of an audio output circuit. [Figure 3] FIG. 2 is a schematic diagram illustrating an example of a main part of an audio output circuit. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited thereto. In addition, in the drawings, in order to explain the embodiments, some parts may be enlarged or emphasized, and the scale may be changed as appropriate.

[0016] FIG. 1 is a block diagram showing an example of a schematic configuration of an audio output circuit 100. FIG. 1 shows the audio output circuit 100 configured together with a speaker SP to form an audio output device 1. The audio output device 1 of FIG. 1 includes the audio output circuit 100 and the speaker SP, and outputs audio from the speaker SP by driving the speaker SP based on a PWM signal generated from audio data. As shown in FIG. 1, the audio output circuit 100 includes a microcomputer 10, a voltage variable power supply 20, a logic level voltage conversion circuit 30, and an H-bridge circuit 40. The audio output circuit 100 employs a fully digital system, and as will be described later, all processes from input of an audio signal (digital data) to generation of a PWM signal that drives the speaker are performed in the digital domain.

[0017] The microcomputer 10 includes a CPU 11, a memory 12, and timers 13 and 14. The microcomputer 10 is a circuit in which the CPU 11, the memory 12, the timers 13 and 14, etc. are integrated into a single LSI chip (Large Scale Integration Circuit).

[0018] The CPU 11 decodes the compressed audio data in the memory 12 and converts it into a PCM format audio signal based on the audio playback middleware 15, which will be described later. The PCM format audio signal is discrete digital data with a predetermined sampling frequency.

[0019] Furthermore, the CPU 11 controls the timers 13 and 14 built into the microcomputer 10 based on the audio playback middleware 15 stored in the memory 12, thereby generating a PWM signal based on the signal level of the PCM audio signal. The PWM signal has a constant output pulse period. However, the PWM signal has different pulse periods (widths) for "H" (high level) and "L" (low level) depending on the audio signal level. Here, the percentage of the PWM signal period during which the signal level is "H" is referred to as the duty ratio.

[0020] The memory 12 stores audio playback middleware 15. The audio playback middleware 15 is a driver for driving the speaker SP. The memory 12 also stores compressed audio data and middleware for decoding and playing back the compressed audio data.

[0021] The timer 13 and the like convert the PCM audio signal into a PWM signal with a pulse width corresponding to the magnitude of the signal level under the control of the audio playback middleware 15. The PWM signal generated here is a drive signal (a signal input to the signal input terminal of the H-bridge circuit 40) that drives the H-bridge circuit 40, and is a pair of differential signals consisting of a PWM signal (PWM0) and a PWM signal (PWM1). This differential PWM signal is generated, for example, as follows based on the PCM audio signal.

[0022] That is, the positive output PWM signal (e.g., PWM0) and the negative output PWM signal (e.g., PWM1) are in phase. Then, by reversing the pulse width change direction of the positive output PWM signal and the negative output PWM signal, a differential signal is generated. The output range of the differential signal is +100% to 0% to -100%. For example, if the duty ratio of the positive output PWM signal is 40% and the duty ratio of the negative output PWM signal is 60%, the differential component (differential output) will be +20%. Conversely, if the duty ratio of the positive output PWM signal is 60% and the duty ratio of the negative output PWM signal is 40%, the differential component will be -20%. Similarly, if the duty ratio of the positive output PWM signal is 30% and the duty ratio of the negative output PWM signal is 70%, the differential component will be +40%. When the differential output is 0%, the duty ratio of the PWM signals for the positive output and negative output is 50%.

[0023] The microcomputer 10 outputs two PWM signals (PWM0, PWM1) generated by the timer 13 and the like from two output pins to the H-bridge circuit 40 via the logic level voltage conversion circuit 30.

[0024] The variable voltage power supply 20 outputs a power supply voltage Vdd to the logic level voltage conversion circuit 30 and the H-bridge circuit 40, and is configured to be able to change the voltage value of the output voltage Vdd. The variable voltage power supply 20 includes a voltage source and a voltage variable device that changes the magnitude of the power supply voltage Vdd output by the voltage source. The voltage variable device changes the voltage value of the power supply voltage Vdd in response to external operations, signal reception, etc. As an example of the specific configuration of such a voltage variable device, FIG. 1 shows a variable resistor VR connected to a power supply. The variable resistor VR has an operating unit (not shown) (e.g., a volume control knob) and changes the voltage value of the power supply voltage Vdd by changing its resistance value in response to the amount of operation of the operating unit (e.g., the amount of rotation of the knob).

[0025] That is, when the user operates the operation unit, the resistance value of the variable resistor VR changes according to the operation level, and the change in the resistance value of the variable resistor VR changes the voltage value of the power supply voltage Vdd output by the voltage variable power supply 20. When the voltage value of the power supply voltage Vdd changes, the volume of the output sound of the sound output device 1 changes accordingly. Therefore, the sound output circuit 100 is configured so that the user can adjust the volume of the sound output device 1 by controlling the magnitude of the voltage value of the power supply voltage Vdd output by the voltage variable power supply 20 through operation of the operation unit.

[0026] The logic level voltage conversion circuit 30 receives two PWM signals (PWM0, PWM1) output from the microcomputer 10, and also receives a power supply voltage Vdd from the voltage variable power supply 20. The logic level voltage conversion circuit 30 converts the voltage levels (logic level voltages) of the two input PWM signals (PWM0, PWM1), and outputs the converted PWM signals (PWM0, PWM1) to the H-bridge circuit 40. The configuration and functions of the logic level voltage conversion circuit 30 will be described in detail later.

[0027] The H-bridge circuit 40 receives two PWM signals (PWM0, PWM1) output from the microcomputer 10. The H-bridge circuit 40 outputs a signal (drive signal) to the speaker SP by causing four field effect transistors (FET1 to FET4) (see FIG. 2) to perform switching (opening and closing) operations based on the PWM signals (PWM0, PWM1) from the microcomputer 10, thereby driving the speaker SP. At this time, the H-bridge circuit 40 passes a current through the speaker SP, which serves as a load, for a period of time corresponding to the difference in pulse width between the two PWM signals (PWM0, PWM1), thereby driving the speaker SP.

[0028] The speaker SP is a dynamic speaker, and includes a moving coil and a diaphragm (both not shown) disposed in a magnetic field. When a current flows through the moving coil, the moving coil vibrates, and this vibration is transmitted to the diaphragm, thereby outputting sound. The speaker SP is connected to an H-bridge circuit 40, and outputs sound according to a voltage applied via the H-bridge circuit 40. Note that the speaker SP is not limited to a dynamic speaker, and may be, for example, a piezoelectric speaker (sometimes called a piezo speaker or piezoelectric sounder) having a piezoelectric element. In this case, the speaker SP is driven by applying a voltage to the piezoelectric element, and outputs sound.

[0029] FIG. 2 is a schematic diagram showing an example of the main parts of an audio output circuit 100. In the following description of FIG. 2, up, down, left, and right refer to directions when viewing FIG. 2 in the direction of the symbols. As shown in FIG. 2, the audio output circuit 100 includes two half-bridge circuits 40A and 40B that constitute an H-bridge circuit 40, and two logic-level voltage conversion circuits 30A and 30B. Next, the specific configurations and operations of the logic-level voltage conversion circuit 30 and the H-bridge circuit 40 will be described.

[0030] The logic level voltage conversion circuit 30A is connected between a signal input terminal that inputs a PWM signal (PWM0) and the half-bridge circuit 40A. The logic level voltage conversion circuit 30B is connected between a signal input terminal that inputs a PWM signal (PWM1) and the half-bridge circuit 40B. The half-bridge circuits 40A, 40B and the logic level voltage conversion circuits 30A, 30B constitute a drive circuit 60 that outputs a drive signal to the speaker SP to drive the speaker SP. That is, the drive circuit 60 that drives the speaker SP is composed of a first drive circuit 50A (the left part of the drive circuit 60) that consists of the half-bridge circuit 40A and the logic level voltage conversion circuit 30A, and a second drive circuit 50B (the right part of the drive circuit 60) that consists of the half-bridge circuit 40B and the logic level voltage conversion circuit 30B.

[0031] The drive circuit 60 includes four field effect transistors FET1 to FET4. In the following description, the field effect transistors FET1 to FET4 will be simply referred to as transistors FET1 to FET4.

[0032] The drive circuit 60 is configured to switch the transistors FET1 to FET4 in response to the input PWM signals (PWM0, PWM1). That is, in the first drive circuit 50A, when the PWM signal (PWM0) is "H," the upper left transistor FET1 is off (open) and the lower left transistor FET2 is on (open); and when the PWM signal (PWM0) is "L," the transistor FET1 is on (closed) and the transistor FET2 is off (open). In this way, the transistors FET1 and FET2 are alternately turned on and off (open and closed) based on the signal level ("H," "L") of the PWM signal (PWM0). In the second drive circuit 50B, when the PWM signal (PWM1) is "H," the upper right transistor FET3 is off (open) and the lower right transistor FET4 is on (closed); and when the PWM signal (PWM1) is "L," the transistor FET3 is on (closed) and the transistor FET4 is off (open). In this way, the transistors FET3 and FET4 are configured to be alternately turned on and off (open and closed) based on the signal level ("H", "L") of the PWM signal (PWM1).

[0033] Of the four transistors FET1, etc. shown in FIG. 2, the two upper transistors FET1 and FET3 are P-type MOS (Metal-Oxide-Semiconductor) FETs. In the following explanation, a P-type MOSFET will be referred to as a PMOSFET. The two lower transistors FET2 and FET4 are N-type MOSFETs. In the following explanation, an N-type MOSFET will be referred to as an NMOSFET. All four of these transistors FET1 to FET4 are enhancement types. The PMOSFETs (FET1 and FET3) turn on when a voltage of a predetermined magnitude and negative with respect to the source voltage is applied to their gates. The NMOSFETs (FET2 and FET4) turn on when a voltage of a predetermined magnitude and positive with respect to the source voltage is applied to their gates. In this way, transistors such as FET1 turn on when a predetermined voltage is applied, and the voltage between the gate and source (hereinafter simply referred to as the "gate-source voltage") required to switch transistors such as FET1 is called the threshold voltage, also known as the threshold voltage.

[0034] In the first drive circuit 50A, the source terminal and gate terminal of the transistor FET1 are each connected to the voltage variable power supply 20. The drain terminal of the transistor FET1 is connected to the drain terminal of the transistor FET2. A resistor R11 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of the transistor FET1 and the voltage variable power supply 20. A resistor R12 (e.g., resistance value 100 ohms (Ω)) and a Schottky barrier diode SBD1 are connected in series between the gate terminal of the transistor FET1 and the voltage variable power supply 20. The gate terminal of the transistor FET2 is connected to a signal input terminal that inputs a PWM signal (PWM0). The source terminal of the transistor FET2 is connected to ground (GND). A resistor R21 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of the transistor FET2 and ground. A resistor R22 (e.g., resistance value 100 ohms (Ω)) is connected between the gate terminal of the transistor FET2 and the signal input terminal that inputs the PWM signal (PWM0). A capacitor C1 (for example, a capacitance of 0.1 microfarads (μF)) is connected between the gate terminal side of transistor FET1 (connection point H1 between the anode terminal of Schottky barrier diode SBD1 and resistor R12) and the gate terminal side of transistor FET2 (connection point L1 between the signal input terminal and resistor R22).

[0035] The second drive circuit 50B, which includes transistors FET3 and FET4, resistors R31, R32, R41, and R42, a Schottky barrier diode SBD2, and a capacitor C2, has the same configuration as the first drive circuit 50A, which includes transistors FET1 and FET2, resistors R11, R12, R21, and R22, a Schottky barrier diode SBD1, and a capacitor C1. Specifically, the source and gate terminals of transistor FET3 are connected to the variable voltage power supply 20. The drain terminal of transistor FET3 is connected to the drain terminal of transistor FET4. A resistor R31 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET3 and the variable voltage power supply 20. A resistor R32 (e.g., resistance value 100 ohms (Ω)) and a Schottky barrier diode SBD2 are connected in series between the gate terminal of transistor FET3 and the variable voltage power supply 20. The gate terminal of transistor FET4 is connected to a signal input terminal that inputs a PWM signal (PWM1). The source terminal of transistor FET4 is connected to ground. A resistor R41 (e.g., resistance value 10 kilohms (kΩ)) is connected between the gate terminal of transistor FET4 and ground. A resistor R42 (e.g., resistance value 100 ohms (Ω)) is connected between the gate terminal of transistor FET4 and a signal input terminal for inputting a PWM signal (PWM1). A capacitor C2 (e.g., capacitance 0.1 microfarads (μF)) is connected between the gate terminal side of transistor FET3 (connection point H2 between the anode terminal of Schottky barrier diode SBD2 and resistor R32) and the gate terminal side of transistor FET4 (connection point L2 between the signal input terminal and resistor R22).

[0036] A speaker SP is connected between a connection point O1 between the drain terminals of transistors FET1 and FET2 and a connection point O2 between the drain terminals of transistors FET3 and FET4. Note that connection point O1 is also the output terminal of the first drive circuit 50A, and connection point O2 is also the output terminal of the second drive circuit 50B.

[0037] In the drive circuit 60, when all four transistors FET1 to FET4 are off, no voltage is applied to the speaker SP. When transistors FET1 and FET4 are on and transistors FET2 and FET3 are off, a current flows through the path (1) in FIG. 2 (voltage variable power supply 20, transistor FET1, speaker SP, transistor FET4, ground). At this time, a current flows in a predetermined direction to the speaker SP, and the power supply voltage Vdd of the voltage variable power supply 20 is applied to the speaker SP. Conversely, when transistors FET2 and FET3 are on and transistors FET1 and FET4 are off, a current flows through the path (2) in FIG. 2 (voltage variable power supply 20, transistor FET3, speaker SP, transistor FET2, ground). At this time, a current flows in the speaker SP in a direction opposite to the predetermined direction, and the power supply voltage Vdd of the voltage variable power supply 20 is applied to the speaker SP.

[0038] The drive circuit 60 applies the power supply voltage Vdd of the voltage variable power supply 20 to the speaker SP to drive the speaker SP, causing the speaker SP to output sound at a volume corresponding to the magnitude of the power supply voltage Vdd.

[0039] As described above, the user can change the magnitude of the voltage value of the power supply voltage Vdd and adjust the volume of the sound output from the speaker SP by operating the operation unit provided on the voltage variable power supply 20. For example, if the user operates the operation unit to lower the power supply voltage Vdd, the volume of the sound output from the speaker SP will decrease accordingly, and conversely, if the power supply voltage Vdd is increased accordingly, the volume of the sound output from the speaker SP will increase accordingly.

[0040] In this way, according to the drive circuit 60, the voltage variable power supply 20 is connected to the H-bridge circuits 40A, 40B that convert audio data into speaker drive signals, and the magnitude of the voltage value of the power supply voltage Vdd applied to the source terminals of the transistors FET1, FET3 is changeable. Therefore, by simply changing the magnitude of the power supply voltage Vdd, it is possible to adjust the volume of the audio output from the speaker SP without degrading the sound quality (for example, without impairing the dynamic range of the audio signal).

[0041] In the above-described configuration of the audio output circuit 100, the logic level voltage conversion circuits 30A and 30B are connected between the signal input terminals for inputting the PWM signals (PWM0 and PWM1) and the half-bridge circuits 40A and 40B. If the audio output circuit is configured without these logic level voltage conversion circuits 30A and 30B, the following problem occurs.

[0042] As described above, the source terminal of transistor FET1 is supplied with power supply voltage Vdd from variable voltage power supply 20. For example, if a user adjusts power supply voltage Vdd from variable voltage power supply 20 to lower the volume, the power supply voltage Vdd may become lower than the power supply voltage of microcontroller 10 (i.e., the logic-level voltage of the microcontroller that generates the PWM signal). In other words, the voltage applied to the source terminal of transistor FET1 may become lower than the power supply voltage of microcontroller 10. In this case, if the signal input terminal of the PWM signal (PWM0) is directly connected to the gate terminal of transistor FET1 without passing through logic-level voltage conversion circuit 30A (i.e., the logic-level voltage of microcontroller 10 is not converted), the gate-source voltage of transistor FET1 may become higher than the threshold voltage, causing transistor FET1 to remain in the off state and not turn on, resulting in no switching operation. Similarly, in this case, the gate-source voltage of transistor FET3 may become higher than the threshold voltage, preventing it from turning on and no longer performing switching operation.

[0043] As described above, if the audio output circuit does not include the logic level voltage conversion circuits 30A and 30B, the transistors FET1 and FET3 may not perform appropriate switching operations. If the transistors FET1 and FET3 do not perform appropriate switching operations, the audio circuit cannot output a current according to the PWM signals (PWM0 and PWM1) to the speaker SP, and cannot output audio according to the audio data.

[0044] In contrast, in the configuration of the audio output circuit 100 described above, the logic level voltage conversion circuits 30A and 30B are provided, so that the transistors FET1 and FET3 can be switched appropriately even if the power supply voltage Vdd is set to a low voltage or is stepped down, and therefore the above-mentioned problem does not occur.

[0045] Next, the operation of the drive circuit 60 will be described in detail. Here, the voltage values ​​applied to the drive circuit 60 are as follows: The power supply voltage of the microcomputer 10 is +5 volts, with ground as the reference potential. Because the power supply voltage of the microcomputer 10 is +5 volts, a voltage of 0 volts (ground) is applied to the signal input terminal of the drive circuit 60 for the PWM signals (PWM0, PWM1) when the PWM signals (PWM0, PWM1) are "L," and a voltage of +5 volts is applied when the PWM signals (PWM0, PWM1) are "H." In addition, the power supply voltage Vdd of the voltage variable power supply 20 is +1 volt. Therefore, the power supply voltage Vdd (voltage value +1 volt) of the voltage variable power supply 20 is lower than the power supply voltage (voltage value +5 volts) of the microcomputer 10.

[0046] The above-mentioned values ​​of the power supply voltage of the microcomputer 10 and the power supply voltage Vdd of the voltage variable power supply 20 are merely examples, and can be set arbitrarily as long as the drive circuit 60 operates.

[0047] Generally, the gate-source voltage (threshold voltage) required to turn on an FET differs depending on its electrical characteristics and changes depending on the voltage applied to the terminals and temperature, but we will assume that the gate-source voltage (threshold voltage) Vgs required to turn on transistors FET1 and FET3 is -2.5 volts, and the gate-source voltage (threshold voltage) Vgs required to turn on transistors FET2 and FET4 is +2.5 volts.

[0048] First, the state of the first drive circuit 50A before the PWM signal (PWM0) is input (hereinafter referred to as the "initial state") will be described. In the initial state, since the PWM signal (PWM0) is not input to the signal input terminal of the PWM signal (PWM0), 0 volts is applied to the signal input terminal of the PWM signal (PWM0). In addition, the potential of the connection point L1 on the signal input terminal side of the capacitor C1 becomes 0 volts.

[0049] In the initial state, before the power supply voltage Vdd of the variable voltage power supply 20 is applied, the charge on the capacitor C1 is 0 (C1:Q=0). FIG. 3 is a schematic diagram showing an example of a first drive circuit 50A. As shown in FIG. 3, when the power supply voltage Vdd (voltage value +1 volt) is applied, the potential at the connection point H1 on the power supply voltage Vdd side becomes +1 volt. This causes charge to accumulate in the capacitor C1, and the voltage of the capacitor C1 is charged up to -1 volt. Because the Schottky barrier diode SBD1 functions to cut off voltages exceeding the power supply voltage Vdd, the potential at the connection point H1 on the power supply voltage Vdd side of the capacitor C1 remains at +1 volt.

[0050] Also, in the initial state, when the power supply voltage Vdd (voltage value +1 volt) is turned on, a voltage of +1 volt is applied to the gate terminal of transistor FET1, and a voltage of +1 volt is also applied to the source terminal. At this time, the gate-source voltage of transistor FET1 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 is turned off.

[0051] In the initial state, a voltage of 0 volts is applied to the gate terminal of transistor FET2, and a voltage of 0 volts is applied to the source terminal, which is connected to ground. At this time, the gate-source voltage of transistor FET2 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET2 is off.

[0052] In this way, in the initial state, neither the transistor FET1 nor the transistor FET2 is driven, so the potential of the output terminal (connection point O1) of the first drive circuit 50A is indefinite.

[0053] Then, when the input of the PWM signal (PWM0) to the first drive circuit 50A begins (after the PWM signal is input), the initial state continues while the PWM signal (PWM0) is "L" (voltage value 0 volts), but when the PWM signal (PWM0) becomes "H" (i.e., when a voltage of +5 volts is applied to the PWM signal (PWM0) input terminal), the first drive circuit 50A operates as follows.

[0054] First, the potential at node L1 on the PWM signal input terminal side of capacitor C1 changes from 0 volts to +5 volts. This causes the voltage of capacitor C1 to change from its initial state of -1 volts to +6 volts, but the Schottky barrier diode SBD1 turns on and it eventually charges up from -1 volts to +4 volts. Once capacitor C1 is charged up to +4 volts, it maintains the post-charge potential difference (voltage value +4 volts) as long as the PWM signal (PWM0) is input. As the voltage of capacitor C1 charges up, a forward voltage bias occurs in Schottky barrier diode SBD1, which turns on temporarily and functions to cut off voltages that exceed the power supply voltage Vdd (voltage value +1 volt). As a result, the potential at node H1 on the power supply voltage Vdd side of capacitor C1 becomes +1 volt.

[0055] Since the potential at node H1 is +1 volts, a voltage of +1 volt is applied to the gate terminal of transistor FET1. At this time, the potential of the gate terminal of transistor FET1 becomes the same potential as the power supply voltage Vdd. In addition, the power supply voltage Vdd (voltage value +1 volt) continues to be applied to the source terminal of transistor FET1. At this time, the gate-source voltage of transistor FET1 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 is turned off.

[0056] Furthermore, since the potential at node L1, which is connected to the signal input terminal for the PWM signal (PWM0), is +5 volts, a voltage of +5 volts is applied to the gate terminal of transistor FET2. 0 volts (ground) continues to be applied to the source terminal of transistor FET2. At this time, the gate-source voltage of transistor FET2 changes from 0 volts to +5 volts, and a voltage higher than the threshold voltage (+2.5 volts) is applied to the gate of transistor FET2, turning transistor FET2 on.

[0057] In this way, when the PWM signal (PWM0) input to the first drive circuit 50A is "H," the transistor FET1 is turned off and the transistor FET2 is turned on. At this time, a voltage of 0 volts (ground) is applied to the output terminal (connection point O1) of the first drive circuit 50A.

[0058] Next, when the PWM signal (PWM0) input to the first drive circuit 50A changes from "H" to "L" (i.e., when a voltage of 0 volts is applied to the PWM signal (PWM0) input terminal), the first drive circuit 50A operates as follows.

[0059] Since the voltage of capacitor C1 is +4 volts, the potential of node H1 changes from +1 volt to -4 volts, which causes a voltage of -4 volts to be applied to the gate terminal of transistor FET1.

[0060] The power supply voltage Vdd of +1 V continues to be applied to the source terminal of transistor FET1. At this time, the gate-source voltage of transistor FET1 is -5 V, which is lower than the threshold voltage (-2.5 V), so transistor FET1 turns on.

[0061] Furthermore, because the potential at node L1, which is connected to the signal input terminal of the PWM signal (PWM0), is 0 volts, a voltage of 0 volts is applied to the gate terminal of transistor FET2. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET2. At this time, the gate-source voltage of transistor FET2 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET2 is turned off.

[0062] In this way, when the PWM signal (PWM0) input to the first drive circuit 50A goes low, the transistor FET1 turns on and the transistor FET2 turns off, and a voltage of +1 volt is applied to the output terminal (node ​​O1) of the first drive circuit 50A.

[0063] Furthermore, when the PWM signal (PWM0) input to the first drive circuit 50A changes from "L" to "H" again, the state returns to the above, and the transistor FET1 is again turned off and the transistor FET2 is again turned on.

[0064] By such operation of the first drive circuit 50A, a PWM signal (PWM0) is input from the PWM signal input terminal, and FET1 and FET2 are alternately turned on and off.

[0065] The operation of the second drive circuit 50B is similar to that of the first drive circuit 50A described above. That is, returning to FIG. 2, in the initial state (before the PWM signal is input), before the power supply voltage Vdd of the voltage variable power supply 20 is applied to the second drive circuit 50B, the charge on capacitor C2 is 0 (C2:Q=0). Then, when the power supply voltage Vdd (voltage value +1 volt) is applied, the potential at connection point H2 on the power supply voltage Vdd side becomes +1 volt. As a result, charge is accumulated in capacitor C2, and the voltage of capacitor C2 is charged up to -1 volt. Because the Schottky barrier diode SBD2 functions to cut off voltages exceeding the power supply voltage Vdd, the potential at connection point H2 on the power supply voltage Vdd side of capacitor C2 remains at +1 volt.

[0066] Also, in the initial state, when the power supply voltage Vdd (voltage value +1 volt) is turned on, a voltage of +1 volt is applied to the gate terminal of transistor FET3, and a voltage of +1 volt is also applied to the source terminal. At this time, the gate-source voltage of transistor FET3 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET3 is turned off.

[0067] In the initial state, a voltage of 0 volts is applied to the gate terminal of transistor FET4, and a voltage of 0 volts is applied to the source terminal, which is connected to ground. At this time, the gate-source voltage of transistor FET4 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET4 is turned off.

[0068] In this way, in the initial state, neither the transistor FET3 nor the transistor FET4 is driven, so the potential of the output terminal (node ​​O2) of the second drive circuit 50B is indefinite.

[0069] Then, when the input of the PWM signal (PWM1) to the second drive circuit 50B begins (after the PWM signal is input), the initial state continues while the PWM signal (PWM1) is "L" (voltage value 0 volts), but when the PWM signal (PWM1) becomes "H" (i.e., when a voltage of +5 volts is applied to the PWM signal (PWM1) input terminal), the second drive circuit 50B operates as follows.

[0070] First, the potential at connection point L2 on the PWM signal input terminal side of capacitor C2 changes from 0 volts to +5 volts. This causes the voltage of capacitor C2 to change from its initial state of -1 volts to +6 volts, but the Schottky barrier diode SBD2 turns on and it eventually charges up from -1 volts to +4 volts. Once capacitor C2 is charged up to +4 volts, it maintains the post-charge potential difference (voltage value +4 volts) as long as the PWM signal (PWM1) is input. As the voltage of capacitor C2 charges up, a forward voltage bias occurs in Schottky barrier diode SBD2, which turns on temporarily and functions to cut off voltages that exceed the power supply voltage Vdd (voltage value +1 volt). This causes the potential at connection point H2 on the power supply voltage Vdd side of capacitor C2 to become +1 volt.

[0071] Since the potential at node H2 is +1 volts, a voltage of +1 volt is applied to the gate terminal of transistor FET3. At this time, the potential of the gate terminal of transistor FET3 becomes the same potential as the power supply voltage Vdd. In addition, the power supply voltage Vdd (voltage value +1 volt) continues to be applied to the source terminal of transistor FET3. At this time, the gate-source voltage of transistor FET3 is 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET3 is turned off.

[0072] Furthermore, the potential at node L3, which is connected to the signal input terminal for the PWM signal (PWM1), is +5 volts, so a voltage of +5 volts is applied to the gate terminal of transistor FET4. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET4. At this time, the gate-source voltage of transistor FET4 changes from 0 volts to +5 volts, and a voltage higher than the threshold voltage (+2.5 volts) is applied to the gate of transistor FET4, so transistor FET4 turns on.

[0073] In this way, when the PWM signal (PWM1) input to the second drive circuit 50B is "H," the transistor FET3 is turned off and the transistor FET4 is turned on. At this time, a voltage of 0 volts (ground) is applied to the output terminal (connection point O2) of the second drive circuit 50B.

[0074] Next, when the PWM signal (PWM1) input to the second drive circuit 50B changes from "H" to "L" (i.e., when a voltage of 0 volts is applied to the PWM signal (PWM1) input terminal), the second drive circuit 50B operates as follows.

[0075] Since the voltage of capacitor C2 is +4 V, the potential of node H2 changes from +1 V to −4 V. As a result, a voltage of −4 V is applied to the gate terminal of transistor FET3.

[0076] The power supply voltage Vdd of +1 V continues to be applied to the source terminal of the transistor FET3. At this time, the gate-source voltage of the transistor FET3 is −5 V, which is lower than the threshold voltage (−2.5 V), so the transistor FET3 is turned on.

[0077] Furthermore, because the potential at node L2, which is connected to the signal input terminal of the PWM signal (PWM1), is 0 volts, a voltage of 0 volts is applied to the gate terminal of transistor FET4. Also, 0 volts (ground) continues to be applied to the source terminal of transistor FET4. At this time, the gate-source voltage of transistor FET4 is 0 volts, which is lower than the threshold voltage (+2.5 volts), so transistor FET4 is turned off.

[0078] In this way, when the PWM signal (PWM1) input to the second drive circuit 50B goes low, the transistor FET3 turns on and the transistor FET4 turns off. At this time, a voltage of +1 volt is applied to the output terminal (node ​​O2) of the second drive circuit 50B.

[0079] Furthermore, when the PWM signal (PWM1) input to the second drive circuit 50B changes from "L" to "H" again, the state returns to the above, and the transistor FET3 is again turned off and the transistor FET4 is again turned on.

[0080] By such operation of the second drive circuit 50B, a PWM signal (PWM1) is input from the PWM signal input terminal, and FET3 and FET4 are alternately turned on and off.

[0081] At the terminals of the speaker SP, a voltage swing between the power supply voltage Vdd (+1 volt) and ground (0 volt) occurs in synchronization with the PWM signals (PWM0, PWM1). When the transistors FET1 and FET4 are both on and the transistors FET2 and FET3 are both off (i.e., PWM0 is "L" and PWM1 is "H"), and when the transistors FET1 and FET4 are both off and the transistors FET2 and FET3 are both on (PWM0 is "H" and PWM1 is "L"), the drive circuit 60 drives the speaker SP with a voltage of +1 volt (power supply voltage Vdd).

[0082] In the configuration of the drive circuit 60 described above, the logic-level voltage conversion circuits 30A and 30B apply a voltage of the same level as the signal voltage of the PWM signals (PWM0 and PWM1) input to the PWM signal input terminals to the gate terminals of the NMOSFETs (transistors FET2 and FET4). When the PWM signals (PWM0 and PWM1) are "L," a voltage value of a voltage level obtained by subtracting the power supply voltage of the microcomputer 10 from the voltage value of the voltage Vdd of the voltage variable power supply 20 (i.e., Vdd-Vm, where Vm is the power supply voltage of the microcomputer 10) is applied to the gate terminals of the PMOSFETs (transistors FET1 and FET3). When the PWM signals (PWM0 and PWM1) are "H," a voltage of the same level as the voltage Vdd of the voltage variable power supply 20 is applied to the gate terminals of the PMOSFETs (transistors FET1 and FET3).

[0083] For example, as described above, when the PWM signals (PWM0, PWM1) input to the PWM signal input terminals are "L" (voltage value 0 volts), the logic level voltage conversion circuits 30A, 30B apply 0 volts to the gate terminals of the transistors FET2, FET4. Furthermore, when the signal voltage of the input PWM signals (PWM0, PWM1) is "L" (voltage value 0 volts), if the power supply voltage Vm of the microcomputer 10 is 5 volts and the voltage Vdd is +1 volt, the logic level voltage conversion circuits 30A, 30B apply -4 volts (Vdd-Vm=(+1)-(+5)) to the gate terminals of the transistors FET1, FET3. This allows the threshold voltage to be applied to the gate terminals, turning on the transistors FET1, FET3 and enabling appropriate switching operation, even when the voltage Vdd is lower than the voltage Vm.

[0084] As described above, voltage Vdd of voltage variable power supply 20 can be set arbitrarily, and may be set to the same voltage as voltage Vm of microcomputer 10. In this case (i.e., when voltage Vdd = voltage Vm in the above), when logic-level voltage conversion circuits 30A and 30B receive an "L" PWM signal (PWM0, PWM1) (voltage value 0 volts), they apply a voltage (voltage value 0 volts) equal to the signal voltage of the input PWM signal (PWM0, PWM1) to the gate terminals of PMOSFETs (FET1, FET3), resulting in no conversion of the input voltage. In this case, as long as voltage Vdd is at a predetermined magnitude, there is no problem in turning on the PMOSFETs.

[0085] The operation of drive circuit 60 described above is for when power supply voltage Vdd of voltage variable power supply 20 is lower than the power supply voltage of microcomputer 10. However, the operation of drive circuit 60 is similar when power supply voltage Vdd of voltage variable power supply 20 is the same as or higher than the power supply voltage of microcomputer 10. For example, if power supply voltage Vdd is set to +8 volts, when an "H" PWM signal (PWM0) is input to first drive circuit 50A, +8 volts is applied to the gate of transistor FET1. At this time, the gate-source voltage of transistor FET1 becomes 0 volts, which is higher than the threshold voltage (-2.5 volts), so transistor FET1 is turned off. Thereafter, capacitor C1 maintains a potential difference of -3 volts. When the PWM signal (PWM0) goes low, +3 volts (Vdd-Vm: (+8V)-(+5V)) is applied to the gate of transistor FET1, and the gate-source voltage of transistor FET1 becomes -5 volts, which is lower than the threshold voltage (-2.5 volts), so transistor FET1 turns on.

[0086] As described above, in the first drive circuit 50A, the voltage of the input PWM signal (PWM0) (i.e., the logic level voltage of the microcomputer 10) is converted and input to the gate of the transistor FET1 using the functions of the capacitor C1, Schottky barrier diode SBD1, and other components of the logic level voltage conversion circuit 30A. In the second drive circuit 50B, the voltage of the input PWM signal (PWM1) (i.e., the logic level voltage of the microcomputer 10) is level-shifted and converted and input to the gate of the transistor FET3 using the functions of the capacitor C2, Schottky barrier diode SBD2, and other components of the logic level voltage conversion circuit 30B. By including these logic level voltage conversion circuits 30A and 30B, the drive circuit 60 can appropriately switch (on / off) the transistors FET1 and FET3 based on the audio signal, even when the power supply voltage Vdd is lower or higher than the power supply voltage of the microcomputer 10, and can output a drive voltage of the same voltage value as the power supply voltage Vdd to the speaker SP.

[0087] That is, the audio output circuit 100 includes a microcomputer that generates a differential PWM signal based on audio data, a drive circuit 60 that switches an H-bridge circuit 40 in accordance with the differential PWM signal to output a drive voltage to the speaker SP, and a voltage-variable power supply 20 that applies a variable voltage to the drive circuit 60 and causes the drive circuit 60 to output a drive voltage corresponding to the variable voltage. The drive circuit 60 also includes a logic-level voltage conversion circuit 30 that converts the voltage of an input PWM signal (PWM0, PWM1) to a different voltage level depending on the power supply of the microcomputer 10 and the voltage of the voltage-variable power supply 20, and inputs the converted voltage to the gate terminals of the PMOSFETs (FET1, FET3) of the H-bridge circuit 40. The audio output circuit 100 controls the output voltage of the H-bridge circuit 40 by changing the voltage of the voltage-variable power supply 20. This configuration of the audio output circuit 100 makes it possible to adjust the output volume of the speaker SP by changing the voltage of the voltage-variable power supply 20, and to output high-quality audio while employing a fully digital system.

[0088] Furthermore, according to the configuration of the drive circuit 60 of the audio output circuit 100, even when the voltage Vdd of the voltage variable power supply 20 is low relative to the signal voltage of the PWM signals (PWM0, PWM1) (i.e., the power supply voltage Vm of the microcomputer 10), the transistors FET1 and FET3 are turned on and off, so that it is possible to output audio at a low volume according to the voltage Vdd.

[0089] Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various modifications or improvements can be made to the above embodiments without departing from the spirit of the present invention. Furthermore, one or more of the requirements described in the above embodiments may be omitted. Such modifications, improvements, and omitted forms are also included within the technical scope of the present invention. [Explanation of symbols]

[0090] 10 Microcomputer 20 Variable voltage power supply 30 Logic level voltage conversion circuit 40 H-bridge circuit 60 Drive circuit 100 Audio output circuit FET1, FET3 PMOSFET FET2, FET4 NMOSFET R11,R21,R31,R41 Resistor SBD1, SBD2 Schottky barrier diodes SP speaker

Claims

1. a microcomputer that generates a differential PWM signal based on audio data; a drive circuit that performs a switching operation of an H-bridge circuit in accordance with the differential PWM signal to output a drive voltage to a speaker, a variable voltage power supply that applies a variable voltage to the drive circuit and causes the drive circuit to output the drive voltage corresponding to the variable voltage; The drive circuit a logic level voltage conversion circuit that converts the voltage of an input PWM signal to a voltage level different from the voltage of a power supply of the microcomputer and the voltage variable power supply, and inputs the converted voltage to a gate terminal of a PMOSFET of the H-bridge circuit; The PMOSFET is a source terminal connected to the variable voltage power supply and a gate terminal connected to the variable voltage power supply via a resistor; The logic level voltage conversion circuit includes: a Schottky barrier diode connected between a gate terminal of the PMOSFET and the voltage variable power supply; a capacitor connected between the anode terminal of the Schottky barrier diode and a PWM signal input terminal, An audio output circuit, characterized in that the output voltage of the H-bridge circuit is controlled by changing the voltage of the variable voltage power supply, thereby making it possible to vary the output volume of the speaker.

2. The FETs constituting the H-bridge circuit are two of the PMOSFETs and two NMOSFETs, the drain terminals of the two NMOSFETs are connected to the drain terminals of different PMOSFETs, a gate terminal of the NMOSFET is connected to the PWM signal input terminal and is also connected to ground via a resistor; 2. The audio output circuit according to claim 1, wherein a source terminal of the NMOSFET is connected to the ground.

3. 3. The audio output circuit according to claim 2, wherein the logic level voltage conversion circuit applies a voltage of a voltage level equal to the signal voltage of the PWM signal to the gate terminal of the NMOSFET, and in a predetermined case applies a voltage of a voltage level obtained by subtracting the voltage value of the voltage variable power supply from the voltage value of the power supply voltage of the microcomputer to the gate terminal of the PMOSFET.

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