Quantum devices

Abstract

To provide a quantum device that correctly determines a difference between a state of a first quantum bit and a state of a second quantum bit by comparing a signal obtained by amplifying a signal indicating the state of the first quantum bit and a signal obtained by amplifying a signal indicating the state of the second quantum bit, and, in detail, improves a correct answer rate in a reading-out in the state of each quantum bit by making an input signal of a second quantum circuit change an input signal obtained by reversing it to the input signal of a first quantum circuit so that an output of the first quantum circuit and an output of a second quantum circuit are reversed between 0 and 1 of a logical value through a determination part.SOLUTION: A quantum device comprises: a first quantum circuit; a second quantum circuit; and a latch circuit connected to the first and second quantum circuits. The latch circuit has a function for latching a state of a first quantum bit output from the first quantum circuit to amplify a signal indicating a state of the first quantum bit, and a function for latching the state of the second quantum bit output from the second quantum circuit to amplify the signal indicating the state of a second quantum bit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to quantum devices, qubit readout devices and electronic circuits. [Background technology]

[0002] Research and development into quantum computers and quantum annealing machines is progressing. For example, Non-Patent Document 1 reports an example of two logical operations using semiconductor quantum bits, while Non-Patent Document 2 reports the creation of more than 50 quantum bits using superconductors. Furthermore, Non-Patent Document 3 is an experimental example of a quantum annealing machine, and this technology has already been commercialized. As for quantum computer technology, the development of related technologies using superconductors, as in this example, is progressing. This is because it is relatively easy to experimentally achieve a superconducting state with no resistance for the time required to maintain a quantum state (coherence time). However, large-scale integration of superconducting devices is difficult.

[0003] Figure 1 of Patent Document 1 shows an electrical gate pulse line connected to a qubit structure that performs quantum operations. While Patent Document 1 describes monitoring changes in capacitance during writing, the technology described in Patent Document 1 does not amplify signals that indicate the state of the qubit as an integrated circuit. Therefore, the technology described in Patent Document 1 cannot accurately determine differences in the qubit states as an integrated circuit to improve the accuracy rate of reading the qubit states. Figure 1 of Non-Patent Document 4 shows a pair of single-electron devices connected in cross-coupled connection. In the technology described in Non-Patent Document 4, the single-electron device is used as a memory in the same way as a static random access memory (SRAM). Therefore, in the technology described in Non-Patent Document 4, the single-electron device cannot be used as a sensor to read the difference in potential between the pair of single-electron devices, and the state of the quantum bit of a quantum circuit connected to the single-electron device cannot be read.

[0004] Non-Patent Document 5 describes the reading of spin qubits (detection of the spin state of qubits). Non-Patent Document 5 also describes that in spin-to-charge conversion, the spin state is detected through the effect on the movement of charge, making it possible to measure electron spin. However, the technology described in Non-Patent Document 5 does not amplify the signal indicating the spin state of the qubit using an integrated circuit. Therefore, the technology described in Non-Patent Document 5 cannot accurately determine differences in the spin states of qubits and improve the accuracy rate of reading the spin states of qubits. Non-Patent Documents 6 and 7 describe techniques for reading out quantum bits. In the technique described in Non-Patent Document 6, because the current change due to the Coulomb blockade phenomenon is small, at the pA level, multiple amplifier circuits are configured in the subsequent stage, and multiple amplification of the signal is performed. Therefore, in the techniques described in Non-Patent Documents 6 and 7, when the number of quantum bits is large, the circuit area becomes very large, making it unrealistic. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 7,830,695 [Non-patent literature]

[0006] [Non-Patent Document 1] M. Veldhorst, CH Yang, JCC Hwang, W. Huang, JP Dehollain, JT Muhonen, S. Simmons, A. Laucht, FE Hudson, KM Itoh, A. Morello & AS Dzurak “A two-qubit logic gate in silicon” Nature volume 526, pages410-414(2015) [Non-patent document 2] Frank Arute, Kunal Arya et al. “Quantum supremacy using a programmable superconducting processor” Nature volume 574, pages505-510(2019) [Non-patent document 3] MW Johnson et al. “Quantum annealing with manufactured spins” Nature vol 473, pp.194-198 (2011). [Non-patent document 4] Souvik Mahapatra, AM Ionescu “A novel single electron SRAM architecture” Materials Science(2004), 4th IEEE Conference on Nanotechnology, 2004 DOI: 10.1109 / NANO.2004.1392327Corpus ID:20005522 [Non-patent document 5] Nakul Shaji et al. “Spin blockade and lifetime-enhanced transport in a few-electron Si / SiGe double quantum dot” Nature Physics 4, 540-544 (2008) [Non-patent document 6] Andrea Ruffino et al. “A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I / Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots” 2021 IEEE International Solid- State Circuits Conference (ISSCC) [Non-Patent Document 7] Andrea Morello et al. “Single-shot readout of an electron spin in silicon” Nature vol 467.p687 (2010) [Non-patent document 8] T Tanamoto, Y Nishi, J Deguchi “Quantum Annealing Machines Based on Semiconductor Nanostructures” Journal of the Physical Society of Japan 88 (6), 061013 (2019) [Non-Patent Document 9] Behzad Razavi “Design of Analog CMOS Integrated Circuits” (MCGRAW HILL BOOK CO, 2000) ISBN: 9780072380323 Summary of the Invention [Problem to be solved by the invention]

[0007] In view of the above, the present invention aims to provide a quantum device that can improve the accuracy rate of reading the state of a quantum bit by accurately determining the difference between the state of a first quantum bit and the state of a second quantum bit, and by operating the second quantum circuit so that the logical value of the output of the first quantum circuit and the logical value of the output of the second quantum circuit are inverted between 0 and 1. Another object of the present invention is to provide a quantum bit reading device that can read the state of a quantum bit in a quantum circuit connected to a single-electron element while miniaturizing the circuit by reading the difference between the potential of a first single-electron element and the potential of a second single-electron element. Another object of the present invention is to provide an electronic circuit that can read the difference between the potential of a first single electron element and the potential of a second single electron element. [Means for solving the problem]

[0008] One aspect of the present invention is a quantum device comprising a first quantum circuit, a second quantum circuit, and a latch circuit connected to the first quantum circuit and the second quantum circuit, wherein the latch circuit has the function of latching the state of a first quantum bit output from the first quantum circuit and amplifying a signal indicating the state of the first quantum bit, and the function of latching the state of a second quantum bit output from the second quantum circuit and amplifying a signal indicating the state of the second quantum bit.

[0009] One aspect of the present invention is a quantum bit reading device comprising a first single-electron element connected to a first quantum circuit, a second single-electron element connected to a second quantum circuit, and a differential amplifier circuit connected to the first single-electron element and the second single-electron element, wherein the difference between the potential of the first single-electron element and the potential of the second single-electron element amplified by the differential amplifier circuit is read.

[0010] A quantum bit reading device according to one aspect of the present invention may include a first amplifier circuit disposed between the first single-electron element and the differential amplifier circuit, and a second amplifier circuit disposed between the second single-electron element and the differential amplifier circuit.

[0011] In one aspect of the quantum bit readout device of the present invention, the first amplifier circuit may include a first conductivity type transistor and a second conductivity type transistor, and the second amplifier circuit may include a first conductivity type transistor and a second conductivity type transistor.

[0012] One aspect of the present invention is a quantum bit reading device comprising a first single-electron element connected to a first quantum circuit, a second single-electron element connected to a second quantum circuit, and an SRAM (Static Random Access Memory) connected to the first single-electron element and the second single-electron element, and reading a difference between the potential of the first single-electron element and the potential of the second single-electron element output via the SRAM.

[0013] In one aspect of the quantum bit reading device of the present invention, the SRAM may include a first access transistor connected to the first single-electron element, a second access transistor connected to the second single-electron element, a first inverter connected to the first access transistor, and a second inverter connected to the second access transistor, and the first inverter and the second inverter may be cross-coupled.

[0014] The quantum bit reading device according to one aspect of the present invention may include a first amplifier circuit disposed between the first single-electron device and the SRAM, and a second amplifier circuit disposed between the second single-electron device and the SRAM.

[0015] One aspect of the present invention is a quantum bit reading device comprising a sense amplifier and an equalizer connected to a first single-electron element connected to a first quantum circuit and a second single-electron element connected to a second quantum circuit, and reading a difference between the potential of the first single-electron element and the potential of the second single-electron element output via the sense amplifier and equalizer.

[0016] In one embodiment of the present invention, the quantum bit readout device may include the same sense amplifiers and equalizers as those found in a typical, more complex dynamic random access memory (DRAM). Typical DRAMs use a circuit that reads the difference between charges stored in two capacitors. A feature of the present invention is the use of a single-electron element instead of the capacitors found in typical DRAMs. In particular, when the single-electron element is a charge quantum bit, it is useful for reading small potential differences between charge quantum bits.

[0017] One aspect of the present invention is a quantum bit readout device comprising: a first single-electron element connected to a first quantum circuit; a second single-electron element connected to a second quantum circuit; and a cross-coupled MOS transistor circuit connected to the first single-electron element and the second single-electron element, wherein the cross-coupled MOS transistor circuit comprises a pair of P-channel MOS transistors connected in cross-couple connection; and a difference between the potential of the first single-electron element and the potential of the second single-electron element output via the cross-coupled MOS transistor circuit is read.

[0018] In one aspect of the quantum bit readout device of the present invention, the differential amplifier circuit may include a first bipolar transistor having a base connected to the first single-electron element, and a second bipolar transistor having a base connected to the second single-electron element.

[0019] In the quantum bit readout device according to one aspect of the present invention, the potential of the first single electron device and the potential of the second single electron device may be output as a result of inversion.

[0020] The quantum bit readout device according to one aspect of the present invention may include a determination unit that determines whether the potential of the first single electron device is 0 or 1 by comparing the potential of the second single electron device with the potential of the first single electron device.

[0021] One aspect of the present invention is an electronic circuit comprising: a first memory cell array; a first selector that selects a first single-electron element from the first memory cell array; a second memory cell array; and a second selector that selects a second single-electron element from the second memory cell array, wherein a difference between a potential of the first single-electron element selected by the first selector and a potential of the second single-electron element selected by the second selector is read.

[0022] The electronic circuit according to an aspect of the present invention may include a determination unit that determines whether the potential of the first single electron element is 0 or 1 by comparing the potential of the second single electron element with the potential of the first single electron element.

[0023] The quantum bit may be a spin quantum bit, or the single-electron device may be a charge quantum bit itself. If the quantum bit is a spin quantum bit, it may be coupled to the single-electron device via a tunnel oxide film or the like. [Effects of the Invention]

[0024] According to the present invention, a quantum device can be provided that can accurately determine the difference between the state of a first quantum bit and the state of a second quantum bit, and can improve the accuracy rate of reading out the state of a quantum bit by adjusting the input signal of the second quantum circuit so that the output of the first quantum circuit and the output of the second quantum circuit are inverted between the logical values ​​of 0 and 1. Furthermore, according to the present invention, it is possible to provide a quantum bit reading device that can read the state of a quantum bit in a quantum circuit connected to a single-electron element while miniaturizing the circuit by reading the difference between the potential of a first single-electron element and the potential of a second single-electron element. Furthermore, according to the present invention, it is possible to provide an electronic circuit that can read the difference between the potential of the first single electron element and the potential of the second single electron element. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a diagram illustrating an example of a quantum device according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a quantum bit readout device according to the first embodiment. [Figure 3] 3 is a diagram for explaining an example of the characteristics of a single-electron device (specifically, a SET (single-electron transistor)) such as the single-electron device shown in FIG. 2. FIG. [Figure 4] FIG. 3 is a diagram for explaining the principle of a first amplifier circuit using MOS coupling such as the amplifier circuit (P-channel MOS transistor) shown in FIG. 2. [Figure 5]3 is a diagram showing the relationship between the gate voltage (horizontal axis) of a single-electron device (specifically, a SET (single-electron transistor)) such as the single-electron device shown in FIG. 2 and the potential (vertical axis) of an output terminal amplified by MOS junction such as the amplifier circuit (P-channel MOS transistor) shown in FIG. [Figure 6] FIG. 10 is a diagram illustrating an example of a quantum bit readout device according to a second embodiment. [Figure 7] 7 is a diagram for explaining a first amplification by a P-channel MOS transistor and an N-channel MOS transistor such as the amplifier circuit shown in FIG. 6. FIG. [Figure 8] 7 is a diagram showing the results of a differential amplification simulation using the differential amplifier circuit shown in FIG. 6. [Figure 9] FIG. 10 is a diagram illustrating an example of a quantum bit readout device according to a third embodiment. [Figure 10] FIG. 10 is a diagram showing the results of a circuit simulation (time change) shown in FIG. [Figure 11] FIG. 10 is a diagram illustrating an example of a quantum bit readout device according to a fourth embodiment. [Figure 12] FIG. 10 is a diagram illustrating an example of a quantum bit readout device according to a fifth embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of a quantum bit readout device according to a sixth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of a quantum bit readout device according to a seventh embodiment. [Figure 15] FIG. 13 is a diagram illustrating an example of a quantum bit readout device according to an eighth embodiment. [Figure 16] FIG. 13 is a diagram illustrating an example of an electronic circuit according to a ninth embodiment. [Figure 17] FIG. 10 is a diagram illustrating an example in which one single electron element (first single electron element 3A1) of a plurality of single electron elements included in a first single electron element array 3A is used as the single electron element 2A in the first to ninth embodiments, and one single electron element (second single electron element 3C1) of a plurality of single electron elements included in a second single electron element array 3C is used as the single electron element 2B in the first to ninth embodiments. [Figure 18] FIG. 14 is a diagram showing the time change of voltage in the quantum bit readout device of the sixth embodiment shown in FIG. [Figure 19] FIG. 13 is a diagram for explaining an example in which a NAND flash memory is used as the first single electron element array and a NAND flash memory is used as the second single electron element array in the electronic circuit of the ninth embodiment. [Figure 20] FIG. 10 is a diagram illustrating a simulation of a situation in which the potential in a single-electron device shifts depending on the presence or absence of an electron in a quantum dot connected to the single-electron device. DETAILED DESCRIPTION OF THE INVENTION

[0026] Before describing embodiments of the quantum device, quantum bit readout device, and electronic circuit of the present invention, a description will be given of prior art related to measurement of quantum devices.

[0027] (Prior art of measurement) Progress has been slow in quantum bits using electron spin or hole spin. This is because quantum devices using spin have faced difficult challenges in the process of measuring the spin state. Measuring the spin state requires electronic circuits, but spin is a magnetic property, and conventional electronic circuits do not have a mechanism for directly measuring the magnetization quantity, so it was necessary to convert the magnetic property into a charge state. Specifically, there is a method called spin blockade. This method utilizes the fact that when a quantum dot is added and the direction of the electron spin inside is fixed, the electrons are blocked or flow depending on whether the spin coming from the quantum bit is up or down. This is based on the Pauli exclusion principle, which states that two electrons with the same spin direction cannot occupy the same energy level. However, as shown in Figure 3, the current value of a single-electron device at which Coulomb blockade can be observed is on the order of nanoamperes, which is extremely small compared to the voltage range in which a typical CMOS circuit operates. For this reason, in order to amplify the minute signal from a single single-electron device, multiple amplifier circuits, as described in Non-Patent Document 6, are required. With this conventional method, an extremely large amount of circuit area is required to amplify the signal of just one single electron, making it difficult to integrate quantum bits.

[0028] (manufacturing cost) Furthermore, creating new device structures poses significant challenges. Non-Patent Document 1 and Non-Patent Document 3, for example, require new ultrafine structures. The gate length of silicon transistors currently used in smartphones is 16 nm or less, and chip fabrication costs more than 1 trillion yen. Even a 40 nm version would require approximately 400 billion yen. Designing a new amplifier circuit from scratch is expected to require enormous development costs, posing a major obstacle to industrialization. Therefore, it is desirable to use conventional circuits as much as possible.

[0029] Hereinafter, embodiments of the quantum device, quantum bit readout device, and electronic circuit of the present invention will be described.

[0030] [First embodiment] FIG. 1 is a diagram illustrating an example of a quantum device 1 according to the first embodiment. 1, the quantum device 1 of the first embodiment includes a quantum circuit 1A, a quantum circuit 1B, a latch circuit 1C, and a determination unit 1D. The latch circuit 1C is connected to the quantum circuit 1A and the quantum circuit 1B by one or more wires. The quantum circuit 1A and the quantum circuit 1B are configured as a pair. Latch circuit 1C has the function of latching the state of the quantum bit (spin state in the case of a spin quantum bit, or charge state in the case of a charge quantum bit) output from quantum circuit 1A and amplifying the signal indicating the state of the spin quantum bit. In other words, latch circuit 1C includes a circuit that amplifies the signal indicating the state of the quantum bit output from quantum circuit 1A. Furthermore, the latch circuit 1C has the function of latching the state of the quantum bit output from the quantum circuit 1B and amplifying the signal indicating the state of the quantum bit. In other words, the latch circuit 1C includes a circuit that amplifies the signal indicating the state of the quantum bit output from the quantum circuit 1B. The latch circuit 1C and decision unit 1D shown in Fig. 1 can be expressed as, for example, the quantum bit readout device 2 shown in Fig. 2. The latched value is determined by the decision unit 1D and is finally output as the calculation result.

[0031] 2 is a diagram showing an example of the quantum bit readout device 2 etc. of the first embodiment, in which the quantum bit is a spin quantum bit. In the example shown in FIG. 2, the quantum bit readout device 2 includes a single electron device 2A, a single electron device 2B, an amplifier circuit 2C, an amplifier circuit 2D, a differential amplifier circuit 2E, and a determination unit 2I (see FIG. 6). The single-electron device 2A measures the state of the spin quantum bit (the spin state of the quantum bit) of the quantum circuit 1A. The gate of the single-electron device 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron device 2A is connected to an amplifier circuit 2C that functions as a first-stage amplifier circuit and a differential amplifier circuit 2E that functions as a second-stage amplifier circuit. The other of the source and drain of the single-electron device 2A is, for example, grounded. The single-electron element 2B measures the state of the spin qubit of the quantum circuit 1B. The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to an amplifier circuit 2D that functions as a first-stage amplifier circuit and a differential amplifier circuit 2E that functions as a second-stage amplifier circuit. The other of the source and drain of the single-electron element 2B is, for example, grounded.

[0032] In the example shown in FIG. 2, an amplifier circuit 2C is disposed between the single electron element 2A and the differential amplifier circuit 2E. The amplifier circuit 2C is configured by a P-channel MOS transistor. Specifically, one of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2C is connected to one of the source and drain of the single electron element 2A. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2C is connected to a predetermined potential V D is connected to. The amplifier circuit 2D is disposed between the single electron element 2B and the differential amplifier circuit 2E. The amplifier circuit 2D is configured by a P-channel MOS transistor. Specifically, one of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2D is connected to one of the source and drain of the single electron element 2B. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2D is connected to a predetermined potential V D is connected to. In the example shown in FIG. 2, the quantum bit readout device 2 includes an amplifier circuit 2C and an amplifier circuit 2D, but in other examples, the quantum bit readout device 2 does not necessarily include the amplifier circuit 2C and the amplifier circuit 2D. The single-electron elements (2A, 2B) are generally arranged in an array as shown in Figures 17 and 19, which will be described later, so that it is possible to select which two single-electron elements to select (in Figures 17 and 19, the single-electron elements are designated by the symbols 3A1 and 3C1, and the single-electron element array is designated by the symbols 3A and 3C). At this time, the selected single-electron elements (2A, 2B) and the amplifier circuit (N-channel MOS transistors 2E3, 2E4 of the differential amplifier circuit 2E, etc.) are connected by transistors (N-channel MOS transistors 2E1, 2E2) that apply a voltage to the word line WL, and a signal is input to the amplifier circuit (differential amplifier circuit 2E).

[0033] In the example shown in FIG. 2, the differential amplifier circuit 2E includes N-channel MOS transistors 2E1, 2E2, 2E3, 2E4, and 2E7, and P-channel MOS transistors 2E5 and 2E6. One of the source and drain of the N-channel MOS transistor 2E1 is connected to one of the source and drain of the single-electron element 2A. The other of the source and drain of the N-channel MOS transistor 2E1 is connected to the gate of the N-channel MOS transistor 2E3. The gate of the N-channel MOS transistor 2E1 is connected to the word line WL. One of the source and drain of the N-channel MOS transistor 2E3 is connected to the first output terminal Vout1 of the differential amplifier circuit 2E, one of the source and drain of the P-channel MOS transistor 2E5, the gate of the P-channel MOS transistor 2E5, and the gate of the P-channel MOS transistor 2E6. The other of the source and drain of the N-channel MOS transistor 2E3 is connected to one of the source and drain of the N-channel MOS transistor 2E7. The other of the source and drain of the N-channel MOS transistor 2E7 is grounded, for example.

[0034] One of the source and drain of the N-channel MOS transistor 2E2 is connected to one of the source and drain of the single-electron element 2B. The other of the source and drain of the N-channel MOS transistor 2E2 is connected to the gate of the N-channel MOS transistor 2E4. The gate of the N-channel MOS transistor 2E2 is connected to the word line WL. One of the source and drain of the N-channel MOS transistor 2E4 is connected to the second output terminal Vout2 of the differential amplifier circuit 2E and one of the source and drain of the P-channel MOS transistor 2E6, and the other of the source and drain of the N-channel MOS transistor 2E4 is connected to one of the source and drain of the N-channel MOS transistor 2E7. The other of the source and drain of the P-channel MOS transistor 2E5 and the other of the source and drain of the P-channel MOS transistor 2E6 are connected to a predetermined potential V D is connected to. The first output terminal Vout1 and the second output terminal Vout2 of the differential amplifier circuit 2E are connected to the determination unit 2I. The differential amplifier circuit of the present invention is the most basic one, and various amplifier circuits such as those shown in Non-Patent Document 9 may be used instead.

[0035] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and the differential amplifier circuit 2E (the potential at the first output terminal Vout1 of the differential amplifier circuit 2E) and the potential of the single electron element 2B amplified by the amplifier circuit 2D and the differential amplifier circuit 2E (the potential at the second output terminal Vout2 of the differential amplifier circuit 2E). In detail, the potential difference between the potential of the single electron element 2A and the potential of the single electron element 2B is amplified by the differential amplifier circuit 2E, the amplifier circuit 2C, and the amplifier circuit 2D, and is output to the output terminals Vout1 and Vout2. In other words, the potential difference between the first output terminal Vout1 and the second output terminal Vout2 is greater than the original potential difference between the potential of the single electron element 2A and the potential of the single electron element 2B. Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the amplifier circuit 2C and the differential amplifier circuit 2E with the potential of the single electron element 2B amplified by the amplifier circuit 2D and the differential amplifier circuit 2E, thereby determining whether the potential is "0" or "1," which is easy to handle in a subsequent digital circuit.

[0036] In the example shown in FIG. 2, the determination unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and the differential amplifier circuit 2E and the potential of the single electron element 2B amplified by the amplifier circuit 2D and the differential amplifier circuit 2E, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single electron elements 2A and 2B while miniaturizing the entire circuit.

[0037] In other words, in the example shown in FIGS. 1 and 2, a signal indicating the state of the quantum bit output from quantum circuit 1A (more specifically, in the case of a spin quantum bit, a signal indicating the spin state of the quantum bit of quantum circuit 1A measured by single-electron device 2A and output) is amplified by latch circuit 1C (more specifically, amplifier circuit 2C and differential amplifier circuit 2E) and the amplified signal (more specifically, the potential of first output terminal Vout1) is used as the signal indicating the state of the quantum bit output from quantum circuit 1B (more specifically, in the case of a spin quantum bit, a signal indicating the spin state of the quantum bit of quantum circuit 1A measured by single-electron device 2A and output) is used as the signal amplified by latch circuit 1C (more specifically, amplifier circuit 2C and differential amplifier circuit 2E). The difference between the signal amplified by the latch circuit 1C (more specifically, the amplifier circuit 2D and the differential amplifier circuit 2E) and the signal (more specifically, the potential at the second output terminal Vout2) is amplified by a larger difference between the signals of the two unit electron elements 2A and the single-electron element 2B without an amplifier circuit. By more accurately comparing the output results of the single-electron elements 2A and 2B, which are minute signals, it is possible to accurately determine the difference between the (spin) quantum bit state of the quantum circuit 1A and the (spin) quantum bit state of the quantum circuit 1B. More specifically, by inputting the input signals of the quantum circuit 1A and the quantum circuit 1B in opposite directions so that the expected logical output of the quantum circuit 1A and the expected logical output of the quantum circuit 1B are opposite, the latch circuit 1C operates so that the actual output signal is inverted between the first output terminal Vout1 and the second output terminal Vout2, thereby improving the accuracy rate of reading out the quantum bit state.

[0038] Figure 3 is a diagram for explaining an example of the characteristics of a single-electron device (specifically, a SET (single-electron transistor)) such as the single-electron device 2A shown in Figure 2. Specifically, Figures 3(A) and 3(B) show the gate voltage dependence of IV (Figure 3(A)) and the gate voltage V and drain voltage dependence (Figure 3(B)) when the capacitances of the two tunnel films of the single-electron device are 1 aF and 10 aF, the gate capacitance is 2 aF, and the tunnel film resistances are 100 kΩ and 1 MΩ. Figures 3(C) and 3(D) show the gate voltage dependence of IV (Figure 3(C)) and the gate voltage V and drain voltage dependence (Figure 3(D)) when the capacitances of the two tunnel films of the single-electron device are 1 aF and 20 aF, the gate capacitance is 2 aF, and the tunnel film resistances are 100 kΩ and 2 MΩ. As shown in this figure, the current flowing through the single-electron device is on the order of nanoamperes, which is small compared to a typical CMOS. Here, aF is an attofarad, and 10 -18 Indicates F.

[0039] FIG. 4 is a diagram illustrating the principle of a first amplifier circuit using coupled MOS transistors, such as amplifier circuit 2C (P-channel MOS transistor) shown in FIG. 2. One of the features of the present invention is that, rather than directly connecting two single-electron devices to a second amplifier circuit, the single-electron device and a MOS transistor are first connected in series, and the potential of the single-electron device is adjusted before connecting it to the second amplifier circuit. The reason for this is that, as explained above in FIG. 3, the current value of the single-electron device is on the order of nanoamperes, which is far from the current and voltage ranges used in conventional CMOS circuits. If the single-electron device were directly connected to the second amplifier circuit, the output signal of the single-electron device would fall within the noise signal level of the second amplifier circuit, making it impossible to accurately determine the signal from the single-electron device. By connecting a MOS transistor to the first amplifier circuit, stable connection to the second amplifier circuit is possible. FIG. 4 illustrates the principles of amplification in the saturation region and the linear region.

[0040] FIG. 5 shows the gate voltage V of a single-electron device (specifically, a SET (single-electron transistor)) such as the single-electron device 2A shown in FIG. G 5A shows the relationship between the gate voltage Vout [V] (horizontal axis) and the potential Vout [V] (vertical axis) of the output terminal amplified by a MOS transistor combination such as the amplifier circuit 2C (P-channel MOS transistor) shown in FIG. 2. In detail, FIG. ... G The figure shows the relationship between the gate voltage V [V] (horizontal axis) and the output terminal potential Vout [V] (vertical axis). Figure 5(B) shows the gate voltage V when the gate width Wp of the P-channel MOS transistor in the amplifier circuit is set to 1 μm. G 5 shows the relationship between [V] (horizontal axis) and the potential Vout [V] (vertical axis) of the output terminal. As shown in Fig. 5, the potential Vout in the saturation region is higher than the potential Vout in the linear region.

[0041] [Second embodiment] A second embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will now be described. The quantum device 1 and quantum bit readout device 2 of the second embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the second embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0042] 6 is a diagram showing an example of the quantum bit readout device 2 etc. of the second embodiment. The latch circuit 1C and the decision unit 1D of the quantum device 1 of the second embodiment can be expressed as the quantum bit readout device 2 shown in FIG. 6, for example. 6, the quantum bit readout device 2 includes a single-electron element 2A, a single-electron element 2B, an amplifier circuit 2C, an amplifier circuit 2D, a differential amplifier circuit 2E, and a determination unit 21. The amplifier circuit 2C includes an N-channel MOS transistor 2C1 and a P-channel MOS transistor 2C2. The amplifier circuit 2D includes an N-channel MOS transistor 2D1 and a P-channel MOS transistor 2D2. The differential amplifier circuit 2E includes N-channel MOS transistors 2E3, 2E4, and 2E7, and P-channel MOS transistors 2E5 and 2E6. The single-electron element 2A measures the state of the spin qubit of the quantum circuit 1A. The gate of the single-electron element 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron element 2A is connected to one of the source and drain of an N-channel MOS transistor 2C1 of an amplifier circuit 2C that functions as a first-stage amplifier circuit, and to the gate of an N-channel MOS transistor 2E3 of a differential amplifier circuit 2E that functions as a second-stage amplifier circuit. The other of the source and drain of the single-electron element 2A is, for example, grounded. The single-electron element 2B measures the state of the spin qubit of the quantum circuit 1B. The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to one of the source and drain of an N-channel MOS transistor 2D1 of an amplifier circuit 2D that functions as a first-stage amplifier circuit, and to the gate of an N-channel MOS transistor 2E4 of a differential amplifier circuit 2E that functions as a second-stage amplifier circuit. The other of the source and drain of the single-electron element 2B is, for example, grounded.

[0043] 6, an amplifier circuit 2C is disposed between the single electron device 2A and the differential amplifier circuit 2E. Specifically, the other of the source and drain of an N-channel MOS transistor 2C1 of the amplifier circuit 2C is connected to one of the source and drain of a P-channel MOS transistor 2C2. The other of the source and drain of the P-channel MOS transistor 2C2 is connected to a predetermined potential V D is connected to. The amplifier circuit 2D is disposed between the single electron device 2B and the differential amplifier circuit 2E. Specifically, the other of the source and drain of the N-channel MOS transistor 2D1 of the amplifier circuit 2D is connected to one of the source and drain of the P-channel MOS transistor 2D2. The other of the source and drain of the P-channel MOS transistor 2D2 is connected to a predetermined potential V D is connected to.

[0044] One of the source and drain of the N-channel MOS transistor 2E3 is connected to the first output terminal Vout1 of the differential amplifier circuit 2E, one of the source and drain of the P-channel MOS transistor 2E5, the gate of the P-channel MOS transistor 2E5, and the gate of the P-channel MOS transistor 2E6. The other of the source and drain of the N-channel MOS transistor 2E3 is connected to one of the source and drain of the N-channel MOS transistor 2E7. The other of the source and drain of the N-channel MOS transistor 2E7 is grounded, for example.

[0045] One of the source and drain of the N-channel MOS transistor 2E4 is connected to the second output terminal Vout2 of the differential amplifier circuit 2E and one of the source and drain of the P-channel MOS transistor 2E6, and the other of the source and drain of the N-channel MOS transistor 2E4 is connected to one of the source and drain of the N-channel MOS transistor 2E7. The other of the source and drain of the P-channel MOS transistor 2E5 and the other of the source and drain of the P-channel MOS transistor 2E6 are connected to a predetermined potential V D is connected to. The first output terminal Vout1 and the second output terminal Vout2 of the differential amplifier circuit 2E are connected to the determination unit 2I.

[0046] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by the N-channel MOS transistor 2C1 and P-channel MOS transistor 2C2 of the amplifier circuit 2C and the differential amplifier circuit 2E (the potential at the first output terminal Vout1 of the differential amplifier circuit 2E) and the potential of the single electron element 2B amplified by the N-channel MOS transistor 2D1 and P-channel MOS transistor 2D2 of the amplifier circuit 2D and the differential amplifier circuit 2E (the potential at the second output terminal Vout2 of the differential amplifier circuit 2E). In detail, the differential amplifier circuit 2E, the N-channel MOS transistor 2C1 and the P-channel MOS transistor 2C2 of the amplifier circuit 2C, and the N-channel MOS transistor 2D1 and the P-channel MOS transistor 2D2 of the amplifier circuit 2D can make the potential difference between the first output terminal Vout1 and the second output terminal Vout2 of the differential amplifier circuit 2E larger than the potential difference between the original potential of the single electron element 2A and the potential of the single electron element 2B. Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the N-channel MOS transistor 2C1 and the P-channel MOS transistor 2C2 of the amplifier circuit 2C and the differential amplifier circuit 2E with the potential of the single electron element 2B amplified by the N-channel MOS transistor 2D1 and the P-channel MOS transistor 2D2 of the amplifier circuit 2D and the differential amplifier circuit 2E, thereby determining whether the single electron element 2A is amplified to be "0" or "1," which is easy to handle in a digital circuit at a subsequent stage.

[0047] In the example shown in FIG. 6, the judgment unit 2I reads the difference between the potential of the single-electron element 2A amplified by the N-channel MOS transistor 2C1 and P-channel MOS transistor 2C2 of the amplifier circuit 2C and the differential amplifier circuit 2E, and the potential of the single-electron element 2B amplified by the N-channel MOS transistor 2D1 and P-channel MOS transistor 2D2 of the amplifier circuit 2D and the differential amplifier circuit 2E, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single-electron elements 2A and 2B while miniaturizing the entire circuit.

[0048] In other words, in the second embodiment, a signal indicating the state of the quantum bit output from quantum circuit 1A (more specifically, in the case of a spin quantum bit, a signal indicating the spin state of the quantum bit of quantum circuit 1A measured by single-electron element 2A and output) is amplified by latch circuit 1C (more specifically, the N-channel MOS transistor 2C1 and P-channel MOS transistor 2C2 of amplifier circuit 2C and differential amplifier circuit 2E) and the amplified signal (more specifically, the potential of the first output terminal Vout1) is compared with a signal indicating the state of the quantum bit output from quantum circuit 1B (more specifically, in the case of a spin quantum bit, a signal indicating the spin state of the quantum bit of quantum circuit 1B measured by single-electron element 2B and output) and the amplified signal (more specifically, the N-channel MOS transistor 2D1 and P-channel MOS transistor 2D2 of amplifier circuit 2D and differential amplifier circuit 2E) and the amplified signal (more specifically, the potential of the second output terminal Vout2). This makes it possible to accurately determine the difference between the state of the (spin) quantum bit of quantum circuit 1A and the state of the (spin) quantum bit of quantum circuit 1B. In detail, the accuracy rate of reading the quantum bit state can be improved by inputting the input signal of quantum circuit 1B through, for example, an inverter together with the input signal of quantum circuit 1A so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 through decision unit 2I (i.e., by using an inverted version of the input signal of quantum circuit 1A as the input signal of quantum circuit 1B).

[0049] 7A and 7B are diagrams for explaining the first amplification by a P-channel MOS transistor and an N-channel MOS transistor such as the amplifier circuit 2C shown in FIG. 6. In detail, FIG. 7A shows the gate voltage V of the single-electron device (SET) in the saturation region under predetermined conditions. G The relationship between the amplified output terminal potential Vout [V] (vertical axis) and the gate voltage V of the single-electron device (SET) in the saturated region under different conditions from those in Figure 7(A). GThe relationship between the amplified output terminal potential Vout [V] (vertical axis) and the gate voltage V of the single-electron device (SET) in the linear region under certain conditions is shown in Figure 7(C). G The relationship between the amplified output terminal potential Vout [V] (vertical axis) and the gate voltage V of the single-electron device (SET) in the linear region under conditions different from those in Figure 7(C) is shown in Figure 7(D). G It shows the relationship between [V] (horizontal axis) and the amplified output terminal potential Vout [V] (vertical axis). In Figure 7, △Vout indicates the increase in potential Vout due to amplification. In Figure 5, one MOS transistor is connected to the single-electron element, but even if two MOS transistors are connected to the single-electron element in the same way, the first amplification operation is possible by controlling the operating regions of the two MOS transistors. Also, although only two MOS transistors are shown in this example, three or more MOS transistors may be connected.

[0050] 8A and 8B are diagrams showing the results of a simulation of differential amplification using the differential amplifier circuit 2E shown in Fig. 6. In detail, Fig. 8A shows the gate voltage V G 6 shows the relationship between the potential Vout [V] (horizontal axis) and the potential Vout [V] (vertical axis) of the first and second output terminals. Here, the potential Vout [V] collectively represents the potential of the first output terminal Vout1 and the potential of the second output terminal Vout2 in FIG. 6, and the gate voltage V G It can be seen that by changing [V], the difference between the potential of the first output terminal Vout1 and the potential of the second output terminal Vout2 becomes significant. Figure 8(B) shows the gate voltage V of the single electron devices 2A and 2B under conditions different from those in Figure 8(A). G The graph shows the relationship between [V] (horizontal axis) and the potential Vout [V] (vertical axis) of the first output terminal and the second output terminal. In the case of spin quantum dots, the gate voltage V G [V] shows a simulated situation in which the potential in the single-electron device shifts depending on the presence or absence of an electron in the quantum dot connected to the single-electron device, as shown in FIG.

[0051] [Third embodiment] A third embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will now be described. The quantum device 1 and quantum bit readout device 2 of the third embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the third embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0052] Fig. 9 is a diagram showing an example of a quantum bit readout device 2 etc. of the third embodiment. The latch circuit 1C and decision unit 1D of the quantum device 1 of the third embodiment can be expressed as the quantum bit readout device 2 shown in Fig. 9, for example. Fig. 9 shows a case where the quantum bit is a spin quantum bit. When the quantum bit is a charge quantum bit, the single-electron element is treated as a charge quantum bit as it is. In the example shown in FIG. 9, the quantum bit readout device 2 includes a single-electron element 2A, a single-electron element 2B, an SRAM (Static Random Access Memory) 2F, and a decision unit 2I. The SRAM 2F includes access transistors 2F1 and 2F2 and inverters 2F3 and 2F4. The inverters 2F3 and 2F4 are cross-coupled. The inverter 2F3 is configured with a P-channel MOS transistor and an N-channel MOS transistor. The inverter 2F4 is configured with a P-channel MOS transistor and an N-channel MOS transistor. Note that, although the number of transistors constituting the SRAM is assumed to be six in the following, an SRAM consisting of eight, nine, ten, or more transistors can also be used as a quantum bit readout device.

[0053] The single-electron element 2A measures the state of the spin qubit of the quantum circuit 1A. The gate of the single-electron element 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron element 2A is connected to the first output terminal Vout1 of the SRAM 2F. The other of the source and drain of the single-electron element 2A is, for example, grounded. The single-electron element 2B measures the state of the spin qubit of the quantum circuit 1B. The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to the second output terminal Vout2 of the SRAM 2F. The other of the source and drain of the single-electron element 2B is, for example, grounded.

[0054] The gate of the access transistor 2F1 is connected to the word line WL. One of the source and drain of the access transistor 2F1 is connected to the first output terminal Vout1 of the SRAM 2F. The other of the source and drain of the access transistor 2F1 is connected to one of the source and drain of the P-channel MOS transistor of the inverter 2F3, one of the source and drain of the N-channel MOS transistor of the inverter 2F3, the gate of the P-channel MOS transistor of the inverter 2F4, and the gate of the N-channel MOS transistor of the inverter 2F4. The other of the source and drain of the P-channel MOS transistor of the inverter 2F3 is connected to a predetermined potential V D The other of the source and drain of the N-channel MOS transistor of the inverter 2F3 is connected to, for example, ground.

[0055] The gate of the access transistor 2F2 is connected to the word line WL. One of the source and drain of the access transistor 2F2 is connected to the second output terminal Vout2 of the SRAM 2F. The other of the source and drain of the access transistor 2F2 is connected to one of the source and drain of the P-channel MOS transistor of the inverter 2F4, one of the source and drain of the N-channel MOS transistor of the inverter 2F4, the gate of the P-channel MOS transistor of the inverter 2F3, and the gate of the N-channel MOS transistor of the inverter 2F3. The other of the source and drain of the P-channel MOS transistor of the inverter 2F4 is connected to a predetermined potential V D The other of the source and drain of the N-channel MOS transistor of the inverter 2F4 is connected to, for example, ground. The first output terminal Vout1 and the second output terminal Vout2 of the SRAM 2F are connected to the determination unit 2I.

[0056] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by SRAM2F (i.e., output via SRAM2F) (the potential at the first output terminal Vout1 of SRAM2F) and the potential of the single electron element 2B amplified by SRAM2F (i.e., output via SRAM2F) (the potential at the second output terminal Vout2 of SRAM2F). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the SRAM2F output the potential of the single electron element 2A amplified by the SRAM2F and the potential of the single electron element 2B amplified by the SRAM2F as inverted results such as "0" and "1." Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the SRAM2F with the potential of the single electron element 2B amplified by the SRAM2F to determine whether the result is "0" or "1," which is easy to handle in a subsequent digital circuit.

[0057] In the example shown in FIG. 9, the determination unit 2I reads the difference between the potential of the single-electron element 2A amplified by the SRAM 2F and the potential of the single-electron element 2B amplified by the SRAM 2F, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single-electron elements 2A and 2B while miniaturizing the entire circuit.

[0058] In other words, in the third embodiment, a signal indicating the state of the (spin) quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, SRAM2F) and a signal (more specifically, the potential at the first output terminal Vout1 of SRAM2F) is compared with a signal indicating the state of the (spin) quantum bit output from quantum circuit 1B and amplified by latch circuit 1C (more specifically, SRAM2F) and a signal (more specifically, the potential at the second output terminal Vout2 of SRAM2F) is compared, thereby making it possible to accurately determine the difference between the state of the (spin) quantum bit of quantum circuit 1A and the state of the (spin) quantum bit of quantum circuit 1B. More specifically, by inputting the input signal of quantum circuit 1B through, for example, an inverter, together with the input signal of quantum circuit 1A so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 through decision unit 2I, the accuracy rate of reading out the state of the quantum bit can be improved.

[0059] 10A and 10B show the results of the circuit simulation (time change) shown in FIG. 9. In detail, FIG. 10A shows the time waveforms (not separated by time) of the potentials of the first output terminal Vout1 and the second output terminal Vout2 of SRAM2F under a predetermined condition with a gate length of 90 nm, and the time waveforms (separated by time) of the potentials of the first output terminal Vout1 and the second output terminal Vout2 of SRAM2F under a condition different from that condition. FIG. 10B shows the time waveforms (not separated by time) of the potentials of the first output terminal Vout1 and the second output terminal Vout2 of SRAM2F under a condition different from that condition with a gate length of 65 nm, and the time waveforms (separated by time) of the potentials of the first output terminal Vout1 and the second output terminal Vout2 of SRAM2F under a condition different from that condition.

[0060] [Fourth embodiment] A fourth embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will now be described. The quantum device 1 and quantum bit readout device 2 of the fourth embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the third embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the fourth embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the third embodiment described above, except for the points described below.

[0061] Fig. 11 is a diagram showing an example of a quantum bit readout device 2 according to the fourth embodiment. The latch circuit 1C and decision unit 1D of the quantum device 1 according to the fourth embodiment can be expressed as the quantum bit readout device 2 shown in Fig. 11, for example. Fig. 11 shows a case where the quantum bit is a spin quantum bit. When the quantum bit is a charge quantum bit, the single-electron element is treated as a charge quantum bit. In the example shown in FIG. 11, the quantum bit readout device 2 includes a single-electron element 2A, a single-electron element 2B, an amplifier circuit 2C, an amplifier circuit 2D, an SRAM 2F, and a determination unit 2I (see FIG. 9). The amplifier circuit 2C is configured with a P-channel MOS transistor. The amplifier circuit 2D is configured with a P-channel MOS transistor. The SRAM 2F includes access transistors 2F1 and 2F2 and inverters 2F3 and 2F4. The inverter 2F3 and the inverter 2F4 are cross-coupled. The inverter 2F3 is configured with a P-channel MOS transistor and an N-channel MOS transistor. The inverter 2F4 is configured with a P-channel MOS transistor and an N-channel MOS transistor.

[0062] The single-electron element 2A measures the state of the spin qubit of the quantum circuit 1A. The gate of the single-electron element 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron element 2A is connected to the first output terminal Vout1 of the SRAM 2F. The other of the source and drain of the single-electron element 2A is, for example, grounded. The single-electron element 2B measures the state of the spin qubit of the quantum circuit 1B. The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to the second output terminal Vout2 of the SRAM 2F. The other of the source and drain of the single-electron element 2B is, for example, grounded.

[0063] One of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2C is connected to the first output terminal Vout1 of the SRAM 2F. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2C is connected to a predetermined potential V D That is, the amplifier circuit 2C is disposed between the single electron device 2A and the SRAM 2F. One of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2D is connected to the second output terminal Vout2 of the SRAM 2F. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2D is connected to a predetermined potential V D That is, the amplifier circuit 2D is disposed between the single electron device 2B and the SRAM 2F. The access transistors 2F1 and 2F2 and the inverters 2F3 and 2F4 of the SRAM 2F are connected in the same manner as the access transistors 2F1 and 2F2 and the inverters 2F3 and 2F4 of the SRAM 2F shown in FIG. The first output terminal Vout1 and the second output terminal Vout2 of the SRAM 2F are connected to the determination unit 2I.

[0064] The judgment unit 2I reads the difference between the potential of the single electron element 2A (i.e., the potential at the first output terminal Vout1 of SRAM2F) amplified by the amplifier circuit 2C and SRAM2F (i.e., output via SRAM2F) and the potential of the single electron element 2B (i.e., the potential at the second output terminal Vout2 of SRAM2F) amplified by the amplifier circuit 2D and SRAM2F (i.e., output via SRAM2F). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the SRAM2F output the potential difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and SRAM2F and the potential of the single electron element 2B amplified by the amplifier circuit 2D and SRAM2F as a value larger than the potential difference between the original output terminal of the single electron element 2A and the output terminal of the single electron element 2B. Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the amplifier circuit 2C and SRAM2F with the potential of the single electron element 2B amplified by the amplifier circuit 2D and SRAM2F to determine whether it is "0" or "1."

[0065] In the example shown in FIG. 11, the determination unit 2I reads the difference between the potential of the single-electron element 2A amplified by the amplifier circuit 2C and SRAM 2F and the potential of the single-electron element 2B amplified by the amplifier circuit 2D and SRAM 2F, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single-electron elements 2A and 2B while miniaturizing the entire circuit.

[0066] In other words, in the fourth embodiment, a signal indicating the state of the (spin) quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, amplifier circuit 2C and SRAM2F) and the amplified signal (more specifically, the potential at the first output terminal Vout1 of SRAM2F) is compared with a signal indicating the state of the spin quantum bit output from quantum circuit 1B and the amplified signal (more specifically, the potential at the second output terminal Vout2 of SRAM2F) is compared. This makes it possible to accurately determine the difference between the state of the (spin) quantum bit of quantum circuit 1A and the state of the (spin) quantum bit of quantum circuit 1B. Specifically, the accuracy rate of reading out the state of the quantum bit can be improved by inputting the input signal of quantum circuit 1B through, for example, an inverter, so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 via decision unit 2I.

[0067] [Fifth embodiment] A fifth embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will be described below. The quantum device 1 and quantum bit readout device 2 of the fifth embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the fifth embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0068] 12 is a diagram showing an example of a quantum bit readout device 2 according to the fifth embodiment. The latch circuit 1C and the decision unit 1D of the quantum device 1 according to the fifth embodiment can be expressed as the quantum bit readout device 2 shown in FIG. 12, the quantum bit readout device 2 includes a sense amplifier 2G1, an equalizer 2G2, transistors 2G3 and 2G4, and a determination unit 2I (see FIG. 6). The sense amplifier 2G1 is composed of a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor, and a second N-channel MOS transistor that function as an amplifier circuit. The equalizer 2G2 is composed of a first N-channel MOS transistor and a second N-channel MOS transistor to whose gates a common equalization signal EQ is input.

[0069] The single-electron device 2A measures the state of a spin qubit in the quantum circuit 1A (not shown in FIG. 12). The single-electron device 2A is included in the quantum circuit 1A. One of the source and drain of the single-electron device 2A is connected to one of the source and drain of the transistor 2G3. The other of the source and drain of the single-electron device 2A is, for example, grounded. Single-electron device 2B measures the state of the spin qubit of quantum circuit 1B (not shown in FIG. 12). Single-electron device 2B is included in quantum circuit 1B. One of the source and drain of single-electron device 2B is connected to one of the source and drain of transistor 2G4. The other of the source and drain of single-electron device 2B is, for example, grounded.

[0070] The other of the source and drain of transistor 2G3 is connected to the first output terminal Vout1 of amplifier circuit 2G. A wiring connecting the other of the source and drain of transistor 2G3 to the first output terminal Vout1 of amplifier circuit 2G functions as a first bit line. A gate of transistor 2G3 is connected to word line WL1. The other of the source and drain of transistor 2G4 is connected to the second output terminal Vout2 of amplifier circuit 2G. A wiring connecting the other of the source and drain of transistor 2G4 to the second output terminal Vout2 of amplifier circuit 2G functions as a second bit line. A gate of transistor 2G4 is connected to word line WL2.

[0071] The first bit line connecting the other of the source and drain of transistor 2G3 to the first output terminal Vout1 of amplifier circuit 2G is connected to the gate of the first P-channel MOS transistor of sense amplifier 2G1 and the gate of the first N-channel MOS transistor of sense amplifier 2G1. A second bit line connecting the other of the source and drain of transistor 2G4 to the second output terminal Vout2 of the amplifier circuit 2G is connected to the gate of the second P-channel MOS transistor of sense amplifier 2G1 and the gate of the second N-channel MOS transistor of sense amplifier 2G1.

[0072] One of the source and drain of the first P-channel MOS transistor of the sense amplifier 2G1 is connected to the second bit line. One of the source and drain of the second P-channel MOS transistor of the sense amplifier 2G1 is connected to the first bit line. A common sense amplifier activation signal SAP is input to the other of the source and drain of the first P-channel MOS transistor of the sense amplifier 2G1 and the other of the source and drain of the second P-channel MOS transistor of the sense amplifier 2G1. One of the source and drain of the first N-channel MOS transistor of sense amplifier 2G1 is connected to the second bit line. One of the source and drain of the second N-channel MOS transistor of sense amplifier 2G1 is connected to the first bit line. A common sense amplifier activation signal SAN is input to the other of the source and drain of the first N-channel MOS transistor of sense amplifier 2G1 and the other of the source and drain of the second N-channel MOS transistor of sense amplifier 2G1.

[0073] One of the source and drain of the first N-channel MOS transistor of the equalizer 2G2 is connected to a first bit line. One of the source and drain of the second N-channel MOS transistor of the equalizer 2G2 is connected to a second bit line. The other of the source and drain of the first N-channel MOS transistor of the equalizer 2G2 is connected to the other of the source and drain of the second N-channel MOS transistor of the equalizer 2G2. The first output terminal Vout1 and the second output terminal Vout2 of the amplifier circuit 2G are connected to the determination unit 2I.

[0074] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2G (i.e., output via the amplifier circuit 2G) (the potential at the first output terminal Vout1 of the amplifier circuit 2G) and the potential of the single electron element 2B amplified by the amplifier circuit 2G (i.e., output via the amplifier circuit 2G) (the potential at the second output terminal Vout2 of the amplifier circuit 2G). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the amplifier circuit 2G output the potential difference between the potential of the single electron element 2A amplified by the amplifier circuit 2G and the potential of the single electron element 2B amplified by the amplifier circuit 2G as a value larger than the potential difference between the original output terminal of the single electron element 2A and the output terminal of the single electron element 2B. Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the amplifier circuit 2G with the potential of the single electron element 2B amplified by the amplifier circuit 2G to determine whether it is "0" or "1."

[0075] In the example shown in FIG. 12, the determination unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2G and the potential of the single electron element 2B amplified by the amplifier circuit 2G, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single electron elements 2A and 2B while miniaturizing the entire circuit.

[0076] In other words, in the fifth embodiment, the signal indicating the state of the (spin) quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, amplifier circuit 2G) and the signal indicating the state of the (spin) quantum bit is amplified by amplifier circuit 2G (more specifically, the potential at the first output terminal Vout1 of amplifier circuit 2G). This is compared with the signal indicating the state of the (spin) quantum bit output from quantum circuit 1B and amplified by latch circuit 1C (more specifically, amplifier circuit 2G) (more specifically, the potential at the second output terminal Vout2 of amplifier circuit 2G). This makes it possible to accurately determine the difference between the state of the (spin) quantum bit of quantum circuit 1A and the state of the (spin) quantum bit of quantum circuit 1B. In more detail, the accuracy rate of reading out the state of the quantum bit can be improved by inputting the input signal of quantum circuit 1B through, for example, an inverter, with the input signal of quantum circuit 1A so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 through judgment unit 2I.

[0077] [Sixth embodiment] A sixth embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will be described below. The quantum device 1 and quantum bit readout device 2 of the sixth embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the fifth embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the sixth embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0078] 13 is a diagram showing an example of a quantum bit readout device 2 according to the sixth embodiment. A latch circuit 1C of the quantum device 1 according to the sixth embodiment can be expressed as the quantum bit readout device 2 shown in FIG. 13, the quantum bit readout device 2 includes a single electron element 2A, a single electron element 2B, an amplifier circuit 2C, an amplifier circuit 2D, an amplifier circuit 2G, and a determination unit 2I (see FIG. 6). The amplifier circuit 2C is configured with a P-channel MOS transistor. The amplifier circuit 2D is configured with a P-channel MOS transistor. The amplifier circuits 2C and 2D may be configured with two or more MOS transistors as shown in FIG.

[0079] The single-electron element 2A measures the state of the spin qubit of the quantum circuit 1A (see FIG. 2). The gate of the single-electron element 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron element 2A is connected to one of the source and drain of a transistor 2G3 of the amplifier circuit 2G and one of the source and drain of a P-channel MOS transistor functioning as the amplifier circuit 2C. The other of the source and drain of the single-electron element 2A is, for example, grounded. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2C is connected to a predetermined potential V D That is, the amplifier circuit 2C is disposed between the single electron device 2A and the amplifier circuit 2G. The single-electron element 2B measures the state of the spin qubit of the quantum circuit 1B (see FIG. 2). The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to one of the source and drain of a transistor 2G4 of the amplifier circuit 2G and one of the source and drain of a P-channel MOS transistor functioning as the amplifier circuit 2D. The other of the source and drain of the single-electron element 2B is, for example, grounded. The other of the source and drain of the P-channel MOS transistor functioning as the amplifier circuit 2D is connected to a predetermined potential V D That is, the amplifier circuit 2D is disposed between the single electron device 2B and the amplifier circuit 2G. The amplifier circuit 2G is configured in the same manner as the amplifier circuit 2G shown in Fig. 12. That is, the first output terminal Vout1 and the second output terminal Vout2 of the SRAM 2F are connected to the determination unit 2I.

[0080] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and the amplifier circuit 2G (i.e., output via the amplifier circuit 2G) (the potential at the first output terminal Vout1 of the amplifier circuit 2G) and the potential of the single electron element 2B amplified by the amplifier circuit 2D and the amplifier circuit 2G (i.e., output via the amplifier circuit 2G) (the potential at the second output terminal Vout2 of the amplifier circuit 2G). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the amplifier circuit 2G output the potential difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and the amplifier circuit 2G and the potential of the single electron element 2B amplified by the amplifier circuit 2D and the amplifier circuit 2G as a value larger than the potential difference between the original output terminal of the single electron element 2A and the output terminal of the single electron element 2B. Furthermore, the determination unit 2I determines whether the potential is "0" or "1" by comparing the potential of the single electron element 2A amplified by the amplifier circuit 2C and the amplifier circuit 2G with the potential of the single electron element 2B amplified by the amplifier circuit 2D and the amplifier circuit 2G.

[0081] In the example shown in FIG. 13, the determination unit 2I reads the difference between the potential of the single electron element 2A amplified by the amplifier circuit 2C and the amplifier circuit 2G and the potential of the single electron element 2B amplified by the amplifier circuit 2D and the amplifier circuit 2G, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single electron elements 2A and 2B while miniaturizing the entire circuit.

[0082] In other words, in the sixth embodiment, a signal indicating the state of the (spin) quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, amplifier circuit 2C and amplifier circuit 2G) (more specifically, the potential at the first output terminal Vout1 of amplifier circuit 2G) and a signal indicating the state of the (spin) quantum bit output from quantum circuit 1B is amplified by latch circuit 1C (more specifically, amplifier circuit 2D and amplifier circuit 2G) (more specifically, the potential at the second output terminal Vout2 of amplifier circuit 2G), and this signal is compared to the signal indicating the state of the (spin) quantum bit. The accuracy rate of reading out the state of the quantum bit can be improved by inputting the input signal of quantum circuit 1B through, for example, an inverter, so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 through determination unit 2I.

[0083] FIG. 18 is a diagram showing the change over time of the voltage in the quantum bit readout device 2 of the sixth embodiment shown in FIG. As shown in FIG. 18, by adjusting the input signals of the equalizer 2G2 and the sense amplifier 2G1 in time, the potential V out1 and the potential V of the second output terminal Vout2 of the amplifier circuit 2G. out2 can be clearly distinguished.

[0084] [Seventh embodiment] A seventh embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will be described below. The quantum device 1 and quantum bit readout device 2 of the seventh embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the seventh embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0085] 14 is a diagram showing an example of the quantum bit readout device 2 etc. of the seventh embodiment. The latch circuit 1C and the decision unit 1D of the quantum device 1 of the seventh embodiment can be expressed as the quantum bit readout device 2 shown in FIG. 14, for example. Figure 14 shows the case where the quantum bit is a spin quantum bit. When the quantum bit is a charge quantum bit, the single-electron element is treated as a charge quantum bit. 14, the quantum bit readout device 2 includes a single-electron element 2A, a single-electron element 2B, a cross-coupled MOS transistor circuit 2H, and a determination unit 21. The cross-coupled MOS transistor circuit 2H includes a pair of cross-coupled P-channel MOS transistors 2H1 and 2H2 and a pair of transistors 2H3 and 2H4.

[0086] The single-electron element 2A measures the state of a quantum bit in the quantum circuit 1A. The gate of the single-electron element 2A is connected to the quantum circuit 1A. One of the source and drain of the single-electron element 2A is connected to one of the source and drain of a transistor 2H3 in the cross-coupled MOS transistor circuit 2H. The other of the source and drain of the single-electron element 2A is, for example, grounded. The single-electron element 2B measures the state of a quantum bit in the quantum circuit 1B. The gate of the single-electron element 2B is connected to the quantum circuit 1B. One of the source and drain of the single-electron element 2B is connected to one of the source and drain of a transistor 2H4 in the cross-coupled MOS transistor circuit 2H. The other of the source and drain of the single-electron element 2B is, for example, grounded.

[0087] The other of the source and drain of the transistor 2H3 is connected to the first output terminal Vout1 of the cross-coupled MOS transistor circuit 2 H. The gate of the transistor 2H3 is connected to the word line WL. The other of the source and drain of the transistor 2H4 is connected to the second output terminal Vout2 of the cross-coupled MOS transistor circuit 2 H. The gate of the transistor 2H4 is connected to the word line WL.

[0088] One of the source and drain of the P-channel MOS transistor 2H1 and the gate of the P-channel MOS transistor 2H2 are connected to the first output terminal Vout1 of the cross-coupled MOS transistor circuit 2H. The other of the source and drain of the P-channel MOS transistor 2H1 is connected to a predetermined potential V D is connected to. One of the source and drain of the P-channel MOS transistor 2H2 and the gate of the P-channel MOS transistor 2H1 are connected to the second output terminal Vout2 of the cross-coupled MOS transistor circuit 2H. The other of the source and drain of the P-channel MOS transistor 2H2 is connected to a predetermined potential V D is connected to. The first output terminal Vout1 and the second output terminal Vout2 of the cross-coupled MOS transistor circuit 2H are connected to the determination unit 2I.

[0089] The determination unit 2I reads the difference between the potential of the single electron element 2A amplified by the cross-coupled MOS transistor circuit 2H (i.e., output via the cross-coupled MOS transistor circuit 2H) (the potential at the first output terminal Vout1 of the cross-coupled MOS transistor circuit 2H) and the potential of the single electron element 2B amplified by the cross-coupled MOS transistor circuit 2H (i.e., output via the cross-coupled MOS transistor circuit 2H) (the potential at the second output terminal Vout2 of the cross-coupled MOS transistor circuit 2H). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the cross-coupled MOS transistor circuit 2H output the potential difference between the potential of the single electron element 2A amplified by the cross-coupled MOS transistor circuit 2H and the potential of the single electron element 2B amplified by the cross-coupled MOS transistor circuit 2H as a value larger than the potential difference between the original output terminal of the single electron element 2A and the output terminal of the single electron element 2B. Furthermore, the determination unit 2I compares the potential of the single electron element 2A amplified by the cross-coupled MOS transistor circuit 2H with the potential of the single electron element 2B amplified by the cross-coupled MOS transistor circuit 2H to determine whether it is "0" or "1."

[0090] In the example shown in FIG. 14, the determination unit 2I reads the difference between the potential of the single-electron element 2A amplified by the cross-coupled MOS transistor circuit 2H and the potential of the single-electron element 2B amplified by the cross-coupled MOS transistor circuit 2H, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single-electron elements 2A and 2B while miniaturizing the entire circuit.

[0091] In other words, in the seventh embodiment, the signal indicating the state of the (spin) quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, the cross-coupled MOS transistor circuit 2H) and amplified (more specifically, the potential at the first output terminal Vout1 of cross-coupled MOS transistor circuit 2H) by comparison with the signal indicating the state of the (spin) quantum bit output from quantum circuit 1B and amplified (more specifically, the potential at the second output terminal Vout2 of cross-coupled MOS transistor circuit 2H) by latch circuit 1C (more specifically, the cross-coupled MOS transistor circuit 2H). This makes it possible to accurately determine the difference between the state of the (spin) quantum bit of quantum circuit 1A and the state of the (spin) quantum bit of quantum circuit 1B. In particular, by inputting the input signal of quantum circuit 1B together with the input signal of quantum circuit 1A via, for example, an inverter, the accuracy rate of reading out the state of the quantum bit can be improved. 14 uses a pair of P-channel MOS transistors, an N-channel MOS transistor may be used, or one end of the single-electron element may not be grounded and another single-electron element or one or more N-channel MOS transistors may be added. In general, one or more P-channel MOS transistors and one or more N-channel MOS transistors may be connected in series or in parallel with the single-electron element.

[0092] [Eighth embodiment] An eighth embodiment of the quantum device, quantum bit readout device, and electronic circuit of the present invention will now be described. The quantum device 1 and quantum bit readout device 2 of the eighth embodiment are configured similarly to the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below. Therefore, the quantum device 1 and quantum bit readout device 2 of the eighth embodiment can achieve the same effects as the quantum device 1 and quantum bit readout device 2 of the first embodiment described above, except for the points described below.

[0093] Fig. 15 is a diagram showing an example of a quantum bit readout device 2 etc. of the eighth embodiment. The latch circuit 1C and decision unit 1D of the quantum device 1 of the eighth embodiment can be expressed as the quantum bit readout device 2 shown in Fig. 15, for example. Fig. 15 shows a case where the quantum bit is a spin quantum bit. When the quantum bit is a charge quantum bit, the single-electron element is treated as a charge quantum bit as it is. 15, the quantum bit readout device 2 includes a differential amplifier circuit 2E and a determination unit 21 (see FIG. 2). The differential amplifier circuit 2E includes bipolar transistors 2E11 and 2E12, resistors 2E13, 2E14, 2E15, and 2E16, and a constant current source 2E17.

[0094] The single-electron device 2A measures the state of a quantum bit in the quantum circuit 1A. The single-electron device 2A is included in the quantum circuit 1A. One of the source and drain of the single-electron device 2A is connected to the base of the bipolar transistor 2E11 and is also connected to a predetermined potential V DThe other of the source and drain of the single-electron element 2A is connected to, for example, ground. The single-electron device 2B measures the state of the quantum bit of the quantum circuit 1B. The single-electron device 2B is included in the quantum circuit 1B. One of the source and drain of the single-electron device 2B is connected to the base of the bipolar transistor 2E12 and is connected to a predetermined potential V D The other of the source and drain of the single-electron element 2B is connected to, for example, ground.

[0095] The emitter of the bipolar transistor 2E11 is connected to a constant current source 2E17. The collector of the bipolar transistor 2E11 is connected to a first output terminal Vout1 of the differential amplifier circuit 2E. The first output terminal Vout1 of the differential amplifier circuit 2E is connected to a predetermined potential V D is connected to. The emitter of the bipolar transistor 2E12 is connected to a constant current source 2E17. The collector of the bipolar transistor 2E12 is connected to a second output terminal Vout2 of the differential amplifier circuit 2E. The second output terminal Vout2 of the differential amplifier circuit 2E is connected to a predetermined potential V D is connected to. The first output terminal Vout1 and the second output terminal Vout2 of the differential amplifier circuit 2E are connected to the determination unit 2I.

[0096] The judgment unit 2I reads the difference between the potential of the single electron element 2A amplified by the differential amplifier circuit 2E (the potential at the first output terminal of the differential amplifier circuit 2E) and the potential of the single electron element 2B amplified by the differential amplifier circuit 2E (the potential at the second output terminal of the differential amplifier circuit 2E). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the differential amplifier circuit 2E amplify the potential difference between the potential of the single electron element 2A amplified by the differential amplifier circuit 2E and the potential of the single electron element 2B amplified by the differential amplifier circuit 2E. Furthermore, the determination unit 2I determines whether the potential is "0" or "1" by comparing the potential of the single electron element 2A amplified by the differential amplifier circuit 2E with the potential of the single electron element 2B amplified by the differential amplifier circuit 2E.

[0097] In the example shown in FIG. 15, the determination unit 2I reads the difference between the potential of the single electron element 2A amplified by the differential amplifier circuit 2E and the potential of the single electron element 2B amplified by the differential amplifier circuit 2E, thereby making it possible to read out the states of the quantum bits of the quantum circuits 1A and 1B connected to the single electron elements 2A and 2B while miniaturizing the entire circuit.

[0098] In other words, in the eighth embodiment, a signal indicating the state of the quantum bit output from quantum circuit 1A is amplified by latch circuit 1C (more specifically, differential amplifier circuit 2E) (more specifically, the potential at the first output terminal Vout1 of differential amplifier circuit 2E), and a signal indicating the state of the quantum bit output from quantum circuit 1B is amplified by latch circuit 1C (more specifically, differential amplifier circuit 2E) (more specifically, the potential at the second output terminal Vout2 of differential amplifier circuit 2E) are compared, thereby making it possible to accurately determine the difference between the state of the quantum bit of quantum circuit 1A and the state of the quantum bit of quantum circuit 1B. In more detail, the input signal of quantum circuit 1B is input through, for example, an inverter together with the input signal of quantum circuit 1A so that the output of quantum circuit 1A and the output of quantum circuit 1B are inverted between 0 and 1 through determination unit 2I, thereby improving the accuracy rate of reading out the state of the quantum bit.

[0099] [Ninth embodiment] A quantum device, a quantum bit readout device, and an electronic circuit according to a ninth embodiment of the present invention will now be described. The electronic circuit 3 of the ninth embodiment is configured similarly to the quantum bit readout device 2 of the seventh embodiment, except for the points that will be described later. Therefore, the electronic circuit 3 of the ninth embodiment can achieve the same effects as the quantum bit readout device 2 of the seventh embodiment, except for the points that will be described later.

[0100] FIG. 16 is a diagram showing an example of the electronic circuit 3 according to the ninth embodiment. In the example shown in FIG. 16, the electronic circuit 3 includes a first single electron element array 3A (see FIG. 17), a first selector 3B (see FIG. 17), a second single electron element array 3C (see FIG. 17), a second selector 3D (see FIG. 17), an amplifier circuit 3E, and a judgment unit 3F. The first single electron element array 3A includes a plurality of single electron elements. The first selector 3B selects one single electron element, the first single electron element 3A1, from the plurality of single electron elements included in the first single electron element array 3A. The second single electron element array 3C includes a plurality of single electron elements. The second selector 3D selects one single electron element, the second single electron element 3C1, from the plurality of single electron elements included in the second single electron element array 3C. The amplifier circuit 3E has a configuration similar to that of the cross-coupled MOS transistor circuit 2H shown in Fig. 14. The amplifier circuit 3E amplifies the potential of the first single electron element 3A1 selected by the first selector 3B and the potential of the second single electron element 3C1 selected by the second selector 3D. The determination unit 3F functions in the same manner as the determination unit 2I shown in Fig. 14. The determination unit 3F determines whether the potential is 0 or 1 by comparing the potential of the first single electron element 3A1 amplified by the amplifier circuit 3E (the potential of the first output terminal Vout1 of the amplifier circuit 3E) with the potential of the second single electron element 3C1 amplified by the amplifier circuit 3E (the potential of the second output terminal Vout2 of the amplifier circuit 3E). That is, in the example shown in FIG. 16, the electronic circuit 3 reads the difference between the potential of the first single electron element 3A1 and the potential of the second single electron element 3C1.

[0101] 17 is a diagram illustrating an example in which one single electron element (first single electron element 3A1) of the plurality of single electron elements included in the first single electron element array 3A is used as the single electron element 2A in the first to ninth embodiments described above, and one single electron element (second single electron element 3C1) of the plurality of single electron elements included in the second single electron element array 3C is used as the single electron element 2B in the first to ninth embodiments. While only single electron elements are depicted in Fig. 17, this is the case in which the single electron elements are charge quantum bits; when applied to spin quantum bits, each single electron element functions as a reader for the spin quantum bit.

[0102] The array structure of Fig. 17 can be applied to the first to ninth embodiments, but particularly when the embodiment of Fig. 16 is applied to the array structure shown in Fig. 17, the first selector 3B selects from the first single electron element array 3A a first single electron element 3A1 (see Fig. 16) that functions in the same way as the single electron element 2A shown in Fig. 9. The first single electron element 3A1 selected by the first selector 3B is connected to the amplifier circuit 3E. The second single electron element array 3C is configured similarly to the first single electron element array 3A. The second selector 3D is configured similarly to the first selector 3B. The second selector 3D selects a second single electron element 3C1 (see FIG. 16) from the second single electron element array 3C, which functions similarly to the single electron element 2B shown in FIG. 9. The second single electron element 3C1 selected by the second selector 3D is connected to the amplifier circuit 3E.

[0103] The amplifier circuit 3E shown in Fig. 17 functions in the same manner as the SRAM 2F shown in Fig. 9. The judgment unit 3F shown in Fig. 17 functions in the same manner as the judgment unit 2I shown in Fig. 9. That is, the judgment unit 3F reads the difference between the potential of the first single electron element 3A1 (the potential at the first output terminal Vout1 of the amplifier circuit 3E) selected by the first selector 3B and amplified by the amplifier circuit 3E (that is, output via the amplifier circuit 3E), and the potential of the second single electron element 3C1 (the potential at the second output terminal Vout2 of the amplifier circuit 3E) selected by the second selector 3D and amplified by the amplifier circuit 3E (that is, output via the amplifier circuit 3E). In detail, the first output terminal Vout1 and the second output terminal Vout2 of the amplifier circuit 3E output the potential of the first single electron element 3A1 amplified by the amplifier circuit 3E and the potential of the second single electron element 3C1 amplified by the amplifier circuit 3E as inverted results such as "0" and "1." Furthermore, the determination unit 3F compares the potential of the first single electron element 3A1 amplified by the amplifier circuit 3E with the potential of the second single electron element 3C1 amplified by the amplifier circuit 3E to determine whether it is "0" or "1."

[0104] 19 is a diagram for explaining an example in which a NAND flash memory is used as the first single electron element array 3A and a NAND flash memory is used as the second single electron element array 3C in the electronic circuit 3 of the ninth embodiment. In detail, Fig. 19 shows the relationship between the control gate, floating gate, tunnel oxide film, source, drain, and electrons of the NAND flash memory functioning as the first single electron element array 3A.

[0105] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and appropriate modifications can be made without departing from the spirit of the present invention. The configurations described in the above-described embodiments and examples may be combined.

[0106] Although the present invention has been described primarily in terms of spin qubits, the present invention is also valid even if all single-electron devices are replaced with charge qubit devices. For example, in the example shown in FIG. 16, the single-electron devices 3A1 and 3C1 themselves can be operated as charge qubits. FIG. 16 particularly shows a state in which the charge qubit (3A1) and the charge qubit (3C1) are coupled through capacitance. The capacitance coupling between the charge qubit (3A1) and the charge qubit (3C1) acts as, for example, an Ising interaction, as shown in Non-Patent Document 8. This interaction does not work when the charge qubits are far apart. In this way, it is also possible for the paired single electrons to be close to each other and interact directly through capacitance. Although a PMOS transistor is described as the first MOS transistor, an NMOS transistor can also be used. In the case of an NMOS transistor, a MOS transistor can also be inserted between the single-electron device and ground. In Figures 17 and 19, adjacent charge qubits can interact with each other.

[0107] In addition, all or part of the functions of each unit of the quantum device 1, quantum bit readout device 2, or electronic circuit 3 in the above-mentioned embodiments may be realized by recording a program for realizing these functions on a computer-readable recording medium, and reading and executing the program recorded on this recording medium into a computer system. Note that the term "computer system" here includes hardware such as an OS and peripheral devices. Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage units such as hard disks built into computer systems. Furthermore, "computer-readable recording media" may also include devices that dynamically store programs for a short period of time, such as communication lines when transmitting programs over networks like the Internet or communication lines like telephone lines, or devices that store programs for a fixed period of time, such as volatile memory within computer systems that serve as servers or clients in such cases. Furthermore, the above-mentioned programs may be programs that realize some of the aforementioned functions, or may be programs that can realize the aforementioned functions in combination with programs already stored in the computer system.

[0108] In the above embodiment, we have described how the state of the spin quantum bit output from quantum circuit 1A and the input signal of quantum circuit 1B are input to quantum circuit 1A via, for example, an inverter (i.e., by using an inverted version of the input signal of quantum circuit 1A as the input signal of quantum circuit 1B), but this often means that the spin direction of one spin quantum dot and the spin direction of the other spin quantum dot are opposite. Furthermore, in the spin qubit examples shown so far, we have considered the input section as a state in which down spin can enter when the spin state in one of the two quantum dots is up. This takes advantage of the fact that the presence of an electron in a quantum dot adjacent to a single-electron device makes it difficult for current to flow through the single-electron device. In other words, this is equivalent to the gate voltage of the single-electron device shifting depending on whether or not there is an electron next to the single-electron device. Figure 20 shows a schematic diagram of this situation, showing that the peak position of the Coulomb oscillation shifts depending on whether or not there is a charge. In the above embodiment, this shift is described as a difference in the gate voltage of the single-electron device. Note that two or more electrodes may be used to control the single-electron device. Furthermore, this is just one example, and it is also possible to have one spin quantum dot in contact with a single-electron device, as in Non-Patent Document 7.

[0109] In the above explanation, the number of qubits in quantum circuit 1B does not necessarily have to be equal to the number of qubits in quantum circuit 1A. In this case, the quantum states of the qubits in quantum circuit 1B can be fixed to 0 or 1, and the quantum states of the qubits in quantum circuit 1A can be determined as a collection of reference qubits. [Explanation of symbols]

[0110] 1...quantum device, 1A...quantum circuit, 1B...quantum circuit, 1C...latch circuit, 1D...decision unit, 2...qubit readout device, 2A...single-electron element, 2B...single-electron element, 2C...amplifier circuit, 2C1...transistor, 2C2...transistor, 2D...amplifier circuit, 2D1...transistor, 2D2...transistor, 2E...differential amplifier circuit, 2E1, 2E2, 2E3, 2E4, 2E5, 2E6, 2E7...transistors, 2E11, 2E12...bipolar transistor, 2E13, 2E14, 2E15, 2E16...resistor, 2E17...constant current source, 2F...SRA M, 2F1, 2F2...access transistor, 2F3, 2F4...inverter, 2G...amplifier circuit, 2G1...sense amplifier, 2G2...equalizer, 2G3, 2G4...transistor, 2H...cross-coupled MOS transistor circuit, 2H1, 2H2...P-channel MOS transistor, 2H3, 2H4...transistor, 2I...determination unit, 3...electronic circuit, 3A...first single electron element array, 3A1...single electron element, 3B...first selector, 3C...second single electron element array, 3C2...single electron element, 3D...second selector, 3E...amplifier circuit, 3F...determination unit

Claims

1. a first quantum circuit; and a first single-electron device connected to a first quantum circuit; a second quantum circuit; and a second single-electron device connected to a second quantum circuit; a differential amplifier circuit connected to the first single electron device and the second single electron device, a difference between the potential of the first single electron device and the potential of the second single electron device amplified by the differential amplifier circuit is read; Quantum device.

2. a first amplifier circuit disposed between the first single electron device and the differential amplifier circuit; a second amplifier circuit disposed between the second single electron device and the differential amplifier circuit; The quantum device of claim 1 .

3. the first amplifier circuit includes a first conductivity type transistor and a second conductivity type transistor; the second amplifier circuit includes a first conductivity type transistor and a second conductivity type transistor; The quantum device of claim 2 .

4. The differential amplifier circuit a first bipolar transistor having a base connected to the first single-electron element; a second bipolar transistor having a base connected to the second single-electron element; The quantum device of claim 1 .

5. a potential of the first single electron element and a potential of the second single electron element are inverted and outputted; 5. A quantum device according to any one of claims 1 to 4.

6. a determination unit that determines whether the potential of the first single electron element is 0 or 1 by comparing the potential of the second single electron element with the potential of the first single electron element; 6. A quantum device according to any one of claims 1 to 5.

Images