Semiconductor Devices

Abstract

To suppress deterioration of transistors.SOLUTION: An embodiment of the invention includes a first period and a second period. In the first period, a first transistor and a second transistor are alternately and repeatedly turned on and off, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off and the third transistor and the fourth transistor are alternately and repeatedly turned on and off. Thus, since the period during which the transistors are turned on can be shortened, characteristics degradation of the transistors is suppressed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device, a display device, and a display device having a driver circuit formed on the same substrate as a pixel portion. The present invention relates to a liquid crystal display device or a driving method thereof, or the semiconductor device and the display device. or an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. Development is underway actively to contribute significantly to the

[0003] A transistor formed of a non-single-crystal semiconductor has an increased threshold voltage or a decreased mobility. As this transistor degradation progresses, the drive circuit becomes difficult to operate, Therefore, there is a problem that the image cannot be displayed. Patent Document 1 discloses a shift register that can suppress the deterioration of transistors. In these documents, in order to suppress the degradation of the transistor characteristics, These two transistors are connected to the output terminal of the flip-flop and VSS (hereinafter referred to as a negative power supply) is connected between one of the transistors and The other transistor is turned on alternately. Since the time required for the transistor to become in this state is shortened, deterioration of the transistor characteristics can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-24350 [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, p.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional technology, the time that the transistor is on is approximately half of one frame period. Alternatively, the transistors may be degraded so that the shift register continues to operate. The channel width of the transistor needs to be increased. This may make it easier for the gate of the transistor to short out with the source or drain. Alternatively, when the channel width of the transistor becomes larger, each of the transistors constituting the shift register The parasitic capacitance of the transistor increases. When the parasitic capacitance of the shift register increases, the circuit that supplies signals or voltages to the shift register Therefore, it is necessary to use a circuit with a large current capacity.

[0007] In view of the above problems, one embodiment of the present invention aims to shorten the on-time of a transistor. Another object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. Another object of one embodiment of the present invention is to reduce the channel width of a transistor. Another object of one embodiment of the present invention is to reduce the layout area. Another object of one embodiment of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to provide a display device with high resolution. Another object of one embodiment of the present invention is to reduce costs. Another object of one embodiment of the present invention is to reduce distortion or delay of a signal. Another object of one embodiment of the present invention is to reduce power consumption. An object of one aspect of the present invention is to reduce the current capacity of an external circuit. An embodiment is to reduce the size of the external circuit or the size of a display device having the external circuit. The objectives of the present invention are as follows. The description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not necessarily solve all of the above problems. [Means for solving the problem]

[0008] One aspect of the present invention is a first switch electrically connected between a first wiring and a second wiring. a second switch electrically connected between the first wiring and the second wiring; a third switch electrically connected between the first wiring and the second wiring; a fourth switch electrically connected between the first and second electrodes; and a pixel including a liquid crystal element. A method for driving a liquid crystal display device having a first switch and a second switch that are electrically non-conductive. a first period in which the third switch and the fourth switch are in a non-conducting state; and a driving method for a liquid crystal display device having the period of

[0009] In one embodiment of the present invention, the first period and the second period are repeated in sequence. It is also possible.

[0010] In one embodiment of the present invention, the first period and the second period may be of approximately equal length. good.

[0011] One aspect of the present invention is a first switch electrically connected between a first wiring and a second wiring. a second switch electrically connected between the first wiring and the second wiring; a third switch electrically connected between the first wiring and the second wiring; a fourth switch electrically connected between the first and second electrodes; and a pixel including a liquid crystal element. A method for driving a liquid crystal display device having a first switch, a second switch, a third switch, a first sub-period in which the first switch and the fourth switch are in a non-conductive state, and a second sub-period in which the first switch is in a conductive state; a second switch that is in a non-conducting state and a third switch that is in a non-conducting state; During this sub-period, the second switch is in a conducting state, and the first switch, the third switch, and a first period having a third sub-period in which the first switch is turned on and a fourth switch is turned off; a fourth switch that turns on the first switch, the second switch, the third switch, and the fourth switch; During the sub-period, the third switch is in a conducting state, and the first switch, the second switch, and In the fifth sub-period, the fourth switch is in a non-conducting state, the fourth switch is in a conducting state, and the first a sixth sub-period in which the first switch, the second switch, and the third switch are in a non-conductive state; and a second period having the first period.

[0012] In one embodiment of the present invention, the first period and the second period are repeated in sequence. It is also possible.

[0013] In one embodiment of the present invention, the first period and the second period are approximately equal in length. Good too.

[0014] In one embodiment of the present invention, the first sub-period and the second sub-period are repeated in sequence. The fourth sub-period and the fifth sub-period may be repeated in sequence.

[0015] In one embodiment of the present invention, a first sub-period, a second sub-period, a third sub-period, and a third sub-period are included. The fourth sub-period, the fifth sub-period, and the sixth sub-period are approximately equal in length. Good too.

[0016] The switch can be of various types. For example, an electrical switch There are various types of switches, such as switches and mechanical switches. In other words, anything that can control the flow of current is sufficient. For example, a transistor (e.g., a bipolar transistor) can be used as a switch. transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal diode, MIS (Metal Insulator Semiconductor) conductor diode, diode-connected transistor, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0017] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode Thus, the device operates by controlling conduction and non-conduction.

[0018] In addition, both N-channel and P-channel transistors are used to An S-type switch may be used as the switch.

[0019] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0020] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements that function as One or more diodes (e.g., diodes) may be connected between A and B. Alternatively, When A and B are functionally connected, a circuit (e.g. For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits , step-down circuits, level shifter circuits that change the potential level of signals, voltage sources, current sources , switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc.), operational amplifiers , differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits may be connected between A and B. For example, Even if there is another circuit between them, if the signal output from A is transmitted to B, then A and B are are considered to be functionally connected.

[0021] When it is explicitly stated that A and B are electrically connected, it means that A and B are electrically connected. When A and B are electrically connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no other connection between A and B) and B are functionally connected (i.e., there is no other connection between A and B). When A and B are connected functionally through a circuit) and when A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that it is

[0022] Note that a display element, a display device which is a device having a display element, a light-emitting element, a device having a light-emitting element The light emitting device can have various forms and various elements. For example, the display element, display device, light-emitting element or light-emitting device may be an EL (electroluminescent EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (responding to current transistors that emit light when exposed to light, electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, graphene Rating light bulb (GLV), plasma display (PDP), digital microphone Chromatic mirror device (DMD), piezoelectric ceramic display, carbon nanotube, Displays whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects, such as The display device using the EL element may be an EL display. As a display device using electron-emitting devices, a field emission display (FED) ) and SED flat panel displays (SED: Surface-conduction and display devices using liquid crystal elements, such as LCDs (Electron-emitter Displays). LCD displays (transmissive LCDs, semi-transmissive LCDs, reflective LCDs) LCDs, direct-view LCDs, projection LCDs), electronic inks, An example of a display device using an electrophoretic element is electronic paper.

[0023] The liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. It is an element that consists of a pair of electrodes and liquid crystal. The optical modulation action of the liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the horizontal electric field, vertical electric field, or diagonal electric field) The liquid crystal element is controlled by nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, Discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal , polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal Examples include side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALCs), and banana-shaped liquid crystals. The liquid crystal driving method is Twisted Nematic (TN). mode, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, MVA (Multi-domain Vertical Alignment gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr systal mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, guest host mode, Blue Phase mode However, the present invention is not limited to this, and the liquid crystal element and its driving method can be used. A variety of different types can be used.

[0024] Note that various types of transistors can be used. There is no limitation on the type of transistor used. For example, amorphous silicon, polycrystalline silicon, Microcrystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) silicon The use of thin film transistors (TFTs) with non-single crystal semiconductor films, such as can be done.

[0025] In addition, when producing polycrystalline silicon, by using a catalyst (such as nickel), It is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. When manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to This further improves the performance and makes it possible to manufacture transistors with good electrical characteristics. It is not possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel). It is possible.

[0026] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline can improve the overall panel performance. It is desirable to do this on the whole body, but it is not limited to this. The crystallinity of the silicon may be improved.

[0027] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like.

[0028] Or ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO , TiO, AlZnSnO (AZTO), or other compound semiconductors or oxide semiconductors Transistors and thin film transistors made by thinning these compound semiconductors or oxide semiconductors It is possible to use a compound semiconductor or an oxide semiconductor. It can be used not only for the channel part of a transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistor elements, pixel electrodes, transparent Furthermore, they can be formed as a film or as an electrode having a transistor. can be formed, thereby reducing costs.

[0029] Alternatively, a transistor formed by inkjet or printing can be used. come.

[0030] Alternatively, transistors having organic semiconductors or carbon nanotubes can be used. This allows transistors to be formed on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks.

[0031] Furthermore, transistors of various structures can be used. For example, MOS transistors The transistors used may be junction transistors, bipolar transistors, etc. This can be done.

[0032] In addition, MOS transistors, bipolar transistors, etc. can be mixed on one substrate. It may be formed.

[0033] In addition, various other transistors can be used.

[0034] Note that a transistor can be formed using various substrates. The substrate is not limited to a specific one. For example, the substrate may be a single crystal substrate (e.g., silicon substrate), SOI substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel Substrate with stainless steel foil, tungsten substrate, tungsten A substrate having a glass foil, a flexible substrate, etc. can be used. Examples include barium borosilicate glass and aluminoborosilicate glass. Examples of substrates include polyethylene terephthalate (PET) and polyethylene naphthalate. Plastics such as polyethersulfone (PEN) and polyethersulfone (PES) or acrylic Other examples include laminated films (polypropylene, etc.) polyethylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), including fibrous materials Paper, base film (polyester, polyamide, polyimide, inorganic vapor deposition film, paper Or, a transistor is formed on one substrate, and then transferred to another substrate. The transistors may be transposed and placed on a different substrate. The substrates that can be placed include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. Substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, fabric substrate (natural fiber (silk, cotton, linen) , synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, (including cupra, rayon, recycled polyester, etc.), leather substrate, rubber substrate, stainless steel A stainless steel substrate, a substrate with stainless steel foil, etc. can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a substrate may be used to form the transistors, and the substrate may be polished to make it thinner. The substrates that can be polished include single crystal substrates, SOI substrates, glass substrates, quartz substrates, and plastic substrates. The substrates used are stainless steel substrates, stainless steel foil substrates, etc. By using these substrates, it is possible to form transistors with good characteristics and to Formation of low-power transistors, manufacturing of durable devices, imparting heat resistance, weight reduction, This allows for a thinner design.

[0035] The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied.

[0036] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. In addition, by arranging gate electrodes above and below the channel, multiple transistors can be formed. The configuration is like that of transistors connected in parallel.

[0037] A structure in which a gate electrode is disposed above a channel region, and a structure in which a gate electrode is disposed below a channel region The structure in which the channel region is divided into multiple regions is also available. a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series Furthermore, the channel region (or a part thereof) can be provided with a source electrode or a drain electrode. A structure in which the two are overlapped can also be applied.

[0038] Note that various types of transistors can be used and can be formed using various substrates. Therefore, all the circuits required to realize a given function can be simultaneously For example, it is possible to form the circuit necessary to realize a predetermined function on a single substrate. All of the circuits are made on various substrates such as glass, plastic, single crystal, or SOI. Alternatively, it may be formed using a substrate that is necessary to realize a predetermined function. A part of the essential circuit is formed on a certain substrate, and a part of the circuit necessary to realize a predetermined function is formed on the substrate. It is also possible for a part of the semiconductor device to be formed on a separate substrate. All of the circuits required for the above may not be formed using the same substrate. Part of the circuitry required to realize this function is formed by transistors on a glass substrate. Another part of the circuitry required to realize a predetermined function is formed on the single crystal substrate, An IC chip consisting of transistors formed on a single crystal substrate is called COG (Chip On Glass). On Glass) and place the IC chip on the glass substrate. Alternatively, the IC chip can be inserted into a TAB (Tape Automate) It is also possible to connect it to the glass substrate using a printed circuit board or a bonding method.

[0039] A transistor is defined as a transistor having at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region. A current can flow through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is difficult to know which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the source or drain. The region that functions as a source or drain is sometimes not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Alternatively, they may be referred to as the first region and the second region. There is a match.

[0040] The transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector may be connected to the first terminal and the second terminal. It may be written as 2 terminals, etc.

[0041] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed on A in direct contact with it. This also includes cases where A and B are not in agreement, i.e., where another object is present between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0042] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When described, it means that layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be formed as follows: It may be a single layer or multiple layers.

[0043] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0044] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. .

[0045] The same applies to the case where B is below A, or B is below A.

[0046] In addition, it is preferable that anything explicitly stated as singular be in the singular. However, it is not limited to this, and plurals are also possible. It is preferable that the items described in the table be plural. However, this is not limited to this. It is also possible for the term to be singular.

[0047] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0048] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current.

[0049] Note that technical terms may be used to describe specific embodiments or examples. Many, but not limited to:

[0050] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0051] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc.

[0052] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial positioning terms such as "diagonally," "in the back," or "in front" may be used to indicate the position of an element or is sometimes used to simply illustrate the relationship of a feature to other elements or features. However, this is not limited to this, and the words and phrases that indicate these spatial arrangements are added to the direction drawn in the drawing. In addition, other orientations are possible. For example, if it is explicitly stated that B is above A, The device shown is not limited to B being above A. It can be flipped or rotated 180 degrees. Since it is possible for B to be under A, it is possible for B to be under A. The phrase "on" can include an orientation of "under" in addition to an orientation of "on." However, the device in the figure is not limited to this and can be rotated in various directions. The term "above" includes the directions "above" and "below," as well as "sideways," "to the right," and "to the left." It is possible to include other directions such as "towards," "diagonally," "behind," or "forward." .

[0053] In one embodiment of the present invention, a first terminal is connected to a first wiring, and a second terminal is connected to a second wiring. a first transistor having a gate connected to the third wiring; and a first terminal connected to the first wiring. a second terminal connected to the second wiring and a gate connected to the fourth wiring; a transistor having a first terminal connected to a first wiring and a second terminal connected to a second wiring; a third transistor having a gate connected to the fifth wiring; and a first terminal connected to the first wiring. a fourth transistor having a second terminal connected to the second wiring and a gate connected to the sixth wiring; and a transistor.

[0054] In one embodiment of the present invention, a first terminal is connected to a first wiring, and a second terminal is connected to a second wiring. a first transistor having a gate connected to the third wiring; and a first terminal connected to the first wiring. a second terminal connected to the second wiring and a gate connected to the fourth wiring; a transistor having a first terminal connected to a first wiring and a second terminal connected to a second wiring; a third transistor having a gate connected to the fifth wiring; and a first terminal connected to the first wiring. a fourth transistor having a second terminal connected to the second wiring and a gate connected to the sixth wiring; a first terminal of the transistor connected to the seventh wiring and a second terminal of the transistor connected to the second wiring; and a fifth transistor having a gate connected to the eighth wiring.

[0055] In one embodiment of the present invention, a first transistor and a second transistor are alternately turned on and off. a first period during which the third transistor and the fourth transistor are turned off; The first transistor and the second transistor are turned off, and the third transistor and the and a second period in which the first and second transistors are alternately turned on and off.

[0056] One aspect of the present invention is a first wiring in which a first wiring and a second wiring are electrically connected via a first path. a second period in which the first wiring and the second wiring are in a conductive state via a second path; a third period in which the first wiring and the second wiring are in a conductive state via a third path; and a fourth period during which the wiring and the second wiring are in a conductive state via a fourth path. [Effects of the Invention]

[0057] According to one embodiment of the present invention, the time during which a transistor is turned on can be shortened. According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. According to one embodiment of the present invention, the channel width of a transistor can be reduced. In addition, one embodiment of the present invention is a display device. Alternatively, one embodiment of the present invention is to provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. One aspect of the present invention is that it can reduce costs. Alternatively, one embodiment of the present invention can reduce power consumption. Alternatively, one embodiment of the present invention can reduce the current capability of an external circuit. Alternatively, one embodiment of the present invention is to provide a display device having a size of an external circuit or the external circuit. The size can be reduced. [Brief explanation of the drawings]

[0058] [Figure 1] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 2] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 3] 1A and 1B are a schematic diagram for explaining the operation of a semiconductor device and a circuit diagram of the semiconductor device; [Figure 4] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 9] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 10] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 11] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 12] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 13] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 14] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 15] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 16] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 17] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 19] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 20] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 21] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 22] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 23] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 24] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 25] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 26] FIG. 2 is a circuit diagram of a shift register. [Figure 27] 10 is a timing chart for explaining the operation of a shift register. [Figure 28] 10 is a timing chart for explaining the operation of a shift register. [Figure 29] FIG. 2 is a schematic diagram for explaining the operation of a shift register. [Figure 30] FIG. 1 is a block diagram of a display device. [Figure 31] FIG. 1 is a block diagram of a display device. [Figure 32] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 33] 1 is a circuit diagram of a pixel and a timing chart for explaining the operation thereof; [Figure 34] FIG. 2 is a circuit diagram of a pixel. [Figure 35] 1A and 1B are a top view and a cross-sectional view of a display device; [Figure 36] FIG. 1 is a cross-sectional view of a transistor. [Figure 37] FIG. 1 is a layout diagram of a shift register. [Figure 38] Layout diagram of a shift register [Figure 39] FIG. 1 is a diagram illustrating an electronic device. [Figure 40] FIG. 1 is a diagram illustrating an electronic device. [Figure 41] 1A and 1B are a circuit diagram of a semiconductor device and a schematic diagram for explaining the operation thereof; [Figure 42] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 43] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 44] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 45] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 46] 1A to 1C are cross-sectional views illustrating a manufacturing process of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0059] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention. It should not be construed as being limited to the description of the embodiment. In the drawings, the same reference numerals are used to indicate the same parts or the same components. A detailed description of the parts having various functions will be omitted.

[0060] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0061] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0062] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0063] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. For example, it is used in a shift register, a gate driver, a source driver, or a display device. Note that the semiconductor device of this embodiment mode can be referred to as a driver circuit. be.

[0064] First, a basic circuit that can be used in the semiconductor device of this embodiment mode is shown in FIG. The circuit in FIG. 41A is made up of a plurality of circuits, ie, a circuit 101 and a circuit 102. The circuit 101 includes a switch 11_1 and a switch 11_2. The circuit 102 includes a plurality of switches, namely, a switch 12_1 and a switch 12_2. It has a plurality of switches: switch 11_1, switch 11_2, switch 12_1, and The switch 12_2 is connected between the wiring 111 and the wiring 112. The circuit of the semiconductor device 100 can be referred to as a semiconductor device or a driver circuit.

[0065] The switch 11_1, the switch 11_2, the switch 12_1, and the switch 12_2 are It has a function of controlling the electrical connection between the line 111 and the wiring 112. As shown in the figure, there are paths 121_1, 121_2, and 121_3 between the wiring 111 and the wiring 112. There are multiple routes, such as route 122_1 and route 122_2. However, this is not limited to these. When N (a natural number) switches are connected between the wire 111 and the wire 112, There can be N paths between 1 and the wiring 112.

[0066] It should be noted that the path between the wiring A (for example, the wiring 111) and the wiring B (for example, the wiring 112) is described as In this case, the wire A can be connected to the wire B via a switch. In addition to the switch, various elements (e.g., transistors) can be connected between the wire A and the wire B. transistors, diodes, resistors, or capacitors, or various circuits (e.g., It is possible to connect various circuits such as a power supply circuit, an inverter circuit, or a shift register circuit. Therefore, for example, a resistor element or a transistor may be connected in series or in parallel with the switch 11_1. Elements such as transistors can be connected.

[0067] As an example, a signal OUT is output from the wiring 111. The signal OUT is H It is often a digital signal with a low level and a high level, and functions as an output signal. Therefore, the wiring 111 can function as a signal line. The wiring 111 can be arranged so as to extend to the pixel portion. Alternatively, the wiring 111 may be connected to a transistor included in the pixel. connected to the gate of a transistor (e.g., a selection transistor or a switching transistor) Therefore, the signal OUT can be used as a selection signal, a transfer signal, a start signal, a reset signal, etc. The wiring 11 can function as a gate signal, a gate signal, or a scanning signal. The wiring 112 can function as a gate line, a scanning line, or an output signal line. As an example, a voltage V1 is supplied to the input terminal 1. The voltage V1 is a signal at an L level. They are often roughly equal in value and are used as ground voltage, power supply voltage, earth, reference voltage, or negative Therefore, the wiring 112 can function as a power supply line. However, the present invention is not limited to this, and the wiring 112 may be a wiring that receives a signal. The wiring 112 can function as a signal line.

[0068] The term "generally" refers to errors due to noise, process variations, and the manufacturing process of the element. This includes various errors such as errors due to variations in process and / or measurement errors.

[0069] As an example, let us assume that the potential of the L level signal is V1 and the potential of the H level signal is V2. And V2>V1. Therefore, when describing voltage V2, voltage V2 is the signal The value is approximately equal to the H level of the The potential of the signal can be lower than V1 or higher than V1. Alternatively, the potential of the H-level signal can be lower than V2, or higher than V2. It is possible to do this.

[0070] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0071] Next, the operation of the circuit of FIG. 41(A) will be explained with reference to the timing chart of FIG. The timing chart of FIG. 42 has multiple periods, and each period has multiple sub-periods. For example, the timing chart of FIG. 42 has a plurality of periods, namely, period A and period B. (Hereinafter, the period is also referred to as a frame period.) The period A includes a period A0, a period A1, and a period A2. A plurality of sub-periods, namely, period A1, period B2, and period A3 (hereinafter, each sub-period is also referred to as one gate selection period). Period B has multiple sub-periods, Period B0, Period B1, and Period B2. do.

[0072] In the example of the timing chart in FIG. 42, the period A and the period B are arranged in that order. However, this is not limiting, and Period A and Period B can be arranged in various orders. Alternatively, the timing chart may have a period other than period A and period B. Alternatively, one of period A and period B can be omitted.

[0073] In the period A, the period A1 and the period A2 are repeatedly arranged, and then the period A0 is arranged. After that, the period A1 and the period A2 are arranged repeatedly again in the period A. However, the present invention is not limited to this, and the periods A0, A1, and A2 may be arranged in various orders. Alternatively, the period A may include a period B0, a period B1, a period B2, and / or , other periods can be arranged. Or, period A0, period A1, and period It is possible to omit either period A0 or A2. Alternatively, period A0 can be placed next to period A1. It can be placed next to period A2, or at the beginning of period A. It can be placed next to any other period.

[0074] In the period B, the period B1 and the period B2 are repeatedly arranged, followed by the period B0. After that, the period B1 and the period B2 are arranged repeatedly again in the period B. However, the present invention is not limited to this, and the periods B0, B1, and B2 may be arranged in various orders. Alternatively, the period B may include the period A0, the period A1, the period A2, and / or , other periods can be arranged. Or, period B0, period B1, and period It is possible to omit either period B0 or ​​period B2. Alternatively, period B0 can be placed next to period B1. It can be placed next to period B2, or at the beginning of period B. It can be placed next to any other period.

[0075] First, the operation during the period A will be described. During the period A, the switches 11_1 and 12_2 Switch 11_1 is turned on and off repeatedly for each sub-period, and switch 11_2 and switch 12_2 are turned on and off repeatedly for each sub-period. The on and off states of the switches 11_1 and 12_1 are inverted to each other. However, the present invention is not limited to this, and the switches 11_1 and 12_1 are It can be turned off or on. 2 and / or switch 12_2 can be turned on.

[0076] During the period A1 of the period A, the switch 11_1 is turned on as shown in FIG. 41(C). , the switches 11_2, 12_1, and 12_2 are turned off. As shown in FIG. 41(D), the path 121_1 is in a conductive state, and the paths 121_2 and 1 Then, the wiring 111 and the wiring 112 are in a non-conductive state. Since the switch 11_1 is turned on, the voltage (for example, For example, a voltage V1 or a signal is supplied to the wiring 111 via the switch 11_1. Then, the wiring 111 and the wiring 112 are brought into a conductive state via the path 121_1. A voltage (for example, voltage V1) or signal supplied to 112 is transmitted to wiring 1 via path 121_1. It is supplied to 11.

[0077] In the period A2 of the period A, the switch 12_1 is turned on, and the switch 11_1 and the switch Therefore, as shown in FIG. 41(E), The path 122_1 is in a conductive state, and the paths 121_1, 121_2, and 122_2 Then, the wiring 111 and the wiring 112 are disconnected via the switch 12_1. Since the wiring 112 is in a conductive state, the voltage (for example, voltage V1) or signal supplied to the wiring 112 is switched In other words, the signal is supplied to the wiring 111 via the switch 12_1. Since the path 122_1 is in a conductive state, the voltage (for example, For example, a voltage V1 or a signal is supplied to the wiring 111 via a path 122_1.

[0078] In the period A0 of the period A, the switches 11_1, 11_2, 12_1, 41(H), the path 121_ 1, the path 121_2, the path 122_1, and the path 122_2 are in a non-conductive state. , the wiring 111 and the wiring 112 are in a non-conductive state, and the voltage ( For example, no voltage (V1) or signal is supplied to the wiring 111.

[0079] Next, the operation of the period B will be described. In the period B, the switch 11_1 and the switch 12 Switch 11_1 is turned off, and switch 11_2 and switch 12_2 are turned on and off for each sub-period. However, this is not limited to this, and the switches 11_2 and 12_3 are often repeated. _2 can be turned off or on. Or, switch 11_1 and / or switch 12_1 can be turned on.

[0080] In the period B1 of the period B, the switch 11_2 is turned on, and the switch 11_1 and the switch Therefore, as shown in FIG. 41(F), The path 121_2 is in a conductive state, and the paths 121_1, 122_1, and 122_ Then, the wiring 111 and the wiring 112 are connected via the switch 11_2. Since the wiring 112 is in a conductive state, the voltage (for example, voltage V1) or signal supplied to the wiring 112 In other words, the signal is supplied to the wiring 111 via the switch 11_2. 2 is in a conductive state via the path 121_2, so that the voltage (e.g. For example, a voltage V1 or a signal is supplied to the wiring 111 via a path 121_2.

[0081] In period B2 of period B, the switch 12_2 is turned on, and the switches 11_1 and 12_2 are turned on. Therefore, as shown in FIG. 41(G), The path 122_2 is in a conductive state, and the paths 121_1, 121_2, and 122_ Then, the wiring 111 and the wiring 112 are connected via the switch 12_2. Since the wiring 112 is in a conductive state, the voltage (for example, voltage V1) or signal supplied to the wiring 112 In other words, the signal is supplied to the wiring 111 via the switch 12_2. 2 is in a conductive state via the path 122_2, so that the voltage (e.g. For example, a voltage V1 or a signal is supplied to the wiring 111 via a path 122_2.

[0082] In the period B0 of the period B, the switches 11_1, 11_2, 12_1, 41(H), the path 121_ 1, the path 121_2, the path 122_1, and the path 122_2 are in a non-conductive state. , the wiring 111 and the wiring 112 are in a non-conductive state, and the voltage ( For example, no voltage (V1) or signal is supplied to the wiring 111.

[0083] As described above, by changing the period during which each switch is on, Therefore, the time required for the element or circuit used as a switch to become It is possible to suppress deterioration such as the above.

[0084] Note that in the periods A0 and B0, the wiring 111 is supplied with the voltage V2 or an H-level signal. (For example, a high-level clock signal) is often input. However, this is not limited to this. In other words, the wiring 111 can be in a floating state without receiving a voltage or a signal. do.

[0085] The time when period A0 starts in period A (or the time from the start of period A to the end of period A0) The time until the start time is the time when period B0 starts in period B (or the start of period B). In most cases, this is roughly equal to the time from the start of period B0 to the start of period B1. Not limited.

[0086] It is possible to replace a period with a step or an operation. For example, the first period, the second period, the third period, the fourth period, the fifth period, the sixth ... When the term "period 2" is mentioned, it can be interchangeable with "first step" and "second step." be.

[0087] If it is possible to operate as shown in Fig. 41(B) to (H), the switch configuration can be 41(A) is not limited to this.

[0088] In addition, two or more of the switches 11_1 to 11_2 and the switches 12_1 to 12_2 (e.g., two, three, or four) switches can be on at the same time. For example, It is possible for the switch 11_1 and the switch 12_1 to be on at the same time.

[0089] It should be noted that the circuit 101 and / or the circuit 102 may have more than two switches. For example, as shown in FIG. 43(A), the circuit 101 includes switches 11_1 to 11_m. (m is a natural number), and the circuit 102 includes switches 12_1 to 12_ It is possible to have a plurality of switches 11_1 to 11_m. Each of the switches corresponds to the switch 11_1 or the switch 11_2 and has the same function. 2_1 to 12_m correspond to the switch 12_1 or the switch 12_2, respectively, and have the same functions. The switches 11_1 to 11_m and the switches 12_1 to 12_m are connected to the wiring 1. 43(B), the wiring 111 is connected between the wiring 111 and the wiring 112. Between the wiring 112 and the wiring 112, there are a plurality of paths 121_1 to 121_m, and a path 122 There are multiple paths, 1 to 121_m. However, this is not limited to this. , and / or the circuits 102 may each have one switch; or The number of switches included in the circuit 101 is different from the number of switches included in the circuit 102. It is possible to do this.

[0090] An example of a timing chart that can be used in the circuit of FIG. 43(A) is shown in FIG. The timing chart of 44 is an example in which m=3. It is possible to have a plurality of switches 11_1 to 11_3, and the circuit 10 2 can have multiple switches 12_1 to 12_3. The timing chart of FIG. 4 has a plurality of periods, namely, period A, period B, and period C. Period C, like Period A or Period B, is divided into multiple periods: Period C0, Period C1, and Period C2. In the example of the timing chart of FIG. 44, there are periods A, B, and However, the present invention is not limited to this, and the period A, the period B, and the period C may be arranged in this order. can be arranged in various orders. Alternatively, the timing chart can be It is possible to have various periods other than Period A, Period B, and Period C. It is possible to omit either period C1 or period C. After the period C2 is repeatedly arranged, the period C0 is arranged. In the period C1, the period C2 is alternately arranged. However, the present invention is not limited to this. C0, period C1, and period C2 can be arranged in various orders. Period C includes Period A0, Period A1, Period A2, Period B0, Period B1, Period B2, and / or Alternatively, other periods may be arranged. It is possible to omit either the period C0 or the period C2. Alternatively, the period C0 is arranged next to the period C1. It can be placed after period C2, or after other periods. It can be placed next to

[0091] In the periods A and B, the switches 11_3 and 12_3 are turned off. As a result, the path 121_3 and the path 122_3 are in a non-conductive state. The switch 11_3 and / or the switch 12_3 can be turned on. do.

[0092] In the period C, the switch 11_3 and the switch 12_3 are turned on and off for each sub-period. Repeat, switch 11_1, switch 11_2, switch 12_1, and switch 12 The on and off states of the switch 11_3 and the switch 12_3 are mutually However, it is not limited to this, and the switch 11_3 and the switch 12_3 can be on or off. switch 11_1, switch 11_2, switch 12_1, and / or switch 12_2 is able to be turned on.

[0093] During period C1 of period C, switch 11_3 is turned on, and switches 11_1 and 11_2 are turned on. 1_2, switch 12_1, switch 12_2, and switch 12_3 are turned off. As a result, the path 121_3 is in a conductive state, and the paths 121_1, 121_2, and 122 are in a conductive state. _1, the path 122_2, and the path 122_3 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 11_3, so the voltage supplied to the wiring 112 is The voltage (for example, voltage V1) or signal is supplied to the wiring 111 via the switch 11_3. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 121_3. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 121_3. The power is supplied to the wiring 111 via the power supply 111 .

[0094] During period C2 of period C, switch 12_3 is turned on, and switches 11_1 and 1 The switches 11_2, 11_3, 12_1, and 12_2 are turned off. As a result, the path 122_3 is in a conductive state, and the paths 121_1, 121_2, and 121_3 are in a conductive state. _3, the path 122_1, and the path 122_2 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 12_3, so the voltage supplied to the wiring 112 The voltage (for example, voltage V1) or signal is supplied to the wiring 111 via the switch 12_3. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 122_3. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 122_3. The power is supplied to the wiring 111 via the power supply 111 .

[0095] In the period C0 of the period C, the switches 11_1, 11_2, 11_3, and Therefore, the switch 12_1, the switch 12_2, and the switch 12_3 are turned off. 21_1, Route 121_2, Route 121_3, Route 122_1, Route 122_2, Route 1 22_3 is in a non-conductive state. Then, the wiring 111 and the wiring 112 are in a non-conductive state. Therefore, the voltage (for example, voltage V1) or signal supplied to the wiring 112 is equal to the voltage or signal supplied to the wiring 111. It will no longer be possible.

[0096] In FIG. 43(A), if m is large, the time when the switch is turned on can be shortened. Therefore, it is possible to suppress the deterioration of the elements or circuits used as switches. However, if m is too large, the circuit size becomes too large. Preferably, m≦6. More preferably, m≦4. Preferably, m=2 or m=3.

[0097] Note that the circuit in FIG. 41A includes a plurality of circuits corresponding to the circuit 101 or the circuit 102. In FIG. 43C, a circuit is shown, which includes a circuit 101, a circuit 102, and a circuit 103. The circuit 103 includes a switch 13_1 and a switch 13_2. The circuit 103 has a plurality of switches, namely, the circuit 101 and the circuit 102. 2, the switch 13_1 corresponds to the switch 11_1 or the switch 12_1, The switch 13_2 corresponds to the switch 11_2 or the switch 12_2. 1 and the switch 13_2 are connected between the wiring 111 and the wiring 112. 3(D), there are a path 121_1 and a path 121_2 between the wiring 111 and the wiring 112. 1_2, route 122_1, and route 122_2, as well as route 123_1 and route 123 However, the circuit is not limited to this, and the circuit may be a circuit 101 or One circuit corresponding to circuit 102, or four or more corresponding to circuit 101 or circuit 102 It is possible to have a circuit of

[0098] An example of a timing chart that can be used in the circuit of FIG. 43(C) is shown in FIG. In the timing chart of 45, period A has a plurality of sub-periods, periods A0 to A3. Period B has multiple sub-periods, periods B0 to B3. Period A has multiple sub-periods, periods A1 to A3. are repeatedly arranged, and then a period A0 is arranged. Then, again, in the period A, Similarly, in period B, periods B1 to B3 are arranged repeatedly. After that, period B0 is placed. Then, period B1 to B3 are placed again. However, the present invention is not limited to this, and in the period A, the periods A0 to A3 are arranged repeatedly. Alternatively, in period B, periods B0 to B3 can be arranged in various orders. Alternatively, in the period A, any of the periods B0 to B3 may be arranged in various orders. Alternatively, period B may be arranged so that period A0 is not included in period B. Any of the periods A to A3 or other periods can be placed in the period A. In this case, any of the periods A0 to A3 can be omitted. Therefore, it is possible to omit any of the periods B0 to B3. The period A0 can be placed after any of the periods A1 to A3, and can also be placed after any of the other periods. Alternatively, in period B, period B0 can be placed next to period B1 to It can be placed next to any of the B3 periods, and it can be placed next to any other period. It is possible.

[0099] In period A, the switch 11_1, the switch 12_1, and the switch 13_1 are turned on in order. The switches 11_2, 12_2, and 13_2 are turned off. However, the present invention is not limited to this, and the switches 11_1, 12_1, and 13_1 can be turned on in various orders. Switch 2_1 and switch 13_1 can be turned off or on. Alternatively, the switch 11_2, the switch 12_2, and / or the switch 13_ 2 can be turned on.

[0100] In the periods A0, A1, and A2 of the period A, the switches 13_1 and 13_2 are Therefore, the path 123_1 and the path 123_2 are in a non-conducting state. However, the present invention is not limited to this, and the switch 13_1 and / or the switch 13_2 may be turned on. It is possible to become.

[0101] During period A3 of period A, switch 13_1 is turned on, and switches 11_1 and 1 The switches 12_1, 12_2, and 13_2 are turned off. As a result, the path 123_1 is in a conductive state, and the paths 121_1, 121_2, and 122 _1, the path 122_2, and the path 123_2 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 13_1, so that the voltage supplied to the wiring 112 is The voltage (for example, voltage V1) or signal is supplied to the wiring 111 via the switch 13_1. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 123_1. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 123_1. The power is supplied to the wiring 111 via the power supply 111 .

[0102] In period B, the switch 11_2, the switch 12_2, and the switch 13_2 are turned on in order. The switches 11_1, 12_1, and 13_1 are turned off. However, the present invention is not limited to this, and the switches 11_2, 12_2, and 13_2 can be turned on in various orders. 2_2 and switch 13_2 can be turned off and on. Alternatively, the switch 11_1, the switch 12_1, and / or the switch 13_ 1 can be turned on.

[0103] In the periods B0, B1, and B2 of the period B, the switches 13_1 and 13_2 are Therefore, the path 123_1 and the path 123_2 are in a non-conducting state. However, the present invention is not limited to this, and the switch 13_1 and / or the switch 13_2 may be turned on. It is possible to become.

[0104] During period B3 of period B, switch 13_2 is turned on, and switches 11_1 and 11_2 are turned on. The switches 12_1, 12_2, and 13_1 are turned off. As a result, the path 123_2 is in a conductive state, and the paths 121_1, 121_2, and 122 _1, the path 122_2, and the path 123_1 are in a non-conductive state. The wiring 112 is in a conductive state via the switch 13_2, so that the voltage supplied to the wiring 112 is The voltage (for example, voltage V1) or signal is supplied to the wiring 111 via the switch 13_2. In other words, the wiring 111 and the wiring 112 are in a conductive state via the path 123_2. Therefore, a voltage (for example, voltage V1) or a signal supplied to the wiring 112 passes through the path 123_2. The power is supplied to the wiring 111 via the power supply 111 .

[0105] In FIG. 43C, the number of circuits corresponding to the circuit 101 or the circuit 102 is large. Therefore, the time that the switch is on can be shortened. However, the deterioration of the elements or circuits used can be suppressed. If the number of circuits corresponding to the circuit 102 is too large, the number of switches increases, and the circuit scale becomes large. Therefore, the number of circuits corresponding to the circuit 101 or the circuit 102 is It is preferably 6 or less, and more preferably 4 or less. Preferably, the number is three or two. However, the number is not limited to this. The number of circuits corresponding to O1 or circuit 102 can be one, or six or more. It is possible to be.

[0106] 43C, similarly to FIG. 43A, the circuit 101 or the circuit 102 Each of the plurality of circuits is composed of three or more switches connected between the wiring 111 and the wiring 112. It is possible to have

[0107] It is possible to divide the wiring into multiple wirings. It is possible to input the same signal or voltage, or to input different signals or voltages. Alternatively, the plurality of wirings may be connected to the same wiring or element. The plurality of wirings can be connected to separate wirings or elements. In one example of FIG. 43(E), the wiring 112 is divided into a plurality of wirings 112A to 112D. The wirings 112A to 112D are connected to the wiring 111, respectively. , switch 11_1, switch 11_2, switch 12_1, and switch 12_2 are connected. The wirings 112A to 112D correspond to the wiring 112. A voltage V1 can be supplied to the wirings 112A to 112D, and the wirings 112A to 112D are used as power supply lines. However, the present invention is not limited to this, and the wirings 112A to 112D can function as It is possible to input different voltages or different signals to the wirings 112A to 112D. Alternatively, any one of the wirings 112A to 112D can be shared. can each be shared with other wires.

[0108] As in FIG. 43(E), the wiring 112 in FIGS. 43(A) and 43(C) It is possible to divide the wiring 111 into a plurality of wirings. A switch can be connected between each of them.

[0109] Next, an example of using a transistor as a switch will be described with reference to FIG. 1(A). 1A shows the switches 11_1, 11_2, and 11_3 of FIG. The switch 12_1 and the switch 12_2 are respectively made up of a transistor 101_1, a transistor 102_2, and a transistor 103_3. The transistors 101_2, 102_1, and 102_2 are used. However, the present invention is not limited to this, and the contents described in Figures 41 to 45 or these In the combined configuration, a transistor can be used as the switch. For example, in Figures 43(A), 43(C), and 43(E), A transistor can be used.

[0110] The transistors 101_1, 101_2, 102_1, and The transistor 102_1 and the transistor 102_2 are N-channel transistors. A transistor is turned on when the voltage difference between the gate and source (Vgs) exceeds the threshold voltage (Vth). However, the present invention is not limited to this, and the transistor 101_1, the transistor The transistor 101_2, the transistor 102_1, and / or the transistor 102_2 are P A P-channel transistor can have a gate and a source. When the potential difference (Vgs) between them falls below the threshold voltage (Vth), the transistor turns on. As the switch, a CMOS switch can be used.

[0111] The connection relationship of the semiconductor device in FIG. 1A will be described. the first terminals of the transistor 101_2, the transistor 102_1, and the transistor 102_2; The transistor 101_1, the transistor 101_2, and the transistor 101_3 are connected to the wiring 112. The second terminals of the transistors 102_1 and 102_2 are connected to the wiring 111. Then, the transistor 101_1, the transistor 101_2, and the transistor 102 The gates of the transistors 102_1 and 102_2 are connected to the wirings 113_1 and 113_2, respectively. , the wiring 114_1, and the wiring 114_2. However, this is not limitative and various other A variety of connection configurations are possible.

[0112] For example, the wiring 113_1 and the wiring 113_2 are connected to the signal S1_1 and the signal S1_2, respectively. The signal S1_1 and the signal S1_2 are digital signals. In many cases, the wiring 114_1 and the wiring 114_2 can function as a clock signal. As an example, it is assumed that signals S2_1 and S2_2 are input to 114_2, respectively. The signal S2_1 is an inverted signal of the signal S1_1 or has a phase shift of 180° from the signal S1_1. It is often a shifted signal and can function as an inverted clock signal. The signal S2_2 is an inverted signal of the signal S1_2 or has a phase difference of 180° from the signal S1_2. It is often a shifted signal and can function as an inverted clock signal. However, the present invention is not limited to this, and includes wiring 111, wiring 112, wiring 113_1, wiring 113_2, wiring The wire 114_1 and the wiring 114_2 may also carry various other signals, currents, or voltages. It is possible to input pressure.

[0113] The signal S1_1 and the signal S1_2 are output every certain period (for example, every frame or every operation period). In many cases, the active state and the inactive state are alternated every time the signal S1 In the case of signals S1_1 and S1_2, the active and inactive states may be reversed. Similarly, the signals S2_1 and S2_2 are generated every certain period (for example, every frame, In many cases, the active state and the inactive state are repeated every one operation period. The active and inactive states of the signals S2_1 and S2_2 are reversed. For example, in the k-th frame (k is a natural number), the signals S1_1 and S2_2 are If the signals S1_1 and S2_2 are in the active state, the signals S1_2 and S2_2 are in the non-active state. After that, in the k+1th frame, the signal S1_1 and the signal S If signal S1_1 becomes inactive, signals S1_2 and S2_2 become active. However, the present invention is not limited to this, and both the signal S1_1 and the signal S1_2 may be in the same state. Similarly, the signal Both S2_1 and S2_2 are in the same state (active or inactive) Alternatively, the signals S1_1, S1_2, S2_1, and S3_2 may be The signal S2_2 is generated every several frames, every time the semiconductor device is powered on, or randomly. , it is possible for the active and inactive states to alternate.

[0114] When a signal is in an active state, it can be either H level or L level. On the other hand, when a signal is inactive, it means that the signal is at a constant value (e.g. For example, the signal goes to a high or low level. When describing a state where a signal is in an active state, it is assumed that the signal is at L level. For example, the signal is not guaranteed to be a constant value even when it goes active. is possible.

[0115] The wiring 113_1, the wiring 113_2, the wiring 114_1, and the wiring 114_2 are signal lines. It can function as a line, a clock signal line, etc. However, it is not limited to this. A voltage is supplied to the wiring 113_1, the wiring 113_2, the wiring 114_1, and the wiring 114_2. When the wiring is connected to the power supply, these wirings can function as power supply lines.

[0116] It is possible to input a multi-phase clock signal to the semiconductor device. For example, n (n is It is possible to input a clock signal with n phases (a natural number of phases) to a semiconductor device. A clock signal is a set of n clock signals that are out of phase with each other. For example, For example, there are n clock signals whose periods are shifted by 1 / n period. However, it is not limited to this.

[0117] Note that the signals S1_1, S2_1, S1_2, and S2_2 are in the active state. In this case, in order to simplify the circuit that generates the signal, the time when it becomes L level and the time when it becomes H level are However, it is not limited to this, and the time The time it remains at the H level can be longer than the time it remains at the L level. The time for which the signal is turned on can be shorter than the time for which the signal is turned on.

[0118] Balanced means that the duty ratio is approximately 50%, that is, the time between the H level and the L level. Non-equilibrium means that the time of the H level is roughly equal to that of the This means that the time between the low level and the low level is different.

[0119] Next, the operation of the semiconductor device in FIG. 1A will be described with reference to the timing chart in FIG. 1B. The timing chart in FIG. 1B corresponds to the timing chart in FIG. Note that the explanation of the operations common to those in Figure 41(A) will be omitted.

[0120] First, the operation in the period A will be described. In the period A, the signals S1_1 and S2_1 are The signal S1_2 and the signal S2_2 are in an active state. Therefore, the signal S1_1 and the signal S2_1 alternate between the H level and the L level for each sub-period. The signals S1_1 and S2_2 are at the L level. In the case of 1, the H level and the L level are often inverted. However, this is not limited to this. The signals S1_1 and S2_1 can be at the L level and at the H level. Alternatively, the signal S1_2 and / or the signal S2_2 may be at the H level. It is possible to become a Bell.

[0121] During a period A1 of the period A, the signal S1_1 becomes H level, and the signals S1_2 and S2_ 1 and signal S2_2 become L level. Therefore, as shown in FIG. 2(A), The transistor 101_1 is turned on, and the transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned on. The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 101_1, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 101_1.

[0122] During a period A2 of the period A, the signal S2_1 becomes H level, and the signals S1_1 and S1_ 2 and signal S2_2 become L level. Therefore, as shown in FIG. 2(B), The transistor 102_1 is turned on, and the transistors 101_1, 101_2, and The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through the line 102_1, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 102_1.

[0123] During a period A0 of the period A, the signals S1_1, S1_2, S2_1, and S2_2 are Therefore, as shown in FIG. 2C, the transistors 101_1 and 101_2 are turned to the L level. The transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned off. As a result, the wiring 111 and the wiring 112 are brought into a non-conductive state.

[0124] Next, the operation in the period B will be described. In the period B, the signals S1_2 and S2_2 are The signal S1_1 and the signal S2_1 are in an active state, and the signal S1_1 and the signal S2_1 are in an inactive state. Therefore, the signals S1_2 and S2_2 alternate between H level and L level every sub-period. The signals S1_1 and S2_1 are at the L level. In the case of 2, the H level and the L level are often inverted. However, this is not limited to this. The signals S1_2 and S2_2 can be at the L level and at the H level. Alternatively, the signal S1_1 and / or the signal S2_1 may be at the H level. It is possible to become a Bell.

[0125] In the period B1 of the period B, the signal S1_2 becomes H level, and the signals S1_1 and S2_ 1 and signal S2_2 become L level. Therefore, as shown in FIG. 3(A), The transistor 101_2 is turned on, and the transistor 101_1, the transistor 102_1, and the transistor 102_2 are turned on. The transistor 102_2 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through 101_2, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 101_2.

[0126] In the period B2 of the period B, the signal S2_2 becomes H level, and the signals S1_1 and S1_ 2 and the signal S2_1 become L level. Therefore, as shown in FIG. 3(B), the transistor The transistor 102_2 is turned on, and the transistors 101_1, 101_2, and The transistor 102_1 is turned off. Then, the wiring 111 and the wiring 112 are connected to the transistor Since the line 112 is turned on through 102_2, the voltage V1 is transferred from the line 112 to the line 111. It is supplied via register 102_2.

[0127] In the period B0 of the period B, the signals S1_1, S1_2, S2_1, and S2_2 are Therefore, as shown in FIG. 2C, the transistors 101_1 and 101_2 are turned to the L level. The transistor 101_2, the transistor 102_1, and the transistor 102_2 are turned off. As a result, the wiring 111 and the wiring 112 are brought into a non-conductive state.

[0128] As described above, the semiconductor device of this embodiment shortens the time during which the transistor is turned on. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment mode. By doing so, the life of these components can be extended.

[0129] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to N-channel or Therefore, compared to CMOS circuits, the number of processes is reduced. It is possible to reduce the number of defects, improve the yield, improve the reliability, or reduce the cost. If all transistors are N-channel, including the elemental part, the semiconductor layer of the transistor a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor However, transistors using these semiconductors tend to deteriorate However, the semiconductor device of this embodiment is designed to suppress the deterioration of the transistor. It is possible.

[0130] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0131] The L level of the signal S1_1, the signal S1_2, the signal S2_1, and / or the signal S2_2 It is possible to make the potential of the capacitor lower than V1. In this case, when the signal goes low, A reverse bias is applied to the transistor, which can reduce the degradation of the transistor. However, the present invention is not limited to this, and the signals S1_1, S1_2, S2_1, and / Or, the L level potential of the signal S2_2 can be higher than V1.

[0132] The H level of the signal S1_1, the signal S1_2, the signal S2_1, and / or the signal S2_2 It is possible to make the potential of the capacitor lower than V2. In this case, the signal becomes H level, When the transistor is turned on, the Vgs of the transistor is reduced. However, the present invention is not limited to this, and the signal S1_1, the signal The potential of the H level of the signal S1_2, the signal S2_1, and / or the signal S2_2 is higher than V2. It is possible to do this.

[0133] The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are Similarly, the channel width of the transistor 102_1 and It is preferable that the channel width of the transistor 102_1 is approximately equal to that of the transistor 102_2. By roughly equalizing the size of the transistors, the current capabilities are roughly equal. Therefore, even if multiple transistors are used, the signal waveform Or, the degree of degradation of the transistor characteristics can be roughly However, the present invention is not limited to this, and the channel of the transistor 101_1 can be made equal. The width of the gate electrode of the transistor 101_1 and the channel width of the transistor 101_2 may be different. The channel width of the transistor 102_1 and the channel width of the transistor 102_2 are different. It is possible to make it happen.

[0134] When referring to the channel width of a transistor, this is expressed as the W / L (W: channel This can be rephrased as the ratio of the channel width (L: channel length).

[0135] As shown in FIG. 4(A), similarly to FIG. 43(E), the wiring 112 is divided into wirings 112A to 112B. It is possible to divide the transistor 101_1 into multiple wirings of 12D. the first terminals of the transistor 101_2, the transistor 102_1, and the transistor 102_2; are connected to the wiring 112A, the wiring 112B, the wiring 112C, and the wiring 112D, respectively.

[0136] As shown in FIG. 3C, the transistor 101_1 and the transistor 101_2 The first terminals of the wirings 113_1 and 113_2 can be connected to the wiring 113_2 and the wiring 113_1, respectively. Alternatively, as shown in FIG. 4B, the transistor 101_1 and the transistor 101_2 , the first terminal of the transistor 102_1, and the first terminal of the transistor 102_2 are connected to the wiring 1. 13_2, wiring 113_1, wiring 114_2, and wiring 114_1. In this case, during the period when the transistor is turned off by the inactive signal, An active signal is input to the first terminal of the transistor. During this time, a low-level signal is input to the gate of the transistor, and a high-level signal is input to the gate of the transistor. This includes the period when the reverse bias is input to the first terminal of the transistor. Since the voltage is applied to the transistor, it is possible to suppress the deterioration of the transistor. are not limited to, but may be, for example, transistor 101_1, transistor 101_2, transistor 102 The first terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to the wiring 114_2 and the wiring 114_3, respectively. The same effect can be obtained when the wiring 113_1, wiring 113_2, and wiring 113_1 are connected. Alternatively, as shown in FIG. 4C, the transistor 101_1 and the transistor 101 The first terminals of the transistors 102_1 and 102_2 are connected to the respective It is possible to connect the wire 114_1, the wire 114_2, the wire 113_1, and the wire 113_2. It is Noh.

[0137] Note that FIG. 5(A) shows a configuration in which a transistor is used as the switch in FIG. 43(C). The switches 13_1 and 13_2 are respectively connected to the transistors 103_ 1 and transistor 103_2 are used. Transistor 103_1 is used as transistor 1. 101_1 or 102_1, and the transistor 103_2 corresponds to a transistor The transistors 103_1 and 103_2 correspond to the transistors 101_1 and 102_2. A first terminal of the transistor 103_2 is connected to the wiring 112, and a second terminal of the transistor 103_1 is connected to the wiring 112. The second terminal of the transistor 103_2 is connected to the wiring 111. The gate of the transistor 103_1 is connected to the wiring 115_1, and the gate of the transistor 103_2 is connected to the wiring 115_2. The wiring 115_1 and the wiring 115_2 are respectively connected to the wiring 115_1 and the wiring 115_2. The signals S3_1 and S3_2 are input. It is often a digital signal and can function as a clock signal.

[0138] It should be noted that the contents described in FIG. 43(C) can be applied to FIG. 5(A).

[0139] As in FIG. 5(A), the semiconductor device in FIG. 3(C) and FIGS. 4(A) to 4(C) is , it is possible to have multiple circuits corresponding to the circuit 101 or the circuit 102.

[0140] FIG. 5B shows a configuration in which a transistor is used as the switch in FIG. 43A. The transistors 101_1 to 101_m are used as the switches 11_1 to 11_m. Transistors 102_1 to 102_m are used as switches 12_1 to 12_m. The first terminals of the transistors 101_1 to 101_m are connected to the wiring 112. The second terminals of the transistors 101_1 to 101_m are connected to the wiring 111. The gates of the transistors 101_1 to 101_m are connected to the wirings 113_1 to 113_m, respectively. The first terminals of the transistors 102_1 to 102_m are connected to the wiring 112. Second terminals of the transistors 102_1 to 102_m are connected to the wiring 111. The gates of the transistors 102_1 to 102_m are connected to the wirings 114_1 to 114_m, respectively. Signals S1_1 to S1_m are input to the wirings 113_1 to 113_m, respectively. Signals S2_1 to S2_m are input to the wirings 114_1 to 114_m, respectively. S1_1 to S1_m are sequentially activated every certain period (for example, every frame). Similarly, the signals S2_1 to S2_m are activated in sequence every certain period (for example, every frame). This shortens the period that the signal is in the active state. This shortens the time that the transistor is on, which reduces the deterioration of the transistor. can be suppressed.

[0141] It should be noted that the contents described in FIG. 43(A) can be applied to FIG. 5(B).

[0142] 5(B), in FIG. 3(C) and FIG. 4(A) to (C), the circuit 101, and circuit 102 may each include multiple transistors. In (A), the circuits corresponding to the circuit 101 or the circuit 102 each include a plurality of transistors. It is possible to have a star.

[0143] As shown in FIG. 6A, the transistor 101_1 is connected to one terminal (hereinafter also referred to as the positive terminal). The other terminal (hereinafter also referred to as a negative electrode) is connected to the wiring 113_1. It can be replaced with a diode 101a_1 connected to the transistor. One terminal of the terminal 101_2 is connected to the wiring 111, and the other terminal is connected to the wiring 113_2. Alternatively, the transistor 1 can be replaced with a diode 101a_2. One terminal of 02_1 is connected to the wiring 111, and the other terminal is connected to the wiring 114_1. Alternatively, the transistor 102 can be replaced with a diode 102a_1. 114_2 is connected to the wiring 111 at one terminal and to the wiring 114_2 at the other terminal. It is possible to replace it with diode 102a_2.

[0144] As shown in FIG. 6B, the transistor 101_1, the transistor 101_2, The transistor 102_1 and the transistor 102_2 can be diode-connected. In this case, the transistor 101_1, the transistor 101_2, and the transistor 1 The first terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to the wiring 113_1 and the wiring 113_2, respectively. The transistor 101_1 is connected to the wiring 114_1 and the wiring 114_2. The second transistors 101_2, 102_1, and 102_2 The terminal and the gate are connected to the wiring 111. 101_1, transistor 101_2, transistor 102_1, and transistor 10 The gates of the first and second gates 113_1, 113_2, 114_1, and 114_2 are connected to the wiring 113_1, wiring 113_2, wiring 114_1, and wiring 114_2, respectively. It can be connected to 4_2.

[0145] 6(A)-(B), as well as FIGS. 3(C), 4(A)-(C), and 5(A). In (B), the transistors (for example, transistor 101_1, transistor 1 101_2, transistor 102_1, and transistor 102_2) are placed in the diode. Alternatively, the gate of the transistor and the first terminal or the second terminal may be connected to each other. By connecting the transistor to the diode, it is possible to make the transistor diode-connected.

[0146] As shown in FIG. 6(C), a P-channel transistor is used as the transistor. It is possible to use the transistor 101p_1, the transistor 101p_2, the transistor The transistor 102p_1 and the transistor 102p_2 are connected to the transistors 101_1 and 102p_2, respectively. corresponding to transistor 101_2, transistor 102_1, and transistor 102_2, When the polarity of the transistor is a P-channel type, the wiring 112 is supplied with a voltage V2, and the signals S1_1, S1_2, S2_1, and S2_2 are , in many cases, the timing is reversed compared to the timing chart of FIG. 1(B).

[0147] As with Fig. 6(C), Figs. 3(C), 4(A)-(C), 5(A)-(B), and Fig. In 6(A) to (B), a P-channel transistor is used as the transistor. It is possible.

[0148] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. It is possible to have the semiconductor device of the first embodiment. Flip-flops, shift registers, gate drivers, source drivers, display devices, etc. Note that the semiconductor device of this embodiment mode can be used for a flip-flop or can be referred to as the driver circuit.

[0149] First, an example of a semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device in (A) includes a circuit 101, a circuit 102, and a transistor 201. The circuit 101 includes a plurality of transistors, namely, a transistor 101_1 and a transistor 101_2. The circuit 102 includes a transistor 102_1 and a transistor 102_2. The semiconductor device has a plurality of transistors.

[0150] The transistor 201 includes the transistor 101_1, the transistor 101_2, and the transistor 101_3. It is preferable that the polarity of the transistors 102_1 and 102_2 is the same as that of the transistors 102_2. However, the transistor 201 is not limited to a P-channel type. It can be of the channel type.

[0151] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 201 is connected to a wiring 211, and the second terminal of the transistor 201 is connected to a wiring 111. A first terminal of the transistor 101_1 is connected to a wiring 112. The second terminal of the transistor 101_1 is connected to the wiring 111. The first terminal of the transistor 101_2 is connected to a wiring 112, and the second terminal of the transistor 101_2 is connected to a wiring 111. A first terminal of the transistor 102_1 is connected to a wiring 112. A second terminal of the transistor 102_1 is connected to the wiring 111. The first terminal of the transistor 102_2 is connected to the wiring 114_1. The second terminal of the transistor 102_2 is connected to the wiring 111. The gate of the transistor 102_2 is connected to the wiring 114_2. However, various other connection configurations are possible.

[0152] The gate of the transistor 201 is denoted as a node A. The gate of the transistor 101_2 is indicated as a node B1. The gate of the transistor 101_2 is indicated as a node B2. Node A, node B1, and node B2 can be referred to as wires.

[0153] Next, an example of a signal or voltage input to or output from each wiring will be described. A signal OUT is output from the wiring 211. A signal CK is input to the wiring 212. The signal CK corresponds to the signal S1 and can function as a clock signal. It is assumed that a voltage V1 is input to the wiring 112. However, this is not limiting. These wires can also be used to input various other signals, voltages, or currents. is.

[0154] Note that the wiring 211 can function as a signal line or a clock signal line. However, the wiring 211 is not limited to this, and can function as various other wirings. be.

[0155] Next, the function of the transistor 201 will be described. The timing for supplying the H-level signal CK to the wiring 111 is controlled according to the potential of the node A. By doing so, it has the function of controlling the timing when the signal OUT becomes H level, and It can function as a backup transistor or a bootstrap transistor. For example, the transistor 201 is turned on during the period A0 described in the first embodiment. Then, a signal CK of H level is supplied to the wiring 111. However, this is not limited to this. Register 201 can have a variety of other functions.

[0156] Note that the semiconductor device can include a circuit 200 as shown in FIG. The circuit 200 can have a variety of configurations, and the circuit 200 can be implemented in one or more The polarity of these transistors is 01_1, transistor 101_2, transistor 102_1, transistor 102_2 , and the polarity of the transistor 201. However, this is not a limitation. For example, the circuit 200 may include an N-channel transistor and a P-channel transistor. That is, the circuit 200 can be a CMOS circuit. The circuit 200 has a plurality of terminals, ie, terminals 200a to 200k. 00b, terminal 200c, terminal 200d, terminal 200e, terminal 200f, terminal 200g, end The terminal 200h, the terminal 200i, the terminal 200j, and the terminal 200k are each connected to a wiring 211_1. , wiring 211_2, wiring 114_1, wiring 114_2, wiring 212, wiring 213, wiring 1 12, node A, wiring 111, node B1, and node B2 are connected. The circuit 200 may have various other terminals, and the terminal 200a 200k or more. Alternatively, each terminal of the circuit 200 may be omitted. It is also possible for the signal lines to be connected to various wires or nodes.

[0157] The wiring 211_1 and the wiring 211_2 are connected to the signals CK_1 and CK_2, respectively. The signals CK_1 and CK_2 are respectively input to the signals S1_1 and S1_2. The wiring 114_1 and wiring 114_2 correspond to each other and can function as a clock signal. Signals CKB_1 and CKB_2 are input to 14_2, respectively. The signals KB_1 and CKB_2 correspond to the signals S2_1 and S2_2, respectively, and are inverted clocks. The wiring 212 is configured to receive a signal SP. The signal SP is often a digital signal and can function as a start signal. Alternatively, the signal SP may be a transfer signal, an output signal, or a signal from another stage (e.g., a previous stage). The signal RE is input to the wiring 213. The signal RE is often a digital signal and functions as a reset signal. Alternatively, the signal RE may be a transfer signal of another stage (for example, the next stage), an output signal However, it is not limited to this and can function as a Various other signals, voltages, or currents can be input to these wires. be.

[0158] The wiring 211_1 and the wiring 211_2 function as a signal line or a clock signal line. Alternatively, the wiring 212 and the wiring 213 may be a signal line, a gate line, or These lines can function as scanning lines, etc. However, they are not limited to this. The lines can also function as various other wirings.

[0159] The circuit 200 outputs signals CK_1, CK_2, CKB_1, CKB_2, signal SP, signal RE, voltage V1, the potential of node A, signal OUT, the potential of node B1, and / or depending on the potential of node B2, the potential of node A, the signal OUT, the potential of node B1, And / or, it has a function of controlling the potential of the node B2 and can function as a control circuit. However, the circuit 200 is not limited to this and may have various other functions. It is possible.

[0160] As shown in FIG. 8A, the semiconductor device includes a circuit 300 and a circuit 400. Various configurations can be used for the circuit 300 and the circuit 400. For example, the circuit 400 includes a and a logic circuit for controlling the potential of the gate of the transistor 101_2. An example of such a logic circuit is a 2-bit logic circuit shown in FIG. A logic circuit that combines AND and NOT of inputs, or a two-input However, the circuit 400 is not limited to this, and various other circuits can be used. It is possible to use the path.

[0161] Note that the circuit 300 and the circuit 400 each include one or more transistors. The polarity of these transistors is transistor 101_1, transistor 101_2, The same polarity as the transistor 102_1, the transistor 102_2, and the transistor 201 However, the present invention is not limited to this. For example, the circuit 300 and / or The circuit 400 may include N-channel and P-channel transistors. That is, the circuit 300 and / or the circuit 400 can be a CMOS circuit. It is possible.

[0162] The circuit 300 has a plurality of terminals 300a to 300i. The terminal 300a, the terminal 300b, the terminal 400f, and the terminal 400c are connected to each other. Terminal 300c, terminal 300d, terminal 300e, terminal 300f, terminal 300g, terminal 300h , and the terminal 300i are respectively connected to the wiring 211_1, the wiring 211_2, the wiring 114_1, the wiring 114_2, wiring 212, wiring 213, wiring 112, the gate of transistor 201, wiring 111. Terminal 400a, terminal 400b, terminal 400c, terminal 400d, terminal The terminals 400e and 400f are connected to the wiring 211_1, the wiring 211_2, and the transistor 201, the wiring 112, the gate of the transistor 101_1, the transistor 101_ 2. However, the present invention is not limited to this, and the circuit 300 and / or the circuit 4 00 may have various other terminals, and any of the terminals 300a to 300i may be Alternatively, any of the terminals 400a to 400f may be omitted. Each terminal of the circuit 300 and / or 400 is connected to various other wires or nodes. It is possible.

[0163] The circuit 300 outputs signals CK_1, CK_2, CKB_1, CKB_2, Depending on the signal SP, the signal RE, the voltage V1, the potential of the node A, and / or the signal OUT, The potential of the node A and / or the wiring 111 is controlled, and the potential of the node A and / or the wiring 111 is controlled. The circuit 400 receives the signals CK_1, CK_2, the potential of node A, and the voltage Depending on V1, the potential of node B1, and / or the potential of node B2, Alternatively, the potential of the node B2 may be controlled, and the potential of the node B2 may be controlled as a control circuit. However, the circuit 300 and the circuit 400 are not limited to this, and may have various other functions. It is possible to do this.

[0164] Next, the operation of the semiconductor device of this embodiment will be described. Regarding the operation of the semiconductor device of (A), Figs. 8(B), 9(A), 9(B), and 10(A) ), Figure 10(B), Figure 11(A), Figure 11(B), Figure 12(A), Figure 12(B), Figure 13 8(A) and 13(B). In FIG. 8(B), the signal CK, the signal CK_ 1, signal CK_2, signal CKB_1, signal CKB_2, signal SP, signal RE, node A potential (Va), the potential of node B1 (Vb1), the potential of node B2 (Vb2), and the signal O UT. One operation period (or one frame period) in the timing chart of FIG. 8(B) is , period T1, period T2, period T3, period T4, and period T5. 0(A), 11(A), 12(A), and 13(A) show the k-th frame. Schematic diagrams of the operation of the semiconductor device in periods T1, T2, T3, T4, and T5. 9(B), 10(B), 11(B), 12(B), and 13(B) are shown. are the periods T1, T2, T3, T4, and T5 of the k+1th frame, respectively. 1A is a schematic diagram showing the operation of the semiconductor device in FIG. The operation of the semiconductor device shown in FIG. 8(A) will be explained in detail with reference to FIG. It is possible to apply this to the operation of the semiconductor device of A) to (B).

[0165] First, in the period T1 of the kth frame, the signal CKB_1 becomes H level, and the signal CKB Since the transistor 102_2 is at the L level, the transistor 102_1 is turned on and the transistor 102 At the same time, the signals CK_1 and CK_2 become L level, so the circuit 400 reduces the potential at nodes B1 and B2. For example, circuit 400 Alternatively, the circuit 400 may provide a signal or voltage V1 at node B1 and node B2. The potentials of the nodes B1 and B2 are reduced by capacitive coupling. As a result, the transistor 101_1 and the transistor 101_2 are turned off. Similarly, the wiring 112 and the wiring 111 are brought into electrical conduction through the transistor 102_1. A voltage V1 is supplied from the wiring 112 to the wiring 111 via the transistor 102_1. At this time, the signal SP becomes H level, so the circuit 300 increases the potential of the node A. For example, the circuit 300 supplies a high-level signal or voltage V2 to node A. Then, The potential of the node A is equal to the L level potential (V1) of the signal CK and the threshold voltage of the transistor 201. When the voltage rises to the sum of V1 and Vth201, the transistor 201 Therefore, the wiring 211 and the wiring 111 are brought into electrical continuity through the transistor 201. Therefore, the L-level signal CK is supplied from the wiring 211 to the wiring 11 via the transistor 201. 1. After that, the potential of node A continues to rise. When the voltage Vth reaches at least V1+Vth201, the circuit 300 outputs a signal or Therefore, node A will maintain the potential at this time and will become a floating As a result, the signal OUT goes low.

[0166] During the period T1 of the kth frame, the circuit 300 outputs a signal or voltage V1 at an L level. However, the present invention is not limited to this. It is possible that no signal or voltage is supplied to the wiring 111 .

[0167] On the other hand, in the period T1 of the k+1th frame, the signal CKB_1 becomes L level, and the signal CK B_2 becomes H level, so the transistor 102_1 is turned off and the transistor 10 The difference from the operation in the k-th frame period T1 is that 2_2 is turned on.

[0168] Next, in the period T2 of the kth frame, the signal CKB_1 becomes L level, and the signal CKB Since the _2 remains at the L level, the transistor 102_1 is turned off and the transistor At the same time, the signal CK_1 goes high and the signal CK_2 goes high. remains at the L level, but the potential of node A remains at a high value, so the circuit 400 For example, the circuit 400 maintains the potentials of the nodes B1 and B2 at a low level. Alternatively, the circuit 400 may continue to provide a signal or voltage V1 to the nodes B1 and B2. The nodes B1 and B2 are connected to each other without supplying a signal or voltage to the nodes B1 and B2. Therefore, the transistor 101_1 and the transistor 101_2 are turned off. As a result, the wiring 112 and the wiring 111 are not electrically connected to each other, as in FIG. 2C. At this time, the circuit 300 may not be supplying a signal or voltage to the node A. In other words, node A remains floating, so the potential (V1+V Therefore, the transistor 201 remains on. Therefore, the wiring 211 and the wiring 111 remain in a conductive state. As a result, the potential of the wiring 111 starts to rise. is left floating, the potential of node A is This is called bootstrap operation. The potential of node A rises to V2+Vth201+α (α is a positive number). The potential of the signal 11 rises to the potential (V2) of the H-level signal CK. OUT becomes H level.

[0169] On the other hand, during the period T2 of the k+1th frame, the signal CK_1 remains at the L level, and the signal The difference from the operation in the k-th frame period T2 is that CK_2 becomes H level. In this case, the potential of node A remains high, so the circuit 400 The potential of node B2 is maintained at a low value.

[0170] Next, in the period T3 of the kth frame, the signal CKB_1 becomes H level, and the signal CKB Since _2 remains at the L level, the transistor 102_1 is turned on, and the transistor At the same time, the signal CK_1 goes low and the signal CK_2 goes high. remains at the L level, the circuit 400 sets the potentials of the nodes B1 and B2 to a low value. For example, the circuit 400 may maintain a low level signal or voltage V1 at nodes B1 and Alternatively, the circuit 400 may continue to provide a signal, voltage, etc. to the nodes B1 and B2. Therefore, the transistor B1 and the node B2 are not supplied with a voltage. The transistor 102_1 and the transistor 102_2 remain off. As a result, Similarly, the wiring 112 and the wiring 111 are brought into electrical continuity through the transistor 102_1. Therefore, the voltage V1 is supplied from the wiring 112 to the wiring 111 via the transistor 102_1. At this time, the signal RE becomes H level, so the circuit 400 decreases the potential of the node A. For example, the circuit 400 supplies a signal or voltage V1 at an L level to the node A. As a result, the transistor 201 is turned off, and the wiring 211 and the wiring 111 are not electrically connected to each other. As a result, the signal OUT becomes L level.

[0171] During the period T3 of the kth frame, the circuit 300 outputs a signal or voltage V1 at an L level. It is possible to supply the same to the wiring 111.

[0172] On the other hand, during the period T3 of the k+1th frame, the signal CKB_1 remains at the L level, and the signal Since the signal CKB_2 goes high, the transistor 102_1 remains off. The difference from the operation in the period T3 of the k-th frame is that the transistor 102_2 is turned on.

[0173] Next, in the period T4 of the kth frame, the signal CKB_1 becomes L level, and the signal CKB Since the _2 remains at the L level, the transistor 102_1 is turned off and the transistor At the same time, the signal CK_1 goes high and the signal CK_2 goes high. remains at L level, the circuit 400 increases the potential of the node B1. 00 provides a high level signal or voltage V2 to node B1. Alternatively, circuit 400 The capacitive coupling increases the potential at node B1. For example, the circuit 400 may apply a low level signal or voltage V1 to node Alternatively, the circuit 400 may provide a signal, voltage, etc. to node B2 without providing a signal, voltage, etc. to node B2. This causes the node B2 to be floating, turning on the transistor 101_1. As a result, the wiring 112 and the wiring 113 are disconnected from each other as in FIG. 2(A). 111 is in a conductive state via the transistor 101_1, so that the voltage V1 is applied to the wiring 112 is supplied to the wiring 111 through the transistor 101_1. , the potential of node A is maintained at V1. For example, the circuit 300 may 1 to node A. Alternatively, the circuit 300 may provide a signal, voltage, etc. to node A. The absence of a voltage causes node A to float. Therefore, transistor 201 is turned off. Therefore, the wiring 211 and the wiring 111 remain in a non-conductive state. No. OUT remains at L level.

[0174] During the k-th frame period T4, the circuit 300 outputs an L-level signal or voltage V1. The signal can be supplied to the wiring 111. However, this is not limitative. It is possible to not supply a signal, voltage, etc. to the wiring 111.

[0175] On the other hand, during the period T4 of the k+1th frame, the signal CK_1 remains at the L level, and the signal The difference from the operation in the k-th frame period T4 is that CK_2 becomes H level. Since circuit 400 keeps node B1 low and raises node B2, The transistor 101_1 remains off and the transistor 101_2 turns on. , the operation is different from that in the period T4 of the kth frame.

[0176] Next, in the period T5 of the kth frame, the signal CKB_1 becomes H level, and the signal CKB Since the signal _2 remains at the L level, the transistor 102_1 is turned on, and the transistor 10 2_2 remains off. At the same time, signal CK_1 goes low and signal CK_2 goes low. Since the potential at node B1 remains at the same level, the circuit 400 decreases the potential at node B1. 400 supplies a low level signal or voltage V1 to node B1. Alternatively, circuit 400 , the potential at node B1 is reduced by capacitive coupling. For example, the circuit 400 may maintain the potential of the node 2 at a low value by applying a low level signal or voltage V1 to the node 2. Alternatively, the circuit 400 may not provide a signal or voltage to the node B2. Therefore, the node B2 is floating, and the transistor 101_1 is turned off. As a result, the wiring 111 and the transistor 101_2 remain off, as in FIG. 2(B). The wiring 112 is electrically connected via the transistor 102_1, so that the voltage V1 is applied to the wiring 1 12 to the wiring 111 through the transistor 102_1. For example, the circuit 300 may output a low-level signal or voltage. The circuit 300 supplies a voltage V1 to node A. Alternatively, the circuit 300 may supply a signal, voltage, etc. to node A. By not supplying a voltage to node A, node A is left floating. Therefore, transistor 201 Since the switch remains off, the wiring 211 and the wiring 111 remain in a non-conductive state. , the signal OUT remains at the L level.

[0177] During the period T5 of the k-th frame, the circuit 300 outputs a signal or voltage V1 at an L level. The signal can be supplied to the wiring 111. However, this is not limitative. It is possible to not supply a signal, voltage, etc. to the wiring 111.

[0178] On the other hand, during the period T5 of the k+1th frame, the signal CKB_1 remains at the L level. Since the signal CKB_2 becomes H level, the transistor 102_1 is turned off and the transistor The operation differs from that in the period T5 of the k-th frame in that the timer 102_2 is turned on.

[0179] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment mode. By doing so, the life of these components can be extended.

[0180] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors may be set to N-channel type or P-channel type. Therefore, compared to CMOS circuits, the number of processes can be reduced. It is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. If all transistors are N-channel, including the semiconductor layer of the transistor, Examples of the semiconductor include non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, and oxide semiconductors. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of this embodiment is designed to suppress the deterioration of the transistor. It is possible.

[0181] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0182] In FIG. 8B, the period T2 is shown as the selection period, and the other periods (period T1, period The periods T3, T4, and T5 can be designated as non-selection periods. T1, period T2, period T3, period T4, and period T5 are respectively referred to as a set period, an output period, and These can be referred to as a reset period, a first non-select period, and a second non-select period.

[0183] As shown in FIG. 14A, the signals CK, CK_1, CK_2, and CKB In signal CKB_1 and signal CKB_2, the time it takes to become H level is shorter than the time it takes to become L level. By doing so, the signal CK becomes low during the period T2. When this occurs, the potential of node A remains high, so the transistor 201 remains on. Therefore, the wiring 211 and the wiring 111 remain electrically connected through the transistor 201. Therefore, the L-level signal CK is transmitted from the wiring 211 to the wiring 111 via the transistor 201. The channel width of the transistor 201 is often large, so the potential of the wiring 111 Therefore, the fall time of the signal OUT can be shortened. However, the present invention is not limited to this, and the signals CK, CK_1, CK_2, and CKB can also be used. In signal CKB_1 and signal CKB_2, the time at H level is longer than the time at L level. It is possible to do this.

[0184] As shown in FIG. 14(B), during the period T2, the voltage V1 or the L level signal is By supplying the signal to the node A and the wiring 111, the signal OUT can be set to L level. This allows the drive frequency to be slowed down, reducing power consumption. It is possible to reduce this.

[0185] Note that as shown in FIG. 5A, the semiconductor device may include multiple circuits corresponding to the circuit 101 or the circuit 102. If multiple clock signals are provided, it is possible to input a multi-phase clock signal to the semiconductor device. A) is an example of a timing chart when a three-phase clock signal is input to a semiconductor device. However, it is not limited to these.

[0186] Note that as shown in FIG. 5B, the circuit 101 or the circuit 102 may include a plurality of transistors. In FIG. 15B, the circuit 101 or the circuit 102 includes three transistors. 10 shows an example of a timing chart for a case where the synchronous oscillator 100 is provided, but the present invention is not limited to this.

[0187] The channel width of the transistor 201 is the same as that of the transistors 101_1 and 101_2. 1_2, the channel width of the transistor 102_1 and the channel width of the transistor 102_2 are larger than This reduces the on-resistance of the transistor 201. Therefore, the rise time or fall time of the signal OUT can be shortened. However, the channel width of the transistor 201 is not limited to this. Transistor 101_2, transistor 102_1, and / or transistor 102_ It is possible to have a channel width smaller than 2.

[0188] In the transistor 201, the parasitic capacitance between the gate and the second terminal is It is preferable that the parasitic capacitance between the first terminal and the second terminal is larger than the parasitic capacitance between the first terminal and the second terminal. This is because the potential of node A tends to become high due to the bootstrap operation. Therefore, a conductive layer functioning as a gate and a conductive layer functioning as a source or a drain are formed. The overlapping area on the second terminal side is preferably larger than that on the first terminal side. , but is not limited to this.

[0189] As described in the first embodiment, the wiring can be divided into multiple wirings. The same signal or voltage can be input to the multiple wirings, and the same signal or voltage can be input to the multiple wirings. Alternatively, the plurality of wirings may be connected to the same wiring. or elements, and the plurality of wirings can be connected to separate wirings or elements. In FIG. 16A, the wiring 112 is connected to the wiring 113 as an example. The diagram shows a configuration in which the wiring is divided into a plurality of wirings 112A to 112D.

[0190] As in FIG. 16(A), in FIG. 7(B) and FIG. 8(A), the wiring is divided into a plurality of wirings. It is possible to divide the wiring 112 into lines. 14_2, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 212, and / or the wiring It is possible to split the line 213 into multiple wires.

[0191] As shown in FIG. 16B, the first terminal of the transistor 101_1 and the The first terminals of the first and second ... The first terminal of the transistor 102_1 and the second terminal of the transistor 102_2 can be The first terminals can be connected to the wiring 114_2 and the wiring 114_1, respectively. By doing so, similarly to FIG. 4(B), the transistors 101_1 to 101_2 and A reverse bias can be applied to the transistors 102_1 and 102_2. However, the present invention is not limited to this and can suppress the deterioration of the transistors. a first terminal of the transistor 101_1, a first terminal of the transistor 101_2, and a first terminal of the transistor 10 The first terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to various wirings or For example, the first terminal of the transistor 101_1 may be connected to various nodes. The first terminal of the transistor 101_1 is connected to the node B2, and the second terminal of the transistor 101_2 is connected to the node B1. It is possible to do this.

[0192] 16(B), in FIG. 7(B) and FIG. 8(A), the transistor 1 The first terminal of the transistor 101_1 and the first terminal of the transistor 101_2 are connected to the wiring 211. The first transistor 102_1 can be connected to the wiring 211_2. The terminal of the transistor 102_1 and the first terminal of the transistor 102_2 are connected to the wiring 114_1 and the wiring 114_2, respectively. It can be connected to _2.

[0193] As shown in FIG. 17A, a transistor 201 is connected between the gate and the second terminal thereof. It is possible to newly connect the capacitive element 202. In this way, the boot During the strap operation, the potential of node A can be increased. As the Vgs of 01 increases, the fall time or rise time of the signal OUT However, the capacitance element 202 is not limited to this, and may be a transistor. In this case, the transistor used as the MOS capacitor To increase the capacitance of the transistor, the gate of the transistor is connected to node A. The first terminal or the second terminal of the transistor is preferably connected to the wiring 111. I wish.

[0194] As in FIG. 17(A), in FIG. 7(B), FIG. 8(A), and FIG. 16(A) to (B), Even if the transistor 201 is turned on, a capacitor 202 is newly connected between the gate and the second terminal of the transistor 201. It is possible to continue.

[0195] It is also possible to split the output signal into two. For example, one output signal can be fed to another stage. It can serve as a signal for transfer to a flip-flop (e.g., the next stage). The other output signal can function as a signal output to a pixel. As shown in FIG. 17B, a transistor 203 can be newly added. The transistor 203 has the same function as the transistor 201 and is an N-channel transistor. A first terminal of the transistor 203 is connected to a wiring 211. The second terminal of the transistor 203 is connected to the wiring 212, and the gate of the transistor 203 is connected to the It is connected to the gate of register 201.

[0196] However, the transistor 203 is not limited to this and can be a P-channel type. Alternatively, the first terminal of the transistor 203 and the first terminal of the transistor 201 are Alternatively, the gate of the transistor 203 and the transistor 204 may be connected to different wirings. The gate of the transistor 201 can be connected to a separate wiring.

[0197] As shown in FIG. 18, not only the transistor 203 but also the circuit 231 and the circuit 23 The circuit 231 has the same function as the circuit 101. The circuit 232 has a function similar to that of the circuit 102. The circuit 231 includes a transistor 231_ The circuit 232 includes a plurality of transistors, namely, a transistor 231_1 and a transistor 231_2. The circuit includes a plurality of transistors, namely, a transistor 232_1 and a transistor 232_2. The transistor 231_1, the transistor 231_2, the transistor 232_1, and the transistor The transistor 232_2 is connected to the transistor 101_1, the transistor 101_2, and the transistor 232_3. The transistors 102_1 and 102_2 correspond to N-channel transistors. The transistor 231_1, the transistor 231_2, the transistor 232_1, and the transistor A first terminal of the transistor 232_2 is connected to the wiring 112. 1, transistor 231_2, transistor 232_1, and transistor 232_2 The second terminal is connected to the wiring 212. The gates of the transistors 232_1 and 232_2 are connected to the nodes B2, node B3, wiring 114_1, and wiring 114_2. The transistor 231_1, the transistor 231_2, the transistor 232_1, And / or the transistor 232_2 can be a P-channel type. , transistor 231_1, transistor 231_2, transistor 232_1, and / or Alternatively, the first terminal and the second terminal of the transistor 232_2 are connected to different wirings. It is possible to do this.

[0198] 17B and 18, an output signal from the wiring 111 is supplied to the pixel. When the output signal from the wiring 212 is a signal for transfer, the transistor 20 The channel width of transistor 3 is preferably smaller than that of transistor 201. In this case, the wiring 111 is connected to a gate line or a pixel, and therefore the load of the wiring 111 is This is because the load on the wiring 1 is often larger than that on the wiring 212. The signal output from the wiring 211 is a signal for transfer, and the signal output from the wiring 212 is a signal for transfer to the pixel. When the signal is output, the channel width of the transistor 203 is It can be larger than the channel width.

[0199] 17B and 18, an output signal from the wiring 111 is supplied to the pixel. When the output signal from the wiring 212 is a transfer signal, the transistor 23 1_1, transistor 231_2, transistor 232_1, and transistor 232_ The channel width of transistor 101_1, transistor 101_2, and transistor 1 02_1, it is preferable that the channel width of the transistor 102_2 is smaller than that of the transistor 102_2. Since the wiring 111 is connected to a gate line or a pixel, the load of the wiring 111 is This is because the load is often larger than that of 12. However, this is not limited to this. transistor 231_1, transistor 231_2, transistor 232_1, and transistor 2 The channel width of transistor 101_1, transistor 101_2, transistor 32_2 is The channel width of the transistor 102_1 can be larger than that of the transistor 102_2.

[0200] 17B and 18, the gate and the second terminal of the transistor 203 are A capacitive element can be connected between the

[0201] 17(B) and 18, as well as FIGS. 7(B), 8(A), 16(A) to 16(B), 17B) and FIG. 17A, the transistor 203, the circuit 231, and / or the circuit It is possible to add a new path 232.

[0202] As shown in FIG. 19(A), a P-channel transistor is used as the transistor. It is possible to use the transistor 101p_1, the transistor 101p_2, the transistor The transistor 102p_1, the transistor 102p_2, and the transistor 201p are respectively Transistor 101_1, transistor 101_2, transistor 102_1, transistor The transistor 102_2 corresponds to the transistor 201 and is a P-channel type. When the polarity of the transistor is P-channel, as shown in FIG. 19(B), the wiring 112 is connected to a voltage V 2 are supplied, and signals CK, CK_1, CK_2, CKB_1, and CKB_ 2. The potential Va, the potential Vb1, the potential Vb2, and the signal OUT are in accordance with the timing chart of FIG. In many cases, the trend is inverted compared to the chart.

[0203] As with FIG. 19(A), FIGS. 7(B), 8(A), 16(A)-(B), and 17 In (A) to (B) and FIG. 18, the transistor is a P-channel transistor. It is possible to use a

[0204] (Embodiment 3) In this embodiment, a specific example of the circuit 300 described in the second embodiment will be described. The circuit 300 can be referred to as a semiconductor device, a driver circuit, or a gate driver. The contents described in the first and second embodiments will not be described here. The contents described in the first to second embodiments can be freely combined with the contents described in this embodiment. can be done.

[0205] First, an example of a circuit 300 will be described with reference to FIG. Transistor 301, transistor 302, transistor 303, transistor 304_1 , transistor 304_2, transistor 305_1, and transistor 305_2. However, the circuit 300 is not limited to this and may include various other components. Alternatively, circuit 300 can omit any of these transistors. is.

[0206] Note that transistor 301, transistor 302, transistor 303, and transistor 3 04_1, transistor 304_2, transistor 305_1, and transistor 305 _2 preferably has the same polarity as the transistor 201 and is an N-channel type. However, the present invention is not limited to this, and the transistors 301, 302, Transistor 303, transistor 304_1, transistor 304_2, transistor 305 _1 and transistor 305_2 can be P-channel.

[0207] Next, an example of the connection relationship of the circuit 300 will be described. is connected to the wiring 212, the second terminal of the transistor 301 is connected to the node A, The gate of the transistor 301 is connected to the wiring 212. The first terminal of the transistor 302 is connected to the wiring 112, and the second terminal of the transistor 302 is connected to the node A. The gate of the transistor 302 is connected to the wiring 213. The first terminal of the transistor 303 is connected to the wiring 112, and the second terminal of the transistor 303 is connected to the wiring 111. The gate of the transistor 303 is connected to the wiring 213. The first terminal of the transistor 4_1 and the first terminal of the transistor 304_2 are connected to the wiring 212. The second terminal of the transistor 304_1 and the second terminal of the transistor 304_2 are connected to the node A. The gates of the transistors 304_1 and 304_2 are connected to the wiring 114. The transistor 305_1 and the transistor 305_2 are connected to the wiring 114_2. A first terminal of the transistor 305_1 and a second terminal of the transistor 305_2 are connected to the node A. A second terminal of the transistor 305_2 is connected to the wiring 111. The gates of the transistors 305_2 are connected to the wirings 211_1 and 211_2, respectively. However, the present invention is not limited to this, and various other connection configurations are possible.

[0208] Next, an example of the function of each transistor will be described. By controlling the conduction state between the wiring 212 and the node A in response to the signal SP, the H level This has the function of controlling the timing at which the signal is supplied to node A, and functions as a diode. The transistor 302 is connected between the wiring 112 and the node A in response to the signal RE. By controlling the conduction state between the The transistor 303 has a function of controlling the voltage Vcc and can function as a switch. By controlling the conduction state between the wiring 112 and the wiring 111 in response to the signal RE, the voltage It has a function of controlling the timing when V1 is supplied to the wiring 111 and functions as a switch. The transistor 304_1 can be connected to the wiring 212 in response to the signal CKB_1. By controlling the conduction state between node A and node B, the timing at which signal SP is supplied to node A is The transistor has the function of controlling the switching and can function as a switch. 304_2 controls the conduction state between the wiring 212 and the node A in response to the signal CKB_2. By doing so, the timing at which the signal SP is supplied to the node A can be controlled. The transistor 305_1 can function as a latch in response to the signal CK_1. The wiring 111 has a function of controlling the electrical continuity between the node A and the wiring 111 and functions as a switch. The transistor 305_2 is connected to the node A in response to the signal CK_2. It has a function of controlling the conduction state with 111 and can function as a switch. However, this is not a limitation, and these transistors can have various other functions. It is Noh.

[0209] Next, the operation of the semiconductor device of FIG. 21A will be described with reference to the timing chart of FIG. 8B. This will be explained in light of the above.

[0210] First, in the period T1 of the kth frame, the signal SP becomes H level, and the transistor 301 turns on. At the same time, the signal CKB_1 becomes H level and the signal CKB_2 becomes L level. This turns on the transistor 304_1 and turns off the transistor 304_2. Therefore, the wiring 212 and the node A are brought into electrical continuity, and the signal SP is transmitted to the wiring 212 is supplied to node A. Then, the potential of node A starts to rise. At this time, signal C Since the signal CK_1 and the signal CK_2 are at the L level, the transistors 305_1 and 305_2 are Therefore, the node A and the wiring 111 are not electrically connected to each other. Since the signal RE is at the L level, the transistor 302 and the transistor 303 are turned off. Therefore, the wiring 112 and the node A are brought out of conduction, and the wiring 112 and the wiring 111 After that, the potential of node A changes from the potential (V2) of the H-level signal SP to The value (V2-Vth301) obtained by subtracting the threshold voltage (Vth301) of the transistor 301 from the When the potential of the node A becomes H level, the transistor 301 is turned off. The potential (V2) of the signal CKB_1 is converted into the threshold voltage (Vth304 When the value obtained by subtracting Vth304_1 from Vth304_2 is reached, the transistor 304_ Here, when the potential of node A becomes V2-Vth301, the transistor The transistors 301 and 304_1 are turned off. Then, node A becomes non-conductive. Then, node A becomes floating, and the potential is V2-Vt Maintain at h301.

[0211] On the other hand, in the period T1 of the k+1th frame, the signal CKB_1 becomes L level, and the signal CK Since B_2 becomes H level, the transistor 304_1 is turned off and the transistor 30 The difference from the operation in the k-th frame period T1 is that 4_2 is turned on.

[0212] Next, in the period T2 of the kth frame, the signal SP becomes L level, and the transistor 301 remains off. Then, the signal CKB_1 goes to the L level and the signal CKB_2 remains at L level, the transistor 304_1 and the transistor 304_2 are off. Therefore, the wiring 212 and the node A remain in a non-conductive state. Signal CK_1 becomes H level and signal CK_2 remains L level. However, node A The potential of the transistor 305_1 and the transistor 305_2 is V2+Vth201+β (β is a positive number). Therefore, the node A and the wiring 111 are not connected to each other. Since the signal RE remains at the L level, the transistor 302 Therefore, the wiring 112 and the node A are not electrically connected. The wiring 112 and the wiring 111 remain in a non-conductive state.

[0213] On the other hand, during the period T2 of the k+1th frame, the signal CKB_1 remains at the L level. The difference from the operation in the k-th frame period T2 is that signal CKB_2 becomes H level. However, even in this case, the potential of node A is V2+Vth201+β, so the transistor 305_1 and transistor 305_2 remain off.

[0214] Next, in the period T3 of the kth frame, the signal SP remains at the L level, so the transistor Then, the signal CKB_1 goes to the H level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned on and the transistor 3 Therefore, the wiring 212 and the node A are brought into electrical continuity. The signal SP at L level is supplied from the wiring 212 to the node A. At this time, the signal CK_1 The signal CK_2 remains at the L level, so the transistors 305_1 and Therefore, the node A and the wiring 111 are not connected to each other. Then, the signal RE goes high, so that the transistors 302 and Therefore, electrical continuity between the wiring 112 and the node A is established. Then, the wiring 112 and the wiring 111 are brought into a conductive state. Then, the voltage V1 flows from the wiring 112 to the A voltage is supplied to the node A, and a voltage V1 is supplied from the wiring 112 to the wiring 111.

[0215] On the other hand, in the period T3 of the k+1th frame, the signal CKB_1 becomes L level, and the signal CK Since B_2 becomes H level, the transistor 304_1 is turned off and the transistor 30 The difference from the operation in the k-th frame period T3 is that 4_2 is turned on.

[0216] Next, in the period T4 of the kth frame, the signal SP remains at the L level, so the transistor Then, the signal CKB_1 goes to the L level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned off and the transistor 3 Therefore, the wiring 212 and the node A remain in a non-conductive state. At this time, signal CK_1 becomes H level and signal CK_2 remains L level. , transistor 305_1 turns on and transistor 305_2 remains off. Therefore, the node A and the wiring 111 are electrically connected. Then, the signal RE becomes L level. Therefore, the transistor 302 and the transistor 303 are turned off. 2 and the node A are brought out of conduction, and the wiring 112 and the wiring 111 are brought out of conduction.

[0217] On the other hand, during the period T4 of the k+1th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 is at a high level, transistor 305_1 remains off and transistor The difference from the operation in the k-th frame period T4 is that the starter 305_2 is turned on.

[0218] Next, in the period T5 of the kth frame, the signal SP remains at the L level, so the transistor Then, the signal CKB_1 goes to the H level, and the signal CKB_ 2 remains at the L level, so the transistor 304_1 is turned on and the transistor 3 Therefore, the wiring 212 and the node A are brought into electrical continuity. A signal SP of L level is supplied to node A. At this time, the signal CK_1 becomes L level. Since the signal CK_2 remains at the L level, the transistor 305_1 is turned off and the transistor The transistor 305_2 remains off. Therefore, the node A and the wiring 111 are not electrically connected. Then, since the signal RE remains at the L level, the transistor 302 and the transistor Therefore, the wiring 112 and the node A are not electrically connected to each other. , the wiring 112 and the wiring 111 remain in a non-conductive state.

[0219] On the other hand, during the period T5 of the k+1th frame, the signal CKB_1 remains at the L level. Since the signal CKB_2 goes high, the transistor 305_1 remains off. The operation differs from that in the k-th frame period T5 in that the transistor 305_2 is turned on.

[0220] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment mode. By doing so, the life of these components can be extended.

[0221] In particular, the transistor 304_1, the transistor 304_2, the transistor 305_1, and The transistor 305_2 has a period in which it remains off and a period in which it alternates between on and off. Therefore, the transistor is turned on for a shorter time, The deterioration of characteristics can be suppressed.

[0222] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors may be set to N-channel type or P-channel type. Therefore, compared to CMOS circuits, the number of processes can be reduced. It is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. If all transistors are N-channel, including the semiconductor layer of the transistor, Examples of the semiconductor include non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, and oxide semiconductors. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of this embodiment is designed to suppress the deterioration of the transistor. It is possible.

[0223] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0224] The channel width of the transistor 304_1 and the channel width of the transistor 304_2 are It is preferable that the channel width of the transistor 305_1 and the channel width of the transistor 305_2 are approximately equal. It is preferable that the channel width of the transistor 305_1 is approximately equal to that of the transistor 305_2. The transistor 304_1 and the transistor 304_2 have the same function. This is because the transistor 5_1 and the transistor 305_2 have the same function. The channel width of the transistor 304_1 is not fixed, and the channel width of the transistor 304_2 is It can be larger or smaller than the width of transistor 3. The channel width of transistor 305_1 can be larger than the channel width of transistor 305_2. And it can be small.

[0225] The channel width of the transistor 303 is larger than that of the transistor 302. This is because the load of the wiring 111 may be larger than the load of the node A. However, the channel width of the transistor 303 is not limited to this. It can be smaller than the channel width of the transistor 302 .

[0226] Note that some of the transistors included in the circuit 300 can be omitted. It is possible to omit either the transistor 305_1 or the transistor 305_2. In this case, the other gate of the transistor 305_1 and the transistor 305_2 receives a signal CK can be input. In FIG. 21B, the transistor 305_2 is omitted. However, the present invention is not limited to this, and various other transistors may be omitted. For example, both the transistor 305_1 and the transistor 305_2 can be Alternatively, the transistor 304_1 and the transistor 304_2 may be omitted. In this case, either the transistor 304_1 or the transistor 304_2 can be omitted. The signal CKB can be input to the other gate of the inverter 304_2. Both transistor 304_1 and transistor 304_2 can be omitted. Alternatively, the transistor 302 can be omitted. 3 can be omitted.

[0227] As shown in FIG. 5B of the first embodiment, the circuit 101 and the circuit 102 are connected to m transistors. 22A, the circuit 300 includes a transistor 304_1. Multiple transistors named ~304_m and transistors 305_1~305_m It is possible to have a plurality of transistors. corresponds to the transistor 304_1 or the transistor 304_2, and the transistor 305 _1 to 305_m correspond to the transistor 305_1 or the transistor 305_2.

[0228] 22(A), the circuit 300 in FIG. 21(B) also includes a transistor 3 Multiple transistors 04_1 to 304_m and transistors 305_1 to 305_ It is possible to have a number m of transistors.

[0229] As shown in FIG. 22B, the transistor 305_1 and the transistor 305_ The first terminal of the transistor 305_1 and the second terminal of the transistor 305_2 are connected to the wiring 112. The gates of 305_2 can be connected to nodes B1 and B2, respectively. However, the present invention is not limited to this, and the first transistor 305_1 and the second transistor 305_2 may be The terminals 114_1 and 114_2 can be connected to the wiring 114_1 and the wiring 114_2, respectively. Alternatively, the first terminals of the transistors 305_1 and 305_2 may be connected to the same The line 211_2 can be connected to the wiring 211_1. The first terminal of the transistor 305_1 and the first terminal of the transistor 305_2 are connected to the node B2 and the node B1, respectively. It is possible to connect with.

[0230] As in FIG. 22(B), in FIG. 21(B) and FIG. 22(A), the transistor The first terminal of the transistor 305_1 and the first terminal of the transistor 305_2 are connected to the wiring 112. The gates of the transistors 305_1 and 305_2 are connected to the nodes B1 and B2, respectively. It is possible to connect to board B2.

[0231] As shown in FIG. 23A, the first terminal of the transistor 301 is connected to the wiring 214. The wiring 214 is supplied with a voltage V2, and the wiring 214 is connected to a power supply However, the wiring 214 is not limited to this and may function as a wire. A signal that goes to H level at T1 can be input.

[0232] As in FIG. 23(A), in FIG. 21(B) and FIGS. 22(A) to 22(B), A first terminal of the transistor 301 can be connected to the wiring 214 .

[0233] As shown in FIG. 23(B), a P-channel transistor is used as the transistor. It is possible to use transistor 301p, transistor 302p, and transistor 3 03p, transistor 304_1p, transistor 304_2p, transistor 305_ 1p and transistor 305_2p are transistors 301 and 305_4p, respectively. 2, transistor 303, transistor 304_1, transistor 304_2, transistor The transistors 305_1 and 305_2 are P-channel types. When the polarity of the transistor is a P-channel type, as shown in FIG. 19(B), the wiring 112 , voltage V2 is supplied, and signals CK, CK_1, CK_2, CKB_1, and CKB_2, the potential Va, and the signal OUT are different from the timing chart of FIG. 8(B). Often it is inverted.

[0234] As in FIG. 23(B), FIGS. 21(B), 22(A)-(B), and 23(A) In this case, a P-channel transistor can be used as the transistor. .

[0235] (Fourth embodiment) In this embodiment, a specific example of the circuit 400 described in Embodiment 2 will be described. The circuit 400 can be referred to as a semiconductor device, a driver circuit, or a gate driver. The contents described in the first and second embodiments will not be described here. The contents described in the first to third embodiments can be freely combined with the contents described in this embodiment. can be done.

[0236] First, an example of a circuit 400 will be described with reference to FIG. Transistor 401_1, transistor 401_2, transistor 402_1, transistor 402_2, a capacitor 403_1, and a capacitor 403_2. Without being limited thereto, the circuit 400 may have various other features. 400 can omit either of these transistors or capacitive elements.

[0237] The transistor 401_1, the transistor 401_2, the transistor 402_1, and and transistor 402_2 preferably have the same polarity as transistor 201, However, the transistor 401_1 is not limited to this, and the transistor 401_2 is a The transistor 401_2, the transistor 402_1, and the transistor 402_2 are P-channel transistors. It can be of the channel type.

[0238] Next, an example of the connection relationship of the circuit 400 will be described. The first terminal of the transistor 401_1 is connected to the wiring 112, and the second terminal of the transistor 401_1 is connected to the node B1. The gate of the transistor 401_1 is connected to the node A. The first terminal of the transistor 401_2 is connected to the wiring 112, and the second terminal of the transistor 401_2 is connected to the wiring 112. is connected to node B2, and the gate of transistor 401_2 is connected to node A. The first terminal of the transistor 402_1 is connected to the wiring 112. A second terminal of the transistor 402_1 is connected to a node B1. A gate of the transistor 402_1 is connected to a wiring A first terminal of the transistor 402_2 is connected to the wiring 112. The second terminal of the transistor 402_2 is connected to the node B2. A gate of the capacitor 403_2 is connected to the wiring 211_1. The other electrode of the capacitor 403_1 is connected to the wiring 211_1, and the other electrode of the capacitor 403_1 is connected to the node B1. One electrode of the capacitor 403_2 is connected to the wiring 211_2. The other electrode of the second electrode is connected to node B2. However, this is not limited to this, and various other A connection configuration is possible.

[0239] Next, an example of the functions of each transistor and each capacitor will be described. The node 401_1 controls the conduction state between the wiring 112 and the node B1 in accordance with the potential of the node A. By controlling the voltage V1, the timing at which the voltage V1 is supplied to the node B1 can be controlled. The transistor 401_2 can function as a switch. By controlling the conduction state between the wiring 112 and the node B2 according to the potential, the voltage V1 The signal is supplied to node B2 via a function to control the timing, and functions as a switch. The transistor 402_1 is connected to the wiring 112 and the node 113 in response to the signal CK_2. By controlling the conduction state between the node B1 and the voltage V1, the timing at which the voltage V1 is supplied to the node B1 can be controlled. Transistor 4 has the function of controlling the switching of the transistor. 02_2 controls the conduction state between the wiring 112 and the node B2 in response to the signal CK_1. By this, it has a function of controlling the timing at which voltage V1 is supplied to node B2, and The capacitance element 403_1 can function as a latch in response to the signal CK_1. The capacitor 403_2 has a function of controlling the potential of the node B1. However, the present invention is not limited to this, and these transistors have the function of controlling the potential of the node B2. The transistors and capacitors can have a variety of other functions.

[0240] Next, the operation of the semiconductor device of FIG. 24A will be described with reference to the timing chart of FIG. 7B. This will be explained in light of the above.

[0241] First, in the period T1 of the kth frame, the potential of the node A is set to a high value (for example, (V2-Vt h301), so the transistors 401_1 and 401_2 are turned on. At this time, signal CK_1 becomes L level and signal CK_2 becomes L level, The transistor 402_1 and the transistor 402_2 are turned off. The node B1 is brought into electrical continuity, and the wiring 112 and the node B2 are brought into electrical continuity. Voltage V1 is supplied from wiring 112 to node B1, and voltage V1 is supplied from wiring 112 to node B2. are supplied to.

[0242] Next, in the period T2 of the kth frame, the potential of the node A becomes a high value (for example, (V2+Vt h201+α)), so the transistor 401_1 and the transistor 401_2 are on. At this time, the signal CK_1 becomes H level and the signal CK_2 becomes L level. Therefore, transistor 402_1 remains off and transistor 402_2 Therefore, the wiring 112 and the node B1 remain electrically connected, and the wiring 112 Then, the voltage V1 flows from the wiring 112 to the node B1. and a voltage V1 is supplied from a wiring 112 to a node B2.

[0243] On the other hand, during the period T2 of the k+1th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes H level, transistor 402_1 is turned on and transistor 4 The difference from the operation in the period T2 of the k-th frame is that 02_2 is turned off.

[0244] Next, in the period T3 of the kth frame, the potential of node A becomes V1, and the transistor At this time, the signal CK_1 is at the L level. Since the signal CK_2 remains at the L level, the transistor 402_1 is turned off. Therefore, the wiring 112 and the node B1 becomes non-conductive, and the wiring 112 and the node B2 become non-conductive. 403_1 receives a signal CK_1 at an L level (potential of the wiring 211_1) and a signal V1 (node ​​B The potential difference between the potential of the capacitor 403_1 and the potential of the capacitor 403_2 is maintained. The potential difference between CK_2 (the potential of the wiring 211_2) and V1 (the potential of the node B2) is maintained. do.

[0245] Next, in the period T4 of the kth frame, the potential of node A remains at V1, so the transistor The transistor 401_1 and the transistor 401_2 remain off. becomes H level, and the signal CK_2 remains L level, so that the transistor 402_1 Therefore, the wiring 112 and the node The wiring 112 and the node B2 are brought into a non-conductive state, and the wiring 112 and the node B2 are brought into a conductive state. Voltage V1 is supplied to node B2 from wiring 112. As a result, node B1 is in a floating state. Therefore, when the signal CK_1 changes from the L level to the H level, the capacitance of the capacitive element 403_1 The coupling causes the potential at node B1 to rise.

[0246] On the other hand, during the period T4 of the k+1th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 becomes H level, transistor 402_1 is turned on and transistor 4 The difference from the k-th frame period T4 is that 02_2 remains off. The wiring 112 and the node B1 are brought into a conductive state, and the wiring 112 and the node B2 are brought into a non-conductive state. Then, the voltage V1 is supplied to the node B1 from the wiring 112. As a result, the node B2 Therefore, when the signal CK_2 changes from the L level to the H level, the capacitance element 40 The potential of node B2 rises due to the capacitive coupling of 3_2.

[0247] Next, in the period T5 of the kth frame, the potential of node A remains at V1, so the transistor The transistor 401_1 and the transistor 401_2 remain off. becomes L level, and the signal CK_2 remains L level, so that the transistor 402_1 Therefore, the wiring 112 and the node As a result, the wiring 112 and the node B2 are brought into a non-conductive state. Therefore, when the signal CK_1 changes from H level to L level, the nodes B1 and B2 are in a floating state. When the potential of the node B1 reaches the level, the potential of the node B1 decreases due to the capacitive coupling of the capacitor 403_1. However, since the signal CK_1 remains at the L level, the potential of the node B1 remains at V1. .

[0248] On the other hand, during the period T5 of the k+1th frame, the signal CK_1 remains at the L level, and the signal Since CK_2 is at the L level, the potential of the node B2 is lowered by the capacitive coupling of the capacitor 403_2. The difference from the k-th frame period T5 is that the potential at node B1 decreases as follows: The difference from the k-th frame period T5 is that it remains V1.

[0249] As described above, the semiconductor device of this embodiment is capable of detecting the operation in the kth frame and the operation in the k+1th frame. By repeating this operation, the time that the transistor is on is shortened. Therefore, the deterioration of the transistor characteristics can be suppressed. A shift register, a gate driver, a display device, or the like includes the semiconductor device of this embodiment mode. By doing so, the life of these components can be extended.

[0250] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors may be set to N-channel type or P-channel type. Therefore, compared to CMOS circuits, the number of processes can be reduced. It is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. If all transistors are N-channel, including the semiconductor layer of the transistor, Examples of the semiconductor include non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, and oxide semiconductors. However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of this embodiment is designed to suppress the deterioration of the transistor. It is possible.

[0251] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0252] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are are preferably approximately equal to the channel width of the transistor 402_1. The channel width of the transistor 402_1 is preferably approximately equal to that of the transistor 402_2. The capacitance value of the capacitance element 403_1 or the area where one electrode overlaps the other electrode and the capacitance element 4 The capacitance value of O3_2 or the area where one electrode overlaps the other electrode is approximately equal. It is preferable that the transistor 401_1 and the transistor 401_2 have the same The transistor 402_1 and the transistor 402_2 have the same function. This is because the capacitor 403_1 and the capacitor 403_2 have the same function.

[0253] The channel width of the transistor 401_1 is larger than the channel width of the transistor 402_1. Alternatively, the channel width of the transistor 401_2 is preferably larger than that of the transistor 401_1. It is preferable that the channel width of the first sigma signal is larger than that of the first sigma signal. However, it is not limited to this. The channel width of the transistor 401_1 is smaller than the channel width of the transistor 402_1. Alternatively, the channel width of the transistor 401_2 can be It is possible that the channel width is smaller than that of 402_2.

[0254] As shown in FIG. 24(B), the wiring 112 may be divided into a plurality of wirings 112G to 112J. It is possible to divide the transistor 401_1, the transistor 401_2, the transistor 401_3, the transistor 401_4, the transistor 401_5, the transistor 401_6, the transistor 401_7, the transistor 401_8, the transistor 401_9, the transistor 401_10, the transistor 401_11, the transistor 401_12, the transistor 401_13, the The first terminals of the transistors 402_1 and 402_2 are connected to the wiring 112G and the wiring 112G, respectively. The wiring 112H, the wiring 112I, and the wiring 112J are connected. Therefore, the voltage V1 can be supplied to the wirings 112G to 112J. It is possible, and the wirings 112G to 112J can function as power supply lines. However, the present invention is not limited to this, and signals can be input to the wirings 112G to 112J. In this case, the wirings 112G to 112J can function as signal lines. In other words, it is possible to supply different signals or different voltages to the wirings 112G to 112J. be.

[0255] As shown in FIG. 24C, the transistor 401_1 and the transistor 402_ The first terminal of the transistor 401 is connected to the wiring 211_2. A first terminal of the star 402_2 can be connected to the wiring 211_1. When the transistor is turned off, the first terminal of the transistor is connected to the A clock signal is input to the transistor. Therefore, a reverse bias can be applied to the transistor. Therefore, deterioration of the characteristics of the transistor can be suppressed. The first terminals of the transistors 401_1 and 402_1 are connected to the wiring 1. 14_2, and the first terminals of the transistors 401_2 and 402_2 The terminal can be connected to the wiring 114_1. In this case, the reverse bias Since the voltage is applied to the transistor, deterioration of the transistor characteristics can be suppressed. The first terminals of the transistor 401_1 and the transistor 401_2 are connected to the wiring 112. It is possible to continue.

[0256] As shown in FIG. 25A, the transistor 402_1 and the transistor 402_ 2 can be omitted.

[0257] 25(A), the transistors 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 42 1 and the transistor 402_2 can be omitted.

[0258] As shown in FIG. 25(B), a MOS capacitor can be used as the capacitance element. The transistor 403a_1 and the transistor 403a_2 are N-channel transistors. In many cases, the first terminal of the transistor 403a_1 and the second terminal of the transistor 403a_2 function as a MOS capacitor. The second terminal of the transistor 403a_1 is connected to the node B1, and the gate of the transistor 403a_1 is connected to the wiring 211. The first and second terminals of the transistor 403a_2 are connected to the node B The gate of the transistor 403a_2 is connected to the wiring 211_2. By doing so, the transistor 403a_1 and the transistor 403a_2 are charged. This makes it easier to form a channel region, allowing the capacitance value to be increased.

[0259] As in FIG. 25(B), in FIGS. 24(B) to 24(C) and FIG. 25(A), A MOS capacitor can be used as the capacitance element.

[0260] As shown in FIG. 5B of the first embodiment, the circuit 101 and the circuit 102 are connected to m transistors. In the case where the semiconductor device has a transistor 401_1, as shown in FIG. a plurality of transistors 402_1 to 402_m; The semiconductor device has a plurality of transistors and a plurality of capacitors 403_1 to 403_m. However, the present invention is not limited to this, and the transistors 402_1 to 402_m may be It can be omitted.

[0261] As in FIG. 25(C), in FIGS. 24(B) to 24(C) and 25(A) to 25(B), However, the semiconductor device includes a plurality of transistors 401_1 to 401_m, A plurality of transistors 402_1 to 402_m and a capacitance element 403_ It is possible to have a number of capacitive elements ranging from 1 to 403 m.

[0262] As shown in FIG. 25(D), a P-channel transistor is used as the transistor. The transistor 401_1p, the transistor 401_2p, the transistor The transistor 402_1p and the transistor 402_2p are , the transistor 401_2, the transistor 402_1, and the transistor 402_2. In the case where the polarity of the transistor is P-channel, as shown in FIG. As shown in (B), a voltage V2 is supplied to the wiring 112, and signals CK, CK_1, The signals CK_2, CKB_1, CKB_2, the potential Va, and the signal OUT are shown in FIG. In many cases, the timing is reversed compared to the timing chart in B).

[0263] As in FIG. 25(D), in FIGS. 24(B) to 24(C) and 25(A) to 25(C), However, it is possible to use a P-channel transistor as the transistor.

[0264] (Embodiment 5) In this embodiment, an example of a shift register will be described. The system can include the semiconductor device according to the first to third embodiments. The soft resistor can be referred to as a semiconductor device or a gate driver. The contents described in the first to fourth embodiments will not be described here. The contents described in the fourth embodiment can be freely combined with the contents described in this embodiment. do.

[0265] First, an example of a shift register will be described with reference to FIG. Multiple flip-flops named 501_1 to 501_N (N is a natural number) It has.

[0266] The flip-flops 501_1 to 501_N are the same as those in the first to fourth embodiments, respectively. 26 corresponds to the semiconductor device described in the section 1. In the example of FIG. 1_N, the case where the semiconductor device of FIG. 7(A) is used is shown. The flip-flops 501_1 to 501_N are not limited to those of the first to fifth embodiments. The semiconductor device or circuit described in the fourth embodiment or various other semiconductor devices or circuits It is possible to use the path.

[0267] Next, the connection relationship of the shift register will be described. ~511_N, wiring 512, wiring 512_1, wiring 512_2, wiring 513, wiring 513 _1, wiring 513, wiring 514, wiring 515, and wiring 516 are connected. In the flip-flop 501_i (i is any one of 1 to N), the wiring 111 and the wiring 21 1, wiring 211_1, wiring 211_2, wiring 114_1, wiring 114_2, wiring 112, The wiring 212 and the wiring 213 are respectively designated as wiring 511_i, wiring 512, wiring 512_1, Wiring 512_2, wiring 513_1, wiring 513_2, wiring 514, wiring 511_i-1, Here, the odd-numbered flip-flops and the even-numbered flip-flops are connected to the wiring 511_i+1. In the flip-flop, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 114_1, In many cases, the connection destination of the wiring 114_2 is different. For example, in the i-th stage (i is one of 1 to N), In the first flip-flop, the wiring 211, the wiring 211_1, the wiring 211_2, the wiring 1 14_1 and the wiring 114_2 are respectively connected to the wiring 512, the wiring 512_1, and the wiring 512_2. In this case, the flip-flop of the (i+1)th stage is connected to the wiring 513_1 and the wiring 513_2. In the flip-flop or the (i-1)th stage, the wiring 211, the wiring 211_ 1, the wiring 211_2, the wiring 114_1, and the wiring 114_2 are respectively the wiring 513, the wiring 513_1, wiring 513_2, wiring 512_1, and wiring 512_2 are connected.

[0268] In the flip-flop 501_1, the wiring 212 may be connected to the wiring 515. In the flip-flop 501_N, the wiring 213 is connected to the wiring 516. In many cases

[0269] Next, an example of a signal or voltage input to or output from each wiring will be described. For example, signals GOUT_1 to GOUT_N are output from the inputs 1 to 511_N, respectively. The signals GOUT_1 to GOUT_N are output from the flip-flops 501_1 to 501_N, respectively. The signals GOUT_1 to GOUT_N are output signals of the signals OU Corresponding to T, output signal, selection signal, transfer signal, start signal, reset signal, gate signal The wiring 512, the wiring 512_1, and the wiring 512_2 can function as a scanning signal. For example, the line 512_2 carries the signals GCK, GCK_1, and GCK_2, respectively. The signal GCK corresponds to the signal CK or the signal CKB, and is a clock signal. The signal GCK_1 can function as a signal CK_1 or a signal CKB. The signal GCK_1 corresponds to the signal GCK_2 and can function as a clock signal. CK_2 or signal CKB_2 and can function as a clock signal. For example, the wiring 513, the wiring 513_1, and the wiring 513_2 are connected to the signal GC KB, signal GCKB_1, and signal GCKB_2 are input. It corresponds to the signal CK or the signal CKB and can function as an inverted clock signal. The signal GCKB_1 corresponds to the signal CK_1 or the signal CKB_1, and is an inverted clock signal The signal GCKB_2 can function as the signal CK_2 or the signal CKB_3. The wiring 514 corresponds to the clock signal _2 and can function as an inverted clock signal. For example, a voltage V1 is supplied to the wiring 515. For example, a signal GSP The signal GSP corresponds to the signal SP and is a start signal or a vertical synchronization signal. The wiring 516 can function as a timing signal. For example, the signal GRE is input to the wiring 516. The signal GRE corresponds to the signal RE and functions as a reset signal. However, this is not limited to this, and various other signals and It is possible to input various voltages or various currents.

[0270] The wirings 511_1 to 511_N are used as signal lines, gate lines, scanning lines, or output signal lines. The wiring 512, the wiring 512_1, and the wiring 512_2 are capable of functioning as a signal line. The wiring 513 can function as a signal line or a clock signal line. The wiring 513_1 and the wiring 513_2 can function as a signal line or a clock signal line. The wiring 514 can function as a power supply line or a ground line. The wiring 516 can function as a signal line. However, this is not limited to this, and these wirings can be used with various other types of wirings. It is possible to function as such.

[0271] In addition, the wiring 512, the wiring 512_1, the wiring 512_2, the wiring 513, the wiring 513_1, the wiring The line 513_2, the wiring 514, the wiring 515, and the wiring 516 are connected to a circuit 520. The circuit 520 inputs a signal or a voltage to the shift register. By supplying the signal, the shift register can be controlled. It can function as a controller.

[0272] Note that the circuit 520 includes, for example, a circuit 521 and a circuit 522. The circuit 521 generates power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage. The circuit 52 has a function of supplying a power to the power supply circuit or a regulator. 2 is a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a It has the function of generating various signals such as video signals and functions as a timing generator. However, the present invention is not limited to this, and the circuit 520 may be implemented by the circuit 521 and the circuit 522. In addition to the circuit 22, various circuits or elements may be included. For example, the circuit 52 0 is an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, AD conversion circuit, operational amplifier, shift register, look-up table, coil, transistor The circuit may include a resistor, a capacitive element, a resistive element, and / or a frequency divider.

[0273] Next, the operation of the shift register in FIG. 26 will be explained with reference to the timing chart in FIG. 27. FIG. 27 is an example of a timing chart for explaining the operation of the shift register. 27 shows the signals GSP, GRE, GCK, GCK_1, and GC K_2, signal GCKB, signal GCKB_1, signal GCKB_2, signal GOUT_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal GOUT_N An example is shown below. The operation of the semiconductor device according to the first to fourth embodiments is the same as that of the first to fourth embodiments. , the explanation of which will be omitted.

[0274] The operation of the flip-flop 501_i will be described. First, when the signal GOUT_i-1 is H, Then, the flip-flop 501_i starts its operation in the period T1. Then, the signal GOUT_i becomes L level. Then, the signals GCK and GCKB are inverted. Then, the flip-flop 501_i starts its operation in the period T2, and the signal GOU T_i becomes H level. The signal GOUT_i is reset to the flip-flop 501_i-1. The signal is input to the flip-flop 501_i+1 as a start signal. Therefore, the flip-flop 501_i-1 starts its operation in the period T3. , the flip-flop 501_i+1 starts operation in the period T1. Then, the signal The GCK and GCKB signals are inverted again. Then, the flip-flop 501_i+1 The operation in the period T2 starts, and the signal GOUT_i+1 becomes H level. _i+1 is input to the flip-flop 501_i as a reset signal. , the flip-flop 501_i starts operating in the period T3, so that the signal GOUT_ After that, the signal GOUT_i-1 goes low until it goes high again. The flip-flop 501_i is inverted every time the signals GCK and GCKB are inverted during the period T4. The operation in period T1 and the operation in period T5 are repeated.

[0275] In addition, in the flip-flop 501_1, instead of the output signal of the previous stage flip-flop, The signal GSP is input from the circuit 520 via the wiring 515. When it becomes H level, the flip-flop 501_1 starts operation in the period T1.

[0276] In addition, in the flip-flop 501_N, instead of the output signal of the next stage flip-flop, The signal GRE is input from the circuit 520 through the wiring 516. When it becomes H level, the flip-flop 501_N starts operation in the period T3.

[0277] The operation of the shift register of this embodiment has been described above. By using the semiconductor device according to the first to fourth embodiments, It is possible to obtain the same advantages as the device.

[0278] It is possible to make the relationship between the signal GCK and the signal GCKB unbalanced. For example, As shown in the timing chart of 28(A), in the signals GCK and GCKB, It is possible to make the period when the signal is at H level shorter than the period when the signal is at L level. This allows the signals GOUT_1 to GOUT_N to be properly output even if they are delayed or distorted. Therefore, in this embodiment, a period in which these signals are simultaneously at H level can be prevented. When a shift register of this type is used in a display device, it is necessary to prevent multiple rows from being selected at the same time. However, the present invention is not limited to this, and the signal GCK and / or the signal GCKB may be used. In this case, the period during which the signal is at the H level can be longer than the period during which the signal is at the L level.

[0279] It is possible to input multiphase clock signals to the shift register. For example, see Figure 2. As shown in the timing chart of 8(B), a clock signal with M phases (M is a natural number) is used. In this case, in the signals GOUT_1 to GOUT_N, The period when the signal is at H level in one stage may overlap with the period when the signal is at H level in the previous or next stage. Therefore, when this embodiment is used in a display device, multiple rows can be selected at the same time. This allows the video signals to the pixels in other rows to be used as precharge voltages. It becomes possible to use it.

[0280] In FIG. 28(B), it is preferable that M≦8. More preferably, it is preferable that M≦6. It is more preferable that M≦4. When the register is used in a scanning line driving circuit of a display device, if M is too large, multiple This is because several kinds of video signals are written to the pixel. This is because the period during which the signal is input becomes longer, which may result in a decrease in display quality.

[0281] As in FIG. 28(B), the timing chart in FIG. 28(A) also includes a multi-phase clock. A lock signal can be used.

[0282] The wiring 516 can be shared with other wiring or can be omitted. 516 is the wiring 512, the wiring 512_1, the wiring 512_2, the wiring 513, the wiring 513_1 , the wiring 513_1, the wiring 513_2, the wiring 514, or the wiring 515. In this case, the wiring 516 is omitted, and in the flip-flop 501_N, the wiring 516 is 512, wiring 512_1, wiring 512_2, wiring 513, wiring 513_1, wiring 513_ 2, wiring 514, or wiring 515. 16 can be omitted. In this case, in the flip-flop 501_N, The transistor 302 and the transistor 303 can be omitted.

[0283] It is possible to add new wiring. For example, as a flip-flop, If a configuration requiring voltage V2 is used, such as in 3(A), a new wiring is added. It is possible to supply a voltage V2 to the wiring. However, the present invention is not limited to this, and various wirings may be newly added depending on the configuration of the flip-flop. It is possible to reduce the number of wirings and eliminate the need for wiring.

[0284] It is possible to divide the output signal as shown in Figure 29. In the example of Figure 29, The flip-flops 501_1 to 501_N are each made of the semiconductor device shown in FIG. 17(B). In the flip-flop 501_i, the wiring 111, the wiring 211, and the wiring 211 _1, wiring 211_2, wiring 114_1, wiring 114_2, wiring 112, wiring 212, wiring The line 213 and the wiring 212 are respectively connected to the wiring 511_i, the wiring 512, the wiring 512_1, and the wiring 212. Wire 512_2, wire 513_1, wire 513_2, wire 514, wire 517_i-1, wire The line 511_i+1 is connected to the wiring 517_i. Even if a load such as a pixel or gate line is connected to 1 to 511_N, the flip-flop of the next stage There is no distortion or delay in the transfer signal for driving the flop. This can reduce the influence of delay in the shift register. The line 212 can be connected to the line 511_i-1. , can be connected to the wiring 517_i+1.

[0285] (Embodiment 6) In this embodiment, an example of a display device will be described.

[0286] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, a circuit 5363_3, a circuit 5363_4, a circuit 5363_5, a circuit 5363_6, a circuit 5363_7, a circuit 5363_8, a circuit 5363_9, a circuit 5363_10, a circuit 5 2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. In the figure, a plurality of wirings 5371 are arranged extending from a circuit 5362, and a plurality of wirings 5372 are arranged in a circuit. The wiring 5363_1 and the wiring 5363_2 are arranged to extend from each other. The intersections of the line 5371 and the wirings 5372 each have a display element such as a liquid crystal element. Pixels 5367 corresponding to the pixel area are arranged in a matrix.

[0287] The circuit 5361 is connected to the circuit 5362, the circuit 5363_1, the circuit 5364, the circuit 5365, and the circuit 5366 in response to the video signal 5360. 363_2 and the circuit 5365, and has a function of supplying a signal, a voltage, a current, or the like to the controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a 362, a start signal for the signal line driver circuit (SSP), a clock signal for the signal line driver circuit ( SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (DA TA), and a latch signal (LAT). Then, a start signal for the scanning line driving circuit (G SP), a clock signal for the scanning line driving circuit (GCK), and an inverted clock for the scanning line driving circuit Alternatively, the circuit 5361 may supply a signal (GCKB) to the circuit 5365. The circuit is intended to provide a backlight control signal (BLC), but is not limited to this. 5361 also transmits various other signals, various voltages, or various currents to a circuit 5362, a circuit The signal can be supplied to a circuit 5363_1, a circuit 5363_2, and a circuit 5365.

[0288] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB) supplied from the circuit 5361. , DATA, LAT) to output video signals to multiple wirings 5371. The circuit 5363_1 and the circuit 536_2 can function as a signal line driver circuit. 3_2 runs in response to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. The circuit 5365 performs the following in response to the signal (BLC) supplied from the circuit 5361: By controlling the amount of power supplied to the lighting device 5366 or the time, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0289] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wirings 53 can function as lines, video signal lines, source lines, or the like. When a scanning signal is input to 72, the plurality of wirings 5372 are signal lines, scanning lines, or gate lines. It can function as a line, etc., but is not limited to this.

[0290] Note that the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2. In this case, the circuit 5363_1 outputs scan signals to the wirings 5372 and the circuit 5363 The timing of the scanning signals output from the _2 to the multiple wirings 5372 is approximately the same. Therefore, the loads driven by the circuits 5363_1 and 5363_2 are reduced. Therefore, the display device can be made larger. Alternatively, the circuits 5363_1 and 5363_2 may have high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be obtained. However, the present invention is not limited to this, and the circuit 5361 can be implemented by a circuit 5363_1 and a circuit 536 It is possible to supply separate signals to 3_2.

[0291] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

[0292] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0293] The pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 30(B), the display element can emit light, so that the circuit 5 365 and the lighting device 5366 can be omitted. In order to supply power, a plurality of wirings 5373 that can function as power supply lines are provided in the pixel portion 53 64. The circuit 5361 distributes a power supply voltage called voltage (ANO). The wiring 5373 is connected to each color element of the pixel. It can be connected to all pixels in common.

[0294] Note that in FIG. 30B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2. The circuit 5361 is a circuit for a scanning line driver circuit. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and scanning line driving The circuit 5363_1 is supplied with signals such as an inverted clock signal (GCKB1) for the operating circuit. The circuit 5361 outputs a start signal (GSP2) for the scanning line driving circuit, Clock signal (GCK2), inverted clock signal for scanning line driver circuit (GCKB2), etc. In this case, the circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings among the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, power consumption can be reduced. Alternatively, the area in which one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 30A, the circuit 5361 can be The same signal can be output to the circuit 5363_1 and the circuit 5363_2.

[0295] 30(B), the circuit 5361 in FIG. 30(A) is the same as the circuit 5363 in FIG. It is possible to provide separate signals to the circuit 5363_1 and the circuit 5363_2.

[0296] An example of the system block of the display device has been described above.

[0297] Next, an example of the configuration of the display device will be described with reference to FIGS. 31(A), (B), (C), (D), and ( Please refer to E) for further explanation.

[0298] In FIG. 31A, a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, a circuit 5363_1, and a circuit 5363_2 are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the board 5380 and the external components can be The number of connections can be reduced, which can improve reliability and yield. can.

[0299] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta Flexible PCB (Flexible Printed Circuit) Alternatively, the substrate may be , the pixel part 5364 is mounted on the same substrate 538 by the COG (Chip on Glass) method. It is possible to implement it in 0.

[0300] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is formed on a single crystal semiconductor. Therefore, it is possible to form a transistor using the substrate. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0301] A signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0302] In FIG. 31(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel portion 5364. The circuit 5362 is formed on a substrate different from that of the pixel portion 5364. The transistors make it possible to configure circuits formed on the substrate 5380. The semiconductor layer of the transistor may be made of a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, It is possible to use an organic semiconductor, an oxide semiconductor, or the like. This allows for larger size, a reduction in the number of steps, cost reduction, and an improvement in yield.

[0303] As shown in FIG. 31C, a part of the circuit 5362 (circuit 5362a) is connected to the pixel section 53 The remaining circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the pixel section 564. The circuit 5362a can be formed on a different substrate from the circuit 364. Circuits that can be configured using transistors (e.g., shift registers, selectors, The circuit 5362b has high mobility and characteristic variations. A circuit (e.g., a shift register) that is preferably constructed using transistors with low They often have a built-in amplifier (e.g., a phase shifter, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) By doing so, as in FIG. 31(B), a non-single layer can be used as the semiconductor layer of the transistor. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used. This makes it possible to further reduce the number of external parts.

[0304] In FIG. 31(D), a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from that of the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0305] As in FIG. 31(D), in FIGS. 31(A) to 31(C), the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0306] In FIG. 31(E), a part of the circuit 5361 (circuit 5361a) is on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. The circuit 5361a is formed by a transistor with low mobility. In some cases, the device has a circuit that can be switched (for example, a switch, a selector, a level shift circuit, etc.). The circuit 5361b uses transistors with high mobility and small variations. A circuit (for example, a shift register, a timing generator, an These often include a resistor, regulator, or analog buffer.

[0307] 31(A) to (D), the circuit 5361a and the pixel section 5364 are mounted on the same substrate. The circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0308] Here, the circuits 5363_1 and 5363_2 are the circuits according to the first to fifth embodiments. In this case, the semiconductor device or shift register of the circuit 5363 can be used. 1, the circuit 5363_2 and the pixel portion are formed on the same substrate, All transistors can be N-channel or P-channel. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all the transistors are N-channel type, As the semiconductor layer of a transistor, non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, Therefore, it is possible to increase the size of the display device and This can reduce costs and improve yields.

[0309] Alternatively, the semiconductor device or shift register according to the first to fifth embodiments may include a transistor. This allows the channel width of the capacitor to be reduced, thereby reducing the layout area. This allows the frame to be smaller, or the layout area to be reduced. This allows for higher resolution.

[0310] Alternatively, the semiconductor device or shift register according to the first to fifth embodiments may have a parasitic capacitance. Therefore, the power consumption can be reduced. Alternatively, the size of the external circuit or the external circuit can be reduced. The size of the display device can be reduced.

[0311] Note that the semiconductor may be a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. A transistor using a semiconductor layer such as a silicon dioxide film has characteristics such as an increase in threshold voltage or a decrease in mobility. However, in the semiconductor device or shifter according to the first to fifth embodiments, The resistive resistor can suppress the deterioration of transistor characteristics, thereby extending the life of the display device. It can be made longer.

[0312] As a part of the circuit 5362, the semiconductor device of the first to fifth embodiments or the shift For example, the circuit 5362a can be implemented by using a register similar to that in the first to third embodiments. The semiconductor device of the fourth aspect may have a shift register.

[0313] (Embodiment 7) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0314] An example of a signal line driver circuit will be described with reference to FIG. A plurality of circuits 602_1 to 602_N (N is a natural number), a circuit 600, and a circuit 6 01. Each of the circuits 602_1 to 602_N includes a transistor 603_ The transistor 603 has a plurality of transistors 1 to 603_k (k is a natural number). _1 to 603_k are assumed to be N-channel type, but are not limited to this. For example, the transistors 603_1 to 603_k can be P-channel type. , and it is possible to use a CMOS type switch.

[0315] The connection relationship of the signal line driver circuit will be described using the circuit 602_1 as an example. The first terminals of the transistors 603_1 to 603_k are connected to the wiring 605_1. The second terminals of the transistors 03_1 to 603_k are connected to the wirings S1 to Sk, respectively. The gates of the gate electrodes 603_1 to 603_k are connected to the wirings 604_1 to 604_k, respectively. For example, the first terminal of the transistor 603_1 is connected to the wiring 605_1. The second terminal of the transistor 603_1 is connected to the wiring S1. The port is connected to the wiring 604_1.

[0316] The circuit 600 transmits signals to circuits 602_1 to 602_k via wirings 604_1 to 604_k. N, and can function as a shift register, decoder, etc. This signal is often a digital signal and can function as a selection signal. The wirings 604_1 to 604_k can function as signal lines. be.

[0317] The circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and is a video signal generator. For example, the circuit 601 can function as a At the same time, a signal is supplied to the circuit 602_1 via the wiring 605_2. The signal is often an analog signal and functions as a video signal. The wirings 605_1 to 605_N can function as signal lines. It is possible to do this.

[0318] The circuits 602_1 to 602_N select the wiring to which the output signal of the circuit 601 is to be output. For example, the circuit 602 has a function of selecting a _1 indicates which of the wirings S1 to Sk the signal output from the circuit 601 to the wiring 605_1 is connected to. It has the function to select whether to output to

[0319] The transistors 603_1 to 603_k are connected to the wiring 6 in response to the output signal of the circuit 600. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0320] Next, the operation of the signal line driver circuit of FIG. 32(A) will be explained with reference to the timing chart of FIG. 32(B). 32B shows a signal 614_1 input to a wiring 604_1. , a signal 614_2 input to the wiring 604_2, a signal 614_k input to the wiring 604_k, _k, a signal 615_1 input to the wiring 605_1, and a signal 615_2 input to the wiring 605_2. An example of No. 615_2 is shown below.

[0321] One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is the period during which pixels belonging to a certain row are selected and a video signal is written to the pixel. This refers to the period during which it is possible to

[0322] One gate selection period is divided into periods T0, T1, and Tk. is a period for simultaneously applying a precharge voltage to pixels belonging to a selected row. The periods T1 to Tk can function as precharge periods. This is the period for writing video signals to pixels belonging to the selected row, and functions as a write period. It is possible to do this.

[0323] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 602_1 as an example.

[0324] First, in a period T0, the circuit 600 applies an H-level signal to the wirings 604_1 to 604_k. Then, the transistors 603_1 to 603_k are turned on, and the wiring 605 At this time, the circuit 601 is in a conductive state between the wiring 605_1 and the wirings S1 to Sk. Since the precharge voltage Vp is supplied to the transistor 6 The signals are output to the wirings S1 to Sk via the signals 03_1 to 603_k. The charge voltage Vp is written to the pixels belonging to the selected row, so that the The corresponding pixels are precharged.

[0325] Next, in the period T1, the circuit 600 outputs an H-level signal to the wiring 604_1. Then, the transistor 603_1 is turned on, and the wiring 605_1 and the wiring S1 are brought into a conductive state. Then, the wiring 605_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 601 outputs a signal Data (S1) to the wiring 605_1, the signal D The ata (S1) is output to the wiring S1 through the transistor 603_1. The signal Data(S1) is supplied to the pixels in the selected row among the pixels connected to the wiring S1. It is written in simple terms.

[0326] Next, in a period T2, the circuit 600 outputs an H-level signal to the wiring 604_2. Then, the transistor 603_2 is turned on, and the wiring 605_2 and the wiring S2 are brought into a conductive state. Then, the wiring 605_1 and the wiring S1 are brought into a non-conductive state, and the wiring 605_1 and The wirings S3 to Sk remain in a non-conductive state. At this time, the circuit 601 outputs the signal Data( S2) is output to the wiring 605_1, the signal Data (S2) is In this way, the signal Data (S1) is output to the wiring S2 via the data input terminal 603_2. Of the pixels connected to line S1, those belonging to the selected row are written.

[0327] After that, until the period Tk, the circuit 600 outputs a high-level signal to the wirings 604_1 to 604_k. Since the signals are output in sequence, the signals are output in the same manner as in the periods T1 and T2, from the period T3 to the period Tk. 00 outputs H-level signals to the wirings 604_3 to 604_k in order. The transistors 603_3 to 603_k are turned on in turn, so that the transistors 603_1 to 603_k are turned on in turn. Therefore, the signal output from the circuit 601 is transmitted to the wirings S1 to Sk in order. In this way, signals can be written in order to the pixels in the selected row. becomes.

[0328] An example of the signal line driver circuit has been described above. Since the circuit has a function as a connector, the number of signals or the number of wirings can be reduced. Alternatively, a voltage for precharging before writing a video signal to the pixel (period T0) is written to the pixel, the time required to write the video signal can be shortened. This allows for larger display devices and higher resolution display devices. It is possible to omit period T0 and not precharge the pixels.

[0329] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so it is preferable that k≦6. More preferably, k≦3. Further preferably, k=2. It's nice.

[0330] In particular, if the color components of a pixel are divided into n (n is a natural number), it is possible to set k=n. For example, if the color components of a pixel are divided into three components, red (R), green (G), and blue (B), , k=3. In this case, one gate selection period includes a period T0, a period T1, , period T2, and period T3. In periods T1, T2, and T3, It is possible to write video signals to red (R), green (G), and blue (B) pixels. However, the order of the periods T1, T2, and T3 is not limited to this, and can be set arbitrarily. It is possible to do this.

[0331] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, then k=n. In this case, one gate selection period is the period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible to do this.

[0332] In addition, since the driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are often low, The circuit 600 and the circuits 602_1 to 602_N may be formed on the same substrate as the pixel portion. In this way, it is possible to reduce the number of connections between the substrate on which the pixel section is formed and the external circuit. This allows for improved yield and reliability. As shown in 1(C), the scanning line driver circuit is also formed on the same substrate as the pixel section, This significantly reduces the number of connections to external circuits.

[0333] The circuit 600 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarities of all the transistors in the circuit 600 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. This can improve yield or reduce costs.

[0334] It should be noted that not only the circuit 600 but also all the transistors included in the circuits 602_1 to 602_N The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 602_1 to 602_N are formed on the same substrate as the pixel portion, the number of steps is This can reduce the number of transistors, improve the yield, or reduce the cost. By making the polarity of the transistor N-channel, the semiconductor layer of the transistor can be made non-single-crystal. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This is because the driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are This is because it is often low.

[0335] (Embodiment 8) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0336] 33A shows an example of a pixel. The pixel 3020 includes a transistor 3021, a liquid crystal element The first terminal of the transistor 3021 is connected to a first terminal of the transistor 3022 and a second terminal of the capacitor 3023. The second terminal of the transistor 3021 is connected to the wiring 3031, and the second terminal of the transistor 3021 is connected to the liquid crystal element 3022. one electrode of the transistor 3021 and one electrode of the capacitor 3023 are connected to the gate of the transistor 3021. The other electrode of the liquid crystal element 3022 is connected to an electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033 .

[0337] For example, a video signal can be input to the wiring 3031. For example, a scan signal, a selection signal, or a gate signal can be input to the input terminal 2. For example, a constant voltage can be supplied to the wiring 3033. For example, a constant voltage may be supplied to the 034. The precharge voltage is supplied to the wiring 3031, and the The writing time can be shortened. Alternatively, a signal is input to the wiring 3033. By doing so, it is possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to the electrode 3034, frame inversion driving can be realized. It is Noh.

[0338] The wiring 3031 can function as a signal line, a video signal line, or a source line. The wiring 3032 can function as a signal line, a scanning line, or a gate line. The wiring 3033 can function as a power supply line or a capacitor line. 4 can function as a common electrode or a counter electrode, but is not limited to this. If a voltage is supplied to the wiring 3031 and the wiring 3032, these wirings are power supply lines. Alternatively, when a signal is input to the wiring 3033, the wiring 3033 can function as a signal line.

[0339] The transistor 3021 controls electrical continuity between the wiring 3031 and one electrode of the liquid crystal element 3022. By controlling the timing of writing a video signal to the pixel, The capacitor element 3023 can function as a switch. The potential difference between the electrode and the wiring 3033 is maintained, and the voltage applied to the liquid crystal element 3022 is The capacitor has a function of keeping the capacitance constant, and functions as a storage capacitor. However, the invention is not limited to this.

[0340] FIG. 33(B) is a timing chart for explaining the operation of the pixel of FIG. 33(A). 33B shows an example of a signal 3042_j (j is a natural number), a signal 3042_j+1 , signal 3041_i (i is a natural number), signal 3041_i+1, and voltage 3042 are shown. FIG. 33(B) shows the k-th (k is a natural number) frame and the k+1-th frame. Note that the signals 3042_j, ​​3042_j+1, 3041_i, and 3041_i +1 and voltage 3042 are signals input to the wiring 3032 in the jth row, a signal input to the wiring 3032 in the i-th column, a signal input to the wiring 3031 in the i+1-th column, 3031 and 3032. The signal input to the wiring 3031 and the voltage supplied to the wiring 3032 are shown in FIG.

[0341] The operation of the pixel 3020 in the jth row and the ith column will be described. When this occurs, the transistor 3021 is turned on. Since the signal 3041_j is connected to one electrode of the transistor 3022, The voltage is input to one electrode of the liquid crystal element 3022 via a capacitor 3023. At this time, the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033 is maintained. Therefore, the liquid crystal element 302 remains in the H level until the signal 3042_j becomes H level again. The voltage applied to the liquid crystal element 3022 is constant. It expresses a gradation.

[0342] In FIG. 33(B), positive and negative signals are alternately arranged for each row selection period. This shows an example of a case where a signal is input to a line 3031. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A negative signal is a signal whose potential is higher than the reference value. (for example, the potential of the electrode 3034). The signal input to the wiring 3031 can have the same polarity during one frame period. do.

[0343] In addition, in FIG. 33(B), the polarity of the signal 3041_i and the polarity of the signal 3041_i+1 are different. However, the present invention is not limited to this example, and the polarity and The polarity of the signal 3041_i+1 can be the same.

[0344] 33B shows a period in which the signal 3042_j is at H level and a period in which the signal 3042_j is at H level. This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 33(C), there is a period in which the signal 3042_j is at H level and a period in which the signal 30 42_j+1 is at H level. In this case, the period when the wiring 303 It is preferable that signals of the same polarity are supplied to all the inputs during one frame. By using the signal 3041_j written to the pixel in the jth row, the pixel in the j+1th row is This allows the time required to write a video signal to the pixel to be shortened. Therefore, the display device can be made high-definition. Alternatively, the same wiring 3031 can be used in one frame period. Since a polarity signal is input, power consumption can be reduced.

[0345] It should be noted that the pixel configuration of FIG. 34(A) and the timing chart of FIG. 33(C) can be combined. In this way, dot inversion driving can be realized. The pixel 3020(i, j) is connected to the wiring 3031_i. j+1) is connected to the wiring 3031_i+1. In this way, the i-th row is connected to the wiring 3031_i and the wiring 3031_i+1 alternately. The pixels belonging to the eye are written with positive and negative polarity signals alternately, row by row. However, the present invention is not limited to this, and the dot inversion driving can be realized. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 3031_i and the wiring 3031 _i+1.

[0346] It should be noted that a sub-pixel structure can be used as the pixel configuration. 34(A) and 34(B) show the configuration when a pixel is divided into two sub-pixels. Figure 34(B) shows a subpixel structure called 1S+2G, and Figure 34(C) shows a subpixel structure called 2S+1 The subpixel structure shown is called G. The subpixel 3020A and the subpixel 3020B are The transistor 3021A corresponds to the pixel 3020. The transistor 3021A and the transistor 3021B correspond to the transistor The liquid crystal element 3022A and the liquid crystal element 3022B correspond to the liquid crystal element The capacitance element 3023A and the capacitance element 3023B correspond to the capacitance element 3023 The wiring 3031A and the wiring 3031B correspond to the wiring 3031. 32A and wiring 3032B correspond to wiring 3032.

[0347] Here, the pixel of this embodiment, the semiconductor device of the first to seventh embodiments, and the shift register By combining it with a display, a signal line driver circuit, or a For example, when a subpixel structure is used as a pixel, the display device can be driven This increases the number of signals required to operate the device. As a result, the number of connections between the substrate on which the pixel unit is formed and the external circuitry increases significantly. However, even if the number of gate lines increases, as shown in the sixth embodiment, Therefore, the scanning line driver circuit can be formed on the same substrate as the pixel portion. The number of connections between the substrate on which the pixel is formed and the external circuit is not significantly increased. Even if the number of source lines increases, the signal line driver of the sixth embodiment can be used. By using a driving circuit, the number of source lines can be reduced. The number of connections between the substrate on which the pixel is formed and the external circuit is not significantly increased. Pixels can be used.

[0348] Alternatively, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit is Therefore, the semiconductor device according to the first to fifth embodiments is provided on the capacitance line. The signals can be supplied using semiconductor devices or shift registers. The semiconductor device or shift register of the first to fifth embodiments is formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel section is formed and the external circuit can be significantly reduced. Therefore, a signal can be input to the capacitance line without increasing the capacitance.

[0349] Alternatively, when AC driving is used, the time required to write a video signal to a pixel becomes shorter. As a result, there may not be enough time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time required to write a video signal to the pixel is short. As a result, there may not be enough time to write the video signal to the pixel. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the seventh embodiment. In this case, a precharge voltage is applied to the pixel before writing a video signal to the pixel. , the video signal can be written to the pixel in a short time. As shown in (B), the period in which one row is selected can overlap with the period in which another row is selected. By this, it is possible to use a video signal of another row as a voltage for precharging. .

[0350] (Embodiment 9) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. Please refer to C) for explanation.

[0351] FIG. 35A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. , or a signal line driver circuit.

[0352] FIG. 35(B) shows an example of the cross section AB of FIG. 35(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5405; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0353] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0354] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in Figure 35(B), As shown in FIG. 5B, an insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node is Alternatively, the power consumption of the driver circuit 5392 can be reduced. This can be done.

[0355] As shown in FIG. 35C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0356] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0357] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and a semiconductor device or shift register according to any one of the first to fifth embodiments. For example, a semiconductor layer of a transistor may be formed of a non-single-crystal semiconductor or an amorphous semiconductor. When a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, the channel of the transistor However, as in this embodiment, the parasitic capacitance of the drive circuit is If the thickness can be reduced, the channel width of the transistor can be reduced. Since the outer area can be reduced, the frame of the display device can be made narrower. This allows the display device to have high definition.

[0358] (Embodiment 10) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0359] FIG. 36A shows an example of the structure of a top-gate transistor. This is an example of the structure of a bottom-gate transistor. 1 is an example of a structure of a transistor manufactured by

[0360] FIG. 36(A) shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, The insulating layer 5261 is formed on the insulating layer 5261, and includes a region 5262a, a region 5262b, a region 5262c, and a region A semiconductor layer 5262 having regions 5262d and 5262e, and a semiconductor layer 5262 having a thickness of 100 μm. The insulating layer 5263 is formed as shown in FIG. 5, and the insulating layer 5264 is formed on the semiconductor layer 5262 and the insulating layer 5263. a conductive layer 5264 formed over the insulating layer 5263 and the conductive layer 5264 and having an opening; an insulating layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265; a layer 5266, a conductive layer 5267 formed on the conductive layer 5266 and on the insulating layer 5265, and having an opening; An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the opening of the insulating layer 5267 5268, and an insulating layer having an opening formed on the insulating layer 5267 and the conductive layer 5268. The insulating layer 5269 is formed on the insulating layer 5269 and in the opening of the insulating layer 5269. 270 and a conductive layer 5271 formed on the insulating layer 5269 and on the light-emitting layer 5270. show.

[0361] FIG. 36B shows a substrate 5300, a conductive layer 5301 formed on the substrate 5300, An insulating layer 5302 formed to cover the conductive layer 5301, and a conductive layer 5301 and an insulating layer 5302 A semiconductor layer 5303a formed on the semiconductor layer 302 and a semiconductor layer 5303b formed on the semiconductor layer 5303a A conductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302 a layer 5304, and a conductive layer 5305 formed on the insulating layer 5302 and the conductive layer 5304, the conductive layer 5305 having an opening. An insulating layer 5305 and a conductive layer formed on the insulating layer 5305 and in the opening of the insulating layer 5305 5306, and a liquid crystal layer 5307 disposed on the insulating layer 5305 and on the conductive layer 5306. 5308 formed on the liquid crystal layer 5307.

[0362] FIG. 36C shows a semiconductor substrate 5352 having a region 5353 and a region 5355, and a semiconductor An insulating layer 5356 formed on the semiconductor substrate 5352 and a an insulating layer 5354 formed on the insulating layer 5356; a conductive layer 5357 formed on the insulating layer 5356; 4. An insulating layer 535 having an opening formed on the insulating layer 5356 and the conductive layer 5357. 8 and a conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358. In this way, transistors are formed in each of the regions 5350 and 5351.

[0363] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a bank. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0364] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, and a silicon substrate. (or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate, Substrate with steel foil, tungsten substrate, tungsten foil Examples of the glass substrate include a barium borosilicate glass substrate and a flexible substrate. Examples of flexible substrates include polyethylene terephthalate (PET) and aluminoborosilicate glass. Polyethylene naphthalate (PET), polyethylene naphthalate (PEN), polyether sulfonate Plastics such as polyethylene terephthalate (PES), or flexible synthetic resins such as acrylic. Other examples include laminated films (polypropylene, polyester, vinyl, polypropylene, etc.) vinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester, Polyamide, polyimide, inorganic vapor deposition film, paper, etc.

[0365] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. However, it is not limited to this, and a plate similar to the substrate 5260 can be used. The region 5353 can be formed by, for example, introducing impurities into the semiconductor substrate 5352. For example, if the semiconductor substrate 5352 is a p-type conductive region, If the region 5353 has n-type conductivity, it functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity. The region 5355 has, for example, a region where impurities are not introduced into the semiconductor substrate 5 352 and functions as a source region or a drain region. The conductive substrate 5352 may have an LDD region formed therein.

[0366] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon oxide (SiOxNy)(x>y), silicon nitride (SiNxOy)(x>y) The insulating layer 5261 has a two-layer structure. For example, a silicon nitride film is provided as the first insulating layer, and a silicon nitride film is provided as the second insulating layer. A silicon oxide film can be provided as an insulating film. The insulating layer 5261 is provided in a three-layer structure. For example, a silicon oxide film is provided as the first insulating film and a silicon dioxide film is provided as the second insulating film. It is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the third insulating film.

[0367] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) , single crystal semiconductor, compound semiconductor or oxide semiconductor (ZnO, InGaZnO, SiG e, GaAs, IZO, ITO, SnO, TiO, AlZnSnO(AZTO)), organic Examples include semiconductors and carbon nanotubes.

[0368] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, a small amount of impurity is added to the region 5262a. The impurity added to the region 5262a can be added to the region 5262b, 5262c, 5262d, or 5262e. The regions 5262b and 5262d are preferably lightly doped with impurities. This region functions as an LDD (Lightly Doped Drain) region. However, the area 5262b and the area 5262d can be omitted. The regions 5262c and 5262e are regions in which impurities are added to the semiconductor layer 5262 at high concentration. The region functions as a source region or a drain region.

[0369] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0370] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0371] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy)(x>y), silicon nitride oxide Films containing oxygen or nitrogen, such as silicon (SiNxOy) (x>y), or their laminated structures There are various types of structures.

[0372] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 Examples of the conductive film 9 include a single-layer conductive film and a laminated structure thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni) , platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), scandium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As) , Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O), Zirconium (Z r), cerium (Ce), or Examples of such compounds include compounds containing one or more elements selected from the above group. In the case of the above, an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide with silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminium Odim (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al -Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium Silver (Mg-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo- W), molybdenum-tantalum (Mo-Ta) alloy materials, and one or more selected from the above group or compounds of nitrogen with multiple elements (titanium nitride, tantalum nitride, molybdenum nitride, etc.) nitride film), or a compound of one or more elements selected from the above group with silicon (thin film). tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes, organic Nanotube materials include nanotubes, inorganic nanotubes, or metallic nanotubes. .

[0373] Silicon (Si) is doped with n-type impurities (such as phosphorus) or p-type impurities (such as boron). The silicon may contain impurities to improve electrical conductivity and / or It is possible for the material to behave like a normal conductor, so that wiring or electrodes It will be easier to use as:

[0374] Silicon can be found in single crystal, polycrystalline (polysilicon), microcrystalline (microcrystalline) Silicon with various crystallinity, such as amorphous silicon It is possible to use silicon that does not have crystallinity, such as single crystal silicon. By using crystalline silicon or polycrystalline silicon, wiring, electrodes, conductive layers, conductive films, The resistance of the silicon can be reduced. By using silicon, wiring and the like can be formed through simple processes.

[0375] When a semiconductor material such as silicon is used as the conductive layer, The material can be formed simultaneously with the semiconductor layer of the transistor.

[0376] Aluminum or silver has high conductivity and can reduce signal delay. Furthermore, aluminum or silver is easy to etch, making it easy to pattern and fine Fine processing can be performed.

[0377] Copper has high conductivity, which can reduce signal delay. When a laminated structure is used, it is preferable to use a laminated structure in order to improve adhesion.

[0378] Molybdenum or titanium is used in oxide semiconductors (ITO, IZO, etc.) or silicon It has the advantages of being less likely to cause defects even when in contact with the environment, being easy to etch, and having high heat resistance. Therefore, the conductive layer in contact with the oxide semiconductor or silicon is preferably Preferably, molybdenum or titanium is used.

[0379] Tungsten is desirable because it has advantages such as high heat resistance.

[0380] Neodymium is desirable because it has advantages such as high heat resistance. By using an alloy material of neodymium and aluminum, the aluminum does not form hillocks. However, it is not limited to this, and aluminum, tantalum, zirconia Aluminum can also be alloyed with aluminum, titanium, or cerium to In particular, alloy materials of aluminum and cerium are less likely to cause arcing. It can be significantly reduced.

[0381] In addition, ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotubes Since the tubes and the like have light-transmitting properties, these materials can be used for the pixel electrode, the counter electrode, or the common electrode. It can be used for light-transmitting parts such as electrodes. In particular, IZO is suitable for etching. IZO is desirable because it is easy to etch and process. When IZO is etched, no residue remains. Therefore, when IZO is used as the pixel electrode, To reduce the occurrence of defects (short circuits, alignment disturbances, etc.) in liquid crystal elements and light-emitting elements can be done.

[0382] The conductive layer may have a single layer structure or a multilayer structure. The single-layer structure simplifies the manufacturing process for wiring, electrodes, conductive layers, conductive films, terminals, etc. This allows for the simplification of the manufacturing process, shortening the number of process days and reducing costs. By using a layered structure, the advantages of each material are utilized while reducing their disadvantages. For example, low resistance materials (aluminum, By including a material such as silicon in the multilayer structure, the resistance of the wiring can be reduced. For example, by sandwiching a low heat-resistant material between high heat-resistant materials in a laminated structure, This makes it possible to improve the heat resistance of wiring, electrodes, etc. while taking advantage of the advantages of heat-resistant materials. An example of such a laminated structure is a layer containing aluminum, a layer containing molybdenum, titanium, It is desirable to have a laminated structure in which the material is sandwiched between layers containing neodymium or the like.

[0383] In addition, when wiring, electrodes, etc. come into direct contact with each other, they may have a negative effect on each other. In this case, one wiring or electrode penetrates into the other wiring or electrode, changing the properties. As another example, if a high resistance part is formed, Or, problems may occur during production, making it impossible to produce normally. In this case, a material that changes its properties when it reacts with other materials is replaced with a material that does not react easily to those other materials. For example, ITO and aluminum can be sandwiched or covered by When connecting, neodymium alloy, titanium, molybdenum are used between ITO and aluminum. For example, when connecting silicon and aluminum, Neodymium alloy, titanium, and molybdenum can be sandwiched between silicon and aluminum. These materials are used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It can also be used for

[0384] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 An example of the insulating film 8 is a single-layer insulating film or a laminated structure of these insulating films. Examples include silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride ( Oxygen-containing silicon nitride (SiOxNy) (x>y), silicon oxynitride (SiNxOy) (x>y) Nitrogen-containing films, carbon-containing films such as DLC (diamond-like carbon), or siloxane San resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene Examples of the material include organic materials such as acrylic and the like.

[0385] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, or a layer in which a plurality of materials among these materials are mixed, or These include laminated structures.

[0386] Examples of the liquid crystal layer 5307 include nematic liquid crystal, cholesteric liquid crystal, and smectic liquid crystal. Crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals, high Molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side Examples include chain-type polymer liquid crystals, plasma-addressed liquid crystals (PALC), and banana-shaped liquid crystals. The LCD driving method is TN (Twisted Nematic) mode. , STN (Super Twisted Nematic) mode, IPS (In-Pl Fringe-Switching mode, FFS (Fringe Field Switching) hing mode, MVA (Multi-domain Vertical Alignment ment) mode, PVA (Patterned Vertical Alignment) t) mode, ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optically Compensated Birefringence) Electrically Controlled Birefring (ECB) ence) mode, FLC (Ferroelectric Liquid Crystal l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, PDLC (Polymer Dispersed Liquid Crystal Galaxy mode, guest host mode, Blue Phase mode, etc. There are some.

[0387] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0388] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0389] In the cross-sectional structure of FIG. 36(A), the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 is omitted, and the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 36(B) are replaced with the insulating layer 526 7 and conductive layer 5268.

[0390] In the cross-sectional structure of FIG. 36(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted. 36(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed on the insulating layer 530. 5 and on the conductive layer 5306.

[0391] In the cross-sectional structure of FIG. 36(C), the insulating layer 5358 and the conductive layer 5359 are 36(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 36(B) may be formed as an insulating layer. It can be formed on 5358 and on conductive layer 5359 .

[0392] The transistor of this embodiment can be applied to the first to ninth embodiments. In particular, in FIG. 36(B), the semiconductor layer is made of a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, or the like. When a crystalline semiconductor, an organic semiconductor, or an oxide semiconductor is used, the transistor deteriorates. However, the semiconductor devices and shift registers according to the first to ninth embodiments may In addition, in a display device, the present invention is useful because it can suppress deterioration of a transistor.

[0393] (Embodiment 11) In this embodiment, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layer of the shift register described in the fifth embodiment is The contents explained in this embodiment are the same as those in the fifth embodiment. In addition to the shift registers described above, the semiconductor devices and shift registers according to the first to tenth embodiments can also be used. The present invention can be applied to a display device or a transistor. It should be noted that this is just an example and is not limiting.

[0394] The layout diagram of this embodiment will be described with reference to FIGS. 37 and 38. FIG. 38 shows an example of a layout diagram of a part of a shift register. 7(A) shows a layout diagram of the semiconductor device.

[0395] The transistors, wirings, and the like shown in FIGS. 37 and 38 are formed by a conductive layer 701, a semiconductor layer 70 2, a conductive layer 703, a conductive layer 704, and a contact hole 705. However, the present invention is not limited to this, and other conductive layers, insulating films, or other contact holes may be newly formed. For example, a contact for connecting the conductive layer 701 and the conductive layer 703 can be formed. It is possible to add new holes.

[0396] The conductive layer 701 can include a portion that functions as a gate electrode or a wiring. The conductor layer 702 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 703 can include a portion that functions as a wiring, a source, or a drain. The conductive layer 704 may include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 705 has the function of connecting the conductive layer 701 and the conductive layer 704. Alternatively, the conductive layer 703 and the conductive layer 704 are connected to each other.

[0397] In the example of Fig. 37, the wiring has an opening 711. In this way, the wiring has an opening. By doing so, it is possible to reduce the parasitic capacitance. However, this is not limited to this, and wiring may have openings. It is possible that this has not been done.

[0398] In the example of FIG. 37, openings are provided at the intersections of the wirings and in the surrounding areas. This reduces the cross capacitance of the wiring, thus reducing noise. Alternatively, it is possible to reduce signal delay or distortion.

[0399] In the example of FIG. 37, a conductive layer 704 is formed on a part of a conductive layer 703 of the wiring. The conductive layer 704 is connected to the conductive layer 703 through a contact hole 705. In this way, the wiring resistance can be reduced, resulting in a reduction in voltage drop, or However, this is not limited to this, and the conductive The layer 704 and the contact hole 705 can be omitted.

[0400] In the example of FIG. 37, the width of the wiring 512 is the width of the wiring 512_1 and the width of the wiring 512_2. It is preferable that the width of the wiring 512 is larger than that of the wiring 512 of FIG. 2 because a large current flows in the wiring 512. For the same reason, the width of the wiring 513 is set to be equal to the width of the wiring 513_1 and It is preferable that the width of the wiring 513_1 is larger than that of the wiring 513_2, but it is not limited to this.

[0401] In the example of FIG. 38, transistor 101_1, transistor 101_2, transistor 1 02_1, transistor 102_2, and / or transistor 201, The area where the conductive layer 701 and the conductive layer 703 of the terminal overlap is It is preferable that the area is smaller than the area where the transistor overlaps with the layer 703. This can reduce noise from the gate of the gate electrode 201 or the wiring 111. This can prevent the concentration of electric fields at the terminals of the transistor, which can prevent the deterioration of the transistor or This can prevent damage to the star.

[0402] Note that a semiconductor layer 702 is formed in a portion where the conductive layer 701 and the conductive layer 703 overlap each other. By doing so, the parasitic capacitance between the conductive layer 701 and the conductive layer 703 can be reduced. For the same reason, the conductive layer A semiconductor layer 702 or a conductive layer 703 is formed in the area where the conductive layer 704 overlaps with the semiconductor layer 701. It is possible.

[0403] The conductive layer 704 is formed on a part of the conductive layer 701. It is possible to connect with the conductive layer 704 through the hole 705. This can reduce the wiring resistance. and a conductive layer 704 are formed, and the conductive layer 701 is connected to the corresponding substrate through a contact hole 705. The conductive layer 703 is connected to the conductive layer 704 through another contact hole 705. It is possible to connect with the conductive layer 704. By doing so, the wiring resistance can be further reduced. It can be further reduced.

[0404] The conductive layer 704 is formed on a part of the conductive layer 703. It is possible to connect with the conductive layer 704 through the hole 705. This can reduce the wiring resistance.

[0405] Note that the conductive layer 701 or the conductive layer 703 is formed under a part of the conductive layer 704, and the conductive layer 704 is connected to the conductive layer 701 or the conductive layer 703 through a contact hole 705. By doing so, the wiring resistance can be reduced. .

[0406] As already mentioned, the parasitic capacitance between the gate and the first terminal of the transistor 201 Therefore, the parasitic capacitance between the gate and the second terminal of the transistor 201 can be increased. As shown in FIG. 38, the first electrode of the transistor 201 can be The width of the conductive layer 703 that can function as the second electrode of the transistor 201 is shown as width 731. The width of the conductive layer 703 that can be used is shown as width 732. This allows the gate of transistor 201 and The parasitic capacitance between the gate and the second terminal of the transistor 201 is larger than the parasitic capacitance between the gate and the first terminal of the transistor 201. It is possible to increase the parasitic capacitance, but this is not a limitation.

[0407] (Embodiment 12) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process for the oxide semiconductor layer will be described. InMO3(ZnO) m It is possible to use layers expressed as (m>0). M is one or more metal elements selected from Ga, Fe, Ni, Mn and Co. There are metal elements. For example, M can be Ga, or Ga and Ni or G In some cases, the above metal elements other than Ga, such as Ga and Fe, may be contained. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. The thin film contains In-Ga elements or oxides of the transition metals. It can be shown as a Zn-O-based non-single crystal film. It is possible to use a mobile ion, typically sodium, in the oxide semiconductor layer. The concentration of 18 / cm 3 Below, and further 1×10 18 / cm 3 If it is below, This is preferable because it can prevent the electrical characteristics of the transistor from changing. The semiconductor layer is not limited to the above, and oxide semiconductors of various other materials can also be used. Alternatively, the semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline (microcrystalline) semiconductor, or the like. (stal or nanocrystalline) semiconductors, amorphous semiconductors, or various non- A single crystal semiconductor or the like can be used.

[0408] Referring to FIGS. 46A to 46C, an example of a manufacturing process of a transistor and a capacitor will be described. 46A to 46C show a transistor 5441 and a capacitor 5442. This is an example of a manufacturing process. The transistor 5441 is an example of an inverted staggered thin film transistor. a wiring is provided on the oxide semiconductor layer via a source electrode or a drain electrode; This is an example of a transistor.

[0409] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0410] Next, an insulating layer 5423 is formed on the entire surface by plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421 The insulating layer 5423 is formed to cover the insulating layer 5424 and the conductive layer 5422. It is often between 100 and 250 nm.

[0411] When a silicon oxide layer is used as the insulating layer 5423, an organic silane gas is used. A silicon oxide layer can be formed by the CVD method. is ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TM S: Chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMD S), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane ( Silicon-containing compounds such as SiH(N(CH3)2)3) or yttrium oxide (Y2 O3) can be used.

[0412] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After forming the contact hole 5424, the contact hole 5424 can be formed. The cross section of this corresponds to FIG. 46(A).

[0413] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and then a n + Forming a layer The thickness of the oxide semiconductor layer is preferably 5 nm to 200 nm. many.

[0414] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. It is preferable to perform reverse sputtering to generate plasma. This removes dust adhering to the surface of the insulating layer 5423 and the bottom of the contact hole 5424. Reverse sputtering is a method of removing aluminum without applying voltage to the target side. In a fluorine atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma on the substrate surface. However, the present invention is not limited to this, and the atmosphere may be changed to nitrogen or helium instead of argon. Alternatively, oxygen, hydrogen, N2O, etc. can be used in an argon atmosphere. Alternatively, the process can be carried out in an argon atmosphere containing Cl2, CF4, etc. It is possible to perform the reverse sputtering in an atmosphere containing the insulating layer 54. The surface of 23 is preferably removed by about 2 to 10 nm. By forming the oxide semiconductor layer without exposing it to heat, the boundary between the gate insulating layer and the semiconductor layer can be This is useful in that it does not allow dirt or moisture to adhere to the surface.

[0415] Next, the oxide semiconductor layer is selectively etched using a third photomask. Then, the resist mask is removed.

[0416] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. It is possible to include

[0417] If a heat treatment (for example, at 200°C to 600°C) is to be carried out after this, the material must be able to withstand this heat treatment. It is preferable that the second conductive layer has heat resistance. Therefore, the second conductive layer is made of Al and Heat-resistant conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce, etc.) elements, alloys combining these elements, or nitrides containing these elements However, it is not limited to this, and the second conductive layer By forming the second conductive layer into a laminated structure, it is possible to provide the second conductive layer with heat resistance. A heat-resistant conductive material such as Ti or Mo can be provided above and below the Al.

[0418] Before forming the second conductive layer by sputtering, argon gas was introduced to Reverse sputtering to generate a smear is performed, and the surface of the insulating layer 5423 and the surface of the oxide semiconductor layer are It is preferable to remove dust adhering to the surface and the bottom surface of the contact hole 5424. However, the present invention is not limited to this, and nitrogen, helium, etc. may be used instead of the argon atmosphere. Alternatively, the process can be carried out in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. Alternatively, it can be performed in an argon atmosphere with Cl2, CF4, etc. added. It is possible.

[0419] When etching the second conductive layer, a part of the oxide semiconductor layer is also etched. By this etching, an oxide semiconductor layer 5425 overlapping with the conductive layer 5421 is formed. the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed or the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed The oxide semiconductor layer 5425 is often thinned by being removed. Therefore, the oxide semiconductor layer may not be etched. Layer on + When a layer is formed, the oxide semiconductor layer is often etched. After this etching, the resist mask is removed. The cross section at this stage corresponds to FIG. 46(B). do.

[0420] Here, if reverse sputtering is performed before forming the second conductive layer by sputtering, The exposed portion of the insulating layer 5423 may be removed, preferably by about 2 to 10 nm. A recess may be formed in the edge layer 5423. Alternatively, the second conductive layer may be etched, After forming the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431, reverse sputtering is performed. As a result, as shown in FIG. 46(B), a conductive layer 5429, a conductive layer 5430, and The end of the conductive layer 5431 may be curved.

[0421] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal layer. The heat treatment (light annealing) here releases the distortion that inhibits carrier movement. The timing of this heat treatment is not limited, and the oxide semiconductor This can be done at various times after the body is formed.

[0422] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 has a single-layer structure. For example, the insulating layer 5432 may be an organic thin film. When an insulating layer is used, a composition that is a material for the organic insulating layer is applied, and the applied composition is heated under an air atmosphere or nitrogen. Heat treatment is carried out at 200°C to 600°C in an atmosphere to form an organic insulating layer. By forming an organic insulating layer in contact with the oxide semiconductor layer, a thin film with high reliability in electrical properties can be obtained. A thin film transistor can be manufactured. Note that an organic insulating layer is used as the insulating layer 5432. In this case, a silicon nitride film or a silicon oxide film can be provided under the organic insulating layer.

[0423] In addition, in FIG. 46(C), a mode in which the insulating layer 5432 is formed using a non-photosensitive resin is shown. For illustration, in the cross section of the region where the contact hole is to be formed, the end of the insulating layer 5432 is However, when the insulating layer 5432 is formed using a photosensitive resin, the contact In the cross section of the region where the cut hole is formed, the end of the insulating layer 5432 can be curved. As a result, the coverage of the third conductive layer or pixel electrode to be formed later is improved.

[0424] Instead of applying the composition, it may be applied by dipping, spraying, or ink depending on the material. Jet method, printing method, doctor knife, roll coater, curtain coater, knife coater It is possible to use a meter or the like.

[0425] Note that the composition of the material for the organic insulating layer was not subjected to heat treatment after the oxide semiconductor layer was formed. The heat treatment can also serve as heat treatment for the oxide semiconductor layer.

[0426] The insulating layer 5432 is formed to a thickness of 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible to do this.

[0427] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross section of the structure up to this stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. In particular, the conductive layer 5434 can function as a transparent electrode or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, it can function as an electrode of the capacitor 5442. However, it is not limited to this, and any other suitable material may be used that has the function of connecting the first conductive layer and the second conductive layer. For example, by connecting the conductive layer 5433 and the conductive layer 5434, The conductive layer 5422 and the conductive layer 5430 are connected to a third conductive layer (conductive layer 5433 and conductive layer 5434). ) can be connected.

[0428] Note that the capacitor 5442 is formed by the conductive layer 5422 and the conductive layer 5434. Since the structure is such that 1 is sandwiched, the capacitance value of the capacitor 5442 can be increased. However, the present invention is not limited to this, and one of the conductive layer 5422 and the conductive layer 5434 may be omitted. It is Noh.

[0429] After removing the resist mask by wet etching, the wafer is etched in air or nitrogen atmosphere. Heat treatment can be carried out at 200°C to 600°C in air.

[0430] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0431] As shown in FIG. 46D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. The insulating layer 5435 can be used to prevent oxidation when the second conductive layer is patterned. It has the function of preventing the nitride semiconductor layer from being eroded and functions as a channel stop film. Therefore, the thickness of the oxide semiconductor layer can be reduced, and the driving voltage of the transistor can be reduced. Reduction of the on-off current, improvement of the on-off ratio of the drain current, improvement of the S value, etc. Note that the insulating layer 5435 can be formed by successively forming an oxide semiconductor layer and an insulating layer over the entire surface. Then, a resist mask is formed by a photolithography process using a photomask. The insulating layer can be selectively patterned using a mask. After that, a second conductive layer is formed on the entire surface, and an oxide semiconductor layer is patterned simultaneously with the second conductive layer. That is, the oxide semiconductor layer and the second conductive layer are patterned using the same mask (reticle). In this case, an oxide semiconductor layer must be formed under the second conductive layer. In this way, the insulating layer 5435 is formed without increasing the number of steps. In such a manufacturing process, an oxide semiconductor layer is formed under the second conductive layer. However, the present invention is not limited to this, and the oxide semiconductor layer may be patterned. After that, an insulating layer is formed on the entire surface and patterned to form an insulating layer 54. 35 can be formed.

[0432] In FIG. 46D, the capacitor 5442 includes a conductive layer 5422 and a conductive layer 5431. The insulating layer 5423 and the oxide semiconductor layer 5436 are sandwiched between the insulating layer 5423 and the oxide semiconductor layer 5436. The oxide semiconductor layer 5436 can be omitted. 5431 is connected via a conductive layer 5437 formed by patterning the third conductive layer. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, the transistor 5441 functions as a switching transistor and The element 5442 can function as a storage capacitor. The conductive layer 5422, the conductive layer 5429, and the conductive layer 5437 are gate lines, capacitance lines, and source lines, respectively. , can function as a pixel electrode. However, it is not limited to this. 46(C) similarly to FIG. 6(D), the conductive layer 5430 and the conductive layer 5431 are connected to the third The connection can be made through a conductive layer.

[0433] As shown in FIG. 46(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. By doing so, the second conductive layer can be patterned. When the oxide semiconductor layer is removed, the oxide semiconductor layer is not formed. Therefore, the thickness of the oxide semiconductor layer can be reduced, and the driving Reduction of dynamic voltage, reduction of off-state current, improvement of on / off ratio of drain current, improvement of S value, etc. Note that the oxide semiconductor layer 5425 is formed by patterning the second conductive layer. After that, an oxide semiconductor layer is formed on the entire surface, and then photolithography is performed using a photomask. The oxide semiconductor layer is selectively patterned using a resist mask formed by a photolithography process. It can be formed by

[0434] In FIG. 46(E), the capacitor element is formed by patterning the conductive layer 5422 and the third conductive layer. The insulating layer 5423 and the insulating layer 5432 are sandwiched between the insulating layer 5423 and the conductive layer 5439 formed by the insulating layer 5423 and the conductive layer 5439. The conductive layer 5422 and the conductive layer 5430 are formed by patterning the third conductive layer. The conductive layer 5439 is connected to the first conductive layer 5438 formed by the first conductive layer 5439. 46(E) is connected to the conductive layer 5440 formed by patterning the conductive layer 5440. 46(C) and (D), the conductive layer 5430 and the conductive layer 5422 are , can be connected via conductive layer 5438.

[0435] The thickness of the oxide semiconductor layer (or channel layer) is determined by the thickness of the depletion layer when the transistor is off. By making the thickness thinner than 1000 nm, it is possible to create a fully depleted state. In order to achieve this, the thickness of the oxide semiconductor layer is set to 2 It is preferably 0 nm or less, more preferably 10 nm or less, and even more preferably is preferably 6 nm or less.

[0436] In addition, the reduction of the transistor operating voltage, the reduction of the off-current, and the improvement of the on-off ratio of the drain current are also important. In order to improve the S value, the thickness of the oxide semiconductor layer is set to be equal to the thickness of the layers constituting the transistor. For example, the oxide semiconductor layer is preferably thinner than the insulating layer 5423. The thickness of the oxide semiconductor layer is preferably thinner than that of the insulating layer 5423. It is preferably 1 / 2 or less, and more preferably 1 / 5 or less. More preferably, it is 1 / 10 or less. However, it is not limited to this. In order to improve reliability, the oxide semiconductor layer may be thicker than the insulating layer 5423. In particular, when the oxide semiconductor layer is removed as shown in FIG. Since the thickness of the conductor layer is preferably thick, the thickness of the oxide semiconductor layer is set to be thicker than that of the insulating layer 5423. It is possible to make the thickness of the film thicker.

[0437] In order to increase the breakdown voltage of the transistor, the thickness of the insulating layer 5423 is set to be thicker than that of the first conductive layer. More preferably, the thickness of the insulating layer 5423 is 5 / 4 of that of the first conductive layer. It is preferable that the ratio is 4 / 3 or more. More preferably, it is 4 / 3 or more. However, the present invention is not limited to this, and the thickness of the insulating layer 5423 may be increased to increase the mobility of the transistor. can be thinner than the first conductive layer.

[0438] The substrate, insulating film, conductive film, and semiconductor layer of this embodiment may be the same as those of other embodiments ( For example, the material described in embodiment 10) or the material similar to that described in this specification It is possible to use.

[0439] The transistor of this embodiment may be used in the semiconductor device of the first to ninth embodiments, the shift register, or the like. By using it in a computer or a display device, the display area can be enlarged. The display can be made highly precise.

[0440] (Embodiment 13) In this embodiment, an example of an electronic device will be described.

[0441] 39(A) to 39(H) and 40(A) to 40(D) ​​are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation keys 5005 (including operation switches or power switches), connection terminals Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), 5008, etc.

[0442] FIG. 39(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, It may have an infrared port 5010, etc. FIG. 39(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 39(C) shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. Figure 39(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 39(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 39(G) shows a television receiver. In addition to the components described above, the image sensor may also include a tuner, an image processor, etc. 39(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 40(A) is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. Figure 40(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 40(C) is a computer, and In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 40(D) ​​shows a mobile phone, which can have the above-mentioned 2, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a lens, etc.

[0443] The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are various For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a three-dimensional image. In electronic devices with an image receiving unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to save the captured image to a recording medium (external or camera). It can have functions such as saving the captured image to a built-in memory, displaying the captured image on the display, etc. Note that the electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0444] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of this embodiment and the semiconductor device of any one of the first to ninth embodiments are characterized in that: By combining it with a device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, cost reduction, larger display area, and higher resolution display area. .

[0445] Next, application examples of the semiconductor device will be described.

[0446] FIG. 40(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0447] FIG. 40(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0448] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0449] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0450] FIG. 40G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0451] FIG. 40(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 40(H) shows a passenger plane with a display panel 5031 on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0452] In this embodiment, the moving body is exemplified by an automobile body and an airplane body. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0453] 101 Circuit 102 circuits 103 Circuit 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 121 Routes 122 routes 123 Routes 200 circuits 201 Transistor 202 Capacitor element 203 Transistor 211 Wiring 212 Wiring 213 Wiring 214 Wiring 231 circuits 232 circuits 300 circuits 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 400 circuits 401 Transistor 402 transistor 403 Capacitor 501 Flip-Flop 511 Wiring 512 Wiring 513 Wiring 514 Wiring 515 Wiring 516 Wiring 517 Wiring 520 circuits 521 circuits 522 circuits 540 pixels 600 circuits 601 circuits 602 circuits 603 Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 701 Conductive layer 702 Semiconductor layer 703 Conductive layer 704 Conductive layer 705 Contact Hole 711 Opening 731 width 732 width 101a diode 101p transistor 102a diode 102p transistor 112A wiring 112B wiring 112C wiring 112D Wiring 112G wiring 112H wiring 112I wiring 112J wiring 200a terminal 200b terminal 200c terminal 200d terminal 200e terminal 200f terminal 200g terminal 200h terminal 200i terminal 200j terminal 200k terminal 201p transistor 300a terminal 300b terminal 300c terminal 300d terminal 300e terminal 300f terminal 300g terminal 300h terminal 300i terminal 301p transistor 302p transistor 303p transistor 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitor element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3042 Voltage 3041_j signal 3042_j signal 400a terminal 400b terminal 400c terminal 400d terminal 400e terminal 400f terminal 403a transistor 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5260 board 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 luminous layer 5271 Conductive layer 5300 board 5301 Conductive layer 5302 Insulation layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 input terminal 5391 Circuit Board 5392 drive circuit 5393 Pixel section 5400 board 5401 Conductive layer 5402 Insulation layer 5404 Conductive layer 5405 Insulation layer 5406 Conductive layer 5408 Insulation layer 5409 Conductive layer 5410 PCB 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulation layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulation layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation layer 5436 Oxide semiconductor layer 5437 Conductive layer 5438 Conductive layer 5439 Conductive layer 5440 Conductive layer 5441 Transistor 5442 Capacitor element 3020A subpixel 3020B subpixel 3021A Transistor 3021B Transistor 3022A Liquid Crystal Element 3022B Liquid crystal element 3023A Capacitive Element 3023B Capacitive Element 3031A Wiring 3031B wiring 3032A Wiring 3032B wiring 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a circuit 5361b circuit 5362a circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

1. having first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a first power supply line; a gate electrode of the second transistor is electrically connected to a first signal line; one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the first power supply line; a gate electrode of the third transistor is electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a second power supply line; a gate electrode of the fourth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the first power supply line; a gate electrode of the fifth transistor is electrically connected to a third gate signal line; an area of ​​an overlapping region of a first conductive layer functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​an overlapping region of a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor and the second conductive layer; In a plan view, the first conductive layer includes a plurality of first regions extending in a first direction, and a second region connected to the plurality of first regions in a region that does not overlap with an oxide semiconductor layer that functions as a channel formation region of the first transistor.

2. having first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a first power supply line; a gate electrode of the second transistor is electrically connected to a first signal line; one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the first power supply line; a gate electrode of the third transistor is electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a second power supply line; a gate electrode of the fourth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the first power supply line; a gate electrode of the fifth transistor is electrically connected to a third gate signal line; an area of ​​an overlapping region of a first conductive layer functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​an overlapping region of a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor and the second conductive layer; the first conductive layer includes, in a plan view, a plurality of first regions extending in a first direction and a second region connected to the plurality of first regions in a region that does not overlap with an oxide semiconductor layer that functions as a channel formation region of the first transistor; The fourth conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor functions as the other of the source electrode and the drain electrode of the third transistor.

3. having first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a first power supply line; a gate electrode of the second transistor is electrically connected to a first signal line; one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the first power supply line; a gate electrode of the third transistor is electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a second power supply line; a gate electrode of the fourth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the first power supply line; a gate electrode of the fifth transistor is electrically connected to a third gate signal line; an area of ​​an overlapping region of a first conductive layer functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​an overlapping region of a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor and the second conductive layer; the first conductive layer includes, in a plan view, a plurality of first regions extending in a first direction and a second region connected to the plurality of first regions in a region that does not overlap with an oxide semiconductor layer that functions as a channel formation region of the first transistor; a fourth conductive layer having a function as the other of the source electrode and the drain electrode of the second transistor and a fifth conductive layer having a function as a gate electrode of the second transistor, the fourth conductive layer having a function as the other of the source electrode and the drain electrode of the second transistor, the fifth conductive layer having a function as a gate electrode of the second transistor, the fifth conductive layer having a function as the other of the source electrode and the drain electrode of the second transistor, the fifth conductive layer having a function as the ...

4. having first to fifth transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a first power supply line; a gate electrode of the second transistor is electrically connected to a first signal line; one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the first power supply line; a gate electrode of the third transistor is electrically connected to a second signal line; one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a second power supply line; a gate electrode of the fourth transistor is electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the first power supply line; a gate electrode of the fifth transistor is electrically connected to a third gate signal line; an area of ​​an overlapping region of a first conductive layer functioning as one of a source electrode and a drain electrode of the first transistor and a second conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​an overlapping region of a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor and the second conductive layer; the first conductive layer includes, in a plan view, a plurality of first regions extending in a first direction and a second region connected to the plurality of first regions in a region that does not overlap with an oxide semiconductor layer that functions as a channel formation region of the first transistor; an area of ​​a region where the fourth conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor overlaps with a fifth conductive layer functioning as a gate electrode of the second transistor is larger than an area of ​​a region where the first conductive layer functioning as one of the source electrode and the drain electrode of the second transistor overlaps with the fifth conductive layer; The fourth conductive layer functions as the other of the source electrode and the drain electrode of the third transistor.

Images