Video processing method and device, electronic device, storage medium, computer program

Abstract

The present disclosure provides a video processing method, apparatus, and electronic device, including: identifying a plurality of video track clips located on a plurality of video editing tracks in a video editing interface; determining cache priorities for track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and based on track clip image frames of the plurality of video track clips within a track timeline of the display area, where the track clip image frames of the video track clips are displayed at track timeline positions of the video track clips corresponding to the track clip image frames within the video track clips; identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priorities and cache frame configuration parameters; and caching the target track clip image frame, thereby improving video editing efficiency.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from a Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on December 29, 2022, bearing application number 202211713263.8 and titled "Video Processing Method, Apparatus and Electronic Device," the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure relate to the field of video processing technology, and in particular to a video processing method. and Device 、 electronic equipment , storage medium, computer program Regarding. [Background technology]

[0003] Since multi-video editing can process multiple video materials, the editing area of ​​the electronic device can display video frames from multiple video materials, and the electronic device must cache the video frames from multiple video materials in memory.

[0004] Currently, electronic devices can cache video frames of each video material in memory based on a cache number preset by the editing application. For example, when editing five video materials using a video editing application with a preset cache number of 30, the electronic device caches 150 video frames in memory, caching 30 video frames for each video material. However, according to the above method, for each video material, the electronic device can only cache a certain number of video frames of the video material. If there are many video materials, the memory occupied by the electronic device will be large, causing a large lag in the video editing process and reducing the efficiency of video editing. Summary of the Invention

[0005] The present disclosure provides a video processing method, apparatus and electronic device for solving the technical problem of low efficiency of video editing in the prior art.

[0006] According to a first aspect, the present disclosure provides a method for manufacturing a semiconductor device, comprising: identifying a plurality of video track clips located on a plurality of video edit tracks in a video editing interface; determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters, and caching the target track clip image frame.

[0007] According to a second aspect, the present disclosure provides a method for manufacturing a semiconductor device, comprising: a first identification module for identifying a plurality of video track clips located on a plurality of video editing tracks in a video editing interface; a second identification module for determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and based on track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; a third identifying module for identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters; a cache module for caching the target track clip image frames.

[0008] According to a third aspect, an embodiment of the present disclosure comprises: a memory for storing computer-executable instructions; a processor that executes the computer-executable instructions stored in the memory; At least one said processor is provided for performing the video processing method of the first aspect above and related thereto.

[0009] According to a fourth aspect, an embodiment of the present disclosure comprises: There is provided a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the video processing method of the first aspect above and which can be related to the first aspect.

[0010] According to a fifth aspect, an embodiment of the present disclosure comprises: There is provided a computer program product comprising a computer program which, when executed by a processor, implements the video processing method of the first aspect above and which can be related to the first aspect.

[0011] The present disclosure provides a video processing method, apparatus, and electronic device. The electronic device identifies multiple video track clips located on multiple video editing tracks in a video editing interface, determines cache priorities for track clip image frames of the multiple video track clips based on whether the multiple video editing tracks are located in a display area of ​​the video editing interface and based on the track clip image frames of the multiple video track clips within a track time axis range of the display area, and determines whether the track clip image frames of the video track clips are displayed at track time axis positions corresponding to the track clip image frames within the video track clips, identifies a target track clip image frame among the track clip image frames of the multiple video track clips based on the cache priorities and cache frame configuration parameters, and caches the target track clip image frame. According to the above method, the electronic device can cache the multiple track clip image frames based on the priorities among the multiple track clip image frames, thereby sequentially caching the track clip image frames and allowing the electronic device to flexibly cache the track clip image frames, improving cache flexibility and, in accordance with the cache frame configuration parameters, avoiding lag caused by a large memory footprint of the electronic device and improving video editing efficiency.

[0012] In order to more clearly describe the embodiments of the present disclosure or the technical solutions in the prior art, the drawings necessary for describing the embodiments or the prior art will be briefly described. The drawings in the following description are only some of the embodiments described in the present application, and it is obvious that those skilled in the art can obtain other drawings from these drawings without performing creative work. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram of an application scene according to an embodiment of the present disclosure. [Figure 2] 1 is a schematic diagram of a flow of a video processing method according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a schematic diagram of a first track clip image frame according to an embodiment of the present disclosure. [Figure 4] FIG. 10 is a schematic diagram of a second track clip image frame according to an embodiment of the present disclosure. [Figure 5] FIG. 10 is a schematic diagram of a third track clip image frame according to an embodiment of the present disclosure. [Figure 6] FIG. 10 is a schematic diagram of a fourth track clip image frame according to an embodiment of the present disclosure. [Figure 7] 10 is a schematic diagram of a management target track clip image frame according to an embodiment of the present disclosure. [Figure 8] 1 is a schematic diagram of a configuration of a video processing device according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram of another configuration of a video processing device according to an embodiment of the present disclosure. [Figure 10] 1 is a schematic diagram illustrating a configuration of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Reference will now be made in detail to illustrative embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise limited, identical numerals in different accompanying drawings refer to identical or similar elements. The embodiments described in the following illustrative examples do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0015] For ease of understanding, the following describes concepts related to embodiments of the present disclosure.

[0016] The electronic device is a device with a wireless transceiver function. The electronic device may be indoors or outdoors, located on land (including handheld, wearable, or vehicle-mounted), or on water (e.g., a ship). The electronic device may be a mobile phone, a tablet computer, a computer with a wireless transceiver function, a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a wireless terminal for industrial control, an in-vehicle electronic device, a wireless terminal for self-driving, a wireless electronic device for remote medical care, a wireless electronic device for a smart grid, a wireless electronic device for transportation safety, a wireless electronic device for a smart city, a wireless electronic device for a smart home, a wearable electronic device, or the like. Electronic devices related to embodiments of the present disclosure may also be referred to as terminals, user equipment (UE), access electronics, vehicle-mounted terminals, industrial control terminals, UE units, UE stations, mobile stations, remote stations, remote electronics, mobile devices, UE electronics, wireless communication devices, UE agents, or UE devices. Electronic devices may be fixed or mobile.

[0017] In related art, electronic devices can simultaneously edit multiple video sources. Since the electronic device needs to display video frames corresponding to the video sources in the editing area, the electronic device can cache video frames of multiple video sources in memory in advance. Currently, electronic devices can cache video frames of each video source in memory according to a preset cache number. For example, if the preset cache number is 30, the electronic device acquires 30 video frames from each video source and caches the 30 video frames in memory. However, according to the above method, the electronic device can only cache a certain number of video frames for each video source. Therefore, if there are many video sources, the electronic device's memory usage increases, causing lag in the video editing process and reducing the efficiency of video editing.

[0018] To solve the technical problems in the related art, the present disclosure provides a video processing method, in which an electronic device can identify multiple video track clips located on multiple video edit tracks in a video editing interface, and a first track clip image frame, in which the video edit track is located in a display area and among the video track clips of the video edit track, is given a first cache priority; a second track clip image frame, in which the video edit track is located in a display area and among the video track clips of the video edit track, is given a second cache priority; a third track clip image frame, in which the video edit track is not located in the display area and among the video track clips of the video edit track, is given a third cache priority; and a fourth track clip image frame, in which the video edit track is not located in the display area and among the track clips of the video edit track, is given a fourth cache priority. A target track clip image frame is identified from the track clip image frames of the multiple video track clips based on the cache priorities and the cache frame configuration parameters, and the target track clip image frame is cached. In this way, since there are different priorities among the track clip image frames in multiple video track clips, the electronic device caches the track clip image frames in order, improving the flexibility of the cache and, in accordance with the cache frame configuration parameters, avoiding the lag phenomenon caused by the large memory occupation of the electronic device, thereby improving the efficiency of video editing.

[0019] Hereinafter, application scenarios of the embodiments of the present disclosure will be described with reference to FIG.

[0020] FIG. 1 is a schematic diagram of an application scene according to an embodiment of the present disclosure. Referring to FIG. 1, the electronic device includes an electronic device, a video track clip A, and a video track clip B. The display page of the electronic device includes a preview area and an editing area capable of displaying track clip image frames in the video track clips. Both video track clip A and video track clip B include multiple track clip image frames (the number of track clip image frames is greater than 9). The editing area of ​​the electronic device displays images 4, 5, and 6 of video track clip A and images d, e, and f of video track clip B.

[0021] 1, the electronic device can identify images 4 to 6 in video track clip A and images d to f in video track clip B as track clip image frames to be cached based on the cache frame configuration parameters, and cache the three track clip image frames in video track clip A and the three track clip image frames in video track clip B in memory. In this way, since the cache frame configuration parameters can indicate the ability of the electronic device to cache image frames, the electronic device can cache only track clip image frames within the display region of the editing area in accordance with the priority among the track clip image frames, thereby improving the flexibility of caching track clip image frames, avoiding an increase in memory occupation rate, increasing the operating speed of the editing application, and further improving the efficiency of video editing.

[0022] The technical solution of the present disclosure and how the technical solution of the present disclosure solves the above-mentioned technical problems will be described in detail below with specific examples. These specific examples may be combined with each other, and the same or similar concepts or processes may not be repeated in some examples. The following describes the examples of the present disclosure with reference to the accompanying drawings.

[0023] 2 is a schematic diagram of a flow of a video processing method according to an embodiment of the present disclosure. Referring to FIG. 2, the method may include:

[0024] S201, identifying a plurality of video track clips located on a plurality of video editing tracks in a video editing interface;

[0025] The implementation body of the embodiments of the present disclosure may be an electronic device or a video processing device provided in the electronic device, where the video processing device may be realized by software or a combination of software and hardware, but the embodiments of the present disclosure are not limited thereto.

[0026] The video editing interface may be used for video editing. For example, multiple video materials may be edited in the video editing interface. Optionally, the video editing track is an editing track for video material editing. For example, in an editing process, the electronic device may edit multiple video materials, each of which may have a corresponding video editing track, and the electronic device may edit the multiple video materials in the multiple video editing tracks.

[0027] Optionally, the video track clips may be clips of video material to be edited in a video editing track. For example, when editing video material A, video material B, and video material C, the electronic device may identify that video editing track 1 containing track clips corresponding to video material A, video editing track 2 containing track clips corresponding to video material B, and video editing track 3 containing track clips corresponding to video material C are included in the video editing process.

[0028] S202, determine cache priorities of track clip image frames of the multiple video track clips based on whether the multiple video editing tracks are located in the display area of ​​the video editing interface and the track clip image frames of the multiple video track clips that are within the track time axis range of the display area.

[0029] Optionally, a track clip image frame of a video track clip is used to display the track timeline position within the video track clip that corresponds to the track clip image frame. For example, a video track clip may include multiple track clip image frames. For example, if the track timeline is 10 seconds, each video track clip may be edited within the 10 seconds. For example, the track clip image frames in each video track clip may have corresponding positions on the track timeline. For any one video track clip, if track clip image frame A is at 1 second on the track timeline and track clip image frame B is at 2 seconds on the track timeline, when editing a preview, the electronic device may display track clip image frame A when playing back to 1 second on the track timeline and display track clip image frame B when playing back to 2 seconds on the track timeline.

[0030] Optionally, the display area of ​​the video editing interface may be a display area in the video editing process of the electronic device. For example, if the video editing process includes 10 video materials, and video editing tracks corresponding to eight of the video materials are located in the display area of ​​the video editing interface, the eight video materials may be displayed on the electronic device, and if the video editing tracks corresponding to the other two video materials are not located in the display area of ​​the video editing interface, the other two video materials will not be displayed on the electronic device.

[0031] Optionally, a track clip image frame within a track time axis of the display area may be a track clip image frame that can be displayed in the display area, for example, the track time axis includes the time axis of the display area, and if a track clip image frame is within the time axis of the display area, the track clip image frame is displayed in the display area of ​​the video editing interface, and if a track clip image frame is not within the time axis of the display area, the track clip image frame is not displayed in the display area of ​​the video editing interface.

[0032] Optionally, determining the cache priority of track clip image frames of multiple video track clips based on whether the multiple video editing tracks are located in the display area of ​​the video editing interface and the track clip image frames of the multiple video track clips that are in the track time axis range of the display area includes the following four cases:

[0033] Case 1: The cache priority of the first track clip image frame is the first priority.

[0034] Optionally, when the video editing track is located in the display area, a first track clip image frame of a video track clip of the video editing track that is within the range of the track time axis of the display area has a first cache priority. For example, when the video editing track is located in the display area, it means that the video track clip of the video editing track is displayable in the display area of ​​the video editing interface, and a first track clip image frame of a video track clip of the video editing track that is within the range of the track time axis of the display area may be an image frame that is displayed in the display area, so the cache priority of such track clip image frame may be first.

[0035] The first track clip image frame will now be described with reference to FIG.

[0036] 3 is a schematic diagram of first track clip image frames according to an embodiment of the present disclosure. Referring to FIG. 3, an electronic device includes a display page including a video editing page. Here, the video editing page includes a display area capable of displaying image frames corresponding to video material. Image 1, Image 2, and Image 3 are track clip image frames in a video track clip. Since the video editing track corresponding to the video track clip is within the display area, Image 1, Image 2, and Image 3 are first track clip image frames, and the cache priorities of Image 1, Image 2, and Image 3 are first priority.

[0037] Case 2: The cache priority of the second track clip image frame is second priority.

[0038] Optionally, when the video editing track is located in the display area, the cache priority of second track clip image frames of the video track clips of the video editing track that are not within the range of the track time axis of the display area is second priority. For example, when the video editing track is located in the display area, it means that the video track clips of the video editing track can be displayed in the display area of ​​the video editing interface, but due to the limited size of the display area, the video track clips of the video editing track may include track clip image frames that are temporarily not displayed in the display area (e.g., image frames that extend beyond the display area of ​​the screen based on operations such as left swipe, right swipe, etc.), and such image frames may be second track clip image frames, and the cache priority of such image frames may be second priority.

[0039] The second track clip image frame will now be described with reference to FIG.

[0040] 4 is a schematic diagram of second track clip image frames according to an embodiment of the present disclosure. Referring to FIG. 4, an electronic device is provided. A display page of the electronic device includes a video editing page. Here, the video editing page includes a display area capable of displaying image frames corresponding to video material. Images 1, 2, 3, 7, 8, and 9 are track clip image frames in a video track clip. Because the video editing track corresponding to the video track clip is within the display area, Images 1, 2, 3, 7, 8, and 9 are temporarily not displayed in the display area. However, when a user swipes the screen to the right, Images 1, 2, and 3 can be displayed in the display area. When a user swipes the screen to the left, Images 7, 8, and 9 can be displayed in the display area. Therefore, Images 1, 2, 3, 7, 8, and 9 may be second track clip image frames, and their cache priority is second.

[0041] Case 3: The cache priority of the image frames of the third track clip is the third priority.

[0042] Optionally, when the video editing track is not in the display area, a third track clip image frame within the track time axis range of the display area among the video track clips of the video editing track has a third cache priority. For example, when the video editing track is not in the display area, a left swipe operation or a right swipe operation will not cause a track clip image frame in the video track clip to be displayed in the display area. However, when an up swipe operation or a down swipe operation is performed, this means that the video editing track corresponding to the video track clip can be positioned in the display area, and therefore a track clip image frame in the video track clip within the track time axis range of the display area can be displayed in the display area. Therefore, such an image frame is a third track clip image frame, and the cache priority of such an image frame is third.

[0043] Hereinafter, the third track clip image frame will be described with reference to FIG.

[0044] 5 is a schematic diagram of third track clip image frames according to an embodiment of the present disclosure. Referring to FIG. 5, an electronic device is provided. A display page of the electronic device includes a video editing page. Here, the video editing page includes a display area capable of displaying image frames corresponding to video material. Images 1, 2, and 3 are track clip image frames in a video track clip. Since the video editing track corresponding to the video track clip is not within the display area, Images 1, 2, and 3 are not displayed in the display area. However, when a user swipes up on the screen, the video editing track corresponding to the video track clip may be present within the display area, and the display area may display Images 1, 2, and 3. Therefore, Images 1, 2, and 3 may be third track clip image frames, and their cache priority is set to third.

[0045] Case 4: The cache priority of the image frame of the fourth track clip is the fourth priority.

[0046] Optionally, a fourth track clip image frame, when the video editing track is not in the display area and is not within the range of the track time axis of the display area among the video track clips of the video editing track, has a cache priority of fourth priority. For example, when the video editing track is not in the display area, a track clip image frame in the video track clip is not displayed in the display area by a left swipe operation or a right swipe operation, but an up swipe operation or a down swipe operation means that the video editing track of the video track clip can be present in the display area, but due to limitations on the display area size, even if the video track clip can be displayed in the display area, some of the track clip image frames cannot be displayed in the display area, and such track clip image frame may be a fourth track clip image frame, and the cache priority of such track clip image frame is fourth priority.

[0047] The following describes the fourth track clip image frame with reference to FIG.

[0048] 6 is a schematic diagram of fourth track clip image frames according to an embodiment of the present disclosure. Referring to FIG. 6, an electronic device is provided. The display page of the electronic device includes a video editing page. Here, the video editing page includes a display area capable of displaying image frames corresponding to video material. Images 1, 2, 3, 7, 8, and 9 are track clip image frames in a video track clip. Since the video editing track corresponding to the video track clip is not within the display area, images 1, 2, 3, 7, 8, and 9 are not displayed in the display area. Even if a user swipes up on the screen so that the video editing track corresponding to the video track clip is within the display area, images 1, 2, 3, 7, 8, and 9 are not displayed in the display area. Therefore, images 1, 2, 3, 7, 8, and 9 are fourth track clip image frames, and their cache priority is set to fourth.

[0049] Optionally, the first priority is greater than the second priority, which is greater than the third priority, which is greater than the fourth priority. For example, because the first track clip image frame has the highest priority, the electronics may cache the first track clip image frame first. Because the second track clip image frame has a lower priority than the first track clip image frame, the electronics may cache the second track clip image frame after caching all of the first track clip image frames. Because the third track clip image frame has a lower priority than the second track clip image frame, the electronics may cache the third track clip image frame after caching all of the first and second track clip image frames. Because the fourth track clip image frame has a lower priority than the third track clip image frame, the electronics may cache the fourth track clip image frame after caching all of the first, second, and third track clip image frames.

[0050] S203, identify a target track clip image frame among the track clip image frames of the plurality of video track clips according to the cache priority and the cache frame configuration parameters, and cache the target track clip image frame.

[0051] Optionally, the cache frame configuration parameter may indicate the capability of the electronic device to cache image frames, for example, the higher the cache frame configuration parameter of the electronic device, the higher the processing power of the electronic device and the more track clip image frames the memory of the electronic device can cache, and the lower the cache frame configuration parameter of the electronic device, the weaker the processing power of the electronic device and the fewer track clip image frames the memory of the electronic device can cache.

[0052] Optionally, the cache frame configuration parameters of the electronic device may be preset parameters, for example, different model numbers of electronic devices have different cache frame configuration parameters, and each electronic device can preset its cache frame configuration parameters, so that the electronic device can obtain the preset cache frame configuration parameters.

[0053] Optionally, the electronic device may determine the cache frame configuration parameter based on a hardware configuration. For example, the electronic device may determine the cache frame configuration parameter based on a memory configuration. For example, if the memory configuration is low, the electronic device may have a low cache frame configuration parameter, and if the memory configuration is high, the electronic device may have a high cache frame configuration parameter. For example, if the electronic device RAM is 2G of operating memory, the cache frame configuration parameter of the electronic device may be 3; if the electronic device RAM is 4G of operating memory, the cache frame configuration parameter of the electronic device may be 5; and if the electronic device RAM is 8G of operating memory, the cache frame configuration parameter of the electronic device may be 7.

[0054] Optionally, the electronic device may also adjust the cache frame configuration parameter based on the memory usage rate of the cached video frames. For example, if the RAM of the electronic device is 8G of working memory, the cache frame configuration parameter of the electronic device may be 7, but if the OOM or memory usage rate of the electronic device is high (e.g., more memory is allocated to decoding video frames), the cache frame configuration parameter of the electronic device may be set to 5.

[0055] Optionally, the electronic device may determine the cache frame configuration parameter based on an editing operation. For example, the electronic device may determine the cache frame configuration parameter based on a swipe speed corresponding to the editing operation. For example, if the user's editing operation instructs the user to swipe the screen at a speed greater than a first threshold, the electronic device may determine the cache frame configuration parameter as 7, and if the user's editing operation instructs the user to swipe the screen at a speed equal to or less than the first threshold, the electronic device may determine the cache frame configuration parameter as 5.

[0056] It should be noted that the electronic device may determine the cache frame configuration parameters in other ways, for example, the electronic device may pre-set the cache frame configuration parameters and further adjust the cache frame configuration parameters in real time based on the swipe speed corresponding to the editing operation, but the embodiments of the present disclosure are not limited thereto.

[0057] Optionally, the electronic device may identify a target track clip image frame among the track clip image frames of the plurality of video track clips based on a possible implementation as follows: determine a first number of track clip image frames cacheable by the electronic device based on a cache frame configuration parameter, and identify a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number.

[0058] Optionally, determine a first number of track clip image frames cacheable by the electronic device based on the cache frame configuration parameters, specifically, obtain a second number of track clip image frames of each video track clip that are within the range of the track time axis of the display area. For example, if the display area can display three track clip image frames per row (one video track clip displayed per row), the second number is 3, and if the display area can display five track clip image frames per row, the second number is 5. For example, in the embodiment shown in FIG. 3, one row in the display area includes image 1, image 2, and image 3, so the second number of track clip image frames within the range of the track time axis of the display area is 3.

[0059] The first number is determined based on the second number and the cache frame configuration parameter. For example, the first number is determined based on the second number, the cache frame configuration parameter, and the number of video editing tracks. For example, if the second number of track clip image frames displayed in each row of the display area is 3, the cache frame configuration parameter is 7, and the number of video editing tracks is 5, the first number of track clip image frames that can be cached in the electronic device is 105 (3*7*5).

[0060] Optionally, identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number includes the following two cases: Case 1: The first number is greater than or equal to the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames.

[0061] If the first number is equal to or greater than the sum of the numbers of the first, second, third, and fourth track clip image frames, the first, second, third, and fourth track clip image frames are identified as target track clip image frames. For example, if the first number is 200 and the sum of the numbers of the first, second, third, and fourth track clip image frames is 150, this means that the electronic device can fully cache all of the track clip image frames and identify all of the track clip image frames as target track clip image frames.

[0062] Case 2: The first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames.

[0063] If the first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, the target track clip image frames are identified in the order of the cache priority, in the order of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames. For example, if the first number is 120 and the total number of the first, second, third, and fourth track clip image frames is 200, it means that 80 track clip image frames cannot be cached by the electronic device, so the electronic device can identify the target track clip image frames based on the order of cache priority. If the number of first track clip image frames is 30, the number of second track clip image frames is 70, the number of third track clip image frames is 30, and the number of fourth track clip image frames is 70, the electronic device can identify 30 first track clip image frames, 70 second track clip image frames, and 20 third track clip image frames as the target track clip image frames.

[0064] Optionally, after identifying the target track clip image frame, the electronic device can cache the target track clip image frame in memory, for example, the electronic device can cache the target track image frame in memory so that the target track clip image frame can be quickly retrieved from memory.

[0065] In addition, since the speed at which the electronic device retrieves track clip image frames from the memory cache is faster than the speed at which the electronic device retrieves track clip image frames from the hard disk cache, when loading a track clip image frame, the electronic device can first retrieve the track clip image frame to be loaded from memory, and if the memory does not contain the track clip image frame, the electronic device can retrieve the track clip image frame to be loaded from the hard disk, and if the hard disk does not contain the track clip image frame either, the electronic device can retrieve the track clip image frame from the document that stores the video material (which caches the video material) and cache the track clip image frame in memory and the hard disk.

[0066] Note that, since the operation of the electronic device to acquire track clip image frames from memory occupies a large amount of CPU resources, the electronic device may be configured in advance to acquire track clip image frames in parallel, thereby avoiding lags in the electronic device when acquiring track clip image frames. For example, the electronic device may limit the number of cache threads of the decode disk to 5 and the number of threads for acquiring frames to 1, thereby enabling the electronic device to decode five track clip image frames and acquire one track clip image frame at a time. This prevents lags in the electronic device when acquiring multiple track clip image frames, improving the smoothness of the electronic device's operation.

[0067] An embodiment of the present disclosure provides a video processing method. An electronic device identifies a plurality of video track clips located on a plurality of video editing tracks in a video editing interface, and identifies a first track clip video frame, a second track clip video frame, a third track clip video frame, and a fourth track clip video frame from the plurality of video track clips based on whether the plurality of video editing tracks are located within a display area of ​​the video editing interface and the track clip image frames from the plurality of video track clips within a track time axis range of the display area. Then, based on cache priorities and cache frame configuration parameters, identifies a target track clip image frame from the track clip image frames of the plurality of video track clips and caches the target track clip image frame. In this way, since the track clip image frames in the plurality of video track clips have different priorities, the electronic device sequentially caches the track clip image frames, improving cache flexibility and, in accordance with the cache frame configuration parameters, avoiding lag caused by a large memory footprint of the electronic device and improving video editing efficiency.

[0068] In addition to any of the above-described embodiments, the embodiments of the present disclosure further include a method for managing target track clip image frames to be cached in memory, and the method for managing target track clip image frames to be cached in memory will be described in detail below with reference to FIG. 7.

[0069] 7 is a schematic diagram of a management target track clip image frame according to an embodiment of the present disclosure. Referring to FIG. 7, the method flow includes:

[0070] S701, obtain the occurrence count corresponding to each target track clip image frame in the memory.

[0071] Optionally, the occurrence count is the total number of occurrences of the target track clip image frame in the first track clip image frame, the second track clip image frame, the third track clip image frame, and the fourth track clip image frame. For example, in an actual application process, the same track clip image frame may be included in multiple video materials, so for any one track clip image frame, when the track clip image frame appears in any one of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, the electronic device can cache the track clip image frame in a memory and obtain the occurrence count corresponding to the track clip image frame. For example, any track clip image frame may be a different track clip image frame of the same video material or a track clip image frame of different video materials, so the track clip image frame can be repeatedly used when editing multiple video materials.

[0072] Optionally, for any one target track clip image frame, the electronic device may obtain the number of occurrences corresponding to the target track clip image frame from the memory according to the following possible implementation form: if the target track clip image frame is within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, add N to the number of occurrences corresponding to the target track clip image frame, where N is a number greater than 0. For example, if target track clip image frame A appears once in the first track clip image frame, once in the second track clip image frame, once in the third track clip image frame, and once in the fourth track clip image frame, the number of occurrences corresponding to the target track clip image frame A in the memory is 4; and if target track clip image frame B appears three times in the first track clip image frame, twice in the second track clip image frame, and does not appear in the third track clip image frame or the fourth track clip image frame, the number of occurrences corresponding to the target track clip image frame B is 5.

[0073] If the target track clip image frame is not within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, the number of occurrences corresponding to the target track clip image frame is subtracted by N. For example, if the target track clip image frame appears once in the first track clip image frame, once in the second track clip image frame, and once in the third track clip image frame, the number of occurrences corresponding to the target track clip image frame is 3; if the user swipes the video material so that the target track clip image frame is not within the range of the first track clip image frames, the number of occurrences corresponding to the target track clip image frame is 2 (3 minus 1); and if the user continues to swipe the video material so that the target track clip image frame is not within the range of the second track clip image frames and the third track clip image frames, the number of occurrences corresponding to the target track clip image frame is 0.

[0074] S702, manage the target track clip image frames to be cached in memory based on the number of occurrences.

[0075] Optionally, the electronic device can delete a target track clip image frame from the memory if the number of occurrences corresponding to the target track clip image frame in the memory is 0. For example, if the number of occurrences corresponding to the target track clip image frame is 0, it means that the target track clip image frame does not need to be displayed in the display area of ​​the video editing interface within a certain period of time, so the electronic device can delete the target track clip image frame from the memory, thereby saving memory resources of the electronic device.

[0076] An embodiment of the present disclosure provides a method for managing target track clip image frames, which obtains an appearance count corresponding to each target track clip image frame in a memory, and manages the target track clip image frames to be cached in the memory based on the appearance count. In this way, the electronic device can delete from the memory the target track clip image frames that do not need to be displayed in the display area within a certain period of time according to a user's editing operation, thereby saving memory resources of the electronic device, avoiding lag in the editing process caused by large memory occupation, and improving the efficiency of video editing.

[0077] 8 is a schematic diagram of a configuration of a video processing device according to an embodiment of the present disclosure. Referring to FIG. 8, the video processing device 8 includes a first specific module 11, a second specific module 12, a third specific module 13, and a cache module 14. the first identification module 11 is used to identify a plurality of video track clips located on a plurality of video editing tracks in a video editing interface; the second identification module 12 is used to determine, based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and the track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, cache priorities of the plurality of track clip image frames for display at track time axis positions of the video track clips that correspond to the track clip image frames in the video track clips; the third identification module 13 is used for identifying a target track clip image frame among the track clip image frames of the plurality of video track clips according to the cache priority and cache frame configuration parameters; The cache module 14 is used to cache the target track clip image frames.

[0078] According to one or more embodiments of the present disclosure, the second identification module 12 is specifically used as follows: The video edit track is located in the display area, and a first track clip image frame of a video track clip of the video edit track that is within a track time axis range of the display area has a first cache priority; The video edit track is located in the display area, and a second track clip image frame of the video edit track, which is not within the range of the track time axis of the display area, has a second cache priority; a third track clip image frame of the video edit track not in the display area and within a track time axis range of the display area among the video track clips of the video edit track has a third cache priority; The cache priority of a fourth track clip image frame, of which the video editing track is not in the display area and which is not in the range of the track time axis of the display area, among the track clips of the video editing track, is fourth priority.

[0079] According to one or more embodiments of the present disclosure, the first priority is greater than the second priority, the second priority is greater than the third priority, and the third priority is greater than the fourth priority.

[0080] According to one or more embodiments of the present disclosure, the third identification module 13 is specifically used as follows: determining a first number of cacheable track clip image frames for the electronic device based on the cache frame configuration parameters; A target track clip image frame is identified among the track clip image frames of the plurality of video track clips based on the cache priority and the first number.

[0081] According to one or more embodiments of the present disclosure, the third identification module 13 is specifically used as follows: if the first number is equal to or greater than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, identify the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames as the target track clip image frames; If the first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, the target track clip image frames are identified in the order of the cache priority: the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames.

[0082] According to one or more embodiments of the present disclosure, the third identification module 13 is specifically used as follows: obtaining a second number of track clip image frames for each video track clip within a track time axis of the display area; The first number is determined based on the second number and the cache frame configuration parameter.

[0083] The video processing device according to the embodiments of the present disclosure is used to implement the technical solutions of the above-mentioned method embodiments, and the implementation principles and technical effects thereof are similar, and the embodiments of the present disclosure will not be repeated in this specification.

[0084] 9 is a schematic diagram of another configuration of a video processing device according to an embodiment of the present disclosure. In addition to the embodiment shown in FIG. 8, referring to FIG. 9, the video processing device 10 further includes an acquisition module 15, which: to obtain in a memory an occurrence count corresponding to each target track clip image frame, the occurrence count being a sum of the occurrence count of the target track clip image frame in the first track clip image frame, the second track clip image frame, the third track clip image frame, and the fourth track clip image frame; Based on the number of occurrences, the target track clip image frames to be cached in the memory are managed.

[0085] According to one or more embodiments of the present disclosure, the acquisition module 15 is specifically used as follows: If the target track clip image frame is within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, add N to the number of occurrences corresponding to the target track clip image frame, where N is a number greater than 0; If the target track clip image frame is not within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, subtract N from the number of occurrences corresponding to the target track clip image frame.

[0086] The video processing device according to the embodiments of the present disclosure is used to implement the technical solutions of the above-mentioned method embodiments, and the implementation principles and technical effects thereof are similar, and the embodiments of the present disclosure will not be repeated in this specification.

[0087] FIG. 10 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 10, a schematic diagram suitable for use in implementing the configuration of an electronic device 1000 according to an embodiment of the present disclosure is shown, and the electronic device 1000 may be a terminal device or a server. Here, the terminal device may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (Portable Android Devices, PADs), portable multimedia players (PMPs), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. The electronic device shown in FIG. 10 is merely an example and does not limit the functionality and scope of use according to the embodiment of the present disclosure.

[0088] 10, electronic device 1000 may include a processing unit (e.g., a central processor, a graphics processor, etc.) 1001 that performs various appropriate operations and processes according to a program stored in read only memory (ROM) 1002 or loaded from a storage device 1008 into random access memory (RAM) 1003. RAM 1003 further stores various programs and data necessary for the operation of electronic device 1000. Processing unit 1001, ROM 1002, and RAM 1003 are connected to one another via a bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0089] Typically, input devices 1006, including, for example, a touch screen, touch panel, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 1007, including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1008, including, for example, a magnetic tape, hard disk, etc.; and communication devices 1009 may be connected to the I / O interface 1005. The communication devices 1009 may enable the electronic device 1000 to communicate and exchange data with other devices wirelessly or via wires. While FIG. 10 illustrates the electronic device 1000 including various devices, it should be understood that it is not necessary for the electronic device 1000 to implement or include all of the devices shown. More or fewer devices may alternatively be implemented or included.

[0090] In particular, the processes described above with reference to the flowcharts may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program embodied in a computer-readable medium, the computer program including program code for performing the methods illustrated in the flowcharts. In such embodiments, the computer program may be downloaded and installed over a network via the communication device 1009, installed from the storage device 1008, or installed from the ROM 1002. When executed by the processing device 1001, the computer program performs the functions defined above in the methods of the embodiments of the present disclosure.

[0091] It should be noted that the computer-readable medium described above in this disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above. The computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in combination with an instruction execution system, apparatus, or device. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in combination with an instruction execution system, apparatus, or device. However, in this disclosure, a computer-readable signal medium may include a propagated data signal, in baseband or as part of a carrier wave, having computer-readable program code embedded therein. Such a propagated data signal may take various forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination of the above. Furthermore, a computer-readable signal medium may be any computer-readable medium, other than a computer-readable storage medium, that can transmit, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.The program code contained in the computer readable medium may be transmitted over any suitable medium, including but not limited to wire, optical cable, RF (radio frequency), etc., or any suitable combination of the above.

[0092] The computer-readable medium described above may be included in the electronic device described above, or may exist separately from the electronic device.

[0093] The above-mentioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to perform the method illustrated in the above-mentioned embodiments.

[0094] Computer program code for carrying out the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, etc., as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may run entirely on the user computer, partially on the user computer, as a separate software package, partially on the user computer and partially on a remote computer, or entirely on a remote computer or server. When remote computers are involved, the remote computers may be connected to the user computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider).

[0095] The flowcharts and block diagrams in the figures illustrate the architecture, functions, and operations that can be implemented in accordance with systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or portion of code, including one or more executable instructions for implementing a given logical function. It should also be noted that in some implementations, the functions noted in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may actually be executed substantially in parallel or may be executed in the reverse order depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in a dedicated hardware-based system that performs a given function or operation, or in a combination of dedicated hardware and computer instructions.

[0096] The units described in the embodiments of the present disclosure may be implemented in a software manner or a hardware manner, and the names of the units may not necessarily limit the units themselves, for example, the first acquisition unit may also be described as "acquiring at least two Internet Protocol units."

[0097] The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0098] In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain or store a program used by or in connection with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a convenient compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0099] According to a first aspect, one or more embodiments of the present disclosure include: identifying a plurality of video track clips located on a plurality of video edit tracks in a video editing interface; determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters, and caching the target track clip image frame.

[0100] According to one or more embodiments of the present disclosure, determining cache priorities of track clip image frames of the plurality of video track clips includes: The video editing track is located in the display area, and among the video track clips of the video editing track, a first track clip image frame within a track time axis range of the display area has a first cache priority; The video edit track is located in the display area, and among the video track clips of the video edit track, a second track clip image frame that is not within the range of the track time axis of the display area has a second cache priority; the video edit track is not in the display area, and among the video track clips of the video edit track, a third track clip image frame within a range of the track time axis of the display area has a third cache priority; The video editing track is not in the display area, and among the track clips of the video editing track, the cache priority of a fourth track clip image frame that is not within the range of the track time axis of the display area is fourth priority.

[0101] According to one or more embodiments of the present disclosure, the first priority is greater than the second priority, the second priority is greater than the third priority, and the third priority is greater than the fourth priority.

[0102] According to one or more embodiments of the present disclosure, identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters includes: determining a first number of cacheable track clip image frames for an electronic device based on the cache frame configuration parameters; identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number.

[0103] According to one or more embodiments of the present disclosure, identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number includes: if the first number is equal to or greater than the sum of the numbers of first track clip image frames, second track clip image frames, third track clip image frames, and fourth track clip image frames, identifying the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames as the target track clip image frames; If the first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, identifying the target track clip image frames in the order of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames based on the cache priority ranking.

[0104] According to one or more embodiments of the present disclosure, determining a first number of cacheable track clip image frames for an electronic device based on the cache frame configuration parameter includes: obtaining, for each video track clip, a second number of track clip image frames that fall within a track time axis of the display area; determining the first number based on the second number and the cache frame configuration parameter.

[0105] According to one or more embodiments of the present disclosure, after caching the target track clip image frames, the method includes: obtaining an occurrence count corresponding to each target track clip image frame in a memory, the occurrence count being a sum of the occurrence count of the target track clip image frame in the first track clip image frame, the second track clip image frame, the third track clip image frame, and the fourth track clip image frame; The method further includes managing the target track clip image frames to be cached in the memory based on the number of occurrences.

[0106] According to one or more embodiments of the present disclosure, for any one target track clip image frame in the memory, obtaining a number of occurrences corresponding to the target track clip image frame in the memory includes: When the target track clip image frame is within a range of a first track clip image frame, a second track clip image frame, a third track clip image frame, or a fourth track clip image frame, adding N to the number of occurrences corresponding to the target track clip image frame, and the N is a number greater than 0; If the target track clip image frame is not within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, subtracting N from the number of occurrences corresponding to the target track clip image frame.

[0107] According to a second aspect, an embodiment of the present disclosure comprises: a first identification module for identifying a plurality of video track clips located on a plurality of video editing tracks in a video editing interface; a second identification module for determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and based on track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; a third identifying module for identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters; a cache module for caching the target track clip image frames.

[0108] According to one or more embodiments of the present disclosure, the second identification module is specifically used as follows: The video editing track is located in the display area, and among the video track clips of the video editing track, a first track clip image frame within a track time axis range of the display area has a first cache priority; The video edit track is located in the display area, and among the video track clips of the video edit track, a second track clip image frame that is not within the range of the track time axis of the display area has a second cache priority; the video edit track is not in the display area, and among the video track clips of the video edit track, a third track clip image frame within a range of the track time axis of the display area has a third cache priority; The video editing track is not in the display area, and among the track clips of the video editing track, a fourth track clip image frame that is not in the range of the track time axis of the display area has a fourth cache priority.

[0109] According to one or more embodiments of the present disclosure, the first priority is greater than the second priority, the second priority is greater than the third priority, and the third priority is greater than the fourth priority.

[0110] According to one or more embodiments of the present disclosure, the third identification module is specifically used as follows: determining a first number of cacheable track clip image frames for the electronic device based on the cache frame configuration parameters; A target track clip image frame is identified among the track clip image frames of the plurality of video track clips based on the cache priority and the first number.

[0111] According to one or more embodiments of the present disclosure, the third identification module is specifically used as follows: if the first number is equal to or greater than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, identify the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames as the target track clip image frames; If the first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, the target track clip image frames are identified based on the cache priority ranking in the order of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames.

[0112] According to one or more embodiments of the present disclosure, the third identification module is specifically used as follows: obtaining, for each video track clip, a second number of track clip image frames that fall within a track time axis of the display area; The first number is determined based on the second number and the cache frame configuration parameter.

[0113] According to one or more embodiments of the present disclosure, the video processing device further comprises an acquisition module, wherein the acquisition module: obtaining an occurrence count corresponding to each target track clip image frame in a memory, the occurrence count being a total of occurrence counts of the target track clip image frame in the first track clip image frame, the second track clip image frame, the third track clip image frame, and the fourth track clip image frame; The number of occurrences is used to manage the target track clip image frames to be cached in the memory.

[0114] According to one or more embodiments of the present disclosure, the acquisition module is specifically used as follows: when the target track clip image frame is within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, adding N to the number of occurrences corresponding to the target track clip image frame, where N is a number greater than 0; If the target track clip image frame is not within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame, N is subtracted from the number of occurrences corresponding to the target track clip image frame.

[0115] According to a third aspect, an embodiment of the present disclosure comprises: a memory for storing computer-executable instructions; a processor that executes the computer-executable instructions stored in the memory; At least one said processor provides an electronic device for carrying out the video processing method of the first aspect above and capable of being related to the first aspect.

[0116] According to a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement the video processing method of the first aspect above and that can be related to the first aspect.

[0117] According to a fifth aspect, an embodiment of the present disclosure provides a computer program product including a computer program that, when executed by a processor, implements the video processing method of the first aspect above and that can be related to the first aspect.

[0118] It should be noted that references to the modifiers "a" and "plurality" in this disclosure are exemplary rather than limiting and should be understood by those skilled in the art to mean "one or more" unless the context clearly indicates otherwise.

[0119] The names of messages or information exchanged between devices in embodiments of the present disclosure are used for illustrative purposes only and are not intended to limit the scope of those messages or information.

[0120] It is understood that before using the technical solutions of each embodiment in this disclosure, the user should be notified of the type, scope of use, usage scenarios, etc. of the personal information involved in the solution in an appropriate manner in accordance with relevant laws and regulations, and the user's approval should be obtained.

[0121] For example, in response to a proactive request from a user, prompt information is sent to the user to explicitly notify the user that the requested operation requires the acquisition and use of the user's personal information, allowing the user to autonomously choose whether or not to provide personal information to software or hardware, such as an electronic device, application, server, or storage medium, that executes the operation of the technical solution of the present disclosure, in response to the prompt information.

[0122] In an optional, non-limiting embodiment, the form in which the prompt information is sent to the user in response to an active request from the user may be, for example, a pop-up window, or the prompt information may be presented in text form in the pop-up window. The pop-up window may also include a selection control for the user to select "agree" or "disagree" to providing personal information to the electronic device.

[0123] It will be appreciated that the above-described notification and user consent acquisition procedures are merely exemplary and are not intended to limit the implementation of the present disclosure, and that other procedures that comply with relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0124] It should be understood that data related to the present technical solution (including but not limited to the data itself, the acquisition or use of the data) should comply with the requirements of corresponding laws and related regulations. The data may include information, parameters, and messages such as cut flow instruction messages.

[0125] The above description merely describes preferred embodiments of the present disclosure and the technical principles applied thereto. Those skilled in the art should understand that the scope of the present disclosure is not limited to a technical solution based on a specific combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalent features without departing from the concept disclosed above. For example, a technical solution in which the above features are replaced with technical features having similar functions disclosed in the present disclosure (but are not limited thereto).

[0126] Additionally, although operations have been described in a particular order, this should not be construed as requiring these operations to be performed in the particular or sequential order shown. Multitasking and parallel processing may be advantageous in certain circumstances.

[0127] Similarly, although details of several specific embodiments are included in the above description, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination.

[0128] Although the present subject matter has been described using language specific to structural features and / or method logic operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above. Rather, the specific features and operations described above are merely example forms of implementing the claims.

Claims

1. identifying a plurality of video track clips located on a plurality of video edit tracks in a video editing interface; determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the cache frame configuration parameters, and caching the target track clip image frame.

10. A video processing method comprising:

2. determining cache priorities of track clip image frames of the plurality of video track clips, The video editing track is located in the display area, and among the video track clips of the video editing track, a first track clip image frame within a range of the track time axis of the display area has a first cache priority; The video edit track is located in the display area, and among the video track clips of the video edit track, a second track clip image frame that is not within the range of the track time axis of the display area has a second cache priority; a third track clip image frame of the video edit track not in the display area and within a range of the track time axis of the display area among the video track clips of the video edit track has a third cache priority; The video editing track is not in the display area, and among the track clips of the video editing track, a fourth track clip image frame that is not in the range of the track time axis of the display area has a fourth cache priority.

2. The method of claim 1 .

3. the first priority is greater than the second priority, the second priority is greater than the third priority, and the third priority is greater than the fourth priority; 3. The method of claim 2.

4. identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters, determining a first number of electronic device cacheable track clip image frames based on the cache frame configuration parameters; identifying the target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number; 2. The method of claim 1.

5. identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and the first number, if the first number is equal to or greater than the sum of the numbers of first track clip image frames, second track clip image frames, third track clip image frames, and fourth track clip image frames, identifying the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames as the target track clip image frames; if the first number is smaller than the sum of the numbers of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames, identifying the target track clip image frames in the order of the first track clip image frames, the second track clip image frames, the third track clip image frames, and the fourth track clip image frames based on the order of cache priority; 5. The method of claim 4.

6. determining a first number of cacheable track clip image frames for an electronic device based on the cache frame configuration parameters; obtaining, for each video track clip, a second number of track clip image frames that fall within a track time axis of the display area; determining the first number based on the second number and the cache frame configuration parameter; 5. The method of claim 4.

7. After caching the target track clip image frames, the method includes: obtaining an occurrence count corresponding to each target track clip image frame in a memory, the occurrence count being a sum of the occurrence count of the target track clip image frame in the first track clip image frame, the second track clip image frame, the third track clip image frame, and the fourth track clip image frame; managing target track clip image frames to be cached in the memory based on the number of occurrences; 7. The method according to any one of claims 1 to 6.

8. For any one target track clip image frame in the memory, obtaining a number of occurrences corresponding to the target track clip image frame in the memory includes: When the target track clip image frame is within a range of a first track clip image frame, a second track clip image frame, a third track clip image frame, or a fourth track clip image frame, adding N to the number of occurrences corresponding to the target track clip image frame, and N is a number greater than 0; subtracting N from the number of occurrences corresponding to the target track clip image frame when the target track clip image frame is not within the range of the first track clip image frame, the second track clip image frame, the third track clip image frame, or the fourth track clip image frame.

8. The method of claim 7.

9. a first identification module for identifying a plurality of video track clips located on a plurality of video editing tracks in a video editing interface; a second identification module for determining cache priorities of track clip image frames of the plurality of video track clips based on whether the plurality of video editing tracks are located in a display area of ​​the video editing interface and based on track clip image frames of the plurality of video track clips that are within a track time axis range of the display area, wherein the track clip image frames of the video track clips are displayed at track time axis positions of the video track clips that correspond to the track clip image frames within the video track clips; a third identifying module for identifying a target track clip image frame among the track clip image frames of the plurality of video track clips based on the cache priority and cache frame configuration parameters; a cache module for caching the target track clip image frames.

1. A video processing device comprising:

10. a memory for storing computer-executable instructions; a processor that executes the computer-executable instructions stored in the memory; causing the processor to perform the video processing method of any one of claims 1 to 6; An electronic device characterized by:

11. storing computer-implemented instructions, which when executed by a processor implement the video processing method of any one of claims 1 to 6; A computer-readable storage medium comprising:

12. A computer program which, when executed by a computing device, causes the computing device to implement the video processing method described in any one of claims 1 to 6.

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