Semiconductor device with tunable polarization direction

Abstract

The present disclosure discloses a semiconductor device comprising multiple epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at the interface between the barrier layer and the channel layer. The charge carrier priority of the channel layer is based on the polarization direction of the barrier layer. The polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, one of which is ohmic to electrons and the other of which is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, a gate terminal, and a set terminal ohmic to the channel layer.

Description

[Technical Field]

[0001] Technical Field The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices with alterable polarization direction. [Background technology]

[0002] background Modern semiconductor devices, such as metal oxide silicon field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), and insulated gate bipolar transistors (IGBTs), have typically been fabricated with silicon (Si) semiconductor material. However, silicon's limited critical electric field and relatively high resistivity make currently available commercial power devices, circuits, and systems bulky and further limit their operating frequencies. Therefore, these commercial devices are unsuitable for many types of applications, such as high-power electronics applications.

[0003] III-N semiconductor devices have many advantages over silicon-based devices. For example, III-N semiconductor devices can carry large currents while providing very low on-resistance and can operate at high voltages with fast switching times. III-N semiconductor devices are made from III-nitride materials. III-nitride materials possess a unique combination of physical properties that are useful in modern microelectronics and optoelectronics. Among these properties are a wide bandgap, a high saturation drift rate, a high breakdown voltage, high thermal conductivity, and remarkable chemical and thermal stability. Due to these properties, III-nitride materials are used in the fabrication of numerous electronic and optoelectronic devices.

[0004] However, despite the advantages of III-nitride materials, there are still many technical challenges that need to be addressed, such as the difficulty of controlling defects due to the lack of a native substrate. x Ga 1_x Incorporating high concentrations of indium into N alloys remains challenging due to phase separation and the lattice mismatch between gallium nitride (GaN) and indium nitride (InN).

[0005] Therefore, there remains a need to characterize III-nitride materials to improve the capabilities / functions of III-N semiconductor devices. Summary of the Invention

[0006] overview An object of some embodiments is to provide a single-channel layer-based III-N semiconductor device that can act as both a p-channel field-effect transistor (also referred to as a p-FET) and an n-channel field-effect transistor (also referred to as an n-FET). Additionally or alternatively, an object of some embodiments is to provide a semiconductor device that can act as both a p-FET and an n-FET while occupying less circuit area. Additionally or alternatively, an object of some embodiments is to provide a semiconductor device with high switching speed.

[0007] Some embodiments provide a semiconductor device including an epitaxial layer including a barrier layer and a channel layer. The semiconductor device further includes a plurality of terminals, e.g., a first source terminal, a second source terminal, a gate terminal, a first drain terminal, a second drain terminal, and a set terminal. In certain embodiments, the first source terminal is ohmic to electrons, and the second source terminal is ohmic to holes. The first drain terminal is ohmic to electrons, and the second drain terminal is ohmic to holes. In some alternative embodiments, the first source terminal is ohmic to holes, the second source terminal is ohmic to electrons, the first drain terminal is ohmic to holes, and the second drain terminal is ohmic to electrons. The first drain terminal and the second drain terminal are interconnected by wiring to form a single output terminal. The gate terminal is disposed on the barrier layer. The set terminal is ohmic to the channel layer.

[0008] Some embodiments are based on the recognition that for a semiconductor device to function as a p-FET, the channel layer must contain holes as majority charge carriers, and for a semiconductor device to function as an n-FET, the channel layer must contain electrons as majority charge carriers. Thus, whether a semiconductor device functions as a p-FET or an n-FET depends on the majority charge carriers in the channel layer.

[0009] Some embodiments are based on the recognition that the charge carrier preference (i.e., whether the majority charge carriers are holes or electrons) in the channel layer depends on the polarization direction of the barrier layer. According to one embodiment, the barrier layer is a III-nitride compound layer, such as a scandium-doped aluminum nitride (ScAlN) layer. ScAlN materials have ferroelectric properties. Ferroelectricity is the characteristic of a material having a spontaneous electric polarization that can be reversed by applying an external electric field. All ferroelectrics are pyroelectric, with the additional property that their natural electric polarization is reversible. Therefore, the polarization direction of a barrier layer that is an ScAlN layer can be changed by applying an electric field across the barrier layer.

[0010] Since the majority charge carriers in the channel layer depend on the polarization direction of the barrier layer, and the polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer, the polarization direction of the barrier layer can be switched by applying an electric field across the barrier layer, thereby allowing the semiconductor device to be used as both an n-FET and a p-FET.

[0011] For example, a first voltage can be applied between the gate terminal and the set terminal to form a two-dimensional electron gas (2-DEG) at the interface between the barrier layer and the channel layer. When the 2-DEG exists at the interface between the barrier layer and the channel layer, the semiconductor device functions as an n-FET. Similarly, a second voltage can be applied between the gate terminal and the set terminal to form a two-dimensional hole gas (2-DHG) at the interface between the barrier layer and the channel layer. When the 2-DHG exists at the interface between the barrier layer and the channel layer, the semiconductor device functions as a p-FET. The second voltage is different from the first voltage. For example, the first voltage applied between the gate terminal and the set terminal can correspond to a positive bias voltage, and the second voltage applied between the gate terminal and the set terminal can correspond to a negative bias voltage. In this way, the semiconductor device can function as both an n-FET and a p-FET.

[0012] In one embodiment, the channel layer is a gallium nitride (GaN) layer. Specifically, the channel layer corresponds to an unintentionally doped GaN layer. GaN is a binary III / V direct bandgap semiconductor and a hard material with a wurtzite crystal structure. In one embodiment, the epitaxial layers (i.e., the barrier layer and the channel layer) are grown on a substrate by a deposition method. Examples of substrates include a sapphire substrate, a GaN substrate, a silicon substrate, and a silicon carbide (SiC) substrate. The deposition method may include, for example, molecular beam epitaxy (MBE). MBE is an epitaxial process in which material growth occurs on a heated crystalline substrate under ultra-high vacuum (UHV) conditions through the interaction of adsorbed species supplied by an atomic or molecular beam. MBE offers several properties favorable for the growth of high-purity epitaxial thin-film metals. For example, UHV conditions result in a grown film with the highest possible purity.

[0013] In some embodiments, the material of the first source terminal and the first drain terminal is different from the material of the second source terminal and the second drain terminal. In other words, the first source terminal and the first drain terminal are made of a material different from the material of the second source terminal and the second drain terminal. For example, the first source terminal and the first drain terminal are Ti-based n-type ohmic contacts, and the second source terminal and the second drain terminal are Ni-based p-type ohmic contacts. In another example, the first source terminal and the first drain terminal are gold (Au)-based n-type ohmic contacts, and the second source terminal and the second drain terminal are Au-based p-type ohmic contacts.

[0014] Alternatively, in some embodiments, the semiconductor device may include only one source terminal and one drain terminal instead of two source terminals and two drain terminals, making the design of the semiconductor device simpler and more cost-effective.

[0015]

[0006] Accordingly, one embodiment discloses a semiconductor device comprising multiple epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at the interface between the barrier layer and the channel layer. The charge carrier priority of the channel layer is based on a polarization direction of the barrier layer, and the polarization direction of the barrier layer is changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, one of which is ohmic to electrons and the other is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, one of which is ohmic to electrons and the other is ohmic to holes. The semiconductor device further comprises a gate terminal disposed on the barrier layer and a set terminal ohmic to the channel layer.

[0016] Accordingly, another embodiment discloses a semiconductor device comprising multiple epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at the interface between the barrier layer and the channel layer. The charge carrier priority of the channel layer is based on a polarization direction of the barrier layer, and the polarization direction of the barrier layer is changed by applying an electric field across the barrier layer. The semiconductor device further comprises a source terminal, a drain terminal, a gate terminal disposed on the barrier layer, and a set terminal ohmic to the channel layer. [Brief explanation of the drawings]

[0017] BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] 1 is a schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 2A] FIG. 2 is a charge balance diagram for a semiconductor device according to some embodiments of the present disclosure when functioning as an n-channel field effect transistor (n-FET). [Figure 2B] FIG. 2 is a charge balance diagram when a semiconductor device functions as a p-channel field effect transistor (p-FET), according to some embodiments of the present disclosure. [Figure 3] 1 is a schematic diagram illustrating a semiconductor device including one source terminal and one drain terminal, according to some embodiments of the present disclosure. [Figure 4] 1A-1C are schematic diagrams illustrating biaxial strain in ScxAl(1-x)N, GaxAl(1-x)N, and InxAl(1-x)N barriers pseudomorphically grown on relaxed indium nitride (InN), gallium nitride (GaN), and aluminum nitride (AlN) buffer layers, according to some embodiments of the present disclosure.

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[0018] Embodiments of the present disclosure will now be further described with reference to the accompanying drawings, in which the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] Detailed Description In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, devices and methods are shown only in block diagram form in order to avoid obscuring the present disclosure.

[0020] As used in this specification and claims, the words "for example," "for example," and "such as," as well as "comprises," "has," "includes," and other verb forms thereof, when used in conjunction with a list of one or more components or other items, should be construed as open-ended. This means that the list should not be viewed as excluding other additional components or items. The term "based on" means based at least in part on. Furthermore, it should be understood that the terms and terminology used herein are for descriptive purposes and should not be viewed as limiting. Any headings used herein are for convenience only and have no legal or limiting effect.

[0021] 1 shows a schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes an epitaxial layer including a barrier layer 101 and a channel layer 103 such that a two-dimensional carrier density is formed at an interface 119 between the barrier layer 101 and the channel layer 103. The semiconductor device 100 further includes a buffer layer 105 and a substrate 107. The semiconductor device 100 includes multiple terminals, such as a first source terminal 109 a, a second source terminal 109 b, a gate terminal 111, a first drain terminal 113 a, a second drain terminal 113 b, and a set terminal 115. The semiconductor device 100 further includes an insulating layer (not shown) between the gate terminal 111 and the barrier layer 101.

[0022] In some embodiments, one of the first source terminal 109a and the second source terminal 109b is ohmic to electrons, and the other is ohmic to holes. Furthermore, one of the first drain terminal 113a and the second drain terminal 113b is ohmic to electrons, and the other is ohmic to holes. For example, in some embodiments, the first source terminal 109a is ohmic to electrons, the second source terminal 109b is ohmic to holes, the first drain terminal 113a is ohmic to electrons, and the second drain terminal 113b is ohmic to holes. The first drain terminal 113a and the second drain terminal 113b are interconnected by a wiring 117 to form one output terminal. The gate terminal 111 is disposed on the barrier layer 101. The set terminal 115 is ohmic to the channel layer 103.

[0023] Some embodiments are based on the recognition that for semiconductor device 100 to function as a p-channel field effect transistor (also referred to as a p-FET), channel layer 103 must contain holes as majority charge carriers, and for semiconductor device 100 to function as an n-channel field effect transistor (also referred to as an n-FET), channel layer 103 must contain electrons as majority charge carriers. Therefore, whether semiconductor device 100 functions as a p-FET or an n-FET depends on the majority charge carriers in channel layer 103.

[0024] Some embodiments are based on the recognition that the charge carrier preference (i.e., whether the majority charge carriers are holes or electrons) in the channel layer 103 depends on the polarization direction of the barrier layer 101. According to one embodiment, the barrier layer 101 is a III-nitride compound layer, such as a scandium-doped aluminum nitride (ScAlN) layer. The barrier layer 101 is sometimes referred to as a "barrier." ScAlN materials have ferroelectric properties. Ferroelectricity is the characteristic of a material having a spontaneous electric polarization that can be reversed by applying an external electric field. All ferroelectrics are pyroelectric, with the additional property that their spontaneous electric polarization is reversible. Therefore, the polarization direction of the barrier layer 101, which is an ScAlN layer, can be changed by applying an electric field across the barrier layer 101.

[0025] Since the majority charge carriers in the channel layer 103 depend on the polarization direction of the barrier layer 101, and the polarization direction of the barrier layer 101 can be changed by applying an electric field across the barrier layer 101, the polarization direction of the barrier layer 101 can be switched by applying an electric field across the barrier layer 101, thereby allowing the semiconductor device 100 to be used as both an n-FET and a p-FET.

[0026] For example, a first voltage may be applied between the gate terminal 111 and the set terminal 115 to form a two-dimensional electron gas (2-DEG) at the interface 119 between the barrier layer 101 and the channel layer 103. When a 2-DEG is present at the interface 119 between the barrier layer 101 and the channel layer 103, the semiconductor device 100 functions as an n-FET. Similarly, a second voltage may be applied between the gate terminal 111 and the set terminal 115 to form a two-dimensional hole gas (2-DHG) at the interface 119 between the barrier layer 101 and the channel layer 103. When a 2-DHG is present at the interface 119 between the barrier layer 101 and the channel layer 103, the semiconductor device 100 functions as a p-FET. The second voltage is different from the first voltage. For example, the first voltage applied between the gate terminal 111 and the set terminal 115 may correspond to a positive bias voltage, and the second voltage applied between the gate terminal 111 and the set terminal 115 may correspond to a negative bias voltage.

[0027] 2A shows a charge balance diagram 200 when the semiconductor device 100 functions as an n-FET, according to some embodiments of the present disclosure. The charge balance diagram 200 is a plot of c-axis (metal polarity) 201 versus charge density 203. From the charge balance diagram 200, it can be observed that at the interface 205 between the barrier layer 101 and the channel layer 103 (representing the interface 119), the charge density 207 of the barrier layer 101 is positive and the charge density 209 of the channel layer 103 is negative. Therefore, a 2-DEG 211 exists at the interface 205 between the barrier layer 101 and the channel layer 103, and the semiconductor device 100 functions as an n-FET.

[0028] 2B shows a charge balance diagram 213 when the semiconductor device 100 functions as a p-FET according to some embodiments of the present disclosure. From the charge balance diagram 213, it can be seen that at the interface 205 between the barrier layer 101 and the channel layer 103, the charge density 215 of the barrier layer 101 is negative and the charge density 217 of the channel layer 103 is negative. Therefore, 2-DHG 219 is present at the interface 205 between the barrier layer 101 and the channel layer 103, and the semiconductor device 100 functions as a p-FET.

[0029] In this way, the semiconductor device 100 can act as both an n-FET and a p-FET.

[0030] In one embodiment, the channel layer 103 of the semiconductor device 100 is a gallium nitride (GaN) layer. Specifically, the channel layer 103 corresponds to an unintentionally doped GaN layer. GaN is a binary III / V direct bandgap semiconductor and a hard material with a wurtzite crystal structure. In one embodiment, the epitaxial layers (i.e., the barrier layer 101 and the channel layer 103) are grown on a substrate 107 by a deposition method. Examples of the substrate 107 include a sapphire substrate, a GaN substrate, a silicon substrate, and a silicon carbide (SiC) substrate. The deposition method may include, for example, molecular beam epitaxy (MBE). MBE is an epitaxial process in which material growth occurs on a heated crystalline substrate under ultra-high vacuum (UHV) conditions through the interaction of adsorbed species supplied by an atomic or molecular beam. MBE offers several properties favorable for the growth of high-purity epitaxial thin-film metals. For example, UHV conditions result in a grown film with the highest possible purity. Furthermore, the gate terminal 111 is made of a metal such as titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), tungsten (W), or platinum (Pt).

[0031] In some embodiments, the material of the first source terminal 109a and the first drain terminal 113a is different from the material of the second source terminal 109b and the second drain terminal 113b. In other words, the first source terminal 109a and the first drain terminal 113a are made of a different material from the material of the second source terminal 109b and the second drain terminal 113b. For example, the first source terminal 109a and the first drain terminal 113a are Ti-based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Ni-based p-type ohmic contacts. In another example, the first source terminal 109a and the first drain terminal 113a are gold (Au)-based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Au-based p-type ohmic contacts.

[0032] Alternatively, in some embodiments, semiconductor device 100 may include only one source terminal and one drain terminal instead of two source terminals and two drain terminals (as shown in FIG. 1), which may result in a simpler and more cost-effective design of semiconductor device 100. Such a semiconductor device is described below with reference to FIG.

[0033] 3 shows a schematic diagram of a semiconductor device 300 according to some embodiments of the present disclosure. The semiconductor device 300 includes a barrier layer 101, a channel layer 103, a buffer layer 105, and a substrate 107. Furthermore, the semiconductor device 100 includes multiple terminals, such as a source terminal 301, a drain terminal 303, a gate terminal 111, and a set terminal 115. The source terminal 301 and the drain terminal 303 are disposed on the channel layer 103. The source terminal 301 and the drain terminal 303 are made of the same material. For example, the source terminal 301 and the drain terminal 303 are Ni-based p-type ohmic contacts. Because the barrier layer 101 of the semiconductor device 300 (and the semiconductor device 100) is made of a III-nitride material, the semiconductor device 300 (and similarly the semiconductor device 100) may also be referred to as a III-nitride semiconductor device.

[0034] Since the ferroelectric properties of ScAlN (i.e., barrier layer 101) enable semiconductor device 100 (or semiconductor device 300) to act as both an n-FET and a p-FET, it is essential to model various material-based parameters of ScAlN, such as lattice parameters, strain parameters, piezoelectric polarization, spontaneous polarization, etc. Various material-based parameters of ScAlN are described below.

[0035] Calculation of lattice parameters and distortion:

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[0038] Wurtzite Sc x Al (1-X) Theoretical approaches and experimental measurements for N are limited to Sc concentrations of 0≦x≦0.5 due to the predicted phase transition to a cubic structure at about x=0.45±0.05.

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[0043] Piezoelectric polarization:

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[0052] For the same biaxial strain ε1 and alloy composition x, Sc x Al (1-X) The value of the piezoelectric polarization of N is In x Al (1-x) N and Ga x Al (1-x) It becomes large compared to N.

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[0055] From Fig. 7, it can be observed that the piezoelectric polarization increases with increasing number of Al atoms substituted by another metal atom (Me = Sc, Ga, In), regardless of the chosen binary buffer layer. For heterostructures grown on AlN buffer layers, the piezoelectric polarization of the barrier is always positive (oriented along the <0001> axis) and is 0.028 C / m for the GaN / AlN heterostructure, In0.20Al0.80N / AlN heterostructure, and Sc0.21Al0.79N / AlN heterostructure, respectively. 2 , 0.057C / m 2 and 0.089 C / m 2 The piezoelectric barrier polarization of the InxAl1-xN / GaN and ScxAl1-xN / GaN heterostructures is also positive for x > 0.18 and x > 0.20, and reaches a maximum value of 0.053 C / m for x = 0.39 and x = 0.38, respectively. 2 and 0.153 C / m 2 For 0≦x<0.18 and 0≦x<0.20, the barriers of InxAl1-xN / GaN and ScxAl1-xN / GaN heterostructures as well as the barrier of GaxAl1-xN / GaN heterostructures exhibit negative piezoelectric polarization, with the highest value for AlN / GaN reaching −0.058 C / m 2 This becomes:

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[0057] Spontaneous and total polarization:

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[0060] For metallic-polar GaAlN, InAlN, and ScAlN barriers, as well as for the buffer layer, the spontaneous polarization is oriented along the <0001> direction. The spontaneous polarization value decreases when Al atoms are substituted by Ga or In, whereas it increases significantly when Al atoms are substituted by Sc atoms.

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[0064] Furthermore, from Figure 9, it is observed that the polarization-induced surface sheet charge of the pseudomorphic heterostructure is always negative. x Al 1-x N / GaN heterostructure and Sc x Al 1-x In the case of the barrier of an InN / GaN heterostructure, and 0≦x<0.11, x Al 1-x For N / GaN heterostructures, -6.2 × 10 13 cm -2 A negative polarization-induced surface sheet charge is observed, which is less than that of the lattice-matched Sc 0.20 Al 0.80 N / GaN heterostructure and In 0.18 Al 0.82For the N / GaN heterostructure, it is −7.99×10 13 cm -2 and -4.17 × 10 13 cm -2 These sheet charges are equivalent to about 8 and 4 elementary electron charges per 100 surface atoms. The positive bond sheet charges at the bottom of the relaxed InN, GaN, and AlN buffer crystals are induced solely by the gradient in spontaneous polarization and are 2.62 × 10, respectively. 13 cm -2 , 2.12 × 10 13 cm -2 , and 5.56 × 10 13 cm -2 It is calculated to be:

[0065] Sheet charge density and polarization-induced 2-DEG:

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[0069] To describe the physical properties of the barrier depending on the alloy composition in the interval of x, the following interpolation is used:

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[0077] When the barrier thickness is larger than the space charge zone, the electron sheet charge is d, independent of the alloy composition of the MeAlN barrier. MeA1N This tendency for increase is due to the reduction in depletion caused by the Ni gate contact when the distance between the Schottky contact and the electron storage location is increased.

[0078] The semiconductor device 100 (or the semiconductor device 300) can be used as a logic inverter. For example, when the semiconductor device 100 functions as a p-FET, the semiconductor device 100 outputs a "1" (high) for an input "0" (low). When the semiconductor device 100 functions as an n-FET, the semiconductor device outputs a "0" for an input "1". Because the semiconductor device 100 can be used as both an n-FET and a p-FET, an inverter circuit using the semiconductor device 100 has a smaller area, which reduces capacitance. As a result, the switching speed is faster. Furthermore, such an inverter based on the semiconductor device 100 can be applied to the design of logic gates and other more complex digital circuits.

[0079] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with an enablement description for implementing one or more exemplary embodiments. Various changes are contemplated that may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosed subject matter as set forth in the appended claims.

[0080] In the following description, specific details are provided to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that the embodiments may be practiced without these specific details. For example, systems, processes, and other elements of the disclosed subject matter may be shown as components in block diagram form in order to avoid obscuring the embodiments in unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. Furthermore, like reference numbers and names in the various drawings indicate like elements.

[0081] Also, particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations can be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process may terminate when its operations are completed, but may include additional steps not described or included in the diagram. Moreover, not all operations in any specifically described process may be performed in all embodiments. A process may correspond to a method, a function, a procedure, a subroutine, a subordinate program, etc. When a process corresponds to a function, the end of the function may correspond to a return of the function to the calling function or the main function.

[0082] The embodiments of the present disclosure may be embodied as methods, which are presented as examples. The operations performed as part of the method may be ordered in any suitable manner. Thus, while the exemplary embodiments are shown as sequential operations, embodiments may be constructed in which the operations are performed in a different order than that shown, including performing some operations simultaneously.

[0083] Although the present disclosure has been described with reference to certain preferred embodiments, it is to be understood that various other adaptations and modifications can be made within the spirit and scope of the disclosure. It is, therefore, the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, a charge carrier priority of the channel layer is based on a polarization direction of the barrier layer, and the polarization direction of the barrier layer is changed by applying an electric field across the barrier layer; and the semiconductor device further comprises: a first source terminal and a second source terminal, one of the first source terminal and the second source terminal being ohmic to electrons and the other being ohmic to holes; a first drain terminal and a second drain terminal, one of the first drain terminal and the second drain terminal being ohmic to electrons and the other being ohmic to holes; a gate terminal disposed on the barrier layer; a set terminal that is ohmic with respect to the channel layer.

2. The semiconductor device of claim 1 , wherein the barrier layer comprises a scandium-doped aluminum nitride (ScAlN) layer.

3. The semiconductor device of claim 1 , wherein the channel layer comprises a gallium nitride (GaN) layer.

4. 2. The semiconductor device of claim 1, wherein a material of the first source terminal and the first drain terminal is different from a material of the second source terminal and the second drain terminal.

5. 10. The semiconductor device of claim 1, wherein the first source terminal and the first drain terminal are titanium (Ti) based n-type ohmic contacts.

6. 10. The semiconductor device of claim 1, wherein the second source terminal and the second drain terminal are nickel (Ni) based p-type ohmic contacts.

7. 10. The semiconductor device of claim 1, wherein the gate terminal is made of one of titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), tungsten (W), or platinum (Pt).

8. The semiconductor device of claim 1 , wherein the first drain terminal and the second drain terminal are interconnected by a wire.

9. The semiconductor device of claim 1 , further comprising an insulating layer between the gate terminal and the barrier layer.

10. 10. The semiconductor device of claim 1, wherein the epitaxial layer is grown on a substrate by molecular beam epitaxy (MBE), the substrate being one of a sapphire substrate, a GaN substrate, a silicon substrate, or a silicon carbide (SiC) substrate.

11. A semiconductor device comprising: a plurality of epitaxial layers including a barrier layer and a channel layer such that a two-dimensional carrier density is formed at an interface between the barrier layer and the channel layer, a charge carrier priority of the channel layer is based on a polarization direction of the barrier layer, and the polarization direction of the barrier layer is changed by applying an electric field across the barrier layer; and the semiconductor device further comprises: a source terminal disposed on the channel layer; a drain terminal disposed on the channel layer; a gate terminal disposed on the barrier layer; a set terminal that is ohmic with respect to the channel layer.

12. The semiconductor device of claim 11 , wherein the source terminal and the drain terminal are made of the same material.

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