Photoelectric conversion device

Abstract

To solve the problem in which: breakdown voltage changes over time due to concentration of an electric field at an end of a cathode area or injection of a hot carrier to an interface of a semiconductor substrate.SOLUTION: A photoelectric conversion device has an avalanche diode arranged on a semiconductor layer having a first surface and a second surface opposite to the first surface. The avalanche diode has a first semiconductor area of a first conductivity type arranged at a first depth, a second semiconductor area of a second conductivity type arranged at a second depth deeper than the first depth with respect to the second surface, a third semiconductor area provided in contact with an end of the first semiconductor area in plan view, first wiring connected with the first semiconductor area, second wiring connected with the second semiconductor area, and third wiring at least partially overlapping the third semiconductor area in plan view. A third voltage supplied to the third wiring has a value between a first voltage supplied to the first wiring and a second voltage supplied to the second wiring.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] There is a photoelectric conversion device in which a reflector is provided in the wiring layer to reflect incident light that has passed through a semiconductor substrate, thereby lengthening the optical path length of the incident light within the photoelectric conversion element and improving the quantum conversion efficiency. Patent Document 1 describes a single-photon avalanche diode (SPAD) that uses an anode wiring as a reflector. Similarly, Patent Document 2 describes a single-photon avalanche diode (SPAD) that has an extended anode wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0286946 [Patent Document 2] US Patent Application Publication No. 2019 / 0181177 Summary of the Invention [Problem to be solved by the invention]

[0004] In the structure described in Patent Document 1, because the cathode wiring is located directly above the guard ring region, there is a problem that hot carriers are trapped near the cathode region, changing the potential around the strong electric field region and causing the breakdown voltage to change over time. Also, in the structure described in Patent Document 2, there is a concern that the anode wiring located directly above the guard ring region causes the electric field to concentrate at the edge of the cathode region, increasing the DCR (Dark Count Rate).

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to reduce the change over time in breakdown voltage caused by injection of hot carriers into the semiconductor substrate interface while suppressing DCR. [Means for solving the problem]

[0006] One aspect of the present invention is The light incident surface A photoelectric conversion device having an avalanche diode disposed in a semiconductor layer having a first surface and a second surface opposite to the first surface, wherein the avalanche diode comprises: With respect to the second surface a first semiconductor region of a first conductivity type arranged at a first depth, a second semiconductor region of a second conductivity type arranged at a second depth that is deeper than the first depth relative to the second surface, and a third semiconductor region provided in contact with an end portion of the first semiconductor region in a plan view; The photoelectric conversion device comprises: a first wiring connected to the first semiconductor region and a second wiring connected to the second semiconductor region, at least partially overlapping the third semiconductor region in a plan view; does not overlap the first semiconductor region, The aforementioned Avalanche diode A third wire that is not connected; Further Has, an avalanche multiplication region is formed across the first semiconductor region and the second semiconductor region, and the impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region; The third voltage supplied to the third wiring is a value between the first voltage supplied to the first wiring and the second voltage supplied to the second wiring. [Effects of the Invention]

[0007] According to the present invention, it is possible to reduce the change over time in breakdown voltage caused by injection of hot carriers into the semiconductor substrate interface while suppressing DCR. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a photoelectric conversion device according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram of a PD substrate of the photoelectric conversion device according to the embodiment. [Figure 3] FIG. 2 is a schematic diagram of a circuit board of a photoelectric conversion device according to an embodiment. [Figure 4]2 is a configuration example of a pixel circuit of a photoelectric conversion device according to an embodiment. [Figure 5] FIG. 2 is a schematic diagram illustrating driving of a pixel circuit of a photoelectric conversion device according to an embodiment. [Figure 6] 1 is a cross-sectional view of a photoelectric conversion element according to a first embodiment. [Figure 7] FIG. 1 is a plan view of a photoelectric conversion element according to a first embodiment. [Figure 8] FIG. 2 is a potential diagram of the photoelectric conversion element according to the first embodiment. [Figure 9] FIG. 3 is a diagram showing the potential and electric field intensity of the photoelectric conversion element according to the first embodiment. [Figure 10] FIG. 3 is a diagram showing an example of voltage setting of a photoelectric conversion element according to the first embodiment. [Figure 11] FIG. 4 is a cross-sectional view of a photoelectric conversion element according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a photoelectric conversion element according to a third embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a photoelectric conversion element according to a fourth embodiment. [Figure 14] FIG. 10 is a functional block diagram of a photoelectric conversion system according to a fifth embodiment. [Figure 15] FIG. 10 is a functional block diagram of a photoelectric conversion system according to a sixth embodiment. [Figure 16] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a seventh embodiment. [Figure 17] FIG. 13 is a functional block diagram of a photoelectric conversion system according to an eighth embodiment. [Figure 18] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0012] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and the signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region, which has majority carriers of charges with the same polarity as the signal charge, is an N-type semiconductor region, and the second conductivity type semiconductor region, which has majority carriers of charges with a polarity opposite to that of the signal charge, is a P-type semiconductor region. The present invention also applies when the cathode of the APD is set to a fixed potential, and the signal is extracted from the anode side. In this case, the first conductivity type semiconductor region, which has majority carriers of charges with the same polarity as the signal charge, is a P-type semiconductor region, and the second conductivity type semiconductor region, which has majority carriers of charges with a polarity opposite to that of the signal charge, is an N-type semiconductor region. The following description focuses on the case where one node of the APD is set to a fixed potential, but the potentials of both nodes may fluctuate.

[0013] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0014] A configuration common to each embodiment of a photoelectric conversion device and a driving method thereof according to the present invention will be described with reference to FIGS. 1 to 5. FIG.

[0015] FIG. 1 is a diagram showing the configuration of a stacked photoelectric conversion device 100 according to an embodiment of the present invention. The photoelectric conversion device 100 is configured by stacking and electrically connecting two substrates: a sensor substrate 11 and a circuit substrate 21. The sensor substrate 11 has a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric conversion device 100 is configured by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in this order. The photoelectric conversion device described in each embodiment is a back-illuminated photoelectric conversion device in which light is incident from a first surface and a circuit substrate is disposed on a second surface.

[0016] In the following description, the sensor substrate 11 and the circuit substrate 21 are described as diced chips, but are not limited to chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in the wafer state and then diced, or may be chipped and then stacked and bonded.

[0017] The sensor substrate 11 has a pixel region 12 arranged thereon, and the circuit substrate 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0018] 2 is a diagram showing an example of the arrangement of the sensor substrate 11. Pixels 101, each having a photoelectric conversion element 102 including an avalanche photodiode (hereinafter, referred to as APD), are arranged in a two-dimensional array in plan view to form a pixel region 12.

[0019] The pixel 101 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. In other words, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0020] 3 is a configuration diagram of the circuit board 21. It has a signal processing unit 103 that processes the charges photoelectrically converted by the photoelectric conversion element 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0021] The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0022] The vertical scanning circuit unit 110 receives a control pulse supplied from the control pulse generating unit 115 and supplies the control pulse to each pixel. The vertical scanning circuit unit 110 uses logic circuits such as a shift register and an address decoder.

[0023] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and the memory holds digital values.

[0024] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0025] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0026] The signal output to the signal line 113 is output via an output circuit 114 to a recording unit or a signal processing unit outside the photoelectric conversion device 100 .

[0027] In Fig. 2, the photoelectric conversion elements in the pixel region may be arranged one-dimensionally. The effects of the present invention can be obtained even with a single pixel, and the case of a single pixel is also included in the present invention. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element; for example, a single signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0028] 2 and 3, a plurality of signal processing units 103 are arranged in a region overlapping the pixel region 12 in a plan view. A vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, column circuits 112, output circuits 114, and a control pulse generating unit 115 are arranged so as to overlap between an edge of the sensor substrate 11 and an edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged around the pixel region 12, and the vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the column circuits 112, the output circuits 114, and the control pulse generating unit 115 are arranged in a region overlapping the non-pixel region in a plan view.

[0029] FIG. 4 is an example of a block diagram including the equivalent circuits of FIGS.

[0030] In FIG. 2, the photoelectric conversion element 102 having the APD 201 is provided on a sensor substrate 11, and the other members are provided on a circuit board 21.

[0031] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With this voltage supplied, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0032] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode are operated at a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode are operated at a potential difference close to or less than the breakdown voltage.

[0033] An APD operated in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is −30 V, and the voltage VH (second voltage) is 1 V. The APD 201 may be operated in either linear mode or Geiger mode. A SPAD is preferable because the potential difference is larger than that of a linear mode APD, resulting in a more pronounced effect in terms of withstand voltage.

[0034] The quench element 202 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The quench element 202 also functions to return the voltage supplied to the APD 201 to voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0035] The signal processing unit 103 has a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may have any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0036] The waveform shaping unit 210 shapes the potential change at the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While an example using one inverter as the waveform shaping unit 210 is shown in FIG. 4, a circuit in which multiple inverters are connected in series, or another circuit having a waveform shaping effect, may also be used.

[0037] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0038] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 3 via a drive line 214 (not shown in Fig. 3) in Fig. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0039] The electrical connection may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0040] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0041] FIG. 5 is a diagram showing a schematic diagram of the relationship between the operation of an APD and an output signal.

[0042] Fig. 5(a) is a diagram illustrating the APD 201, quench element 202, and waveform shaping unit 210 of Fig. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. Fig. 5(b) shows the waveform change at node A in Fig. 5(a), and Fig. 5(c) shows the waveform change at node B in Fig. 5(a).

[0043] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. As the voltage drop increases and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, as shown at time t2, and the voltage level at node A drops no more than a certain value. After that, between time t2 and time t3, a current flows through node A from voltage VL to compensate for the voltage drop, and at time t3, node A settles to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0044] The arrangement of the signal lines 113, the column circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the signal lines 113 may be arranged to extend in the row direction, and the column circuits 112 may be arranged at the ends of the signal lines 113.

[0045] The photoelectric conversion devices of the respective embodiments will be described below.

[0046] (First embodiment) The photoelectric conversion device according to the first embodiment will be described with reference to FIGS.

[0047] FIG. 6 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the first embodiment, taken in a direction perpendicular to the surface direction of the substrate, and corresponds to the AA' cross section in FIG. 7(a).

[0048] The structure and function of the photoelectric conversion element 102 will be described. The photoelectric conversion element 102 has an N-type first semiconductor region 311, a third semiconductor region 313, a fifth semiconductor region 315, and a sixth semiconductor region 316. It also includes a P-type second semiconductor region 312, a fourth semiconductor region 314, a seventh semiconductor region 317, and a ninth semiconductor region 319.

[0049] 6, an N-type first semiconductor region 311 is formed near the surface facing the light incident surface, and an N-type third semiconductor region 313 is formed around it. A P-type second semiconductor region 312 is formed at a position overlapping the first semiconductor region and the second semiconductor region in plan view. An N-type fifth semiconductor region 315 is further disposed at a position overlapping the second semiconductor region 312 in plan view, and an N-type sixth semiconductor region 316 is formed around it.

[0050] The first semiconductor region 311 has a higher N-type impurity concentration than the third semiconductor region 313 and the fifth semiconductor region 315. A PN junction is formed between the P-type second semiconductor region 312 and the N-type first semiconductor region 311. By making the impurity concentration of the second semiconductor region 312 lower than that of the first semiconductor region 311, the entire region of the second semiconductor region 312 that overlaps the center of the first semiconductor region in a planar view becomes a depletion layer region. At this time, the potential difference between the first semiconductor region 311 and the second semiconductor region 312 is greater than the potential difference between the second semiconductor region 312 and the fifth semiconductor region 315. Furthermore, this depletion layer region extends to a portion of the first semiconductor region 311, and a strong electric field is induced in the extended depletion layer region. This strong electric field causes avalanche multiplication in the depletion layer region that extends to the portion of the first semiconductor region 311, and a current based on the amplified charge is output as a signal charge. When light incident on the photoelectric conversion device 102 is photoelectrically converted and avalanche multiplication occurs in this depletion layer region (avalanche multiplication region), the generated charges of the first conductivity type are collected in the first semiconductor region 311.

[0051] 6, the third semiconductor region 313 and the fifth semiconductor region 315 are formed to have approximately the same size, but the size of each semiconductor region is not limited to this. For example, the fifth semiconductor region 315 may be formed to be larger than the third semiconductor region 313, so that charges are collected in the first semiconductor region 311 from a wider range.

[0052] Furthermore, the third semiconductor region 313 may be a P-type semiconductor region instead of an N-type semiconductor region. In this case, the impurity concentration of the third semiconductor region 313 is set to be lower than the impurity concentration of the second semiconductor region 312. If the impurity concentration of the third semiconductor region 313 is too high, an avalanche multiplication region will be formed between the third semiconductor region 313 and the first semiconductor region 311, resulting in an increase in DCR (Dark Count Rate).

[0053] A trench-based uneven structure 325 is formed on the surface of the semiconductor layer facing the light incident surface. The uneven structure 325 is surrounded by a P-type fourth semiconductor region 314 and scatters light incident on the photoelectric conversion element 102. Because incident light travels obliquely through the photoelectric conversion element, an optical path length equal to or greater than the thickness of the semiconductor layer 301 can be ensured, enabling photoelectric conversion of light with longer wavelengths than without the uneven structure 325. Furthermore, the uneven structure 325 prevents reflection of incident light within the substrate, thereby improving the photoelectric conversion efficiency of the incident light. Furthermore, by combining this with a third wiring 331C shaped to cover the surface of the semiconductor substrate facing the light incident surface, which is a feature of the present invention, the third wiring 331C efficiently reflects light diffracted obliquely by the uneven structure 325, further improving near-infrared sensitivity. The uneven structure 325 is not an essential component of the present invention, and the effects of the present invention can be achieved even with a photoelectric conversion element without the uneven structure 325.

[0054] The fifth semiconductor region 315 and the concave-convex structure 325 are formed so as to overlap in a planar view. The area where the fifth semiconductor region 315 and the concave-convex structure 325 overlap in a planar view is larger than the area of ​​the portion of the fifth semiconductor region 315 that does not overlap with the concave-convex structure 325. Charges generated at a position far from the avalanche multiplication region formed between the first semiconductor region 311 and the fifth semiconductor region 315 take longer to travel to the avalanche multiplication region than charges generated at a position close to the avalanche multiplication region. This may increase timing jitter. By arranging the fifth semiconductor region 315 and the concave-convex structure 325 so as to overlap in a planar view, the electric field deep in the photodiode can be increased, shortening the collection time of charges generated at a position far from the avalanche multiplication region, thereby reducing timing jitter.

[0055] Furthermore, the fourth semiconductor region 314 three-dimensionally covers the concave-convex structure, which can suppress the generation of thermally excited charges at the interface of the concave-convex structure, thereby suppressing the DCR of the photoelectric conversion element.

[0056] Pixels are separated from each other by a pixel isolation portion 324 with a trench structure, and a seventh P-type semiconductor region 317 formed around it separates adjacent photoelectric conversion elements from each other by a potential barrier. Since the photoelectric conversion elements are also separated by the potential of the seventh semiconductor region 317, a trench structure such as the pixel isolation portion 324 is not essential as a pixel isolation portion, and even when providing the pixel isolation portion 324 with a trench structure, its depth and position are not limited to the configuration of FIG. 6. The pixel isolation portion 324 may be a DTI (deep trench isolation) that penetrates the semiconductor layer, or a DTI that does not penetrate the semiconductor layer. Metal may be embedded in the DTI to improve the light shielding performance. The pixel isolation portion 324 may be composed of SiO, a fixed charge film, a metal member, polysilicon, or a combination of a plurality of them. The pixel isolation portion 324 may be configured to surround the entire circumference of the photoelectric conversion element in plan view, or may be configured only at the opposite side portions of the photoelectric conversion element, for example. A voltage may be applied to the embedded member to induce charges at the trench interface to suppress DCR.

[0057] The distance from the pixel isolation portion to the pixel isolation portion of an adjacent pixel or a pixel provided at the closest position can also be regarded as the size of one photoelectric conversion element 102. When the size of one photoelectric conversion element 102 is L, the distance d from the light incident surface to the avalanche multiplication region satisfies L√2 / 4 < d < L×√2. When the size and depth of the photoelectric conversion element satisfy this relational expression, the electric field strength in the depth direction and the electric field strength in the plane direction in the vicinity of the first semiconductor region 311 become approximately the same. Since the variation in the time taken for charge collection can be suppressed, the timing jitter can be improved.

[0058] On the light incident surface side of the semiconductor layer, a pinning film 321, a planarization film 322, and a microlens 323 are further formed. A filter layer (not shown) or the like may be further arranged on the light incident surface side. Various optical filters such as a color filter, an infrared cut filter, and a monochrome filter can be used for the filter layer. For the color filter, an RGB color filter, an RGBW color filter, or the like can be used.

[0059] A wiring structure including a conductor and an insulating film is provided on the surface of the semiconductor layer facing the light incident surface. The photoelectric conversion element 102 shown in FIG. 6 has, from the side closest to the semiconductor layer, an oxide film 341 and a protective film 342, and further has a wiring layer made of a conductor laminated thereon. An interlayer film 343, which is an insulating film, is provided between the wiring and the semiconductor layer and between the wiring layers. The protective film 342 is a film that protects the avalanche diode from plasma damage and metal contamination during etching. SiN, a nitride film, is generally used, but SiON, SiC, SiCN, etc. may also be used.

[0060] The cathode wiring 331A (first wiring) is connected to the first semiconductor region 311 and supplies a cathode voltage (first voltage). The anode wiring 331B (second wiring) supplies an anode voltage (second voltage) to the seventh semiconductor region 317 via the ninth semiconductor region 319, which is an anode contact. The third wiring 331C is disposed between the cathode wiring 331A and the anode wiring 331B and is supplied with a third voltage that is higher than the anode voltage and lower than the cathode voltage. In other words, the third voltage is set to a value between the cathode voltage (first voltage) and the anode voltage (second voltage). Note that if the first semiconductor region 311 is a P-type semiconductor region and the second semiconductor region 312 is an N-type semiconductor region, the third wiring 331C is supplied with a third voltage that is higher than the anode voltage and lower than the cathode voltage.

[0061] In this embodiment, the cathode wiring 331A, the anode wiring 331B, and the third wiring 331C are formed in the same wiring layer. The wiring is made of a conductor containing a metal such as Cu or Al. In this cross section, the outer periphery of the cathode wiring is designated 332A, and the inner periphery of the third wiring 331C facing 332A is designated 332B. The dotted line 332C is a virtual line that divides the distance between the outer periphery of the cathode wiring 332A and the inner periphery of the third wiring 331C at an equal distance. Furthermore, the outer periphery of the third wiring 331C facing the anode wiring 331B is designated by the dotted line 332D.

[0062] 7A and 7B are plan views of two pixels of the photoelectric conversion device according to the first embodiment, in which Fig. 7A is a plan view seen from the surface opposite to the light incident surface, and Fig. 7B is a plan view seen from the light incident surface side.

[0063] 7(a), the first semiconductor region 311, the third semiconductor region 313, and the fifth semiconductor region 315 are circular and arranged concentrically. This structure suppresses localized electric field concentration at the edge of the strong electric field region between the first semiconductor region 311 and the second semiconductor region 312, thereby achieving the effect of reducing DCR. The shape of each semiconductor region is not limited to a circle, and may be, for example, a polygon with its center of gravity aligned.

[0064] The dotted lines on the first semiconductor region 311 and the third semiconductor region 313 indicate the ranges in which the cathode wiring 331A and the third wiring 331C are provided in a plan view. The cathode wiring 331A is circular in a plan view. The third wiring 331C has a surface with a circular hole at its inner periphery, and at least a portion of the third wiring 331C overlaps the third semiconductor region in a plan view. Here, in FIG. 7, the inner peripheries of the holes provided in the cathode wiring 331A and the third wiring 331C are circular, but the wiring shape is not limited to this and may be a polygon, such as a hexagon or octagon. Also, in FIG. 7, the third wiring 331C and the third semiconductor region are approximately the same size, but the planar shape of the third wiring 331C is not limited to this.

[0065] An avalanche multiplication region is formed between the first semiconductor region 311 and the second semiconductor region 312 in the depth direction, and an electric field relaxation region is provided to surround this avalanche multiplication region. The electric field relaxation region does not need to cover the entire periphery of the avalanche multiplication region; it only needs to cover a portion of the periphery of the avalanche multiplication region. The boundary between the anode wiring 331B and the insulating film facing the cathode wiring 331A overlaps this electric field relaxation region in a plan view. Alternatively, it can be said that an imaginary line 332C equally dividing the distance between the cathode wiring outer periphery 332A and the anode wiring inner periphery 332B overlaps the electric field relaxation region.

[0066] 7(a) in the AA' direction (diagonal direction of the pixel), and is not formed in the BB' direction cross section (opposite side direction of the pixel). In the BB' direction cross section, the ninth semiconductor region 319 is not formed, but instead the seventh semiconductor region 317 extends to the surface facing the light incident surface.

[0067] In FIG. 7(b), the concave-convex structure 325 is formed in a lattice shape in a plan view. The concave-convex structure 325 is formed so as to overlap the first semiconductor region 311 and the fifth semiconductor region 315, and the center of gravity of the concave-convex structure 325 is contained within the avalanche multiplication region in a plan view. In the lattice-shaped trench structure shown in FIG. 7(b), the trench depth at the trench intersection is deeper than the trench depth at the trench portion where the trench extends alone. However, the bottom of the trench at the trench intersection is located closer to the light incident surface than half the thickness of the semiconductor layer. Here, the trench depth is the depth from the second surface to the bottom, and can also be referred to as the depth of the recess of the concave-convex structure 325.

[0068] FIG. 8 is a potential diagram of the photoelectric conversion element 102 shown in FIG.

[0069] Dotted line 70 in FIG. 8 indicates the potential distribution of line segment FF' in FIG. 6, and solid line 71 in FIG. 8 indicates the potential distribution of line segment EE' in FIG. 6. FIG. 8 shows the potential as seen from electrons, which are the main carrier charge in the N-type semiconductor region. If the main carrier charge is holes, the relationship between high and low potentials is reversed. Depth A (first depth) in FIG. 8 corresponds to height A in FIG. 6. Similarly, depth B (third depth) corresponds to height B, depth C corresponds to height C, and depth D (second depth) corresponds to height D.

[0070] 8, the potential height of the solid line 71 at depth A is A1, the potential height of the dotted line 70 is A2, the potential height of the solid line 71 at depth B is B1, and the potential height of the dotted line 70 is B2. Also, the potential height of the solid line 71 at depth C is C1, the potential height of the dotted line 70 is C2, and the potential height of the solid line 71 at depth D is D1, and the potential height of the dotted line 70 is D2.

[0071] 6 and 8, the potential height of the first semiconductor region 311 corresponds to A1, and the potential height near the center of the second semiconductor region 312 corresponds to B1. In addition, the potential height of the fifth semiconductor region 315 corresponds to A2, and the potential height of the outer edge of the second semiconductor region 312 corresponds to B2.

[0072] With respect to the dotted line 70 in Figure 8, the potential gradually decreases from depth D to depth C. Then, the potential gradually increases from depth C to depth B, and the potential reaches the B2 level at depth B. Furthermore, the potential decreases from depth B to depth A, and reaches the A2 level at depth A.

[0073] On the other hand, with respect to the solid line 71, the potential gradually decreases from depth D to depth C and from depth C to depth B, reaching level B1 at depth B. Then, the potential sharply decreases from depth B to depth A, reaching level A1 at depth A. At depth D, the potentials of the dotted line 70 and the solid line 71 are approximately the same height, and in the regions indicated by line segments EE' and FF', there is a potential gradient that gradually decreases toward the second surface of the semiconductor layer 301. Therefore, charges generated in the photodetector move toward the second surface due to the gentle potential gradient.

[0074] In the avalanche diode of this embodiment, the P-type second semiconductor region 312 has a lower impurity concentration than the N-type first semiconductor region 311, and potentials are supplied to the first semiconductor region 311 and the second semiconductor region 312 such that they are reverse biased to each other. As a result, a depletion layer region is formed on the second semiconductor region 312 side. With this structure, the second semiconductor region 312 acts as a potential barrier for charges photoelectrically converted in the fourth semiconductor region 314, making it easier for the charges to be collected in the first semiconductor region 311.

[0075] In FIG. 6 , the second semiconductor region 312 is formed over the entire surface of the photoelectric conversion element. However, for example, the portion overlapping the first semiconductor region 311 in plan view may be an N-type semiconductor region without the P-type second semiconductor region 312. The impurity concentration of this N-type semiconductor region is set lower than the impurity concentration of the first semiconductor region 311. When an N-type semiconductor layer is used, the second semiconductor region 312 may not be provided in the portion overlapping the first semiconductor region 311 in plan view. In this case, it is also possible to recognize that a fourth semiconductor region 314 having a slit is formed. In this case, due to the potential difference between the second semiconductor region 312 and the slit portion, the potential decreases from the line segment FF' to the line segment EE' at depth C in FIG. 6 . This facilitates the movement of charges photoelectrically converted in the fourth semiconductor region 314 toward the first semiconductor region 311. On the other hand, when the second semiconductor region 312 is formed over the entire surface as shown in Figure 6, the applied voltage to obtain the strong electric field required for avalanche multiplication can be lowered compared to when a slit is formed, and noise caused by the formation of a localized strong electric field region can be suppressed.

[0076] The charges that have moved to the vicinity of the second semiconductor region 312 are accelerated by the steep potential gradient from depth B to depth A of the solid line 71 in FIG. 8, that is, by the strong electric field, and are avalanche multiplied.

[0077] In contrast, the potential distribution between the fifth semiconductor region 315 and the P-type second semiconductor region 312 in Fig. 6, i.e., from depth B to depth A of the dotted line 70 in Fig. 8, is such that avalanche multiplication does not occur. Therefore, the charge generated in the fourth semiconductor region 314 can be counted as signal charge without increasing the area of ​​the strong electric field region (avalanche multiplication region) relative to the size of the photodiode. Note that although the fifth semiconductor region 315 has been described so far as having an N-type conductivity, it may also be a P-type semiconductor region as long as its concentration satisfies the above-mentioned potential relationship.

[0078] Furthermore, the charges photoelectrically converted in the second semiconductor region 312 flow into the fourth semiconductor region 314 due to the potential gradient from depth B to depth C of the dotted line 70 in FIG. 8. For the reasons described above, the fourth semiconductor region 314 has a structure in which the charges easily move to the second semiconductor region 312. Therefore, the charges photoelectrically converted in the second semiconductor region 312 move to the first semiconductor region 311 and are detected as signal charges by avalanche multiplication. Therefore, the fourth semiconductor region 314 is sensitive to the charges photoelectrically converted in the second semiconductor region 312.

[0079] 3. In addition, dotted line 70 in FIG. 8 indicates the cross-sectional potential of line segment FF' in FIG. 3. In the dotted line 70, the intersection of height A and line segment FF' in FIG. 6 is denoted as A2, the intersection of height B and line segment FF' is denoted as B2, the intersection of height C and line segment FF' is denoted as C2, and the intersection of height D and line segment FF' is denoted as D2. Electrons photoelectrically converted in the fourth semiconductor region 314 in FIG. 6 move along the potential D2 to C2 in FIG. 8. However, the electrons cannot overcome the potential barrier between C2 and B2. Therefore, the electrons move to the center of the fourth semiconductor region 314 in FIG. 6, indicated by line segment EE'. The electrons move along the potential gradient from C1 to B1 in FIG. 8, are avalanche-multiplied by the steep potential gradient from B1 to A1, and are detected as signal charges after passing through the first semiconductor region 311.

[0080] 6 moves along the potential gradient from potential B2 to C2 in FIG. 8. Then, as described above, it moves to the center of the fourth semiconductor region 314 indicated by the line segment EE' in FIG. 6. Then, it is avalanche-multiplied by the steep potential gradient from B1 to A1. The avalanche-multiplied charges pass through the first semiconductor region 311 and are detected as signal charges.

[0081] Here, a strong electric field is applied around the first semiconductor region, causing an imbalance in the thermal state between the sensor substrate and the carriers, resulting in the generation of hot carriers. Hot carriers are trapped in trap sites around the cathode region near the wiring layer. As the number of trapped hot carriers increases over time, the potential near the cathode region and the electric field strength in the strong electric field region also change over time, raising concerns about changes in the breakdown voltage over time.

[0082] Fig. 9(a) is a schematic diagram of the potential distribution between the ZZ' cross sections in Fig. 6, and Fig. 9(b) is a schematic diagram of the electric field intensity distribution between the XX' cross sections in Fig. 6. In Figs. 9(a) and 9(b), the solid line shows the case where the third wiring 331C is not arranged, the dashed-dotted line shows the case where an intermediate potential higher than the anode potential and lower than the cathode potential is supplied to the third wiring 331C, and the dashed line shows the case where the anode potential is supplied to the third wiring 331C.

[0083] To suppress changes in the breakdown voltage over time, it is desirable that the potential at height A be higher than the minimum potential between height A and height Z in the Z-Z' cross section in the third semiconductor region 313. In other words, it is desirable that a potential barrier be formed at height A with respect to the height at which the potential is minimum between height A and height Z. The potential difference between the minimum potential between height A and height Z and the potential at height A is expressed as potential barrier ΔV.

[0084] As shown in FIG. 9(a), the lower the voltage supplied to the third wiring 331C, the more likely the above-described potential arrangement is satisfied. On the other hand, as shown in FIG. 9(b), the lower the voltage supplied to the third wiring 331C, the more the electric field is concentrated at the edge of the first semiconductor region 311. The electric field concentrates at the edge of the first semiconductor region 311, increasing the dark current and increasing the DCR. Therefore, when an anode potential is supplied to the third wiring 331C, the increase in DCR can become an issue. It is desirable that the voltage supplied to the third wiring 331C be higher than the anode potential.

[0085] A suitable voltage setting for the third wiring 331C will be described in more detail with reference to FIG.

[0086] Figure 10 is a conceptual diagram showing the relationship between the potential barrier ΔV formed at height A on the first vertical axis and the peak electric field strength near the end of the first semiconductor region 311 on the second vertical axis and the voltage supplied to the third wiring 331C.

[0087] As described in the description of FIG. 9, the lower the voltage supplied to the third wiring 331C, the larger the potential barrier ΔV becomes, and the greater the peak electric field strength near the end of the first semiconductor region 311 becomes.

[0088] 10 shows the lower limit of the potential barrier ΔV recommended for suppressing the change in breakdown voltage over time and the upper limit of the peak electric field strength near the edge of the first semiconductor region 311 recommended for suppressing an increase in DCR. The voltage at which the potential barrier ΔV and the peak electric field strength near the edge of the first semiconductor region 311 satisfy their respective recommended values ​​is the suitable voltage setting value for the third wiring. For example, the potential barrier ΔV is preferably 200 mV or more, and the peak electric field strength near the edge of the first semiconductor region 311 is preferably 300 kV / cm or less. Depending on the device structure, these values ​​are not necessarily limited.

[0089] For example, the height of the third wiring 331C from the interface of the semiconductor layer is about 0.1 μm, the anode voltage is about −30 V, and the cathode voltage is about 1 V. In this case, according to the recommended values ​​in FIG. 10, the range of −10 V to −20 V is the suitable voltage for the third wiring 331C.

[0090] When the voltage supplied to the third wiring 331C becomes higher than the voltage supplied to the cathode wiring, the potential barrier ΔV becomes negative, and a potential gradient is formed in the direction in which electrons are accelerated. Therefore, the voltage supplied to the third wiring 331C must be lower than Vdd supplied to the cathode wiring or the voltage (Vdd - Vex) that can be applied to the cathode wiring when the SPAD is operating. Here, Vdd is the drain voltage of the MOS transistor on the lower substrate side, and Vex is an excess bias voltage that exceeds the breakdown voltage of the SPAD.

[0091] Alternatively, the voltage supplied to the third wiring 331C may be a GNR voltage (ground voltage) lower than Vdd. The GND potential is a reference potential for the pixel circuit, such as the ground potential. In this case, a pad or the like for supplying a voltage to the sensor from the outside is not required, simplifying the design of the entire chip and reducing its area.

[0092] Furthermore, the voltage Vmid supplied to the third wiring 331C may be set to Vmid=(Van-Vca) / 2, which minimizes the voltage difference between the cathode voltage Vca and the anode voltage Van. While the above value is optimal for ensuring the withstand voltage of the third wiring 331C, the voltage difference between the wirings can be sufficiently reduced if the range is at least {(Van-Vca) / 2}×0.8≦Vmid≦{(Van-Vca) / 2}×1.2. This increases the degree of freedom in wiring layout, as wiring placement is limited by the withstand voltage between the wirings.

[0093] In this way, by supplying a suitable voltage greater than the anode voltage and less than the cathode voltage to the third interconnect 331C, it is possible to reduce the change in breakdown voltage over time while suppressing the DCR. Furthermore, to further enhance the effect of suppressing the change in breakdown voltage over time, it is desirable to shorten the depthwise distance between the semiconductor layer and the third interconnect 331C. Specifically, the interconnect layer on which the third interconnect 331C is provided is the layer among the multiple interconnect layers that is as close as possible to the semiconductor layer, preferably the closest layer. Here, the multiple interconnect layers are those arranged above the upper surfaces of the contact plugs that connect the anode interconnect 331A and the first semiconductor region. That is, in a direction perpendicular to the in-plane direction of the second surface of the semiconductor layer, the distance between the interconnect layers constituting the multiple interconnect layers and the second surface is configured to be greater than the distance between the portion of the contact plug farthest from the second surface (the upper surface of the contact plug) and the second surface of the semiconductor layer.

[0094] (Second embodiment) A photoelectric conversion device according to the second embodiment will be described with reference to FIG.

[0095] The following description will omit the parts that are common to the first embodiment and will mainly focus on the parts that are different from the first embodiment. In this embodiment, the cathode wiring 331A, the anode wiring 331B, and the third wiring 331C are formed at different heights relative to the semiconductor layer.

[0096] FIG. 11 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the second embodiment, taken in a direction perpendicular to the surface direction of the substrate.

[0097] In the first embodiment, the cathode wiring 331A, the anode wiring 331B, and the third wiring 331C were formed in the same wiring layer. In the present embodiment, the cathode wiring 331A, the anode wiring 331B, and the third wiring 331C are formed at different positions in the depth direction of the semiconductor layer. This makes it easier to ensure the distance between the cathode wiring 331A, the anode wiring 331B, and the third wiring 331C, and increases the degree of freedom in wiring layout.

[0098] Furthermore, by arranging the third wiring 331C closer to the surface of the semiconductor layer than the cathode wiring 331A and the anode wiring 331B, the contribution of the voltage of the third wiring 331C to the potential and electric field inside the semiconductor layer increases. As a result, the range of suitable voltage settings shown in Figure 10 shifts to the right in Figure 10. Therefore, the GND voltage can be included in the suitable voltage conditions for the voltage applied to the third wiring 331C.

[0099] The voltage difference between the cathode voltage and the voltage applied to the third wiring 331C becomes smaller. In terms of planar layout, the third wiring 331C is closer to the cathode wiring than the anode wiring, so if the voltage difference between the voltage applied to the third wiring 331C and the cathode voltage becomes smaller, the degree of freedom in wiring layout can be increased.

[0100] (Third embodiment) A photoelectric conversion device according to the third embodiment will be described with reference to FIG.

[0101] The following description will omit the parts common to the first and second embodiments, and will mainly focus on the parts different from the first embodiment. In this embodiment, the third wiring 331C overlaps the cathode wiring on a plane.

[0102] 12 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to this modification, taken in a direction perpendicular to the surface of the substrate. The third wiring 331C is provided in a wiring layer closer to the surface of the semiconductor layer than the cathode wiring 331A and the anode wiring 331B, and overlaps with the cathode wiring in a planar view.

[0103] In this configuration, the third wiring 331C can also be used as a light reflecting structure. Some of the light incident on the back surface of the substrate passes through the semiconductor layer and is transmitted to the front surface of the substrate. By efficiently reflecting this light by the third wiring 331C, the sensitivity can be improved.

[0104] It should be noted that the first embodiment also allows for the reflection of a portion of the light transmitted through the substrate. However, in the configuration of the first embodiment, the third wiring 331C is disposed at the same height as the anode wiring and cathode wiring, and the locations where the wiring can be disposed are limited in terms of withstand voltage. On the other hand, in the configuration of this embodiment, the third wiring 331C can cover a wider area and can reflect light at a position closer to the semiconductor layer. This allows for more light to be returned to the pixel, resulting in a greater improvement in sensitivity.

[0105] Moreover, by overlapping the third wiring 331C with the anode wiring in plan view, further improvement in sensitivity can be expected.

[0106] (Fourth embodiment) The fourth embodiment will be described with reference to FIG.

[0107] In this embodiment, an extension (fourth wiring) 331D of the third wiring 331C is arranged and connected to the third wiring 331C. The fourth wiring may be made of polysilicon or a metal such as tungsten. FIG. 13 shows the fourth wiring 331D made of polysilicon as an example. The fourth wiring 331D is arranged between the oxide film 341 and the protective film 342.

[0108] This configuration allows wiring to be placed directly above the semiconductor layer, and the depth direction distance between the semiconductor layer and the fourth wiring 331D is shorter than in the previous embodiment. The voltage supplied to the third wiring 331C can be efficiently applied to the semiconductor layer, which can enhance the effect of suppressing changes in breakdown voltage over time. Furthermore, because the effect of suppressing changes in breakdown voltage over time can be obtained with a smaller voltage supply, restrictions on wiring layout due to the withstand voltage of the wiring can be reduced.

[0109] (Fifth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 14. Fig. 14 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0110] The photoelectric conversion devices described in the first to sixth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Also included in the photoelectric conversion system is a camera module equipped with an optical system such as a lens and an imaging device. Fig. 14 illustrates a block diagram of a digital still camera as an example of such systems.

[0111] 14 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The system further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0112] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0113] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0114] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0115] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0116] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0117] (Sixth embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 15. Fig. 15 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0118] FIG. 15(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 includes an image capture device 1310. The image capture device 1310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the image capture device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0119] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high possibility of a collision, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0120] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 14(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). A vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0121] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0122] (Seventh embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 16. Fig. 16 is a block diagram showing an example of the configuration of a range image sensor which is the photoelectric conversion system of this embodiment.

[0123] 16, the range image sensor 401 is configured to include an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. The range image sensor 401 can obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 409 and reflected from the surface of the subject.

[0124] The optical system 407 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 408, forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 408.

[0125] The photoelectric conversion device 408 is the photoelectric conversion device of each of the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404.

[0126] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 408. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0127] In the range image sensor 401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0128] (Eighth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram showing an example of a schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0129] 17 shows an operator (doctor) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150. As shown in the figure, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0130] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the example shown, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0131] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0132] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is sent to a camera control unit (CCU) 1135 as RAW data.

[0133] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0134] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0135] The light source device 1203 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0136] The input device 1137 is an input interface for the endoscopic surgery system 1150. A user can input various information and instructions to the endoscopic surgery system 1150 via the input device 1137.

[0137] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0138] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 1203. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0139] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0140] The light source device 1203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, specific tissue, such as blood vessels on the surface of the mucous membrane, can be photographed with high contrast by irradiating light with a narrower band than the light (i.e., white light) used in normal observation. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0141] (Ninth embodiment) The photoelectric conversion system of this embodiment will be described with reference to FIGS. 18(a) and 18(b). FIG. 18(a) illustrates glasses 1600 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 18(a).

[0142] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0143] FIG. 18(b) illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0144] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0145] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0146] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0147] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0148] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first and second field-of-view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0149] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0150] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0151] (Modified embodiment) The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0152] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0153] Furthermore, the photoelectric conversion systems shown in the fifth and sixth embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 14 and 15. The same applies to the ToF system shown in the seventh embodiment, the endoscope shown in the eighth embodiment, and the smart glasses shown in the ninth embodiment.

[0154] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0155] 100 Photoelectric conversion device 102 Avalanche diode 311 first semiconductor region 312 Second semiconductor region 313 The Third Semiconductor Region 331A First Wire 331B Second Wiring 331C 3rd Wiring

Claims

1. A photoelectric conversion device having an avalanche diode disposed in a semiconductor layer having a first surface that is a light incident surface and a second surface opposite the first surface, The avalanche diode is a first semiconductor region of a first conductivity type disposed at a first depth relative to the second surface; a second semiconductor region of a second conductivity type disposed at a second depth relative to the second surface that is deeper than the first depth; a third semiconductor region provided in contact with an end portion of the first semiconductor region in a plan view, a first wiring connected to the first semiconductor region; a second wiring connected to the second semiconductor region; a third wiring, at least a portion of which overlaps the third semiconductor region in a plan view, but does not overlap the first semiconductor region, and is not connected to the avalanche diode; an avalanche multiplication region is formed across the first semiconductor region and the second semiconductor region; an impurity concentration in the third semiconductor region is lower than an impurity concentration in the first semiconductor region; A photoelectric conversion device characterized in that the third voltage supplied to the third wiring is a value between the first voltage supplied to the first wiring and the second voltage supplied to the second wiring.

2. A photoelectric conversion device as described in claim 1, characterized in that the impurity concentration of the first conductivity type in the third semiconductor region is lower than the impurity concentration of the second conductivity type in the second semiconductor region.

3. the first wiring and the third wiring are formed in a plurality of wiring layers stacked on the second surface side, The photoelectric conversion device described in claim 1 or claim 2, characterized in that the third wiring is formed in a wiring layer that is farther from the second surface than the farthest part from the second surface of the contact that connects the first semiconductor region and the first wiring, and is closer to the second surface than the first wiring.

4. 4. The photoelectric conversion device according to claim 3, wherein at least a portion of the first wiring and at least a portion of the third wiring overlap each other in a plan view.

5. the second wiring and the third wiring are formed in a plurality of wiring layers stacked on the second surface side, The photoelectric conversion device described in any one of claims 1 to 4, characterized in that the third wiring is formed in a wiring layer that is farther from the second surface than the farthest part from the second surface of the contact that connects the second semiconductor region and the second wiring, and is closer to the second surface than the second wiring.

6. 6. The photoelectric conversion device according to claim 5, wherein at least a portion of the second wiring and at least a portion of the third wiring overlap each other in a plan view.

7. 7. The photoelectric conversion device according to claim 1, wherein at least a part of the third wiring is made of polysilicon.

8. the third wiring is formed in a plurality of wiring layers stacked on the second surface side, The photoelectric conversion device described in any one of claims 1 to 7, characterized in that the third wiring is formed in a wiring layer that is farther from the second surface than the farthest part from the second surface of the contact that connects the first semiconductor region and the first wiring, and in the wiring layer closest to the second surface among the multiple wiring layers.

9. 9. The photoelectric conversion device according to claim 1, wherein the first wiring and the second wiring are formed in the same wiring layer stacked on the second surface side.

10. 10. The photoelectric conversion device according to claim 1, wherein when the first voltage is Vca, the second voltage is Van, and the third voltage is Vmid, the third voltage is within a range of {(Van-Vca) / 2} x 0.8 ≤ Vmid ≤ {(Van-Vca) / 2} x 1.

2.

11. 11. The photoelectric conversion device according to claim 1, wherein the third voltage is a ground voltage.

12. 12. The photoelectric conversion device according to claim 1, further comprising a fourth semiconductor region of the second conductivity type arranged at a third depth that is deeper than the second depth relative to the second surface.

13. a fifth semiconductor region of the first conductivity type is provided between the second semiconductor region and the fourth semiconductor region; 13. The photoelectric conversion device according to claim 12, wherein the impurity concentration of the first conductivity type in the fifth semiconductor region is lower than the impurity concentration of the first conductivity type in the first semiconductor region.

14. 14. The photoelectric conversion device according to claim 13, wherein a potential difference between the first semiconductor region and the second semiconductor region is larger than a potential difference between the second semiconductor region and the fifth semiconductor region.

15. 15. The photoelectric conversion device according to claim 1, further comprising an oxide film and a nitride film stacked on the second surface.

16. 16. The photoelectric conversion device according to claim 1, wherein the semiconductor layer has a plurality of uneven structures provided on the first surface.

17. 17. The photoelectric conversion device according to claim 16, wherein at least a portion of the third wiring is included in a region where the plurality of concave-convex structures are formed in a plan view.

18. A photoelectric conversion device as described in claim 1, characterized in that the potential difference between the second semiconductor region and the third semiconductor region is smaller than the potential difference between the second semiconductor region and the first semiconductor region.

19. The photoelectric conversion device according to any one of claims 1 to 18, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

20. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 18, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by:

Images