Photoelectric conversion devices and equipment

Abstract

To provide a technique advantageous for reducing a multiplication factor.SOLUTION: A photoelectric conversion device has a photoelectric conversion unit arranged on a semiconductor substrate comprising a first principal surface and a second principal surface on the opposite side of the first principal surface. The photoelectric conversion unit includes: a first region of a first conductivity type that forms part of the first principal surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type that is arranged apart from the first region; a third region of a second conductivity type opposite to the first conductivity type that is arranged at a position closer to the second principal surface than the first region and the second region; and a fourth region that is arranged between the first region and the second region. The second region and the third region function as an avalanche photodiode. The first region and the second region can be conductive to each other through the fourth region.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Single Photon Avalanche Diode (SPAD) is known as a photodetector that can detect weak light at the single photon level by utilizing avalanche multiplication. Patent Document 1 discloses a photodetector having pixels that include avalanche photodiodes (APDs) that function as SPADs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-064086 Summary of the Invention [Problem to be solved by the invention]

[0004] Let's consider the charge multiplication factor in an APD. In a SPAD, a voltage equal to the breakdown voltage Vbd plus an excess bias Vex is generally applied between the cathode and anode of the APD. Avalanche breakdown is detected by the change (decrease) in the cathode potential when an avalanche current flows. If the APD's cathode capacitance is Cc and the change in cathode potential when avalanche breakdown occurs is ΔV, the amount of charge discharged from the cathode due to avalanche breakdown is expressed as Cc × ΔV. If the unit charge is qe, the number of electron-hole pairs generated in one avalanche breakdown, i.e., the carrier multiplication factor, is expressed as Cc × ΔV / qe. Because the charge multiplication factor and carrier multiplication factor are the same, hereafter we will simply refer to them as multiplication factor. The cathode capacitance Cc has a large capacitance component, e.g., approximately 8 fF, due to the wiring pattern connected to the cathode and the detection circuit used to detect avalanche breakdown. Furthermore, if the change in cathode potential ΔV at which avalanche breakdown is detected is ΔV=2.4V, which is about the excess bias Vex, then the multiplication factor will be 120,000. A high multiplication factor makes it possible to detect weak light at the single-photon level, but on the other hand, the following issues arise.

[0005] A large number of carriers generated by avalanche breakdown flow between the anode and cathode, to which the breakdown voltage Vbd is applied. Therefore, a large current flows when a single photon is incident, resulting in a large amount of energy being consumed. When many pixels are arranged and the number of incident photons increases, the energy consumption also increases.

[0006] An object of the present invention is to provide a technique that is advantageous in suppressing the multiplication factor. [Means for solving the problem]

[0007] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device in which a photoelectric conversion unit is arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the photoelectric conversion unit comprises: a first region of a first conductivity type that forms part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type that is arranged away from the first region; a third region of a second conductivity type opposite to the first conductivity type that is arranged closer to the second main surface than the first region and the second region; and a fourth region that is arranged between the first region and the second region, wherein the second region and the third region function as an avalanche photodiode, and the first region and the second region are configured to be electrically conductive through the fourth region. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a technique that is advantageous in suppressing the multiplication factor. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 3] 3A and 3B are diagrams showing an example of operation of a pixel of the photoelectric conversion device of FIG. 2. [Figure 4] 3A and 3B are diagrams showing an example of operation of a pixel of the photoelectric conversion device of FIG. 2. [Figure 5] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 6] FIG. 6 is a cross-sectional view showing an example of the configuration of the APD and PD shown in FIG. 5. [Figure 7] 6A and 6B are diagrams showing an equivalent circuit diagram and an operation example of the pixel in FIG. 5. [Figure 8] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 9] FIG. 6 is a cross-sectional view showing an example of the configuration of the APD and PD shown in FIG. 5. [Figure 10]2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 11] 11 is a cross-sectional view showing an example of the configuration of the APD and PD shown in FIG. 10. [Figure 12] 12 is a cross-sectional view showing a modified example of the APD and PD shown in FIG. [Figure 13] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 14] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 15] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 16] 16A to 16C are diagrams showing a part of the manufacturing method of the pixel in FIG. 15. [Figure 17] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 18] 18A to 18C are diagrams showing a part of a manufacturing method of the pixel of FIG. 17. [Figure 19] 18 is a diagram showing the distribution of impurity ions in the depth direction of the semiconductor substrate in the regions 204, 238, and 239 of the pixel in FIG. 17. [Figure 20] 2 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 21] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 22] 22 is a cross-sectional view showing an example of the configuration of the APD and PD shown in FIG. 21. [Figure 23] 22A and 22B are diagrams showing an equivalent circuit diagram and an operation example of the pixel in FIG. 21. [Figure 24] 2 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 25] 25 is a diagram showing an example of operation of the pixel in FIG. 24. [Figure 26] FIG. 1 is a diagram showing an example of the configuration of a device incorporating a photoelectric conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0011] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 26. The following embodiments are merely examples of the present disclosure and do not limit the scope of the claimed invention. Furthermore, in the following embodiments, a single photon avalanche diode (SPAD) is described, in which electrons are used as signal charge carriers and a change in cathode potential due to an avalanche current is detected. Therefore, a semiconductor region of a first conductivity type having charges of the same polarity as the signal charge as majority carriers is an N-type semiconductor region, and a semiconductor region of a second conductivity type opposite to the first conductivity type is a P-type semiconductor region. However, holes may be used as signal charge carriers, or a change in anode potential may be detected. In this case, a semiconductor region of a first conductivity type having charges of the same polarity as the signal charge as majority carriers is a P-type semiconductor region, and a semiconductor region of a second conductivity type opposite to the first conductivity type is an N-type semiconductor region.

[0012] First, a photoelectric conversion device applicable to an embodiment of the present disclosure will be described based on a general SPAD operation using FIG. 1 . FIG. 1 is a block diagram showing an example configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 includes a pixel array 101, a control pulse generation circuit 115, a horizontal scanning circuit 111, a readout circuit 112, a vertical scanning circuit 110, a signal line 113, and drive lines 213 and 214. The pixel array 101 includes a plurality of pixels 104 arranged in a matrix. Each pixel 104 may include a photoelectric conversion unit 102 including an avalanche photodiode (APD) and a signal processing circuit 103. The photoelectric conversion unit 102 converts light into an electrical signal. The signal processing circuit 103 outputs the converted electrical signal to the readout circuit 112.

[0013] The vertical scanning circuit 110 receives control pulses supplied from the control pulse generating circuit 115 and supplies the control pulses to the pixels 104. The vertical scanning circuit 110 can use logic circuits such as a shift register and an address decoder.

[0014] The signal output from the photoelectric conversion unit 102 of each pixel 104 is processed by a signal processing circuit 103. The signal processing circuit 103 is provided with, for example, a counter and a memory, and digital values ​​are held in the memory.

[0015] The horizontal scanning circuit 111 inputs control pulses to the signal processing circuit 103 to sequentially select each column in order to read out the digital signals of the pixels 104 from the memory in which they are stored. For the selected column, a signal is output from the signal processing circuit 103 of the pixel selected by the vertical scanning circuit 110 to a signal line 113. The signal output to the signal line 113 is output via an output circuit 114 to a recording device, a signal processing device, or the like disposed outside the photoelectric conversion device 100.

[0016] 1, pixels 104 are arranged two-dimensionally in pixel array 101. However, this is not limiting, and pixels 104 may be arranged one-dimensionally in pixel array 101. The function of signal processing circuit 103 does not necessarily need to be provided one by one corresponding to each of all pixels 104; for example, one signal processing circuit 103 may be shared by multiple pixels 104, and signal processing may be performed sequentially.

[0017] Fig. 2 is a block diagram showing an example of the configuration of one pixel 104 shown in Fig. 1. First, the basic configuration and operation of the pixel 104 including an APD will be described using Fig. 2 and Figs. 3(a), 3(b), 4(a), and 4(b) described below. Next, the detailed configuration of the pixel 104 of this embodiment will be described using Fig. 5 and subsequent Figs.

[0018] As shown in FIG. 2, an APD 201 is disposed in the photoelectric conversion unit 102 of the pixel 104. The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A potential VL is supplied to the anode of the APD 201. A potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the APD 201. This provides a reverse bias voltage between the anode and cathode that causes the APD 201 to perform avalanche multiplication. With this voltage supplied, charges generated by incident light undergo avalanche multiplication, generating an avalanche current. In the following description, for simplicity, VL = -Vbd and VH = Vex. Here, Vbd is the breakdown voltage of the APD 201, and Vex is the excess voltage. Typically, VL is approximately -20V to -30V, and VH is approximately 2V to 3V.

[0019] 2, the signal processing circuit 103 of the pixel 104 may include a quenching element 202, a waveform shaping circuit 210, a counter circuit 211, and a selection circuit 212. However, the signal processing circuit 103 is not limited to this, and may also include other circuits related to signal processing.

[0020] The quench element 202 is connected to a supply line that supplies the potential VH and the APD 201. The quench element 202 has a function of converting a change in avalanche current generated in the APD 201 into a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0021] The waveform shaping circuit 210 shapes the potential change at the cathode of the APD 201 obtained when a photon is detected, and outputs a pulse signal. As a result, the waveform shaping circuit 210 functions as a detection circuit that detects avalanche breakdown occurring in the APD 201. For example, an inverter circuit may be used as the waveform shaping circuit 210. A configuration example including a single inverter is conceivable as the waveform shaping circuit 210. However, this is not limited thereto, and a circuit in which multiple inverters are connected in series may be used as the waveform shaping circuit 210. Alternatively, other circuits having a waveform shaping effect may be used as the waveform shaping circuit 210.

[0022] The counter circuit 211 counts the number of pulse signals output from the waveform shaping circuit 210 and holds the counted value. When a reset control pulse is supplied from the vertical scanning circuit 110 shown in FIG. 1 via a drive line 213, the counter circuit 211 resets the value held in the counter circuit 211.

[0023] 1 via a drive line 214, the selection circuit 212 switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 can be configured to include, for example, a buffer circuit for outputting a signal.

[0024] A switching element such as a transistor may be disposed between the quench element 202 and the APD 201 or between the photoelectric conversion unit 102 and the signal processing circuit 103 to switch the electrical connection. Similarly, the supply of the potential VH, the potential VL, etc. supplied to the photoelectric conversion unit 102 may be electrically switched using a switching element such as a transistor.

[0025] In the configuration shown in FIG. 2, a counter circuit 211 is used in the signal processing circuit 103. However, this is not limiting. Instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire the timing at which the pulse signal output from the waveform shaping circuit 210 is detected using a time-to-digital conversion circuit (TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 210 is converted into a digital signal by the TDC. To measure the output timing of the pulse signal, the TDC receives a control pulse pREF from the vertical scanning circuit 110 via a drive line (which may be the same as the drive lines 213 and 214). The TDC acquires, as a digital signal, a signal in which the input timing of the signal output from the pixel 104 via the waveform shaping circuit 210 is used as a relative time based on the control pulse pREF.

[0026] 3(a) and 3(b) are diagrams schematically illustrating the relationship between the operation of the APD 201 and the output signal. Fig. 3(a) is a diagram illustrating the APD 201, the quench element 202, and the waveform shaping circuit 210 shown in Fig. 2. Here, the input side of the waveform shaping circuit 210 is referred to as node A, and the output side is referred to as node B. Fig. 3(b) shows the potential changes at node A and node B.

[0027] From time t0 to time t1, a potential difference (voltage) of potential VH-potential VL is applied to the APD 201. When a photon is incident on the APD 201 at time t1, avalanche breakdown occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the potential at node A drops. As the potential drop increases further and the potential difference applied to the APD 201 decreases, the avalanche breakdown in the APD 201 stops as shown at time t2, and the potential level at node A does not drop below a certain value. The potential at which this avalanche breakdown stops is approximately 0 V, that is, a potential at which the voltage applied to the APD 201 is approximately Vbd. After that, from time t2 to time t3, a current flows through node A from potential VL to compensate for the potential drop, and at time t3, node A stabilizes to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping circuit 210 and output as a signal to node B.

[0028] Here, the quench element 202 and the waveform shaping circuit 210 may be formed on the same semiconductor substrate as the APD 201. However, this is not limiting, and a chip on which the APD 201 is disposed and a chip on which the quench element 202 and the waveform shaping circuit 210 are disposed may be formed separately and stacked together. For example, as indicated by the dotted line in Fig. 2, a chip (semiconductor substrate) on which the photoelectric conversion unit 102 is disposed and a chip (semiconductor substrate) on which the signal processing circuit 103 is disposed may be formed separately and stacked together.

[0029] 4(a) and 4(b) are diagrams schematically illustrating the relationship between the operation and output signal of an APD 201 having a configuration different from that shown in FIGS. 3(a) and 3(b). FIG. 4(a) is an equivalent circuit diagram corresponding to FIG. 3(a), but a P-channel (P-type) MOS (MIS) transistor 203 is provided instead of the quench element 202. FIG. 4(b) shows the potential changes at node A, node B, and node C in FIG. 4(a). Similar to FIG. 3(a), node A and node B are the input and output nodes, respectively, of the waveform shaping circuit 210. Node C is a node connected to the gate electrode of the transistor 203.

[0030] The transistor 203 is a switch for resetting the potential of node A to potential VH, and is controlled by the potential of node C. When the potential of node C shown in FIG. 4(b) is high, the transistor 203 is in an off state (non-conductive state, hereinafter sometimes referred to as OFF). When the potential of node C is low, the transistor 203 is in an on state (conductive state, hereinafter sometimes referred to as ON). A periodic pulse is input to node C, and FIG. 4(b) shows a portion of it. The operation shown in FIG. 4(b) will be described below.

[0031] First, at time t0, the potential of node A is reset to the potential VH by the transistor 203. After that, when the transistor 203 is turned off, the potential of node A becomes floating at the potential VH.

[0032] Assume that a photon is incident on the APD 201 at time t1. When the incident photon causes avalanche breakdown in the APD 201, the avalanche current decreases the potential of node A, and the avalanche breakdown stops at time t2. The potential of node A remains low and floating, but when a pulse to reset node A is input to node C at time t3, the potential of node A is reset to potential VH again. Therefore, an avalanche breakdown detection pulse is generated at node B on the output side of the waveform shaping circuit 210, which remains High between times t1 and t2, from the time the potential of node A reaches the decision threshold until time t3.

[0033] In the operation shown in FIG. 4(b), consider the case where a photon is incident at time t1 and a subsequent photon is incident between time t1 and time t3, i.e., the subsequent photon is incident while the potential of node A remains low. In this case, the APD 201 cannot cause further avalanche breakdown in response to the second and subsequent photons incident between time t1 and time t3. Therefore, even if multiple photons are incident between time t1 and time t3, the number of avalanche breakdowns detected by the waveform shaping circuit 210 is one. Also, for example, in the operation shown in FIG. 4(b), if no photons are incident between time t0 and time t3, the potential of node A remains at potential VH, and the potential of node B remains at a low level. In other words, the number of avalanche breakdowns detected is zero.

[0034] In the operation described with reference to FIG. 4(b), it is distinguished whether the number of photons incident on the APD 201 during one cycle of the reset pulse input to node C was zero or one or more. Therefore, if multiple photons are incident on node C during one cycle of the reset pulse, a signal detection loss occurs. On the other hand, if photons are incident one after another without interruption, the operation described with reference to FIG. 3(b) causes the APD 201 to undergo avalanche breakdown without stopping, and avalanche current continues to flow, resulting in a so-called pile-up state. In the pile-up state, the potential at node A remains low, preventing the waveform shaping circuit 210 from generating a detection pulse and resulting in a (wasteful) current flow in the APD 201. Therefore, pile-up can be a major issue in terms of power consumption during SPAD operation.

[0035] In addition to the continuous flow of current due to pile-up, the following problems may occur during SPAD operation: As described above, the following problems may arise due to the large multiplication factor during SPAD operation.

[0036] One issue is the problem of luminescence crosstalk. A large number of carriers are generated in response to the incidence of photons in the APD 201. It is known that some of the generated carrier pairs recombine to emit light. In a pixel array 101 having multiple pixels 104 (photoelectric conversion units 102), if avalanche breakdown occurs due to a photon incident on a certain pixel 104, secondary photons emitted from that pixel 104 may be incident on surrounding pixels 104, potentially resulting in spurious signals. This is called luminescence crosstalk. For example, as mentioned above, if the multiplication factor is 120,000 and it is assumed that 0.01% of the 120,000 carrier pairs generated by the incidence of a single photon recombine, then 12 secondary photons that cause luminescence crosstalk will be generated.

[0037] The next problem is changes in dark current. Carriers generated by avalanche multiplication are accelerated in high-electric-field regions and become so-called hot carriers. Some of these hot carriers are captured at the interface near the cathode of the APD 201, changing the state of the interface. In the APD described in Patent Document 1, the area around the cathode is depleted, and many dark current carriers are generated from the interface. However, the electric field strength around the cathode is relatively low, and only a small portion of the carriers generated at the interface cause avalanche. However, these interface-generated carriers that cause avalanche appear as dark current in the SPAD. When the state of the interface changes due to hot carrier capture, the carrier generation rate at the interface changes, resulting in a change in the dark current value. This change occurs over time when the SPAD is used, which can lead to problems such as the initial dark current correction becoming ineffective.

[0038] Furthermore, as mentioned above, the energy consumption increases as the number of signal photons increases. For example, if Vbd = 25 V, it is estimated that 120,000 carriers are generated by the incidence of one photon, consuming approximately 0.5 pJ of energy. When many pixels are arranged and the number of incident photons increases, the energy consumption also increases. This can place a heavy load on the power supply system of the photoelectric conversion device 100 operating as a SPAD.

[0039] As described above, the avalanche multiplication factor increases due to the large capacitance components resulting from the wiring pattern connected to the cathode of the APD 201 and the detection circuit for detecting avalanche breakdown, such as the waveform shaping circuit 210. This can lead to the problems of light emission crosstalk, dark current variations, and power consumption, as described above. If the junction capacitance of the diode at the cathode of the APD 201 increases, this can become a more serious problem. The junction capacitance of the diode at the cathode of the APD 201 is a separate capacitance component from the capacitance resulting from the wiring pattern connected to the cathode of the APD 201 and the detection circuit for detecting avalanche breakdown, such as the waveform shaping circuit 210.

[0040] The above-mentioned problems can become more pronounced in the pileup state that can occur in the operation shown in Figure 3(b). The operation shown in Figure 4(b) has the significant advantage of not causing such pileup. While signal detection loss can occur when multiple photons are incident during one reset pulse period input to node C, the SPAD is advantageous for photon detection in situations where the number of incident photons is low. In situations where the number of incident photons is low, it is unlikely that multiple photons will be incident during one reset pulse period. Therefore, it is expected that signal detection loss will be minimal in such situations. However, problems such as light emission crosstalk, dark current changes, and power consumption due to a large multiplication factor can still exist in the operation shown in Figure 4(b).

[0041] The photoelectric conversion device 100 of the present disclosure for suppressing light emission crosstalk, changes in dark current, and power consumption will be described in detail below, based on the operation shown in Fig. 4(b). However, each embodiment of the present disclosure is also applicable to the operation shown in Fig. 3(b).

[0042] (First embodiment) Fig. 5 is a plan view of the photoelectric conversion unit 102 arranged in the pixel 104 in the first embodiment of the present disclosure. Fig. 6 is a cross-sectional view taken along line AB of the photoelectric conversion unit 102 shown in Fig. 5. Fig. 5 is a plan view of the main surface 251 (first main surface) of the semiconductor substrate 250 shown in Fig. 6.

[0043] The photoelectric conversion unit 102 included in the pixel 104 arranged in the photoelectric conversion device 100 is formed on a semiconductor substrate 250 having a main surface 251 and a main surface 252 (second main surface) opposite to the main surface 251. In the configuration shown in Figures 5 and 6, the photoelectric conversion unit 102 includes a region 204 (first region), a region 206 (second region), a region 208 (third region), and a region 207 (fourth region).

[0044] Region 204 is a heavily doped N-type conductivity region that constitutes a part of the main surface 251 of the semiconductor substrate 250. Region 204 is connected to a detection circuit (e.g., the above-described waveform shaping circuit 210) for detecting avalanche breakdown via a connection pattern 205. Although connection pattern 205 does not constitute a part of the main surface 251, connection pattern 205 is shown in FIG. 5 to clearly show the connection position between region 204 and connection pattern 205. Region 206 is a heavily doped N-type conductivity region that is disposed away from region 204. As shown in FIG. 6, region 206 may constitute a part of the main surface 251 of the semiconductor substrate 250. Unlike region 204, region 206 is not directly connected to connection pattern 205 that is connected to the detection circuit. Region 206 is connected to connection pattern 205 via regions 207 and 204, as will be described later. Region 208 is a region of P conductivity type opposite to N type, and is disposed closer to main surface 252 of semiconductor substrate 250 than regions 204 and 206 .

[0045] Region 204 may be the cathode of a photodiode (PD) including a PN junction formed by regions 204 and 208, and region 208 may be the anode of the PD formed by regions 204 and 208. Similarly, region 206 may be the cathode of an APD including a PN junction formed by regions 206 and 208, and region 208 may be the anode of the APD formed by regions 206 and 208. As shown in FIG. 6, region 208 may be formed over substantially the entire surface of one pixel 104 (photoelectric conversion unit 102) between regions 204 and 206 and a main surface 252 of a semiconductor substrate 250 (below regions 204 and 206 in the drawing). As shown in FIG. 6, region 208 extends from one region 230 to the other region 230 in a cross-sectional view.

[0046] Region 207 is disposed between region 204 and region 206. Region 204 and region 206 are configured to be electrically conductive through region 207. Region 207 preferably has a lower impurity concentration than regions 204 and 206. In the configurations shown in FIGS. 5 and 6, region 207 is an N-type region with a low impurity concentration that functions as a resistor connecting region 204 and region 206.

[0047] As shown in FIG. 6 , the photoelectric conversion unit 102 may further include regions 209, 230, 231, and 190. Region 209 is a P-type region formed to constitute a main surface 252 of a semiconductor substrate 250. Region 230 is a P-type region formed at the boundary of each pixel 104 (photoelectric conversion unit 102) to separate them from one another. Region 231 (fifth region) is a photoelectric conversion region, and is a P-type or N-type region with a lower impurity concentration than regions 204 and 206, located between region 208 and the main surface 252 (region 209) of the semiconductor substrate 250. Region 190 is a region located between regions 204, 207, and 206 and region 208, in a region surrounded by the main surface 251, region 208, and region 230 of the semiconductor substrate 250. Region 190 is a P-type or N-type region that is lightly doped relative to regions 204 and 206. Regions 190 and 231 may be lightly doped relative to regions 208, 209, and 230.

[0048] 5 and 6, when light is incident on the photoelectric conversion unit 102 during operation of the photoelectric conversion device 100, the PN junction including the regions 206 and 208 functions as the above-mentioned APD 201 and causes avalanche breakdown. On the other hand, the PN junction including the regions 204 and 208 does not function as the above-mentioned APD 201 and does not generally cause avalanche breakdown. Therefore, the PN junction including the regions 204 and 208 may be referred to as a parasitic PD 232 hereinafter.

[0049] To allow regions 206 and 208 to function as the APD 201 and prevent regions 204 and 208 from functioning as the APD 201, the distance D1 between regions 206 and 208 is shorter than the distance D2 between regions 204 and 208, as shown in FIG. 6 . Therefore, during operation, a higher electric field is generated in the PN junction formed by regions 206 and 208 than in the PN junction formed by regions 204 and 208. Therefore, a depletion region is formed in the region of region 208 that overlaps with region 206 in the orthogonal projection onto the principal surface 251 of the semiconductor substrate 250. Charges generated in region 231 by the incidence of light flow through this depletion region into region 206, causing avalanche breakdown. Region 190 is essentially depleted during operation. Therefore, electrical conduction between regions 204 and 206 is primarily achieved through N-type region 207, which functions as a resistor. The concentration of the first conductivity type impurity in the region 204 may be lower than the concentration of the first conductivity type impurity in the region 206. This can also make it difficult for avalanche breakdown to occur in the region 204 and the region 208.

[0050] In this embodiment, photons incident on region 231 may be incident from main surface 251 or main surface 252 of semiconductor substrate 250. Here, it is assumed that photons are incident from main surface 252 of semiconductor substrate 250. In other words, photoelectric conversion device 100 is a so-called back-illuminated photoelectric conversion device. It is also assumed that signal processing circuit 103 including waveform shaping circuit 210 and the like is formed on a separate substrate that is connected via connection pattern 205 to semiconductor substrate 250 on which region 231, APD 201, and the like are disposed.

[0051] 7(a) and 7(b) are diagrams for explaining the SPAD operation of this embodiment. FIG. 7(a) is an equivalent circuit diagram of a portion of the photoelectric conversion unit 102 and the signal processing circuit 103, and FIG. 7(b) shows the potential changes at nodes A to D during SPAD operation. Nodes A to C are located in the same positions as those shown in FIG. 4(a). Node D is the cathode of the APD 201, in other words, the potential of region 206. Furthermore, node A is the potential of region 204, which is the cathode of the parasitic PD 232, when the wiring resistance of the connection pattern 205 can be ignored.

[0052] First, at time t0, transistor 203 resets the potential of node A and, via region 207, the potential of node D to potential VH. Transistor 203 functions as a reset circuit for resetting the potentials of regions 204 and 206 to a predetermined potential (potential VH) in accordance with a reset pulse input to node C. After that, when transistor 203 turns OFF, the potentials of node A and node D become floating at potential VH.

[0053] Next, at time t1, a photon is incident on the photoelectric conversion unit 102, causing avalanche breakdown in the APD 201. The avalanche current causes the potential of node D to decrease. At this time, the potential of node A also decreases due to the current flowing through region 207, but the decrease in potential is slower than the change in the potential of node D. When the avalanche breakdown stops at time t2, a current flows through region 207 so that node A and node D have the same potential. During this process, the potential of node A exceeds the threshold of the waveform shaping circuit 210, and a pulse is generated at node B to detect the avalanche breakdown in the APD 201.

[0054] In the above operation, an avalanche current flows from time t1 to time t2. Here, the configuration shown in FIG. 4(a), in which the APD 201 is directly connected to the waveform shaping circuit 210, is referred to as the comparative example configuration. In the potential change shown in FIG. 7(b), the potential at node D drops to the potential at which avalanche breakdown stops, similar to the operation shown in FIG. 4(b) in the comparative example configuration. Meanwhile, the potential at node A, which is subject to large capacitance due to the connection pattern 205 and the waveform shaping circuit 210 (detection circuit), cannot follow the change in the potential at node D because the region 207 functions as a resistor. Therefore, the potential change at time t2 is small. Therefore, if the capacitance of the parasitic PD 232 added to the comparative example configuration is sufficiently small compared to the other capacitances added to node A, the discharge charge at node A is suppressed compared to the operation of the comparative example configuration. As a result, the multiplication factor of the avalanche breakdown occurring in the APD 201 is suppressed compared to the comparative example configuration.

[0055] A quantitative explanation will now be given. As a condition, the size of the pixel 104 is assumed to be several μm square, e.g., 5 μm square. In this case, the diameter of the regions 204 and 206 is, e.g., about 1 μm. The region 204 constituting the parasitic PD 232 may be smaller than the region 206. Under these conditions, the capacitance of the PN junction in the region 206 is approximately 0.8 fF, the additional capacitance (parasitic capacitance) from the connection pattern 205 to the input of the waveform shaping circuit 210 is approximately 7.2 fF, and the capacitance of the PN junction in the region 204 is approximately 0.6 fF. In this embodiment, the capacitance due to the presence of the region 204 is increased compared to the configuration of the comparative example. However, it can be seen that the capacitance component due to the region 204 is sufficiently smaller than the capacitance components from the connection pattern 205 to the input of the waveform shaping circuit 210 due to the connection pattern 205 and the waveform shaping circuit 210.

[0056] Next, we consider what resistance value of region 207, which functions as a resistor, should have to be in order to have the effect of suppressing the carrier multiplication factor. Here, the resistance in region 207 is not necessarily ohmic resistance. The resistance value of region 207 is a value obtained by V1 / I1, where I1 is the current flowing through region 207 when the potential difference between region 204 and region 206 is V1.

[0057] First, let us assume that the potential drop at the cathode (region 206) of APD 201 when avalanche breakdown occurs is 2.4 V. The avalanche current in this case, although dependent on the characteristics of APD 201, is approximately 50 μA under the above conditions. Therefore, for region 206, which has a capacitance of 0.8 fF, it takes approximately 40 ps for the potential to drop by 2.4 V. To prevent the potential of region 204 from following the potential change in region 206, the product of the resistance value of region 207 and the capacitance value of region 206—the so-called CR time constant—must be approximately 40 ps or greater. Given the above conditions, since the capacitance of region 206 is 0.8 fF, the resistance value of region 207 must be approximately 50 kΩ or greater. In practice, the conditions may vary somewhat. For example, if the avalanche current is 100 μA, it takes 20 ps for the potential of region 206 to drop by 2.4 V, and the resistance value of region 207 needs to be approximately 25 kΩ. Furthermore, if the drop in the cathode (region 206) potential when avalanche breakdown occurs is approximately 1.9 V, the resistance value of region 207 needs to be approximately 20 kΩ. Therefore, it is preferable for region 207 to function as a resistor of 20 kΩ or more. Considering the junction capacitance of region 206, the amount of avalanche current, and other factors that can be actually formed, it is believed that the effect of suppressing the multiplication factor cannot be expected unless the resistance value of region 207 is at least approximately 20 kΩ.

[0058] On the other hand, the greater the resistance value of region 207, the greater the effect of suppressing the multiplication factor. However, if the resistance value of region 207 is too high, the response time from the actual onset of avalanche breakdown to its detection becomes longer. For example, if the period of the pulse input to node C is 20 μs, a response time significantly shorter than the pulse period will result in a loss of avalanche breakdown detection. Therefore, if a response time of 0.2 μs or less is required, the above-mentioned time constant is 0.2 μs or less, and the upper limit of the resistance value of region 207 is estimated to be 250 MΩ. Generally, it is difficult to form a resistor of several hundred MΩ within pixel 104 (semiconductor substrate 250). Therefore, the lower limit of the resistance value of region 207 is important in the design of an actual pixel 104 (photoelectric conversion unit 102).

[0059] As described above, when the multiplication factor at the time of avalanche breakdown decreases, the magnitude of the potential change (potential drop) at node A also decreases. Therefore, the threshold value for determining avalanche breakdown in the waveform shaping circuit 210 needs to be set to a value according to the multiplication factor that has changed due to the provision of the parasitic PD 232.

[0060] The present embodiment, described above with reference to FIGS. 5 to 7(a) and 7(b), will now be summarized. The addition of the parasitic PD 232 to the comparative example configuration adds capacitance of the PN junction in region 204 to node A, which is a disadvantage in terms of suppressing the multiplication factor when avalanche breakdown occurs. However, the capacitance of the PN junction in region 204 is significantly smaller than the capacitance caused by the connection pattern 205, the waveform shaping circuit 210, and the like. Therefore, it does not significantly affect the multiplication factor. Meanwhile, by setting the resistance of region 207 to an appropriate value, electrical conduction between node A and node D can be prevented to a desired degree. This significantly reduces the amount of charge discharged from node A when avalanche breakdown occurs, compared to the SPAD operation of the comparative example configuration. In other words, the configuration of this embodiment suppresses the carrier multiplication factor when avalanche breakdown occurs, thereby effectively addressing three problems: light emission crosstalk, changes in dark current, and power consumption when multiple photons are incident.

[0061] Here, the configurations of the parasitic PD 232, the APD 201, and the region 207 are not limited to those shown in Figures 5 and 6. For example, as shown in Figure 8, the region 207 may connect the region 204 and the region 206 via a detour rather than via the shortest route. The region 207 that is laid out to detour increases the distance between the region 204 and the region 206, making it easier to increase the resistance value.

[0062] 9, region 206 for configuring APD 201 has a two-tiered configuration of region 206a and region 206b. Region 206a of region 206 is a shallow N-type region in contact with main surface 251 of semiconductor substrate 250, like region 204. Region 206b of region 206 is an N-type region formed at a deeper location (closer to main surface 252 of semiconductor substrate 250) than region 206a and continuing from region 206a.

[0063] Regions 204 and 206 shown in FIG. 6 have different depths within a single layer structure, and therefore can be formed using different masks. On the other hand, region 206a of regions 204 and 206 shown in FIG. 9 can be formed using the same mask. Therefore, the planar positional relationship between regions 204 and 206 (region 206a) on the main surface 251 of the semiconductor substrate 250 is formed with a constant positional relationship, regardless of mask misalignment. This leads to a stable resistance value for region 207, which is an electrical conductive path connecting regions 204 and 206. Region 206b of region 206 is formed using a mask different from the masks used to form regions 204 and 206a. Even in this case, only the position of the depletion region of P-type region 208 is determined, and mask misalignment of region 206b relative to region 206a does not significantly affect the characteristics. The configurations shown in FIGS. 8 and 9 may be used in combination. 8 and 9, the multiplication factor can be suppressed and SPAD operation with stabilized characteristics can be realized, which can contribute to further improvement of the characteristics of the photoelectric conversion device 100.

[0064] 6 and 9, the region 206 is disposed closer to the main surface 252 of the semiconductor substrate 250 than the region 204, thereby making the distance between the region 206 and the region 208 shorter than the distance between the region 204 and the region 208. However, this is not limiting. For example, the region 204 and the region 206 may have the same shape, and the portion of the region 208 that overlaps with the region 206 may have a step so as to approach the region 206. For example, the region 204 and the region 206 may be formed using the same mask. Alternatively, the region 208 may include a uniform region as shown in FIGS. 6 and 9 and a region that is continuous with the uniform region and that approaches the region 206 in the region that overlaps with the region 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. This also makes it possible to achieve the SPAD operation with reduced multiplication factor that combines the APD 201 and the parasitic PD 232, as described above. Furthermore, since the regions 204 and 206 can be formed using one mask, the SPAD operation characteristics can be stabilized, similar to the configuration shown in FIG.

[0065] Furthermore, the outer edge of each region, such as the above-mentioned regions 204, 206, and 208, may be a portion where the impurity concentration is 1 / 10 of the portion where the impurity concentration is highest in the region. Furthermore, for example, the outer edge of each region, such as regions 204, 206, and 208, may be a portion where the impurity concentration is 1 / 100 of the portion where the impurity concentration is highest in the region. Furthermore, for example, the outer edge of each region, such as regions 204, 206, and 208, may be a portion where the impurity concentration is 1×10 16 Furthermore, when adjacent regions have different conductivity types, the outer edge of each region may be a portion where the conductivity type changes.

[0066] (Second embodiment) Next, a photoelectric conversion device 100 according to a second embodiment of the present disclosure will be described. Fig. 10 is a plan view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. Fig. 11 is a cross-sectional view taken along line AB of the photoelectric conversion unit 102 shown in Fig. 10. Fig. 10 is a plan view of a main surface 251 of a semiconductor substrate 250 shown in Fig. 11. The equivalent circuit of this embodiment shown in Figs. 10 and 11 may be similar to the circuit of the first embodiment shown in Fig. 7(a) and described above using Figs. 5 to 9, and may also operate in the same manner.

[0067] 11, in this embodiment, the regions 204 and 206 have a structure in which they are stacked in the depth direction. More specifically, the region 206 is disposed between the region 204 and the region 208. Herein, the depth direction is the direction from the main surface 251 toward the main surface 252 of the semiconductor substrate 250. Hereinafter, the closer one approaches the main surface 252 from the main surface 251, the deeper one will be expressed as "getting deeper."

[0068] The APD 201 is composed of regions 206 and 208. A low concentration of P-type impurities or a low concentration of N-type impurities is introduced into region 207. A low-density N-type conductivity electron layer is formed in region 207 during operation, regardless of the conductivity type of the impurities, and serves as a resistor connecting region 204 and region 206. When region 207 is effectively an N-type region, the operation of region 207 is the same as in the first embodiment described above. Here, the "effective" conductivity type refers to the conductivity type with the higher impurity concentration when P-type impurities and N-type impurities are mixed, and the difference between the impurity concentrations is the effective concentration. In the above-described and following embodiments, the conductivity type of each region may be the effective conductivity type.

[0069] The following describes a case where region 207 is effectively a P-type region but its majority carriers are electrons. If region 207, which is effectively a P-type impurity region, is neutral or completely depleted during operation, electrical continuity between regions 204 and 206 is cut off, and region 206 of APD 201 is always floating. Therefore, information about the occurrence of avalanche breakdown in APD 201 is not transmitted, and region 206 does not function as a SPAD. On the other hand, if the depth and impurity concentration of P-type region 207 are appropriate, the majority carriers in region 207 can be electrons with a low density, and region 207 can function as a resistor between regions 204 and 206. Specifically, the Debye length of P-type region 207 is set to be approximately the depth of region 207. This allows the majority carriers in region 207 to be electrons with a low density.

[0070] Regions 204 and 206 are high-concentration N-type regions, containing a high density of electrons as majority carriers. The quasi-Fermi levels of regions 204 and 206 do not change so that majority carriers become holes in P-type region 207. This is because the limit on the change in the quasi-Fermi level is determined by the Debye length. Therefore, in P-type region 207, electrons become majority carriers, albeit at a low density, and region 207 can act as a resistor. A P-type region with a moderate concentration of region 207 can more easily achieve a lower-density electron layer than an N-type region. Therefore, region 207 is more likely to function as a high-resistance region. Compared to the configurations described using Figures 5 to 9, the configuration shown in Figure 11 can have a shorter distance between region 204 and region 206. Therefore, a higher resistance per unit length of region 207 may be required than in the above-described configurations.

[0071] As described above, when region 207 acts as a resistor and exhibits a desired resistance value, the multiplication factor when avalanche breakdown occurs can be suppressed more than that of the SPAD of the comparative example, based on the same operating principle as in the first embodiment described with reference to Figures 5 to 9. As a result, even in the configurations shown in Figures 10 and 11, the problems of light emission crosstalk, changes in dark current, and power consumption caused by a large multiplication factor can be improved.

[0072] 10 and 11, in orthogonal projection onto the main surface 251 of the semiconductor substrate 250, the regions 204 and 206 are arranged to overlap each other. Therefore, the areas occupied by the regions 204 and 206 are smaller than in the plan view of FIG. 5. This can be easily applied when reducing the size of the pixel 104 (photoelectric conversion unit 102). Furthermore, the three layers of the regions 204, 206, and 207 can be formed using the same mask. This makes it less likely that variations in characteristics will occur due to mask misalignment in the regions 204, 206, and 207, and further reduces manufacturing costs.

[0073] FIG. 12 is a modified example of the configuration shown in FIG. 11. In the configuration shown in FIG. 12, region 233 (sixth region) is a P-type region, and is doped with an effective P-type impurity concentration such that it is essentially depleted during operation. Region 207 has approximately the same depth as region 233, and is an N-type or P-type impurity doped region formed locally in the central portion of region 204 and region 206 in orthogonal projection onto main surface 251 of semiconductor substrate 250. As described above, region 207 is a region where electrons become majority carriers at a low density during operation. Therefore, when region 207 is P-type, its effective impurity concentration is lower than the effective impurity concentration of region 233.

[0074] In the configurations shown in FIGS. 11 and 12, region 207 serves as an electrical conduction path between region 204 and region 206. Region 207 in the configuration shown in FIG. 12 has a smaller cross-sectional area perpendicular to the current flow direction than region 207 in the configuration shown in FIG. 11, making it easier to obtain a high resistance value. Regions 204, 206, and 233 can be formed using the same mask. In the configuration shown in FIG. 12, N-type impurities may be introduced into region 207 using a mask different from the mask used to form regions 204, 206, and 233. This allows region 207 to be effectively N-type or a P-type region with a lower effective impurity concentration than region 233. The mask used to form region 207 and connection pattern 205 may also be used. The N-type impurities used to form region 206 essentially have a distribution with the center spreading in the depth direction. Therefore, depending on the design of the distribution of the impurity concentrations, when the regions 204, 206, and 233 are formed using the same mask, the region 207 may be formed locally at the same time.

[0075] In the configuration of this embodiment, the region 204 and the region 206 are arranged to overlap each other in an orthogonal projection onto the main surface 251 of the semiconductor substrate 250. In this case, the region 206 may be arranged to be included in the region 204. Furthermore, the region 204 may be arranged to be included in the region 206.

[0076] The configuration of this embodiment, like the configuration shown in the first embodiment described above, can also suppress the carrier multiplication factor when avalanche breakdown occurs. This effectively alleviates the aforementioned problems of light emission crosstalk, dark current variations, and power consumption. Furthermore, even when the size of the pixel 104 is reduced, the configuration of this embodiment in which the regions 204, 207, and 206 overlap can be effectively applied. Furthermore, the configuration in which the regions 204, 207, and 206 overlap can further reduce characteristic variations while suppressing an increase in the number of manufacturing processes.

[0077] (Third embodiment) Next, a photoelectric conversion device 100 according to a third embodiment of the present disclosure will be described with reference to FIG. 13. FIG. 13 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 according to this embodiment. The photoelectric conversion device 100 according to this embodiment differs from the modified example of the second embodiment shown in FIG. 12 in that the photoelectric conversion unit 102 has a region 232. Other than this point and points described below, the photoelectric conversion device 100 is substantially the same as the second embodiment, and therefore description thereof may be omitted. The circuit diagram and SPAD operation according to this embodiment are also the same as those described in FIGS. 5, 7(a), 7(b), etc.

[0078] In this embodiment, region 232 is connected to a detection circuit for detecting avalanche breakdown via connection pattern 205. Region 232 is a high-impurity-concentration N-type conductivity region that constitutes part of main surface 251 of semiconductor substrate 250. Region 232 forms an ohmic connection between region 204 and connection pattern 205. The N-type impurity concentration of region 232 is higher than the N-type impurity concentration of region 204. In a plan view, region 204 is arranged to surround region 232.

[0079] In plan view, region 207 is disposed at a position overlapping connection pattern 205. In this case, after the step of forming a through hole in which connection pattern 205 is provided, region 207 can be formed by utilizing the through hole, and N-type impurities may be introduced to a depth approximately the same as that of region 233. On the other hand, in this case, the resistance value of region 207 may be affected by region 232. In order to reduce the effect on the resistance value, region 207 and connection pattern 205 may be disposed so as not to overlap each other in plan view, as shown in FIG. 14 .

[0080] The preferred impurity concentrations for each region are described below. Note that the impurity concentration here refers to the effective impurity concentration, which is the difference in impurity concentration when P-type and N-type impurities are mixed. The impurity concentrations shown below are merely examples, and the regions described in each embodiment are not limited to the ranges of impurity concentrations shown below.

[0081] For example, the impurity concentration of the region 204 is 1×10 15 ~1×10 20 cm -3 The impurity concentration of the region 206 is preferably in the range of 5×10 16 ~2×10 18 cm -3 By setting the impurity concentration of the region 206 to a predetermined value or more, it becomes easier for the region 206 to function as a part of the APD 201, and by setting the impurity concentration of the region 206 to a predetermined value or less, it becomes easier to electrically separate the region 206 from the region 204. The impurity concentration of the region 208 is preferably in the range of 2×10 16 ~2×10 17 cm -3 It is preferable that the impurity concentration of the region 208 is within the range of 2×10. By setting the impurity concentration of the region 208 to a predetermined value or more, it becomes easier for the region 208 to function as part of the APD 201, and by setting the impurity concentration of the region 208 to a predetermined value or less, it becomes easier for the region 208 to penetrate vertically and deplete during operation. The impurity concentration of the region 233 is determined by the distance between the region 204 and the region 206 and the impurity distribution of these two regions. Therefore, although it varies depending on the conditions, it is preferable that the impurity concentration of the region 233 is within the range of 2×10. 16 ~2×10 18 cm -3 The area 209 and the area 230 are preferably within the range of, for example, 5×10 16 ~2×10 18 cm -3 The area 232 is preferably in the range of, for example, 1×10 19 ~1×10 20 cm -3 As described above, the region 207 may be either a P-type or an N-type. For example, the region 207 may be formed by introducing an N-type impurity into a part of the region 233 to have an impurity concentration of, for example, 5×10 16 cm -3A conductive path is formed as a P-type or N-type region as described below. During operation, region 233 is depleted, and within the depleted region 233, region 207 has a low potential for electrons, becoming a conductive path for electrons. Note that if the semiconductor substrate before ion implantation is P-type, a portion of the semiconductor substrate located between region 204 and region 206 may become P-type region 233 even without introducing P-type impurity ions to form region 233.

[0082] 13, the impurity concentrations of the region 204 and the region 232 are different, but the region 204 may be formed with a high impurity concentration similar to that of the region 232, and no impurity may be introduced into the region corresponding to the region 232. Furthermore, when the region 232 is formed, the region 207 may be formed naturally by the tailing of the N-type impurity distribution in the depth direction.

[0083] The configuration of this embodiment, like the configurations shown in the first and second embodiments, can suppress the carrier multiplication factor when avalanche breakdown occurs. This effectively alleviates the aforementioned problems of light emission crosstalk, dark current variations, and power consumption. Furthermore, the presence of region 232 allows the configuration of this embodiment, in which regions 204, 207, and 206 overlap, to be effectively applied even when the size of pixel 104 is reduced. Furthermore, the configuration in which regions 204, 207, and 206 overlap can further reduce characteristic variations while suppressing an increase in the number of manufacturing processes.

[0084] (Fourth embodiment) Next, a photoelectric conversion device 100 according to a fourth embodiment of the present disclosure will be described with reference to FIG. 15. FIG. 15 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 according to this embodiment. The photoelectric conversion device 100 according to this embodiment differs from the third embodiment shown in FIG. 13 in that the region 233 has a doughnut shape with a hollow center in a plan view. Other than this point and points described below, the photoelectric conversion device 100 according to this embodiment is substantially the same as the third embodiment, and therefore description thereof may be omitted. The circuit diagram and SPAD operation according to this embodiment are also the same as those described in FIGS. 5, 7(a), 7(b), etc.

[0085] 16 is a diagram showing a method for forming the region 233 of the photoelectric conversion unit 102 arranged in the pixel 104 in this embodiment. In the figure, a resist 240 is arranged on a semiconductor substrate. The resist 240 is used when forming the region 204, the region 206, and the region 233. P-type impurity ions 241 are ions used to form the region 233.

[0086] Following a typical semiconductor manufacturing process, resist is applied to the entire surface of the semiconductor substrate, and then the resist is partially etched away from regions overlapping regions 204 and 206 in a plan view. Next, N-type impurity ions are implanted shallowly to form region 204 corresponding to the first cathode, and N-type impurity ions are implanted to a predetermined depth to form region 206 corresponding to the second cathode. Furthermore, as shown in FIG. 16 , P-type impurity ions 241 are implanted obliquely with respect to the interface of the semiconductor substrate while rotating the semiconductor substrate, thereby forming a doughnut-shaped region 233. The hollowed-out portion is a low-impurity P-type semiconductor or an N-type semiconductor. The desired region 207 can be formed by controlling the impurity concentration of region 190, the impurity concentration of region 233, the diameter of the hollowed-out portion, and the like.

[0087] When an N-type impurity is introduced into the region 233 to form a P-type or N-type region 207 with a low impurity concentration, the amount of N-type impurity introduced per unit area must be approximately equal to the amount of P-type impurity in the region 233. For example, if the P-type impurity concentration in the region 233 is 1×10 17 / cm 3 Assuming that the N-type impurity introduced to form the region 207 is 1.1×10 17 / cm 3 So, 1×10 16 / cm 3 An N-type region 207 is formed having a concentration of 1×10 16 / cm 3 The N-type region 207 contains 2.1 × 10 17 / cm 3 If the region 207 is a cube with a side length of 0.3 μm, the region 207 contains 1.1×10 17 ×(0.3×10 -4 ), or 2970 N-type impurity ions will be present. Similarly, there will be 2700 P-type impurity ions. The effective number of N-type impurity ions will be (2970 - 2700), or 270. These numbers are average numbers, and in reality the numbers will vary. Statistics teaches us that the standard deviation of variation is the root of the average number. In this case, the variation in the number of P-type and N-type impurity ions combined is the root of (2970 + 2700), or about 75. In other words, for an average effective number of N-type impurity ions of 270, the standard deviation of the variation is 75. Therefore, the concentration is 1 x 10 16 / cm 3 The standard deviation of the N-type carrier conduction path is 1±0.28×10 16 / cm 3This results in very large variations. The cause of this large variation is the presence of a large number of P-type impurity ions and a large number of N-type impurity ions in region 207, as described above. If large variations occur in region 207 among multiple pixels, that is, if the resistance value of region 207 varies significantly from pixel to pixel, the effectiveness of the present invention will be reduced in actual operation. However, according to this embodiment, only a small number of impurities are present in the hollowed-out portion of region 233, which becomes region 207. Applying the numerical values ​​of the above example, region 207 contains an average of only 270 N-type impurity ions. The standard deviation of this variation is approximately 16 times the square root of 270, which is significantly reduced from the standard deviation of 75 in the above example. Therefore, according to this embodiment, the characteristic variations among multiple pixels are small, and, like the first to third embodiments, three problems are improved: light emission crosstalk, changes in dark current, and power consumption when multiple photons are incident.

[0088] (Fifth embodiment) Next, a photoelectric conversion device 100 according to a fifth embodiment of the present disclosure will be described with reference to FIG. 17. FIG. 17 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. The photoelectric conversion device 100 in this embodiment differs from the third embodiment shown in FIG. 13 in that it includes regions 238 and 239. Other than this point and points described below, the photoelectric conversion device 100 is substantially the same as the third embodiment, and therefore description thereof may be omitted. The circuit diagram and SPAD operation in this embodiment are also the same as those described in FIG. 5, FIG. 7(a), FIG. 7(b), etc.

[0089] Region 238 is a P-type region formed at a depth similar to that of region 233 in a cross-sectional view, and over a wider area so as to surround region 233 in a planar view. Region 239 is an N-type region formed at a depth similar to that of region 206 in a cross-sectional view, and over a wider area so as to surround region 206 in a planar view. Regions 233 and 206 have shapes that overlap with region 204 in a planar view, and regions 238 and 239 have shapes that overlap with each other in a planar view. The following description will be given assuming the above-mentioned shapes, but the shapes are not limited to these.

[0090] Region 207 can be formed by introducing N-type impurities into a portion of region 233. However, in this case, as explained in the fourth embodiment, if the impurity concentration in region 233 is high, a problem may occur in which the characteristics of region 207 vary greatly. In order to reduce the variation in characteristics, it is necessary to reduce the concentration of P-type impurities in region 233. However, it may be difficult to reduce the concentration of P-type impurities in region 233 without variation.

[0091] FIG. 16 shows how P-type impurity ions are implanted obliquely into the semiconductor substrate to form the doughnut-shaped region 233 after regions 204 and 206 are formed in the openings of the resist 240. However, accurately forming a doughnut shape is not easy; P-type impurity ions are generally implanted almost perpendicularly into the semiconductor substrate to form the uniform region 233. When regions 204 and 206 are formed, a high-concentration N-type impurity layer is deposited between these two regions, i.e., in the region where region 233 is to be formed. Therefore, a situation may arise in which a larger amount of P-type impurity must be introduced to form region 233, which exceeds the N-type impurity and electrically isolates regions 204 and 206. The cause of this problem arises when region 206 is formed. Generally, implanting impurity ions creates a certain distribution in the depth direction of the semiconductor substrate. Therefore, when region 206 is formed, a certain N-type impurity distribution also occurs shallower than the peak. However, this problem arises due to a different mechanism.

[0092] Typically, semiconductor device fabrication involves repeatedly forming desired openings in resist and then implanting impurity ions into a semiconductor substrate. Essentially, only the impurity ions that enter the resist openings are selectively introduced into the semiconductor substrate. However, when the opening area is small and the energy of the impurity ion implantation is increased to form devices in deep areas, the phenomenon of some of the impurity ions implanted into the resist penetrating the openings becomes more pronounced. That is, relatively high-energy ions implanted into the resist move in the depth direction while gradually losing kinetic energy. Because these impurity ions exhibit random motion in the planar direction, impurity ions implanted particularly close to the resist openings may emerge at the resist openings and penetrate into the semiconductor substrate at the openings. By the time these impurity ions emerge at the resist openings, they have lost some of their kinetic energy and are generally deposited shallower than the desired depth. These unwanted impurity ions are often generated near the boundaries of the resist openings. When the resist opening area is large, these unwanted impurity ions are limited to the boundaries of the resist openings. However, when the opening area is small, these unwanted impurity ions practically penetrate the entire resist opening.

[0093] The situation described above occurs during implantation of N-type impurity ions to form region 206, and unwanted N-type impurity ions that pass through the resist are deposited shallower than the depth at which region 206 is to be formed, i.e., in the region where region 233 is to be formed. Therefore, a larger number of P-type impurity ions are required to form region 233. A large number of P-type and N-type impurity ions will be mixed in the region where region 207 is to be formed, which may result in large variations in the characteristics of region 207 as described in the fourth embodiment. A method for easily reducing such large variations in the characteristics of region 207 will be described below.

[0094] In this embodiment, the impurity concentration of region 206 is reduced to reduce the amount of N-type ion implantation used to form region 206. The amount of unnecessary N-type impurity ions entering the region where region 233 is to be formed is also reduced in proportion to the implantation amount. Meanwhile, region 206, which corresponds to the second cathode, plays a role in forming the APD together with region 208, and therefore requires a certain minimum impurity concentration. Therefore, region 239, which has a larger planar area than region 206, is assigned to partially form region 206. N-type impurity ions are implanted to form region 239 under approximately the same energy conditions as those for the N-type impurity ion implantation used to form region 206. This reduces the amount of N-type impurity ions required to form region 206.

[0095] For example, the amount of N-type impurity ions required per unit area in the region 206 is 1×10 13 / cm 2 The implantation amount of N-type impurity ions when forming the region 206 is set to 6×10 12 / cm 2 , the implantation amount of N-type impurities when forming the region 239 is 4×10 12 / cm 2 In total, the amount of N-type impurity ions introduced into the region 206 is 1×10 13 / cm 2 When forming region 239, the influence of unnecessary N-type impurity ions passing through the resist remains near the boundary of region 239 and hardly penetrates into region 233. Therefore, by forming region 206 together with region 239, the amount of unnecessary N-type impurity ions penetrating region 233 can be reduced. This allows for a reduction in the amount of P-type impurity ions introduced to form region 233, in other words, the amount of N-type impurity ions introduced to form region 207. Therefore, the characteristic variation of region 207 can be reduced. During operation, it is preferable that the regions of region 239 other than region 206 are depleted. Otherwise, the PN junction capacitance of region 206 increases, which would at least partially defeat the original purpose of the present invention, which is to reduce the carrier multiplication factor during avalanche generation.

[0096] 18 is a pixel cross-sectional view of the process of forming region 238 and region 239 shown in FIG. 17. After ion implantation of regions 204, 206, and 233, the process shown in FIG. 18 is carried out without a thermal process. In the figure, a resist 242 having an opening corresponding to the region where region 238 will be formed is disposed on the semiconductor substrate. The figure also shows the direction of implantation of P-type impurity ions 243 to form region 238. After region 238 is formed, N-type impurity ion implantation to form region 239 is carried out using the same resist 242.

[0097] It is generally known that implanting impurity ions parallel to the crystal axis of a semiconductor substrate causes channeling, resulting in the ions penetrating deeper than the desired depth into the semiconductor substrate. Since the direction perpendicular to the surface of a semiconductor substrate is usually the direction of the crystal axis, implanting impurity ions perpendicular to the surface of the semiconductor substrate also causes channeling. Meanwhile, semiconductor regions into which impurity ions are introduced at high concentrations partially lose their crystalline structure, causing them to become amorphous. Therefore, even if impurity ions are implanted into an amorphous region, channeling is suppressed because the crystal axis is disrupted.

[0098] In the step of FIG. 18, ion implantation has already been performed in the region 204, the region 206, and the region 233. In particular, the region 204 is implanted with approximately 1×10 18 cm -3Assume that the above high-concentration impurity ions have been introduced, and this portion has become amorphous. When P-type impurity ions are implanted to form region 238 in this state, channeling is suppressed in region 204 in a planar view, but channeling occurs in other portions. In the portion where channeling occurs, the P-type impurity ions penetrate deeply, and some of them reach region 239. Therefore, the effective N-type impurity concentration of region 239 in this portion decreases, making it more likely to be depleted. Meanwhile, in the portions of regions 204 and 206 in a planar view, the proportion of P-type impurity ions reaching the depth of region 206 is smaller, and the effective N-type impurity concentration of region 206 does not decrease significantly. Therefore, by using the method for forming region 238 shown in FIG. 18 , the N-type impurity concentration in the portions of region 239 other than regions 204 and 206 in a planar view can be selectively reduced, enabling these portions to be depleted during operation.

[0099] 19 shows the depth direction distribution of impurity ions in regions 204, 238, and 239. Of the two impurity ion distributions in region 238, the solid line represents the distribution in regions 204 and 206 on the planar layout. The dotted line represents the distribution in other regions, and shows that the distribution extends significantly to region 239.

[0100] The concentration of P-type impurities in region 233 is determined by the sum of the P-type impurity implantation in the process shown in Fig. 16 and the P-type impurity implantation in the process shown in Fig. 18, but the P-type impurity implantation in the process shown in Fig. 16 may not be performed. Furthermore, the N-type impurity ions in region 206 and region 239 may be implanted obliquely, slightly offset from the direction perpendicular to the surface of the semiconductor substrate, to suppress channeling. This improves the APD characteristics formed by region 206 and region 208, and the overlap of the impurity distributions in region 239 other than region 206 with region 238 becomes large, making depletion more likely during actual operation.

[0101] After the steps of forming region 238 and region 239 shown in FIG. 18 are completed, region 207 is formed. Region 207 may be formed in the same step as region 232, or in a separate step. If formed in separate steps, regions 207 and 232 may be positioned so as not to overlap in plan view, as shown in FIG. 14. It is also possible to set the N-type impurity concentration of region 204 to a very high concentration, and not form region 232. Region 207 may also be formed at the same time by forming region 232 slightly deeper.

[0102] In the configuration of this embodiment, the carrier multiplication factor when an avalanche breakdown occurs can be suppressed, similar to the configurations shown in the first to fifth embodiments. Furthermore, according to this embodiment, while suppressing the characteristic variations, effects are exhibited with respect to three problems, namely, light emission crosstalk, changes in dark current, and power consumption when a large number of photons are incident.

[0103] (Sixth embodiment) Next, the operation of the SPAD according to the sixth embodiment of the present disclosure will be described with reference to FIG. 20 . FIG. 20 is an equivalent circuit diagram of a portion of the photoelectric conversion unit 102 and the signal processing circuit 103. Compared to the equivalent circuit shown in FIG. 7( a), the configuration shown in FIG. 20 additionally includes a transistor 234. The transistor 234 is an N-type MOS transistor. The gate electrode of the transistor 234 is connected to node B. When node B goes high, the transistor 234 turns on and sets the potentials of node A and node D to a potential level that prevents avalanche breakdown in the APD 201. In other words, when the waveform shaping circuit 210 (detection circuit) detects avalanche breakdown, the transistor 234 functions as a setting circuit that sets the potentials of the regions 204 and 206 to a potential that prevents avalanche breakdown in the photoelectric conversion unit 102. In the configuration shown in FIG. 20 , when the transistor 234 turns on, the potentials of the regions 204 and 206 become 0 V, which is the ground level.

[0104] In the first to fifth embodiments described above, as shown in FIG. 7(b), the multiplication factor is suppressed when avalanche breakdown occurs, and as a result, the potentials of node A and node D remain high even after the avalanche breakdown occurs. Therefore, if more photons are incident in this state, a further avalanche breakdown may occur, and the potentials of node A and node D may become even lower due to discharge caused by the avalanche current. In this case, node B has already reached a high level due to the incidence of the first photon, and the incidence of the second or subsequent photons does not change the state of node B. In other words, the avalanche breakdown caused by the incidence of the second or subsequent photons is not detected as a signal, resulting in the generation of unnecessary electron-hole pairs.

[0105] Therefore, the circuit shown in FIG. 20 includes a transistor 234. When avalanche breakdown occurs due to the incidence of one photon during one cycle of the periodic reset pulse input to node C, the signal at node B generated by the waveform shaping circuit 210 goes high, indicating that avalanche breakdown has been detected. This turns on the transistor 234, and nodes A and D are grounded. As a result, avalanche breakdown does not occur in the APD 201, even if subsequent photons are incident until the next reset pulse is input to node C. In other words, the occurrence of avalanche breakdown is kept to a necessary minimum.

[0106] This embodiment is effective when the transistor 203 operates as a reset circuit for resetting the potentials of the region 204 (node ​​A) and the region 206 (node ​​D) to a predetermined potential. When the transistor 234 resets the node A and the node D (when the transistor 234 is ON), no electron-hole pairs are generated in the APD 201. The reset by the transistor 234 is a discharge across a potential difference of about 2 V to the ground level. Therefore, the required electrical energy is much smaller than the discharge across a potential difference of about 20 to 30 V to the large negative potential VL that occurs when an avalanche breakdown occurs.

[0107] As described above, according to this embodiment, in addition to suppressing the carrier multiplication factor when avalanche breakdown occurs, it is possible to prevent unnecessary avalanche breakdown from occurring within one cycle of the reset pulse periodically input to node C. Therefore, this embodiment has an even greater improvement effect on the problems of light emission crosstalk, changes in dark current, and power consumption than the first to fifth embodiments described above.

[0108] (Seventh embodiment) Next, a photoelectric conversion device 100 according to a seventh embodiment of the present disclosure will be described with reference to FIGS. 21 to 23(a) and 23(b). FIG. 21 is a plan view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. FIG. 22 is a cross-sectional view of the photoelectric conversion unit 102 taken along line AB shown in FIG. 21. FIG. 21 is a plan view of a main surface 251 of a semiconductor substrate 250 shown in FIG. 22. FIG. 23(a) is an equivalent circuit diagram of a portion of the photoelectric conversion unit 102 and the signal processing circuit 103, and FIG. 23(b) shows potential changes at nodes A to E during SPAD operation. Nodes A to D are located in the same positions as those shown in FIG. 7(a). Node E is a node connected to a gate electrode 235 of a transistor 237, which will be described later.

[0109] In the configurations shown in FIGS. 21 and 22 , region 206 may constitute a part of a main surface 251 of a semiconductor substrate 250. Furthermore, photoelectric conversion unit 102 further includes a transistor 237 that causes regions 204 and 206 to function as a source region and a drain region, respectively, and region 207 to function as a channel region. Transistor 237 is an N-type MOS transistor. Transistor 237 includes a gate electrode 235 and a gate insulating film 236 disposed between gate electrode 235 and main surface 251 of semiconductor substrate 250. Since region 190 is essentially depleted during operation, controlling the potential of gate electrode 235 determines whether a channel region (region 207) directly below gate electrode 235 is formed or not. As a result, transistor 237 controls conduction between region 204 and region 206. As shown in the equivalent circuit diagram of FIG. 23(a), the transistor 237 is disposed between node D connected to the cathode of the APD 201 and node A connected to the cathode of the parasitic PD 232.

[0110] Next, the operation of the SPAD of this embodiment will be described with reference to Figure 23(b). A pulse that turns on the transistor 237 is periodically input to node E, which is connected to the gate electrode 235 of the transistor 237. This causes the transistor 237 to conduct at a predetermined cycle. Furthermore, a reset pulse is input to node C at the same cycle as that of node E. This causes the transistor 203, which functions as a reset circuit for resetting the potentials of the regions 204 and 206 to a predetermined potential (potential VH), to reset the potentials of the regions 204 and 206 at the same cycle as that of the transistor 237.

[0111] At time t0, the reset of nodeA and nodeD ends. While transistor 237 is conducting due to the input of a pulse to nodeE, a reset pulse is input to nodeC, turning transistor 203 ON. This initiates the reset, resetting not only the potential of region 204 (nodeA) but also the potential of region 206 (nodeD). Next, transistor 237 turns OFF, and then transistor 203 turns OFF. As a result, nodeA and nodeD become floating at potential VH.

[0112] When a photon is incident at time t1, avalanche breakdown occurs in APD 201, and the potential of region 206 (node ​​D) drops to near the ground level, stopping avalanche multiplication. At this time, node D, which has only a small capacitance, has a small discharge capacity and therefore a small carrier multiplication factor. At time t2, node D becomes floating, maintaining the potential at which avalanche multiplication stopped.

[0113] Next, at time t3, node E goes high, turning on transistor 237. This causes node A and node D to become conductive, and a potential change occurs so that node A and node D have the same potential. The potential of node A drops and the potential of node D rises, but because the capacitance added to node A is large and the capacitance added to node D is small, the potential change of node A is small. Waveform shaping circuit 210 (detection circuit) detects avalanche breakdown according to the potential of node A (region 204) when transistor 237 becomes conductive. Therefore, avalanche breakdown in APD 201 can be detected by setting the decision threshold of waveform shaping circuit 210 to an appropriate value so that small potential changes of node A can be detected.

[0114] At time t4, the potential of node C goes low, turning on transistor 203 and again resetting nodes A and D. Next, at time t5, the potential of node C goes high, and the state returns to the state at time t0.

[0115] In this embodiment, the carrier multiplication factor when avalanche breakdown occurs may be further reduced compared to the first to fifth embodiments. In the configurations shown in the first to fifth embodiments, a certain degree of electrical conduction is always maintained between node A and node D through region 207, which functions as a resistor. Therefore, when avalanche breakdown occurs in the APD 201, a certain degree of discharge occurs at node A, which has a large capacitance. In contrast, in this embodiment, electrical conduction between node A and node D can be almost completely cut off while the transistor 237 is turned off and no channel region is generated. Therefore, when avalanche breakdown occurs in the APD 201, only discharge occurs at node D, which has a small load capacitance.

[0116] Consider the case where multiple photons are incident during one reset cycle by transistor 203 (reset circuit). Even in this case, in this embodiment, the avalanche breakdown caused by the first incident photon causes the potential of node D to drop sufficiently to about the ground level. Therefore, avalanche breakdown due to the incidence of the second or subsequent photons does not occur. Therefore, in this embodiment, there is no need to provide transistor 234 as shown in the third embodiment.

[0117] As described above, according to this embodiment, the carrier multiplication factor when an avalanche breakdown occurs can be further suppressed compared to the above-described embodiments. Therefore, this embodiment exhibits further improvements in each of the above-described three problems, namely, light emission crosstalk, changes in dark current, and power consumption.

[0118] (Eighth embodiment) Next, a photoelectric conversion device 100 according to an eighth embodiment of the present disclosure will be described. This embodiment can be considered a modification of the seventh embodiment, and similar to the configurations shown in FIGS. 21 and 22, an APD 201 and a parasitic PD 232 are connected by a transistor 237. Meanwhile, in this embodiment, as shown in FIG. 24, a comparator 220 is used as a detection circuit for detecting avalanche breakdown instead of the waveform shaping circuit 210. Node A is connected to the negative input terminal of the comparator 220, and node F is connected to the positive input terminal.

[0119] Next, the SPAD operation in this embodiment will be described with reference to Fig. 25. This embodiment operates to handle the incidence of multiple photons in one signal detection operation (operation between two consecutive reset pulses input to node C), count the number of incident photons, and perform signal processing.

[0120] As shown in FIG. 25, in this embodiment, as in the seventh embodiment described above, a pulse is periodically input to node E, and transistor 237 conducts at a predetermined cycle. On the other hand, unlike the seventh embodiment, a reset pulse is not input to node C at the same cycle as node E, but a reset pulse that resets the potentials of regions 204 and 206 is input each time the transistor conducts a predetermined number of times. In the example shown in FIG. 25, one reset pulse is input to node C for every four pulses input to node E. The relationship between the reset pulse input to node C and the pulse input to node E when a reset pulse is input to node C may be the same as the relationship shown in FIG. 23(b).

[0121] During one cycle in which a reset pulse is input to node C, pulses that turn on transistor 237 are periodically input to node E. In the example shown in FIG. 25 , photons are incident at times t1, t2, and t3. These photons are incident during the first, third, and fourth cycles of the four cycles in which a pulse is input to node E during one cycle in which a reset pulse is input to node C. Even if avalanche breakdown occurs in APD 201 due to incident photons, the input of a pulse to node E causes transistor 237 to conduct, and the potential of node D (region 206) rises. Therefore, three avalanche breakdowns occur in APD 201 in response to the three incident photons. Each time transistor 237 turns on, the potential of node A drops by an amount equivalent to the total discharge amount in the three avalanche breakdowns. The potential of node A from time t4 to time t5 is the potential that drops by an amount equivalent to the total discharge amount in the three avalanche breakdowns. The capacitance added to the APD 201 (region 206) is small, and the amount of discharge per avalanche breakdown is small. Therefore, this embodiment utilizes the fact that multiple avalanche breakdowns can occur in the APD 201 even when node A (and node D) are not reset to the potential VH.

[0122] 25, nodeF and nodeB are shown enlarged from time t4 to time t5. Step-like potentials V0, V1, V2, V3, and V4 are input to nodeF, which is connected to the positive input terminal of comparator 220. Vn (n=0, 1, 2, 3, 4) are potentials corresponding to the number of avalanche breakdowns that occur during one cycle of the reset pulse input to nodeC. Each value is set so that when Vn, where n≧k, is input to nodeF for k occurrences of avalanche breakdown, nodeB, which corresponds to the output of comparator 220, is inverted from High to Low.

[0123] Generally, comparator 220 constantly flows current during operation, so it may be configured to operate only during the period from time t4 to time t5. Also, during current-off periods other than the period from time t4 to time t5, the potential of node B may be set to High. Such a circuit configuration of a comparator is very common, so details are omitted.

[0124] In the example shown in FIG. 25, node B inverts at time t6 when node F becomes V3. Therefore, the number of avalanche breakdowns that have occurred is determined to be three. In this way, comparator 220 (detection circuit) generates a multi-level signal corresponding to the potential of node A while transistor 237 is conducting a predetermined number of times and before transistor 203 (reset circuit) resets the potentials of node A and node D. This makes it possible to count the number of avalanche breakdowns that have occurred due to the incidence of multiple photons in one signal detection operation (operation between two consecutive reset pulses input to node C).

[0125] This embodiment is not limited to the configuration shown in FIG. 24 . A circuit configuration that does not pass a steady-state current during operation of the comparator 220 is also possible. The connection between the parasitic PD 232 and the APD 201 may be a region 207 that functions as a resistor, as in the first and second embodiments. When the region 207 functions as a resistor, an N-type transistor with its source region connected to node A and its drain region connected to the negative input terminal may be placed between the negative input terminal and node A of the comparator 220, with the gate electrode at a constant potential. Using the saturation region operation of this transistor, discharge occurs from the drain region due to avalanche breakdown occurring in the APD 201. As long as the saturation region operation is maintained, a potential change equivalent to the total discharge charge due to multiple avalanche currents occurs in the drain region. The comparator 220 detects this potential change in the drain region and can count the number of avalanche breakdowns that have occurred.

[0126] Here, the count of the comparator 220 does not necessarily have to match the actual number of avalanche breakdowns. It is sufficient to provide a circuit that converts the analog quantity, i.e., the total discharge charge generated by multiple avalanche breakdowns, into a digital quantity. For example, a digital signal of "1" may correspond to 2.5 avalanche breakdowns in the APD 201. In other words, the conversion gain, which is the digital signal divided by the actual number of avalanche breakdowns, can take a value other than 1. Setting a small conversion gain allows a small digital signal to represent a large number of avalanche breakdowns.

[0127] Furthermore, for example, a circuit equivalent to a source follower may be connected to node A instead of comparator 220. In this case, the circuit connected to node A may have a configuration that performs AD conversion on the source follower output, such as that used in a readout circuit for a CMOS sensor.

[0128] As explained with reference to FIG. 2, in a SPAD, the number of avalanche breakdown occurrences in each pixel 104 is generally counted using a counter circuit 211, and the maximum count is determined by the number of bits in the counter circuit 211. Since the size of the pixel 104 is limited, the number of bits that can be formed in the counter is also limited. Therefore, by reducing the conversion gain of the digital signal / actual number of avalanche breakdown occurrences described above, it is possible to accommodate a greater number of incident photons. In other words, the saturation signal of the pixel 104 can be increased. Reducing this conversion gain can be effective, particularly when the number of incident photons is large.

[0129] As described above, according to this embodiment, similar to the seventh embodiment, the carrier multiplication factor when avalanche breakdown occurs can be suppressed. In other words, this embodiment provides an improvement over the three problems mentioned above: light emission crosstalk, changes in dark current, and power consumption. Furthermore, compared to the seventh embodiment, the reset pulse input to node C can be made shorter in period. This makes it possible to reduce the power consumption required for the drive pulse (reset pulse). Furthermore, as described above, it is also possible to increase the saturation signal of the pixel.

[0130] An application example of the photoelectric conversion device 100 according to the above-described embodiment will now be described. FIG. 26 is a schematic diagram of an apparatus EQP equipped with the photoelectric conversion device 100. As shown in FIG. 26, the photoelectric conversion device 100 is housed in a semiconductor package PKG. The package PKG may include a base on which the photoelectric conversion device 100 is fixed, a cover such as glass facing the photoelectric conversion device 100, and conductive connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the photoelectric conversion device 100. The apparatus EQP may further include at least one of a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0131] The optical system OPT forms an image on the pixel array 101 and may be, for example, a lens, a shutter, or a mirror. The control device CTRL controls the operation of the photoelectric conversion device 100 and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device 100 and may be, for example, a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays data obtained by the photoelectric conversion device 100. The memory device MMRY is a magnetic device or a semiconductor device that stores data obtained by the photoelectric conversion device 100. The memory device MMRY may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN may have a moving or propulsive part such as a motor or an engine. The mechanical device MCHN also drives components of the optical system OPT for, for example, zooming, focusing, and shutter operation. The device EQP displays the data output from the photoelectric conversion device 100 on the display device DSPL, and transmits the data to the outside via a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0132] The device EQP incorporating the photoelectric conversion device 100 can be applied to surveillance cameras, on-board cameras mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, and industrial robots. In addition, the device EQP incorporating the photoelectric conversion device 100 can be applied not only to transportation equipment but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[0133] The device EQP is suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The device EQP may also be transportation equipment such as vehicles, ships, and aircraft. The device EQP as transportation equipment is suitable for transporting the photoelectric conversion device 100 and assisting and / or automating driving (piloting) using the photographing function. The processing device for assisting and / or automating driving (piloting) can perform processing for operating a mechanical device as a mobile device based on information obtained by the photoelectric conversion device 100. Alternatively, the device EQP may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0134] According to the above-described embodiment, it is possible to provide a technique that is advantageous for suppressing the multiplication factor. Therefore, if the photoelectric conversion device according to this embodiment is used in equipment EQP, the value of the equipment can also be improved.

[0135] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0136] (Item 1) A photoelectric conversion device in which a photoelectric conversion unit is disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type that forms a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region disposed between the first region and the second region, the second region and the third region function as an avalanche photodiode; A photoelectric conversion device, characterized in that the first region and the second region are configured to be electrically conductive through the fourth region.

[0137] (Item 2) 2. The photoelectric conversion device according to item 1, wherein the first region and the third region do not function as an avalanche photodiode.

[0138] (Item 3) 3. The photoelectric conversion device according to item 1 or 2, wherein the distance between the second region and the third region is shorter than the distance between the first region and the third region.

[0139] (Item 4) A photoelectric conversion device in which a photoelectric conversion unit is disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type that forms a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region arranged to connect the first region and the second region, A photoelectric conversion device, wherein the distance between the second region and the third region is shorter than the distance between the first region and the third region.

[0140] (Item 5) 5. The photoelectric conversion device according to any one of items 1 to 4, wherein the fourth region has a lower impurity concentration than the first region and the second region.

[0141] (Item 6) the photoelectric conversion unit further includes a fifth region between the third region and the second main surface, the fifth region having an impurity concentration lower than those of the first region and the second region; A photoelectric conversion device according to any one of items 1 to 5, characterized in that charges generated in the fifth region by the incidence of light flow into the second region through a depletion region formed in a region of the third region that overlaps with the second region in an orthogonal projection onto the first principal surface.

[0142] (Item 7) 7. The photoelectric conversion device according to any one of items 1 to 6, wherein the fourth region includes the first conductivity type region.

[0143] (Item 8) 8. The photoelectric conversion device according to item 7, wherein the fourth region functions as a resistor connecting the first region and the second region.

[0144] (Item 9) 9. The photoelectric conversion device according to item 8, wherein the fourth region functions as a resistor of 20 kΩ or more.

[0145] (Item 10) 10. The photoelectric conversion device according to any one of items 1 to 9, wherein the second region constitutes a part of the first main surface.

[0146] (Item 11) 10. The photoelectric conversion device according to any one of items 1 to 9, wherein the second region is disposed between the first region and the third region.

[0147] (Item 12) The photoelectric conversion device described in any one of items 1 to 11, further comprising a setting circuit that sets the potential of the first region and the second region to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit when the detection circuit detects avalanche breakdown.

[0148] (Item 13) 13. The photoelectric conversion device according to any one of items 1 to 12, further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential.

[0149] (Item 14) the second region constitutes a part of the first main surface, the photoelectric conversion unit further includes a transistor that causes the first region and the second region to function as a source region or a drain region, respectively, and the fourth region to function as a channel region; 7. The photoelectric conversion device according to any one of items 1 to 6, wherein the transistor controls conduction between the first region and the second region.

[0150] (Item 15) further comprising a reset circuit for resetting the potentials of the first region and the second region to predetermined potentials; The transistor is turned on at a predetermined period, Item 15. The photoelectric conversion device according to item 14, wherein the reset circuit resets the potentials of the first region and the second region at the same cycle as the transistor.

[0151] (Item 16) Item 16. The photoelectric conversion device according to item 15, wherein the detection circuit detects an avalanche breakdown in accordance with the potential of the first region when the transistor is conductive.

[0152] (Item 17) further comprising a reset circuit for resetting the potentials of the first region and the second region to predetermined potentials; The transistor is turned on at a predetermined period, Item 15. The photoelectric conversion device according to item 14, wherein the reset circuit resets the potentials of the first region and the second region every time the transistor conducts a predetermined number of times.

[0153] (Item 18) Item 18. The photoelectric conversion device of item 17, wherein the detection circuit generates a digital signal corresponding to the potential of the first region when the transistor is conductive for the predetermined number of times and before the reset circuit resets the potentials of the first region and the second region.

[0154] (Item 19) 19. The photoelectric conversion device according to any one of items 15 to 18, wherein the reset circuit starts resetting while the transistor is conducting.

[0155] (Item 20) Item 12. The photoelectric conversion device according to item 11, characterized in that it includes at least a region where the first region and the second region overlap in a planar view, and has a sixth region of the second conductivity type arranged at a depth between the first region and the second region.

[0156] (Item 21) The photoelectric conversion device according to item 20, wherein the fourth region is surrounded by the sixth region in a plan view, has approximately the same depth as the sixth region, and is a region of the first conductivity type or a region of the second conductivity type that has a lower impurity concentration than the sixth region. (Item 22) A photoelectric conversion device according to any one of items 1 to 21, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0157] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0158] 100 Photoelectric conversion device 102 Photoelectric conversion unit 204,206,207,208 area 201 APD 250 Semiconductor Substrates 251,252 Main surface

Claims

1. A photoelectric conversion device in which a photoelectric conversion unit is disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a portion of the first major surface and connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type disposed apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region disposed between the first region and the second region, the second region is disposed between the first region and the third region, the second region and the third region function as an avalanche photodiode; The first region and the second region are configured to be electrically conductive through the fourth region, A photoelectric conversion device characterized by including at least a region where the first region and the second region overlap in a planar view, and having a sixth region of the second conductivity type arranged at a depth between the first region and the second region.

2. A photoelectric conversion device in which a photoelectric conversion unit is arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a portion of the first major surface and connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type disposed apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region disposed between the first region and the second region, the second region and the third region function as an avalanche photodiode; The first region and the second region are configured to be electrically conductive through the fourth region, A photoelectric conversion device comprising a sixth region of a second conductivity type that is in contact with at least the first region and the second region and is disposed at a depth between the first region and the second region.

3. 3. The photoelectric conversion device according to claim 1, wherein the fourth region has a lower impurity concentration than the first region and the second region.

4. 3. The photoelectric conversion device according to claim 1, wherein the first region and the third region do not function as an avalanche photodiode.

5. 3. The photoelectric conversion device according to claim 1, wherein the distance between the second region and the third region is shorter than the distance between the first region and the third region.

6. A photoelectric conversion device in which a photoelectric conversion unit is disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a part of the first main surface and connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type disposed apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region arranged to connect the first region and the second region, the second region is disposed between the first region and the third region, a distance between the second region and the third region is shorter than a distance between the first region and the third region; A photoelectric conversion device characterized by including at least a region where the first region and the second region overlap in a planar view, and having a sixth region of the second conductivity type arranged at a depth between the first region and the second region.

7. A photoelectric conversion device in which a photoelectric conversion unit is arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a part of the first main surface and connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type disposed apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being located closer to the second main surface than the first region and the second region; a fourth region arranged to connect the first region and the second region, a distance between the second region and the third region is shorter than a distance between the first region and the third region; A photoelectric conversion device comprising a sixth region of a second conductivity type that is in contact with at least the first region and the second region and is disposed at a depth between the first region and the second region.

8. 8. The photoelectric conversion device according to claim 6, wherein the fourth region has a lower impurity concentration than the first region and the second region.

9. the photoelectric conversion unit further includes a fifth region between the third region and the second main surface, the fifth region having an impurity concentration lower than those of the first region and the second region; The photoelectric conversion device of claim 1 or 2, characterized in that charges generated in the fifth region by the incidence of light flow into the second region through a depletion region formed in a region of the third region that overlaps with the second region in an orthogonal projection onto the first principal surface.

10. 3. The photoelectric conversion device according to claim 1, wherein the fourth region includes a region of the first conductivity type.

11. 11. The photoelectric conversion device according to claim 10, wherein the fourth region functions as a resistor connecting the first region and the second region.

12. 12. The photoelectric conversion device according to claim 11, wherein the fourth region functions as a resistor of 20 kΩ or more.

13. 8. The photoelectric conversion device according to claim 2, wherein the second region is disposed between the first region and the third region.

14. The photoelectric conversion device according to claim 1 or 2, further comprising a setting circuit that sets the potential of the first region and the second region to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit when the detection circuit detects avalanche breakdown.

15. 3. The photoelectric conversion device according to claim 1, further comprising a reset circuit for resetting the potentials of the first region and the second region to predetermined potentials.

16. The photoelectric conversion device of any one of claims 1, 2, 6, or 7, characterized in that the fourth region is surrounded by the sixth region in a planar view, has approximately the same depth as the sixth region, and is a region of the first conductivity type or a region of the second conductivity type having an impurity concentration of the second conductivity type lower than the impurity concentration of the sixth region.

17. The photoelectric conversion device according to claim 1 , 2 , 6 , or 7 ; a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

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