MEMORY, STORAGE SYSTEM, AND METHODS FOR OPERATING A MEMORY - Patent application

Abstract

A memory, a storage system, and an operating method for a memory, which belong to the field of storage technology, are disclosed, which include receiving an operation command from a controller, in which the operation command maps a plurality of initial word line identifiers to a plurality of physical word line identifiers, and performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers, wherein at least one of a third-type memory cell row is distributed between a first memory cell row and a second memory cell row in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows correspond to the same parity data.

Description

[Technical Field]

[0001] The present application relates to the field of storage, and in particular to memories, storage systems, and methods for operating memories. [Background technology]

[0002] When writing data to a memory such as a 3D NAND (NAND gate), parity data can be generated according to the written data to avoid errors in subsequent data reads. In this way, when data is read from the memory, the read data is verified according to the parity data, and if the verification fails, the correct data can be restored according to the parity data. Therefore, how to ensure successful data restoration when the verification fails is a current research hotspot. Summary of the Invention [Problem to be solved by the invention]

[0003] The examples of the present application provide a memory, a storage system, and a method for operating a memory that can be configured to improve the ability for data protection. The technical solutions are as follows: [Means for solving the problem]

[0004] In one aspect, a memory is provided, the memory comprising: a memory array including a plurality of rows of memory cells; a plurality of word lines respectively coupled to a plurality of rows of memory cells; coupled to a plurality of word lines; receiving an operation command from a controller, the operation command carrying a plurality of initial word line identifiers; Mapping a plurality of initial word line identifiers to a plurality of physical word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers; and a peripheral circuit configured to perform the Including, At least one of the third type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and data stored in the plurality of first type memory cell rows corresponds to the same parity data.

[0005] In some examples, the peripheral circuitry includes: The method is configured to take each of the plurality of initial word line identifiers as a dummy word line identifier, and obtain the physical word line identifier corresponding to each of the initial word line identifiers from the stored mapping relationship between the dummy word line identifiers and the physical word line identifiers.

[0006] In some examples, the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier, and a mapping relationship between a second dummy word line identifier and a second physical word line identifier; The two memory cell rows coupled to the two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

[0007] In some examples, the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, and a difference between the first dummy word line number and the second dummy word line number is 1; The first physical word line identifier includes a first physical word line number, the second physical word line identifier includes a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1.

[0008] In some examples, the first dummy word line number is less than the second dummy word line number; The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0009] In some examples, at least one of the third type memory cell rows is distributed between every two adjacent memory cell rows of the plurality of first type memory cell rows.

[0010] In some examples, the number of third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is the reference quantity.

[0011] In some examples, the peripheral circuitry includes: When a word line mapping command is received from the controller, the memory controller is configured to perform an operation of mapping a plurality of initial word line identifiers to a plurality of physical word line identifiers.

[0012] In some examples, the peripheral circuitry includes: When a word line mapping command from the controller is not received, an operation corresponding to the operation command is performed on the plurality of second-type memory cell rows via the plurality of second-type word lines indicated by the plurality of initial word line identifiers. further configured as follows: Here, the plurality of second-type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows corresponds to the same parity data.

[0013] In some examples, the operation instruction includes a write instruction, the write instruction further carrying a plurality of data to be written corresponding one-to-one to the plurality of initial word line identifiers; The peripheral circuits are The memory cell is configured to take the data to be written corresponding to each of the initial word line identifiers as the data to be written corresponding to the respective physical word line identifiers, and to perform a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written in the plurality of first-type memory cell rows.

[0014] In some examples, the operating instructions include a read instruction; The peripheral circuits are configured to perform a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to retrieve data stored respectively within the plurality of first-type memory cell rows.

[0015] In some examples, the peripheral circuitry includes: If the data stored in a third memory cell row of the plurality of first-type memory cell rows includes erroneous data, determining an initial word line identifier corresponding to the physical word line identifier of the third memory cell row; Obtaining parity data based on the determined initial word line identifier; Correcting the data stored in the third row of memory cells based on the parity data. It is further configured as follows.

[0016] In another aspect, a storage system is provided that includes a memory and a controller coupled to the memory and configured to control the memory, a controller configured to send an operation command to the memory, the operation command carrying a plurality of initial word line identifiers; the memory is configured to receive an operation command, map a plurality of initial word line identifiers to a plurality of physical word line identifiers, and perform an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers; At least one of the third type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and data stored in the plurality of first type memory cell rows corresponds to the same parity data.

[0017] In some examples, the controller is further configured to send a word line mapping instruction to the memory; The memory is further configured to perform an operation to map the plurality of initial word line identifiers to a plurality of physical word line identifiers in response to a word line mapping command.

[0018] In some examples, the controller is further configured to not send word line mapping instructions to the memory; The memory is further configured to perform an operation corresponding to the operation command on the plurality of second-type memory cell rows via the plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows corresponds to the same parity data.

[0019] In some examples, the operation instruction includes a write instruction, the write instruction further carrying a plurality of data to be written corresponding one-to-one to the plurality of initial word line identifiers; The memory is configured to take data to be written corresponding to each of the initial word line identifiers as data to be written corresponding to the respective physical word line identifiers, and perform a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store a plurality of data to be written in the plurality of first-type memory cell rows.

[0020] In some examples, the operating instructions include a read instruction; The memory is configured to perform a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to retrieve data stored in each of the plurality of first-type memory cell rows; The memory is further configured to send results of the data read to the controller, the results of the data read carrying data respectively stored in the plurality of rows of memory cells of the first type; The controller is configured to receive the results of the data read.

[0021] In another aspect, a method of operating a memory is provided, the method comprising: receiving an operation command from a controller, the operation command carrying a plurality of initial word line identifiers; mapping a plurality of initial word line identifiers to a plurality of physical word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers; Including, At least one of the third type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and data stored in the plurality of first type memory cell rows corresponds to the same parity data.

[0022] In some examples, the step of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers comprises: The method includes taking each of a plurality of initial word line identifiers as a dummy word line identifier, and obtaining a physical word line identifier corresponding to each of the initial word line identifiers from a stored mapping relationship between the dummy word line identifiers and the physical word line identifiers.

[0023] In some examples, the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier, and a mapping relationship between a second dummy word line identifier and a second physical word line identifier; The two memory cell rows coupled to the two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

[0024] In some examples, the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, and a difference between the first dummy word line number and the second dummy word line number is 1; The first physical word line identifier includes a first physical word line number, the second physical word line identifier includes a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1.

[0025] In some examples, the first dummy word line number is less than the second dummy word line number; The second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0026] In some examples, at least one of the third type memory cell rows is distributed between every two adjacent memory cell rows of the plurality of first type memory cell rows.

[0027] In some examples, the number of third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is the reference quantity.

[0028] In some examples, the step of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers comprises: If a word line mapping command is received from the controller, performing an operation of mapping a plurality of initial word line identifiers to a plurality of physical word line identifiers is included.

[0029] In some examples, the method comprises: If no word line mapping command is received from the controller, performing an operation corresponding to the operation command on the plurality of second-type memory cell rows via the plurality of second-type word lines indicated by the plurality of initial word line identifiers; The plurality of second-type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows corresponds to the same parity data.

[0030] In some examples, the operation instruction includes a write instruction, the write instruction further carrying a plurality of data to be written corresponding one-to-one to the plurality of initial word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers, The method includes taking the data to be written corresponding to each of the initial word line identifiers as the data to be written corresponding to the respective physical word line identifiers, and performing a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written in the plurality of first-type memory cell rows.

[0031] In some examples, the operating instructions include a read instruction; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers, The method includes performing a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to obtain data stored in each of the plurality of first-type memory cell rows.

[0032] In some examples, the method comprises: If the data stored in a third memory cell row of the plurality of first-type memory cell rows is incorrect data, determining an initial word line identifier corresponding to the physical word line identifier of the third memory cell row; obtaining parity data based on the determined initial word line identifier; Further comprising correcting the data stored in the third row of memory cells based on the parity data.

[0033] In the example of the present application, at least one of the third-type memory cell rows is distributed between the first and second memory cell rows of the plurality of first-type memory cell rows, and the data stored in the plurality of first-type memory cell rows corresponds to the same parity data. Therefore, the method provided by the example of the present application allows multiple data corresponding to the same parity data to be written to discontinuous memory cell rows. In this way, data stored in adjacent memory cell rows in a memory array can be implemented to correspond to different parity data. In this way, even if the distance between adjacent memory cell rows is too short, thereby causing charge interaction and further causing the data stored in adjacent memory cell rows to be simultaneously erroneous, since the data stored in the adjacent memory cell rows correspond to different parity data, the data stored in the adjacent memory cell rows can be corrected respectively through at least two parity data, thereby improving the ability to protect data.

[0034] In order to more clearly illustrate the technical solutions in the examples of the present application, the accompanying drawings that need to be used in the description of the examples are briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples of the present application, and those skilled in the art can also obtain other drawings according to these accompanying drawings without any creative efforts. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a schematic diagram of a storage system 10 provided by an example of the present application. [Figure 2] 1 is a schematic diagram of a memory device provided by an example of the present application; [Figure 3] FIG. 2 is a schematic diagram of another memory device provided by an example of the present application. [Figure 4] 1 is a schematic diagram of a memory 100 provided by an example of the present application. [Figure 5]1 is a schematic diagram of a cross section of a memory array 110 including a memory string 111 provided by an example of the present application. [Figure 6] FIG. 2 is a schematic diagram of a peripheral circuit provided by an example of the present application. [Figure 7] 1 is a flowchart of a method of operating a memory provided by an example of the present application. [Figure 8] 10 is a flowchart of another method of operating a memory provided by an example of the present application. [Figure 9] 1 is a flowchart of data writing provided by an example of the present application; [Figure 10] 1 is a flowchart of data reading provided by an example of the present application; [Figure 11] 10 is a flowchart of another method of operating a memory provided by an example of the present application. [Figure 12] 10 is a flowchart of another method of operating a memory provided by an example of the present application. [Figure 13] FIG. 2 is a structural schematic diagram of a controller provided by an example of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0036] To make the objectives, technical solutions and advantages of the present application clearer, the implementation of the present application is described in more detail below in conjunction with the accompanying drawings.

[0037] 1 is a schematic diagram of a storage system 10 provided by an example of the present application. As shown in FIG. 1, the storage system 10 includes one or more memories 100 and a controller 200 coupled to the memories 100 and configured to control the memories 100.

[0038] Controller 200 may be configured to control operations performed by memory 100, such as read, erase, and programming operations. Controller 200 may further be configured to manage various functions related to data stored or to be stored in memory 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some examples, controller 200 may further be configured to process error correcting codes (ECC) associated with data read from or written to memory 100. Controller 200 may also perform any other suitable functions, such as formatting memory 100.

[0039] The controller 200 may communicate with external devices according to a specific communication protocol. In some examples, the controller 200 may communicate with external devices via at least one of various interface protocols. The interface protocol may be a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Development Environment (IDE) protocol, a Firewire protocol, or the like.

[0040] In some examples, the controller 200 and one or more memories 100 may be integrated into various types of electronic devices. The electronic device 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. In this scenario, as shown in FIG. 1 , the storage system 10 further includes a host 300. The controller 200 is coupled to the host 300. The controller 200 may manage the data stored in the memory 100 and communicate with the host 300 to implement the functionality of the aforementioned electronic device.

[0041] In other examples, the controller 200 and one or more memories 100 may be integrated into various types of memory devices.

[0042] 2, the controller 200 and the single memory 100 may be integrated into a memory card 400. The memory card 400 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a CompactFlash (CF) card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Reduced Size MMC (RS-MMC), a Micro MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. As shown in FIG. 2, the memory card 400 may further include a connector 410 for coupling the memory card 400 to a host.

[0043] 3, the controller 200 and the plurality of memories 100 may be integrated into a solid-state disk (SSD) 500. The solid-state drive 500 may also include a connector 510 that couples the solid-state drive 500 to a host. At least one of the storage capacity or operating speed of the solid-state drive 500 is greater than at least one of the storage capacity or operating speed of the memory card 400.

[0044] Additionally, the memory 100 in Figures 1 to 3 can be any memory included in the examples of the present application. For example, the memory 100 can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be described and explained below.

[0045] 4 is a schematic diagram of a memory 100 provided by an example of the present application. As shown in FIG. 4, the memory 100 includes: a memory array (110) including a plurality of rows of memory cells; a plurality of word lines 120 respectively coupled to a plurality of rows of memory cells; The memory includes peripheral circuitry 130 coupled to the plurality of word lines 120 and configured to perform an operation such as programming (i.e., writing data) or reading data on a selected memory cell row of the plurality of memory cell rows, the selected memory cell row being the memory cell row to which the selected line is coupled, and in order to perform an operation such as programming or reading data, the peripheral circuitry 130 is configured to perform a method of operating a memory provided by an example of the present application.

[0046] 1, a NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, with each of the memory strings 111 extending vertically above the substrate (not shown). In some examples, each of the memory strings 111 includes a plurality of memory cells 112 coupled in series and stacked vertically.

[0047] 4, each of the memory strings 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called a lower select transistor, a lower select gate (BSG), or a source select transistor, and the drain select gate is also called an upper select transistor, a upper select gate (TSG), or a drain select transistor. The source select gate 113 and the drain select gate 114 may be configured to activate a selected string 111 during read and program operations.

[0048] In some examples, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115 from which data can be read or written via an output bus (not shown).

[0049] In some examples, each of the memory strings 111 is configured to apply a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a non-select voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. Alternatively, in some examples, each of the memory strings 111 is configured to be selected or non-selected via applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a non-select voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0050] As shown in FIG. 4, the memory strings 111 may be organized into multiple blocks 140, and for any block 140 of the multiple blocks 140, the block 140 may have a source line (SL) 118, and the sources of all memory strings 111 within the block 140 are coupled via the source line 118, also referred to as a common source line or array common source (ACS).

[0051] Here, source line 118 may be used for grounding in some operations to implement grounding of the sources of each memory cell of the memory string later in block 140. In some examples, in some other operations, the sources of each memory cell of the memory string in block 140 may also be connected to a high voltage via source line 118.

[0052] Here, each block 140 is the basic data unit for an erase operation, i.e., all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, a source line coupled to the selected block may be biased with an erase voltage (Vers), for example, a high positive voltage (20V or greater).

[0053] It should be understood that in other examples, the erase operation may be performed at a half-block level, a quarter-block level, or any suitable number or percentage of blocks.

[0054] As shown in FIG. 4, adjacent memory strings 111 and memory cells 112 in the same layer within the same block 140 may be coupled via word lines 120, which are configured to select which layer of memory cells 112 within the block 140 is affected by read and program operations.

[0055] In some examples, each of the word lines 120 is coupled to a page 150 to which a memory cell 112 belongs, and the page 150 is a basic data unit for program operations. Here, the size of the page 150 may be related to the number of memory strings 111 coupled to the word line 120 in one block 140. Each of the word lines 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page 150. It may be understood that a memory cell row is a plurality of memory cells 112 arranged on the same page 150.

[0056] It should be noted that memory cells in the same layer in one block 140 correspond to the same word line, but the memory cells in the same layer can be divided into one or more pages, i.e., one word line can be coupled to one or more pages, for example, in the case of SLC, one word line is coupled to one page, and in the case of MLC, one word line is coupled to two pages.

[0057] 5 is a schematic diagram of a cross section of a memory array 110 including memory strings 111 provided by examples of the present application. As shown in FIG. 5, the memory strings 111 may extend vertically above a substrate 101 and through stacked layers 102. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0058] The stacked layer 102 may include alternating gate conductive layers 103 and inter-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and inter-gate dielectric layers 104 in the stacked layer 102 may determine the number of memory cells 112 in the memory array 110.

[0059] The gate conductive layers 103 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some examples, each of the gate conductive layers 103 includes a metal layer, such as a tungsten layer. In other examples, each of the gate conductive layers 103 includes a doped polysilicon layer. Additionally, each of the gate conductive layers 103 may include a control electrode surrounding the memory cell 112, which may extend laterally across the upper portion of the stack layer 102 as a DSG line 116, across the lower portion of the stack layer 102 as an SSG line 117, or between the DSG line 116 and the SSG line 117 as a word line 120.

[0060] As shown in FIG. 5 , the memory string 111 includes a channel structure 105 extending vertically through the stacked layers 102. In some examples, the channel structure 105 includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). The semiconductor channel includes silicon, e.g., polysilicon. The memory film is a composite dielectric layer including a tunnel layer, a storage layer (also called a “charge trap / storage layer”), and a blocking layer.

[0061] In some examples, the channel structure 105 has a cylindrical shape (e.g., a pillar shape), with the layers in the semiconductor channel and storage film radially arranged in that order from the center of the pillar to the outer surface of the pillar.

[0062] Although not shown in FIG. 5, it should be understood that memory array 110 may also include other additional components, including, but not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0063] 4 , peripheral circuitry 130 may be coupled to memory array 110 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116. Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 110 by applying at least one of voltage or current signals to, and sensing at least one of voltage or current signals from, memory cells 112 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116.

[0064] The peripheral circuit 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 6 shows some examples of the peripheral circuit 130, including a page buffer / sense amplifier 131, a column decoder / bitline (BL) driver 132, a row decoder / wordline (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 6 may also be included.

[0065] The page buffer / sense amplifiers 131 may be configured to read data from and program (write) data into the memory array 110 according to control signals from the control logic unit 135. For example, the page buffer / sense amplifiers 131 may store a page of programming data (written data) to be programmed into one page 150 of the memory array 110. The page buffer / sense amplifiers 131 may perform a program verify operation to confirm that the data has been correctly programmed into the memory cells 112 coupled to the selected word line 120. The page buffer / sense amplifiers 131 may also sense low-power signals from the bit lines 115, which represent data bits stored in the memory cells 112, and the page buffer / sense amplifiers 131 may amplify small voltage swings to recognizable logic levels during read operations.

[0066] The column decoder / bit line driver 132 is controlled by a control logic unit 135 and may be configured to select one or more memory strings 111 by applying a bit line voltage generated from a voltage generator 134 .

[0067] The row decoder / word line driver 133 is controlled by the control logic unit 135 and may be configured to select / deselect blocks 140 of the memory array 110 and to select / deselect word lines 120 of the blocks 140. The row decoder / word line driver 133 may also be configured to drive the word lines 120 with a word line voltage (VWL) generated from a voltage generator 134. In some examples, the row decoder / word line driver 133 may also select / deselect and drive the SSD lines 117 and the DSG lines 116. As described in more detail below, the row decoder / word line driver 133 is configured to perform an erase operation on memory cells 112 coupled to selected word lines 120.

[0068] The voltage generator 134 may be controlled by the control logic unit 135 and configured to generate word line voltages (e.g., read voltages, programming voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0069] The control logic unit 135 may be coupled to each of the peripheral circuits described above and may be configured to control the operation of each peripheral circuit.

[0070] The registers 136 may be coupled to the control logic unit 135, and may include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0071] Interface (I / F) 137 may be coupled to control logic unit 135 and may function as a control buffer that buffers and relays control commands received from a host (not shown) to control logic unit 135 and buffers and relays status information received from control logic unit 135 to the host. Interface 137 may also be coupled to column decoder / bit line drivers 132 via data bus 138 and may function as a data I / O interface and data buffer that buffers and relays data to and from memory array 110.

[0072] The above description of the memory-related hardware example has the same beneficial effect as the following method example. For technical details not disclosed in the memory-related hardware example, please refer to the description of the method example in this application for understanding.

[0073] Based on the memory shown in FIGS. 1 to 6, the controller 200 can write data to or read data from memory cells in the memory array 110 through the peripheral circuit 130 in the memory 100. After writing data to a memory cell, the charge stored in the memory cell reaches a certain state, but the charge stored in the memory cell may subsequently change due to the influence of the surrounding environment, and therefore, after the data is read from the memory cell, an error may occur in the data read. Based on this, after data is written to the memory array, parity data is also generated and stored for the written data. Then, if there is an error in the read data, the read data can be corrected according to the stored parity data to restore the correct data.

[0074] There may be multiple ways to generate parity data. In some examples, the ways to generate parity data include 1WL_RAID (Redundant Array of Independent Disks), 2WL_RAID, ..., nWL_RAID, etc. 1WL_RAID may be understood as generating one parity data for data stored in multiple consecutive rows of memory cells. nWL_RAID may be understood as generating n pieces of parity data for data stored in multiple consecutive rows of memory cells, where n is an integer greater than 1.

[0075] The larger n indicates that the amount of parity data generated for the data stored in the plurality of consecutive memory cell rows is larger, and therefore, even if the data stored in two or more of the plurality of consecutive memory cell rows has an error, the correct data can be restored based on the plurality of parity data. Therefore, the larger n indicates that the nWL_RAID method has a higher protection capability.

[0076] Here, the parity data may be stored in an SRAM (static random access memory). In this scenario, a large n may easily increase the cost of the SRAM. In some examples, the parity data may also be stored in a memory array. In this scenario, a large n may easily cause troublesome operations when writing data to the memory, further reducing the write performance of the memory. Based on this, in many scenarios, the parity data may be generated by the 1WL_RAID method to avoid problems caused by nWL_RAID.

[0077] Currently, the increase in the number of WL layers in 3D NAND leads to a continuous decrease in the width between adjacent WLs. In this case, charges stored in adjacent memory cell rows coupled to adjacent WLs are likely to affect each other, thereby increasing the probability of simultaneously generating errors in data stored in adjacent memory cell rows coupled to adjacent WLs. However, in the 1WL_RAID approach, data stored in multiple consecutive memory cell rows has only one copy of parity data, so only data stored in one of the multiple consecutive memory cell rows is allowed to have an error. If data stored in all three or more (including two) of the multiple consecutive memory cell rows has an error, the correct data may not be restored based on the parity data.

[0078] Based on this, the present application provides a method for operating a memory, in which parity data can be generated in 1WL_RAID mode while allowing data stored in adjacent memory cell rows to have errors, thereby indirectly improving the protection capability of the nWL_RAID approach.

[0079] The method of operating the memory provided by the examples of this application is described and explained below.

[0080] 7 is a flowchart of a method for operating a memory provided by an example of the present application. In some examples, the method is applied to the peripheral circuits of the memory shown in FIGS. 1-6 and the control logic units in the peripheral circuits, and subsequent examples will be described and illustrated with the peripheral circuits as the subject of execution. As shown in FIG. 7, the method includes the following operations:

[0081] Operation 701: A peripheral circuit receives an operation command from a controller, where the operation command carries a plurality of initial word line identifiers.

[0082] In some examples, the controller may write data to the memory array via an operation command. In this scenario, the controller sends an operation command including a write command to the memory, and the peripheral circuitry of the memory receives the operation command. Here, the write command also carries multiple pieces of data to be written that correspond one-to-one to the multiple initial word line identifiers. The peripheral circuitry may then write the data to be written to memory cell rows corresponding to the multiple initial word line identifiers via operations 702 and 703.

[0083] Here, when the controller sends a write command to the memory, one piece of parity data corresponding to the multiple pieces of data to be written is also generated. For example, the write command may also carry the parity data to store the parity data in the memory array. In some examples, the controller may also store the parity data in another memory device, for example, an SRAM. The examples of this application do not limit the way in which the controller stores the parity data.

[0084] In some other examples, the controller may read data from the memory array via an operation command. In this scenario, the controller sends an operation command including a read command to the memory, and peripheral circuitry of the memory receives the operation command. The peripheral circuitry may then read data from rows of memory cells corresponding to the multiple initial word line identifiers via operations 702 and 703.

[0085] Here, the initial word line identifier is configured to uniquely identify a word line. In some examples, the initial word line identifier may include an initial word line number. For example, the multiple initial word line identifiers may be WL1 to WL5. In some examples, the initial word line identifier may also include other symbols that can represent word lines. For example, the multiple initial word line identifiers may include Wla to WLe.

[0086] Operation 702: The peripheral circuitry maps a plurality of initial word line identifiers to a plurality of physical word line identifiers.

[0087] In an example of the present application, in order to avoid writing multiple data to be written corresponding to the same parity data to multiple consecutive rows of memory cells, when the peripheral circuit receives a write command sent by the controller, multiple initial word line identifiers in the write command may also be mapped to multiple physical word line identifiers so that the rows of memory cells indicated by the multiple physical word line identifiers after mapping are discontinuous.

[0088] That is, in the example of the present application, the peripheral circuit does not directly write data according to the word line indicated by the initial word line identifier in the write command, but maps the initial word line identifier in the write command according to a specific rule to facilitate writing subsequent data according to the word line indicated by the mapped physical word line identifier.

[0089] Therefore, when the peripheral circuitry receives a read command from the controller, it also needs to map the initial word line identifier carried in the read command to a physical word line identifier in order to read the correct data.

[0090] In some examples, an implementation of the peripheral circuitry that maps multiple initial word line identifiers to multiple physical word line identifiers may be to take each of the multiple initial word line identifiers as a dummy word line identifier and obtain the physical word line identifier corresponding to each of the initial word line identifiers from a stored mapping relationship between the dummy word line identifiers and the physical word line identifiers.

[0091] 8 is a flowchart of another method for operating a memory provided by an example of the present application. As shown in FIG. 8, when a peripheral circuit receives an operation command from a controller, the peripheral circuit first maps an initial word line identifier in the operation command to a physical word line identifier according to a mapping relationship between a dummy word line identifier and a physical word line identifier, and then executes the operation command based on the mapped physical word line identifier.

[0092] In order to improve the efficiency of writing or reading data, a mapping relationship between the dummy word line identifier and the physical word line identifier can be preset in the peripheral circuit. In this way, when the peripheral circuit writes data, the initial word line identifier can be mapped based on the mapping relationship.

[0093] In some examples, the above-described mapping relationship may not be set in the peripheral circuit. In this scenario, when the peripheral circuit writes or reads data, the initial word line identifiers may be temporarily mapped according to a specific algorithm. The following examples will illustrate the mapping according to the mapping relationship.

[0094] For ease of understanding, the mapping relationships are explained and described below.

[0095] In some examples, the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier and a mapping relationship between a second dummy word line identifier and a second physical word line identifier, where two memory cell rows coupled to two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

[0096] Here, the mapping relationship may include a plurality of dummy word line identifiers and physical word line identifiers corresponding to the plurality of dummy word line identifiers, and the first dummy word line identifier and the second dummy word line identifier may be two of the plurality of dummy word line identifiers.

[0097] The two memory cell rows coupled to the two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second dummy word line identifier, and therefore via this mapping relationship, so that when the memory cell rows indicated by the multiple initial word line identifiers are contiguous, the memory cell rows indicated by the multiple physical word line identifiers after mapping can be implemented to be discontinuous.

[0098] In some examples, the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, and a difference between the first dummy word line number and the second dummy word line number is 1, i.e., two memory cell rows respectively indicated by the first dummy word line number and the second dummy word line number are adjacent. The first physical word line identifier includes a first physical word line number, the second physical word line identifier includes a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1, i.e., other memory cell rows are distributed between the two memory cell rows respectively indicated by the first physical word line number and the second physical word line number.

[0099] In some scenarios, the difference between two physical word line numbers after every two adjacent dummy word line numbers are mapped can be set as a fixed value. In this scenario, if the first dummy word line number is smaller than the second dummy word line number, the second physical word line number is the sum of the first physical word line number and a reference value, and the reference value is a positive integer.

[0100] For example, if the reference value is 5, the difference between two physical word line numbers after every two adjacent dummy word line numbers are mapped is 5.

[0101] Table 1 is a schematic diagram of the mapping relationship provided by an example of the present application. As shown in Table 1, the physical word line identifiers corresponding to the dummy word line identifiers WL1 to WL5 are WL1, WL6, WL11, WL16, and WL21, respectively. The physical word line identifiers corresponding to the dummy word line identifiers WL6 to WL10 are WL26, WL31, WL36, WL41, and WL46, respectively. The physical word line identifiers corresponding to the dummy word line identifiers WL11 to WL15 are WL51, WL56, WL61, WL66, and WL71, respectively.

[0102] Here, the five data corresponding to the dummy word line identifiers WL1 to WL5 correspond to the same parity data, the five data corresponding to the dummy word line identifiers WL6 to WL10 correspond to the same parity data, and the five data corresponding to the dummy word line identifiers WL11 to WL16 correspond to the same parity data, and the explanations of the other parity data in Table 1 will not be given one by one.

[0103] As shown in Table 1, for five data corresponding to the same parity data, when the controller writes five data, the five initial word line numbers carried in the write command sent by the controller are five consecutive initial word line numbers, but after the peripheral circuit maps the five initial word line numbers according to Table 1, the difference between the two physical word line numbers corresponding to every two adjacent initial word line numbers among the five initial word line numbers is 5, so that the five data are written sequentially into five memory cell rows, and the other five memory cell rows can also be implemented to be distributed among every two adjacent memory cell rows among the five memory cell rows.

[0104] [Table 1]

[0105] Here, the mapping relationship shown in Table 1 may be pre-written into the peripheral circuit by an engineer. In some examples, the mapping relationship may be written into a register of the peripheral circuit. When a control logic unit in the peripheral circuit maps the initial identifier to a physical word line identifier, the mapping relationship may be obtained from the register.

[0106] In other scenarios, the difference between two physical word line identifiers after all adjacent dummy word line numbers are mapped may not be set as a fixed value, but may be set as a difference that varies according to a specific rule. For example, the physical word line identifiers corresponding to the dummy word line identifiers WL1 to WL5 are WL1, WL3, WL6, WL10, and WL15, respectively. Here, the difference between two physical word line identifiers after all adjacent dummy word line numbers are mapped increases sequentially according to the rules of 2, 3, 4, and 5.

[0107] In other scenarios, each dummy word line number may also be processed according to a specific mathematical rule, and the obtained number is the corresponding physical word line number. In this way, it is also possible to implement a scheme in which two physical word line numbers after adjacent dummy word line numbers are mapped are not adjacent. For example, the physical word line identifiers corresponding to the dummy word line identifiers WL1 to WL5 are WL2, WL6, WL12, WL20, and WL30, respectively. Here, the physical word line number after each dummy word line number is mapped is obtained by multiplying the dummy word line number by 2.

[0108] The above are examples for illustrating the representation formats of the mapping relationship. It should be noted that the mapping relationship provided by the examples of the present application is not limited to the several representation formats described above, and includes any mapping relationship that can map adjacent dummy word line numbers to two discontinuous physical word line numbers, and these mapping relationships will not be described one by one using examples here.

[0109] Additionally, the above description is given taking the example that the word line identifier is a word line number. In some examples, if the word line identifier includes another symbol configured to identify a word line, the mapping relationship can also be designed with reference to the above-described approach.

[0110] Operation 703: The peripheral circuit performs an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers, where at least one of the third-type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to the same parity data.

[0111] Here, the first type memory cell row may be understood as a memory cell row coupled to the first type word line, and therefore may also be called a selected memory cell row, and the third type memory cell row may be understood as another memory cell row other than the memory cell row coupled to the first type word line, and therefore may also be called an unselected memory cell row.

[0112] In some examples, to maximize the protection capability of the parity data, at least one of the third type memory cell rows is distributed between every two adjacent memory cell rows in the plurality of first type memory cell rows.

[0113] That is, for some data corresponding to the same parity data, there are no adjacent memory cell rows among the memory cell rows in which some data are stored, in order to avoid the possibility that correct data may not be restored if each of the data in the adjacent memory cell rows causes an error.

[0114] In some examples, the number of third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is the reference quantity.

[0115] For example, if the difference between two physical word line identifiers corresponding to two adjacent dummy word line identifiers in the mapping relationship in operation 702 is the parameter value, the number of third-type memory cell rows distributed among every two adjacent memory cell rows of the plurality of first-type memory cell rows is the reference quantity, where the reference value is the same as the reference quantity, for example, referring to Table 1, both of them are 5.

[0116] In some examples, in part, at least one of the third-type memory cell rows may also be distributed between two adjacent memory cell rows of the plurality of first-type memory cell rows, and in another part, the two adjacent memory cell rows are physically adjacent. Compared to a solution in which the plurality of first-type memory cell rows are consecutive memory cell rows in the memory array, this solution may also improve the protection capability of the parity data.

[0117] Here, when a physical word line identifier corresponding to the initial word line is obtained through the mapping relationship in operation 702, a situation in which the third type memory cell row is distributed between every two adjacent memory cell rows of the plurality of first memory cell rows is associated with a physical word line identifier corresponding to the dummy word line identifier in the mapping relationship.

[0118] Assuming that the initial word line identifiers are WL1 to WL5 as shown in Table 1, the corresponding physical word line identifiers after mapping are WL1, WL6, WL11, WL16, and WL21, respectively. In this scenario, the first-type memory cell rows are five memory cell rows coupled to WL1, WL6, WL11, WL16, and WL21, respectively. Here, there are five third-type memory cell rows distributed between every two adjacent memory cell rows.

[0119] Other examples of third-type memory cell rows distributed between every two adjacent memory cell rows of a plurality of first-type memory cell rows may be referred to above, and therefore will not be described one by one here.

[0120] Additionally, it can be seen that the operation instruction can include a write instruction or a read instruction based on operation 701. Operation 703 is explained and described below in two scenarios.

[0121] Scenario 1: The operation command includes a write command.

[0122] In Scenario 1, an implementation form of performing an operation corresponding to an operation instruction on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers may be to take the data to be written corresponding to each of the initial word line identifiers as the data to be written corresponding to the respective physical word line identifiers, and perform a program operation on a plurality of first-type memory cell rows via a plurality of first-type word lines to store a plurality of data to be written to the plurality of first-type memory cell rows.

[0123] At least one of the third-type memory cell rows is distributed between the first and second memory cell rows in the plurality of first-type memory cell rows, and the data stored in the plurality of first-type memory cell rows corresponds to the same parity data. Therefore, through the method provided by the example of the present application, it can be implemented so that multiple data corresponding to the same parity data can be written to discontinuous memory cell rows. In this way, it can be implemented so that data stored in adjacent memory cell rows in the memory array correspond to different parity data. In this way, even if the distance between adjacent memory cell rows is too short, thereby causing charge interaction and further causing the data stored in adjacent memory cell rows to be simultaneously erroneous, since the data stored in the adjacent memory cell rows correspond to different parity data, the data stored in the adjacent memory cell rows can be corrected respectively through at least two parity data, thereby improving data protection capability.

[0124] 9 is a flowchart of data writing provided by an example of the present application. As shown in FIG. 9, the data writing process includes the following operations:

[0125] (1) The controller obtains the data to be written to the memory array.

[0126] (2) The controller divides the data to be written into multiple pieces of data, and each piece of data corresponds to a part of a consecutive WL number. For example, WL1 to WL5 correspond to one piece of data to be written, and WL6 to WL10 correspond to one piece of data to be written.

[0127] (3) The controller generates a plurality of parity data according to the plurality of data.

[0128] In some examples, the parity data can be generated by a parity check. In some examples, for any data, the total number of bits that are each 1 in the data in binary code is determined, and then parity data is generated to record the parity of the total number. This can facilitate subsequent verification of the read data according to the parity data.

[0129] The above content is an example to illustrate a method for generating parity data. In some examples, the parity data may be generated in other ways, which will not be described one by one here.

[0130] (4) The controller sends a write command to the memory, and the write command carries a plurality of data and consecutive WL numbers corresponding to each data.

[0131] (5) The memory receives the write command and performs the following operations for each data and corresponding consecutive WL number: Each WL number of the consecutive WL numbers is taken as a dummy WL number, and mapped according to a mapping relationship to obtain a physical WL number corresponding to each dummy WL number, to obtain several discontinuous physical WL numbers, and then data is written sequentially into several discontinuous memory cell rows indicated by the discontinuous physical WL numbers.

[0132] Additionally, in the process of writing data, some data corresponding to the same parity data are written to discontinuous memory cell rows, so that when writing data to the memory array, program disturb occurring in adjacent memory cell rows while data is being written can be reduced.

[0133] Scenario 2, the operation command includes a read command.

[0134] In scenario 2, an implementation form for performing an operation corresponding to an operation instruction on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by a plurality of physical word line identifiers may be performing a read operation on a plurality of first-type memory cell rows via a plurality of first-type word lines to obtain data stored respectively within the plurality of first-type memory cell rows.

[0135] Additionally, after the peripheral circuit acquires the data stored in each of the plurality of first-type memory cell rows, the peripheral circuit may further transmit read result data carrying the data stored in each of the plurality of first-type memory cell rows to the controller, so that the controller receives the data read result. The controller determines the data to be read at this time based on the read result data.

[0136] Additionally, after the peripheral circuit acquires the data stored respectively in the plurality of first-type memory cell rows, if the data stored in a third memory cell row of the plurality of first-type memory cell rows includes erroneous data, the peripheral circuit determines an initial word line identifier corresponding to the physical word line identifier of the third memory cell row, acquires parity data based on the determined initial word line identifier, and corrects the data stored in the third memory cell row based on the parity data.

[0137] Here, after the peripheral circuit acquires the data stored in each of the plurality of first-type memory cell rows, the peripheral circuit can verify whether the plurality of data includes erroneous data. The example of the present application does not limit the manner in which the peripheral circuit verifies whether the read data includes erroneous data. For example, the peripheral circuit can send the read data to a controller, and a host connected to the controller can determine whether the read data includes erroneous data.

[0138] In some examples, when the controller writes data to the memory array, the controller also generates a correspondence between the initial word line identifier and the parity data. The correspondence may be stored in the memory array or another memory device. If the correspondence is stored in the memory array, the peripheral circuitry may obtain, based on the correspondence, an identifier of the parity data corresponding to the initial word line identifier corresponding to the physical word line identifier of the third memory cell row, and may obtain the parity data based on the identifier of the parity data. If the correspondence is stored in another memory device, the peripheral circuitry may transmit the initial word line identifier corresponding to the physical word line identifier of the third memory cell row to the other memory device, and the other memory device may obtain, based on the correspondence, an identifier of the parity data corresponding to the initial word line identifier corresponding to the physical word line identifier of the third memory cell row, and the parity data may be obtained by the peripheral circuitry based on the identifier of the parity data.

[0139] Here, there may be multiple implementation forms for the peripheral circuit to obtain the parity data based on the identifier of the parity data. For example, if the parity data is stored in the memory array, the peripheral circuit may directly read the parity data based on the identifier of the parity data. As another example, if the parity data is stored in another memory device, the peripheral circuit may directly read the parity data from the other memory device via the controller based on the identifier of the parity data.

[0140] Additionally, reference may be made to an implementation in which a peripheral circuit determines an initial word line identifier corresponding to the physical word line identifier of the third memory cell row and maps the initial word line identifier to the physical word line identifier in operation 702. For example, the initial word line identifier corresponding to the physical word line identifier of the third memory cell row may be determined through a mapping relationship shown in Table 1, and a detailed description will not be given here.

[0141] Additionally, in some examples, after the peripheral circuit acquires the plurality of data respectively stored in the first type memory cell rows, the peripheral circuit may also directly transmit the plurality of data to the controller, and the controller may determine whether the memory data includes erroneous data and correct the erroneous data based on the pre-stored mapping relationship between the initial word line identifiers and the parity data. In this scenario, since the controller has stored the mapping relationship between the initial word line identifiers and the parity data, the controller does not need to perform word line mapping and may directly correct the erroneous data based on the pre-stored mapping relationship between the initial word line identifiers and the parity data.

[0142] 10 is a flowchart of data reading provided by an example of the present application. As shown in FIG. 10, the data reading process includes the following operations:

[0143] (1) The controller sends a read command to the memory, and the read command carries a plurality of consecutive WL numbers, for example, WL1-5, WL6-10, etc., corresponding to the data to be read.

[0144] (2) The memory receives the read command and performs the following operations for each portion of the consecutive WL numbers:

[0145] Each WL number in a portion of the consecutive WL numbers is taken as a dummy WL number and mapped according to a mapping relationship to obtain a physical WL number corresponding to each dummy WL number, and then corresponding data is read from the memory cell row indicated by the physical WL corresponding to each dummy WL number to obtain the data corresponding to this portion of the consecutive WL numbers, and the read result data is sent to the controller.

[0146] (3) The controller verifies and corrects the results of the data read according to the parity data corresponding to each part of the consecutive WL numbers.

[0147] The technical effects of the solutions provided by the examples of the present application are further explained and described below in combination with Table 1 and Table 2.

[0148] [Table 2]

[0149] In Table 2, when the peripheral circuit receives a write command, the peripheral circuit directly writes data according to the word line indicated by the initial word line identifier. For example, the five initial word line numbers carried by the write command are WL1 to WL5, respectively, and five pieces of data, and these five pieces of data correspond to the same parity data. When the peripheral circuit receives a write command, the peripheral circuit directly stores the five pieces of data in the five memory cell rows respectively coupled to WL1 to WL5. In this way, the five pieces of data corresponding to the same parity data are written to the five consecutive memory cell rows. Thereafter, if the data stored in two adjacent memory cell rows among the five consecutive memory cell rows both have an error, the data stored in the two adjacent memory cell rows may not be restored according to the parity data.

[0150] However, as shown in Table 1, for five data corresponding to the same parity data, the five initial word line numbers carried in the write command sent by the controller are five consecutive initial word line numbers, but after the peripheral circuit maps the five initial word line numbers according to Table 1, the difference between two physical word line numbers corresponding to every two adjacent initial word line numbers of the five initial word line numbers is 5.

[0151] For example, the five initial word line numbers carried by a write command are WL1 to WL5, respectively, and five data pieces, which correspond to the same parity data. When the peripheral circuit receives the write command, the peripheral circuit determines, according to Table 1, that the physical word line numbers to which the initial word line numbers WL1 to WL5 are mapped are WL1, WL6, WL11, WL16, and WL21, and stores the five data pieces in the five memory cell rows coupled to WL1, WL6, WL11, WL16, and WL21, respectively. In this way, the five data pieces corresponding to the same parity data are written into the five spaced apart memory cell rows, and the five third-type memory cell rows are distributed between every two adjacent third-type memory cells. Then, if the data stored in two adjacent memory cell rows among the plurality of consecutive memory cell rows both have an error, for example, if the data stored in two adjacent memory cell rows coupled to WL1 and WL2 both have an error, the data stored in the two adjacent memory cell rows coupled to WL1 and WL2 correspond to different parity data, and therefore correction can be performed according to the corresponding parity data.

[0152] Additionally, in examples of the present application, the controller may also control whether the peripheral circuitry executes the operation instructions in accordance with operation 702 and operation 703. Based on this, in some examples, an implementation of mapping multiple initial word line identifiers to multiple physical word line identifiers in operation 702 may be that the peripheral circuitry may perform an operation of mapping multiple initial word line identifiers to multiple physical word line identifiers when a word line mapping instruction from the controller is received.

[0153] 11 is a schematic flowchart of another memory operation command provided by an example of the present application. As shown in FIG. 11, when the peripheral circuit receives an operation command from the controller, the peripheral circuit first determines whether a word line mapping command from the controller is currently received. If the determination result is Yes, operation 702 and operation 703 are performed, that is, the peripheral circuit maps multiple initial word line identifiers to multiple physical word line identifiers and performs an operation corresponding to the operation command on multiple first-type memory cell rows through multiple first-type word lines indicated by the multiple physical word line identifiers. Here, at least one of the third-type memory cell rows is distributed between the first and second memory cell rows in the multiple first-type memory cell rows, and the data stored in the multiple first-type memory cell rows correspond to the same parity data.

[0154] Therefore, when the peripheral circuit does not receive a word line mapping command from the controller, the peripheral circuit performs an operation corresponding to the operation command on a plurality of second type memory cell rows via a plurality of second type word lines indicated by a plurality of initial word line identifiers, where the plurality of second type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second type memory cell rows corresponds to the same parity data.

[0155] 12 is a schematic flowchart of another memory operation command provided by an example of the present application. As shown in FIG. 12, when the peripheral circuit receives an operation command from the controller, the peripheral circuit first determines whether a word line mapping command from the controller is currently received. If the determination result is No, operation 702 and operation 703 are not performed, and the operation corresponding to the operation command is performed on a plurality of second-type memory cell rows via a plurality of second-type word lines indicated by a plurality of initial word line identifiers.

[0156] Based on this, in a scenario where it is required that the peripheral circuit executes operation instructions in accordance with operations 702 and 703, for example, in a scenario where the importance of the data to be written is high, the controller may send a word line mapping command to the peripheral circuit to cause the peripheral circuit to execute operations 702 and 703 in response to the word line mapping command in order to improve the protection capability of the parity data for the data to be written.

[0157] In some examples, in scenarios where the peripheral circuitry may not execute the operation instructions in accordance with operations 702 and 703, for example, in scenarios where the importance of the data to be written is general, the controller may not send a word line mapping instruction to the peripheral circuitry so that the peripheral circuitry directly executes the operation on the memory cell row indicated by the initial word line identifier.

[0158] Here, the word line mapping command may include predix CMD (a type of command).

[0159] In short, in one example of the present application, at least one of the third-type memory cell rows is distributed between the first and second memory cell rows in the plurality of first-type memory cell rows, and the data stored in the plurality of first-type memory cell rows corresponds to the same parity data. Therefore, by the method provided by the example of the present application, multiple data corresponding to the same parity data can be written to discontinuous memory cell rows. In this way, data stored in adjacent memory cell rows in a memory array can be implemented to correspond to different parity data. In this way, even if the distance between adjacent memory cell rows is too short, thereby causing charge interaction and further causing the data stored in adjacent memory cell rows to be simultaneously erroneous, since the data stored in the adjacent memory cell rows correspond to different parity data, the data stored in the adjacent memory cell rows can be corrected respectively through at least two parity data, thereby improving data protection capability.

[0160] Based on the example shown in FIG. 7 , the example of the present application also provides a memory, which includes a memory array including a plurality of memory cell rows, a plurality of word lines respectively coupled to the plurality of memory cell rows, and peripheral circuits coupled to the plurality of word lines and configured to implement a method of operating the memory provided by the example of the present application.

[0161] In some examples, the peripheral circuit is configured to receive an operation command from a controller, the operation command carrying a plurality of initial word line identifiers; map the plurality of initial word line identifiers to a plurality of physical word line identifiers; and perform an operation corresponding to the operation command on a plurality of first type memory cell rows via a plurality of first type word lines indicated by the plurality of physical word line identifiers, wherein at least one of the third type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and data stored in the plurality of first type memory cell rows corresponds to the same parity data.

[0162] In some examples, the peripheral circuitry is configured to take each of the plurality of initial word line identifiers as a dummy word line identifier and obtain a physical word line identifier corresponding to each of the initial word line identifiers from a stored mapping relationship between the dummy word line identifiers and the physical word line identifiers.

[0163] In some examples, the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier, and a mapping relationship between a second dummy word line identifier and a second physical word line identifier, wherein two memory cell rows coupled to the two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and other memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier.

[0164] In some examples, the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, the difference between the first dummy word line number and the second dummy word line number is 1, the first physical word line identifier includes a first physical word line number, the second physical word line identifier includes a second physical word line number, and the difference between the first physical word line number and the second physical word line number is greater than 1.

[0165] In some examples, the first dummy word line number is smaller than the second dummy word line number, and the second physical word line number is the sum of the first physical word line number and a reference value, where the reference value is a positive integer.

[0166] In some examples, at least one of the third type memory cell rows is distributed between every two adjacent memory cell rows of the plurality of first type memory cell rows.

[0167] In some examples, the number of third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is the reference quantity.

[0168] In some examples, the peripheral circuitry is configured to perform operations to map a plurality of initial word line identifiers to a plurality of physical word line identifiers when a word line mapping command is received from the controller.

[0169] In some examples, the peripheral circuitry is also configured, when no word line mapping command is received from the controller, to perform an operation corresponding to the operation command on a plurality of second-type memory cell rows via a plurality of second-type word lines indicated by the plurality of initial word line identifiers, where the plurality of second-type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and the data stored in the plurality of second-type memory cell rows corresponds to the same parity data.

[0170] In some examples, the operation instruction includes a write instruction, and the write instruction also carries a plurality of data to be written corresponding one-to-one to the plurality of initial word line identifiers. The peripheral circuit is configured to take the data to be written corresponding to each of the initial word line identifiers as the data to be written corresponding to a respective physical word line identifier, and perform a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written in the plurality of first-type memory cell rows.

[0171] In some examples, the operation instruction includes a read instruction, and the peripheral circuitry is configured to perform a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to retrieve data stored in the plurality of first-type memory cell rows, respectively.

[0172] In some examples, the peripheral circuit is also configured to, when the data stored in a third memory cell row of the plurality of first type memory cell rows is incorrect data, determine an initial word line identifier corresponding to the physical word line identifier of the third memory cell row, obtain parity data based on the determined initial word line identifier, and correct the data stored in the third memory cell row based on the parity data.

[0173] For the implementation of the functions of the peripheral circuits described above, reference may be made to the example shown in FIG. 7, which will not be repeated here.

[0174] Additionally, examples of the present application also provide a storage system including a memory and a controller coupled to the memory and configured to control the memory.

[0175] The controller is configured to send an operation command to the memory, the operation command carrying a plurality of initial word line identifiers, and the memory is configured to receive the operation command, map the plurality of initial word line identifiers to a plurality of physical word line identifiers, and perform an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers.

[0176] Here, at least one of the third type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first type memory cell rows, and the data stored in the plurality of first type memory cell rows corresponds to the same parity data.

[0177] In some examples, the controller is further configured to send a word line mapping command to the memory, and the memory is further configured to perform an operation in response to the word line mapping command to map the plurality of initial word line identifiers to the plurality of physical word line identifiers.

[0178] In some examples, the controller is further configured to not send a word line mapping instruction to the memory, and the controller is further configured to perform an operation corresponding to the operation instruction on a plurality of second-type memory cell rows via a plurality of second-type word lines indicated by the plurality of initial word line identifiers, where the plurality of second-type memory cell rows includes a plurality of consecutive memory cell rows in the memory array, and data stored in the plurality of second-type memory cell rows corresponds to the same parity data.

[0179] In some examples, the operation instruction includes a write instruction, and the write instruction also carries a plurality of data to be written that correspond one-to-one to the plurality of initial word line identifiers. The controller is configured to take the data to be written corresponding to each of the initial word line identifiers as the data to be written corresponding to a respective physical word line identifier, and perform a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written in the plurality of first-type memory cell rows.

[0180] In some examples, the operation instructions include a read instruction, wherein the controller is configured to perform a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to obtain data stored respectively in the plurality of first-type memory cell rows, the memory is further configured to send results of the data read to the controller, the results of the data read carrying data stored respectively in the plurality of first-type memory cell rows, and the controller is configured to receive the results of the data read.

[0181] For the implementation of the functions of the controller and memory described above, reference may be made to the example shown in FIG. 7, which will not be repeated here.

[0182] 13 is a structural schematic diagram of a controller provided by an example of the present application. As shown in FIG. 13, the controller 1300 includes a processing unit 1301, which may be, for example, an MCU (microcontroller unit).

[0183] Here, the controller 1300 is configured to implement the functions of the controller in the above example to implement the storage system provided in the example of the present application. For the implementation form, reference may be made to the example shown in Figure 7, and will not be described in detail here.

[0184] Additionally, examples of the present application also provide a peripheral circuit, wherein a control logic unit in the peripheral circuit includes at least one software module, and the at least one software module is configured to perform any of the operations in the method for operating a memory in the example shown in FIG.

[0185] Additionally, examples of the present application also provide a computer storage medium storing instructions that, when executed by peripheral circuitry in the memory, perform any of the operations in the method of operating the memory in the example shown in FIG.

[0186] In another aspect, a computer program product is provided that includes instructions that, when executed in peripheral circuitry, perform any of the operations in the method for operating a memory in the example shown in FIG.

[0187] Those skilled in the art may understand that all or part of the operations for implementing the examples described above may be completed by hardware, or may also be completed by instructing relevant hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.

[0188] The above description is only an example of the present application and is not intended to limit the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall fall within the protection scope of the present application. [Explanation of symbols]

[0189] 10 Storage Systems 100 Memory, Electronic Devices 101 Substrate 102 Laminated layer 103 Gate conductive layer 104 Inter-gate dielectric layer 105 channel structure 110 Memory cell array, memory array 111 Memory String, String 112 memory cells 113 Source Select Gate (SSG), Source Select Gate 114 Drain Select Gate (DSG), Drain Select Gate 115 bit lines 116 DSG Line 117 SSG Line 118 Source Line (SL), Source Line 120 Word Line 130 Peripheral Circuits Page 131 Buffer / Sense Amplifier 132 Column Decoder / Bit Line (BL) Driver 133 Row decoder / word line (WL) driver 134 Voltage Generator 135 Control Logic Unit 136 registers 137 Interface, Interface (I / F) 138 Data Bus 140 blocks 150 pages 200 Controller 300 Host 400 memory card 410 Connector 500 Solid State Disks (SSDs), Solid State Drives 510 Connector 1300 Controller 1301 Processing Unit

Claims

1. a memory array including a plurality of rows of memory cells; a plurality of word lines respectively coupled to the plurality of memory cell rows; peripheral circuitry coupled to the plurality of word lines, receiving an operational command from a controller, the operational command including a plurality of initial word line identifiers; mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers; and a peripheral circuit configured to perform the A memory comprising: at least one of the third-type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first-type memory cell rows, data stored in the plurality of first-type memory cell rows corresponds to the same parity data, and the third-type memory cell row is another memory cell row other than the memory cell rows coupled to the plurality of first-type word lines; Memory.

2. The peripheral circuitry identifying each of the plurality of initial word line identifiers as a dummy word line identifier; obtaining a physical word line identifier corresponding to each of the plurality of initial word line identifiers from a stored mapping relationship between the dummy word line identifiers and the physical word line identifiers; It was configured as follows: The memory of claim 1.

3. the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier, and a mapping relationship between a second dummy word line identifier and a second physical word line identifier; two memory cell rows coupled to two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent to each other, and memory cell rows other than the two memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier; The memory of claim 2.

4. the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, and a difference between the first dummy word line number and the second dummy word line number is 1; the first physical word line identifier comprises a first physical word line number, the second physical word line identifier comprises a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than 1; The memory of claim 3.

5. the first dummy word line number is smaller than the second dummy word line number; the second physical word line number is the sum of the first physical word line number and a reference value, and the reference value is a positive integer; The memory of claim 4.

6. 2. The memory of claim 1, wherein at least one of the third-type memory cell rows is distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows.

7. 7. The memory of claim 6, wherein a quantity of the third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is a reference quantity.

8. The peripheral circuitry configured to, in response to determining that a word line mapping command has been received from the controller, perform an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers. The memory of claim 1.

9. The peripheral circuitry In response to determining that the word line mapping command is not received from the controller, performing the operation corresponding to the operation command on a plurality of second-type memory cell rows via a plurality of second-type word lines indicated by the plurality of initial word line identifiers. further configured as follows: the plurality of second-type memory cell rows comprises a plurality of consecutive memory cell rows in the memory array, and data stored in the plurality of second-type memory cell rows corresponds to the same parity data; The memory of claim 8.

10. the operation command includes a write command including a plurality of data to be written corresponding to the plurality of initial word line identifiers; The peripheral circuitry identifying data to be written corresponding to each of the initial word line identifiers as data to be written corresponding to a respective physical word line identifier; performing a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written to the plurality of first-type memory cell rows; It was configured as follows: The memory of claim 1.

11. the operating instructions include a read instruction; The peripheral circuitry performing a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to obtain data stored in the plurality of first-type memory cell rows; It was configured as follows: The memory of claim 1.

12. The peripheral circuitry In response to determining that data stored in a third memory cell row of the plurality of first-type memory cell rows is erroneous data, determining the initial word line identifier corresponding to the physical word line identifier of the third memory cell row; obtaining the parity data based on the determined initial word line identifier; correcting the data stored in the third row of memory cells based on the parity data; Further configured as follows: The memory of claim 11.

13. receiving an operation command, the operation command including a plurality of initial word line identifiers; mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers; a memory configured to: a controller coupled to the memory and configured to control the memory and send the operating instructions to the memory; A storage system comprising: at least one of the third-type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first-type memory cell rows, data stored in the plurality of first-type memory cell rows corresponds to the same parity data, and the third-type memory cell row is another memory cell row other than the memory cell rows coupled to the plurality of first-type word lines; Storage system.

14. the controller is further configured to send a word line mapping command to the memory; the memory is further configured to perform, in response to the word line mapping command, an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers. The storage system according to claim 13.

15. the memory is further configured to, in response to determining that a word line mapping command is not received, perform the operation corresponding to the operation command on a plurality of second-type memory cell rows via a plurality of second-type word lines indicated by the plurality of initial word line identifiers; the plurality of second-type memory cell rows comprises a plurality of consecutive memory cell rows in a memory array, and data stored in the plurality of second-type memory cell rows corresponds to the same parity data; The storage system according to claim 13.

16. the operation command includes a write command including a plurality of data to be written that correspond one-to-one to the plurality of initial word line identifiers; The memory identifying data to be written corresponding to each of the initial word line identifiers as data to be written corresponding to a respective physical word line identifier; performing a program operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to store the plurality of data to be written to the plurality of first-type memory cell rows; It was configured as follows: The storage system according to claim 13.

17. the operating instructions include a read instruction; The memory performing a read operation on the plurality of first-type memory cell rows via the plurality of first-type word lines to obtain data stored in the plurality of first-type memory cell rows; sending results of a data read to the controller, the results of the data read carrying the data stored respectively within the plurality of rows of first-type memory cells; configured to: the controller is configured to receive the results of the data read; The storage system according to claim 13.

18. receiving an operational command from a controller, the operational command including a plurality of initial word line identifiers; mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers; performing an operation corresponding to the operation command on a plurality of first-type memory cell rows via a plurality of first-type word lines indicated by the plurality of physical word line identifiers; 1. A method of operating a memory, comprising: at least one of the third-type memory cell rows is distributed between the first memory cell row and the second memory cell row in the plurality of first-type memory cell rows, data stored in the plurality of first-type memory cell rows corresponds to the same parity data, and the third-type memory cell row is another memory cell row other than the memory cell rows coupled to the plurality of first-type word lines; method.

19. mapping the plurality of initial word line identifiers to a plurality of physical word line identifiers; identifying each of the plurality of initial word line identifiers as a dummy word line identifier; obtaining a physical word line identifier corresponding to each of the plurality of initial word line identifiers from a stored mapping relationship between the dummy word line identifiers and the physical word line identifiers; 20. The method of claim 18, comprising:

20. the mapping relationship includes a mapping relationship between a first dummy word line identifier and a first physical word line identifier, and a mapping relationship between a second dummy word line identifier and a second physical word line identifier; two memory cell rows coupled to two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent to each other, and memory cell rows other than the two memory cell rows are distributed between the two memory cell rows coupled to the two word lines indicated by the first physical word line identifier and the second physical word line identifier; 20. The method of claim 19.

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