A small array of color-tunable pixels

Abstract

A monolithically integrated red, green, and blue (RGB) light-emitting diode (LED) array with reduced mesa etching steps and number of contact terminals is fabricated. The LED array may have two or three p-n junctions grown continuously on a wafer. One of the p-n junctions has a reverse film deposition order of the n layer and the p layer. An emission active region is embedded between the n layer and the p layer of each of the p-n junctions. Each active region emits light of a different wavelength. The wafer is etched into multiple levels of mesas, two separate voltage terminals and a ground contact are formed, and the bias between specific semiconductor layers is controlled. All of the p-n junctions share a common ground contact.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to arrays of light emitting diode (LED) devices and methods of fabricating the same. More particularly, the present embodiments relate to monolithically integrated red, green, and blue (RGB) emitter arrays with reduced mesa etching steps and contact terminal counts. [Background technology]

[0002] Visualization systems such as virtual reality and augmented reality systems are becoming increasingly common in fields such as entertainment, education, medicine, business, etc. Efforts to improve visualization systems such as virtual reality and augmented reality systems are ongoing.

[0003] MicroLEDs (μLEDs) are small-sized LEDs (typically ∼50 μm in diameter or less) that can be used to generate extremely high-resolution color displays when red, green, and blue wavelength μLEDs are closely aligned. Fabrication of μLED displays typically involves picking isolated μLEDs from separate blue, green, and red WL wafers and arranging them closely alternatingly on the display.

[0004] There is growing interest in high-resolution color LED displays, which require fine pixel pitches. Assembling red, green, and blue LEDs grown on separate wafers presents challenges when LED sizes are in the tens of microns range or less. Monolithic RGB integration is an approach that circumvents the problem of maneuvering tiny LEDs into the correct locations on the display, but it presents its own set of problems. Current monolithic RGB arrays require at least three bias terminals and a ground connection. For high-resolution displays, the available space for all of these mesa etch and terminals is limited, making the design difficult to implement in practice. Summary of the Invention [Problem to be solved by the invention]

[0005] Another approach to monolithic RGB is to use a single pn junction containing three quantum wells. Depending on the applied bias, more or less light is generated in a particular well, allowing some control over the color point. While such an approach is attractive because it requires only two terminals per pixel, excessive voltage across the active region is unavoidable, and filters are required to obtain acceptable color characteristics for the display. Therefore, while this approach simplifies die manufacturing, it is less suitable for producing efficient displays with low power consumption.

[0006] Therefore, there is a need for improved μLED devices and improved manufacturing methods. [Means for solving the problem]

[0007] SUMMARY OF THE INVENTION Embodiments of the present disclosure relate to light emitting diode (LED) arrays and methods of manufacturing the LED arrays. In one or more embodiments, a light emitting diode (LED) array has a first light emitting stack on a second light emitting stack, the second light emitting stack on a third light emitting stack, the third light emitting stack on a reflective p-contact electrode bonded to a backplane, the first light emitting stack having a first electrical contact on a first n-type layer on a first color active region, the first color active region on a first p-type layer, the first p-type layer on a first tunnel junction, the second light emitting stack having a second electrical contact on a second n-type layer in contact with the first tunnel junction and on the second tunnel junction, the second tunnel junction on a second p-type layer, the second p-type layer on the second color active region, and the third light emitting stack having a third electrical contact on a third n-type layer in contact with the second color active region and on the third p-type layer.

[0008] A further embodiment of the present disclosure relates to a method for manufacturing an LED array. In one or more embodiments, the method includes the steps of sequentially forming at least three p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer with a color active region buried between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; and dry etching the epitaxial stack to remove the at least one p-n junction. accessing an n-type layer of the at least one n-type layer to form an electrical contact and a mesa; conformally depositing a dielectric layer on the mesa; removing a portion of the dielectric layer to form a dielectric opening on a top surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer on a portion of the mesa to form a gap across the center of the mesa to allow light to be emitted externally; and depositing an electrode grid on top of the LED array.

[0009] Additional embodiments of the present disclosure relate to a visualization or display system, in one or more embodiments, the visualization system includes a battery, a radio, a sensor, video generation processing, a light source including an LED array according to the previous embodiments, a modulator, a modulation processor, a beam combiner, projection optics, a screen, and a lens.

[0010] So that the foregoing features of the present disclosure may be understood in detail, a more particular description of the above briefly summarized disclosure may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings are merely illustrative of typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, as it may admit of other equally effective embodiments. The embodiments described herein are shown by way of example and not by way of limitation to the figures of the accompanying drawings, in which like reference numerals represent like elements. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates a process flow diagram of a method for fabricating an LED array according to one or more embodiments. [Figure 2A] FIG. 1 is a schematic diagram showing how reversing the order of the p and n layers facilitates control of the emission wavelength by the applied voltage. [Figure 2B] FIG. 1 is a schematic diagram showing how reversing the order of the p and n layers facilitates control of the emission wavelength by the applied voltage. [Figure 3] 10 is a graph showing measured data for an LED with opposite polarization and the same quantum well design, according to one or more embodiments. [Figure 4] 1 is a graph showing the measured spectrum of a red and green switchable color LED with p-GaN grown before the quantum wells according to one or more embodiments. [Figure 5] 1A-1C are cross-sectional views of epitaxy used in variations of LEDs before processing, according to one or more embodiments. [Figure 6] 6A-6C are cross-sectional views of μLED arrays after processing of the LED variation shown in FIG. 5, according to one or more embodiments. [Figure 7] FIG. 7 is a schematic diagram of a top-down top view of the μLED array shown in FIG. [Figure 8] Figure 7 shows the top view layout of the conformal dielectric layer underneath the metal wiring shown in the μLED array. [Figure 9] 10A-10C are cross-sectional views of epitaxy used in another LED variation before processing, according to one or more embodiments. [Figure 10] FIG. 10 is a cross-sectional view of a μLED array after processing another LED variation shown in FIG. 9 , according to one or more embodiments. [Figure 11] FIG. 1 shows a block diagram of an example visualization system using a μLED array of one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, the same reference numerals have been used, where possible, to indicate common, equivalent elements in the drawings. The drawings are not drawn to scale; for example, the height and width of the mesas are not shown to scale.

[0013] Before describing some example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] The term "substrate," as used herein in accordance with one or more embodiments, refers to a structure, intermediate, or final object having a surface or a portion of a surface on which a process acts. Also, references to a substrate in some embodiments refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, references to deposition on a substrate in some embodiments include deposition on a bare substrate or deposition on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0015] In one or more embodiments, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. In exemplary embodiments, substrate surfaces on which processing is performed include materials such as silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable materials, such as metals, metal nitrides, III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, light-emitting diode (LED) devices. In some embodiments, the substrate is subjected to a pretreatment process, in which the substrate surface is polished, etched, reduced, oxidized, hydroxylated, annealed, UV-cured, e-beam-cured, and / or baked. Also, in addition to performing film treatments directly on the surface of the substrate itself, in some embodiments, any of the disclosed film treatment steps may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer would be the substrate surface.

[0016] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used herein, a wafer serves as a substrate for forming the LED devices described herein.

[0017] Different examples of lighting systems and / or light-emitting diodes (LEDs) are described in more detail below with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional embodiments. Accordingly, it is understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit the present disclosure in any manner. Like reference numerals refer to like elements throughout.

[0018] Semiconductor light-emitting devices, or optical power emitting devices, such as devices that emit ultraviolet (UV) or infrared (IR) optical power, are among the most efficient light sources currently available. These devices can include light-emitting diodes, resonant-cavity light-emitting diodes, vertical-cavity laser diodes, edge-emitting lasers, and the like (hereafter referred to as "LEDs"). Their compact size and low power requirements make LEDs attractive candidates for many different applications. For example, they may be used as light sources (e.g., flashlights, camera flashes) in portable battery-powered devices such as cameras and mobile phones. They may also be used for automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video torches, general lighting (e.g., home, store, office, and studio lighting, theater / stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, display backlights, and IR spectroscopy. A single LED may provide light that is less bright than an incandescent light source, and therefore, for applications where higher brightness is desired or required, a multi-connected device or array of LEDs (such as a monolithic LED array, a micro LED array, etc.) may be used.

[0019] The present invention relates generally to the fabrication of micro light emitting diode (μLED) displays and multi-wavelength light emitters with wide bandwidth for free-space visible light communication. Multiple emission wavelengths may be combined within a single LED device using epitaxial tunnel junctions.

[0020] The fabrication of μLEDs can be simplified if two or more active regions emitting different wavelengths are integrated within a single wafer. Such an approach may be possible in the AlInGaN material system, as blue, green, and red LEDs have all been demonstrated to be fabricated in this system. However, the use of multicolor chips in μLED displays requires not only the stacking of multiple layers capable of emitting different wavelengths in a single epitaxial growth run, but also the ability to vary the relative emission intensities between emitters of different wavelengths.

[0021] In one or more embodiments, bias-based control of LED color is used to reduce the number of terminals to a more manageable number than current technology. However, independent control of some of the separate junctions is used to avoid the problems of low color purity and high voltage inherent in other approaches. Also, in one or more embodiments, an improved method of controlling LED wavelength via voltage is provided.

[0022] In one or more embodiments, "reverse polarity" LEDs are advantageously used in display applications. As used herein, the term "reverse polarity" refers to growing the p-GaN layer of an LED before the quantum wells, rather than after the quantum wells. It is widely recognized that highly efficient p-side-down LEDs are difficult to achieve due to unintentional incorporation of acceptor dopants into the quantum wells. However, in one or more embodiments, it is significantly recognized that this problem can be mitigated by using special growth conditions. Reverse polarity LEDs are so named because the direction of the p-n junction and InGaN polarization fields is reversed from conventional means.

[0023] As used herein, the term "p-n junction" refers to the boundary between two semiconductor layers of opposite conductivity type, p-type and n-type. The "p" side contains an excess of holes, and the "n" side contains an excess of electrons. The excess of holes and electrons can be obtained by intentional doping with acceptor or donor impurities, respectively, and / or may result from the presence of native crystalline defects. The boundary does not necessarily need to be abrupt, flat, or smooth. The boundary may include an impurity concentration gradient between the p-type and n-type layers and / or a layer of intrinsic (neutral) conductivity type. The boundary may be characterized by a protrusion of the p-type semiconductor into the n-type semiconductor, or vice versa.

[0024] Embodiments of the present disclosure are illustrated by the drawings, which show devices and processes for forming the devices according to one or more embodiments of the present disclosure. The processes shown are merely examples that can be used for the disclosed processes, and those skilled in the art will understand that the disclosed processes are not limited to the applications shown.

[0025] In one or more embodiments, the polarity-reversed orientation facilitates control of the net electric field across the quantum well in a manner that is advantageous for wavelength control. The benefits of this concept are conceptually illustrated in Figures 2A, 2B, and 3, and the measured spectrum of a color-shifted LED is shown in Figure 4.

[0026] Figures 2A and 2B are schematic diagrams showing how reversing the order of the p and n layers facilitates control of the emission wavelength with applied voltage. The larger the electric field magnitude across the indium gallium nitride (InGaN) quantum well, the higher the wavelength due to the quantum-confined Stark effect. The graph in Figure 3 shows measured data for an LED with opposite polarity and the same quantum well design.

[0027] Figure 4 is a graph showing the measured spectrum for a red-green switchable color LED with p-GaN grown before the quantum wells. The spectrum is characterized by a distinct peak that varies with voltage, rather than multiple peaks with voltage-dependent heights, as in existing LEDs that use multiple quantum wells of different colors in the same active region. The quantum wells in Figure 4 are wider than those shown in Figures 2A and 2B, allowing for a larger wavelength shift with voltage.

[0028] One or more embodiment μLED arrays are advantageous in that they require fewer contact terminals and mesa etching compared to conventional μLED arrays. One or more embodiment μLED arrays require only two independent bias terminals and a common ground electrode. One or more embodiment μLED arrays also allow for better control of emitted color compared to conventional single-junction RGB technologies. Without intending to be bound by theory, one or more embodiment μLED arrays are believed to enable lower display power consumption than published single-junction RGB technologies.

[0029] In one or more embodiments, two or three light-emitting stacks are grown sequentially on the same epitaxial wafer. One of these junctions has the n-layer and p-layer deposition order reversed compared to the other junctions. In one or more embodiments, a light-emitting active region is buried between the n-layer and p-layer of each junction. Each active region emits light at a different wavelength than the other active regions. At least one junction has the property that its emission shifts from one primary color to a different (shorter) primary color as the bias across the junction is increased. For example, the emission may shift from red to green or from green to blue.

[0030] In one or more embodiments, the epitaxial growth includes at least one tunnel junction, avoiding the need for contacts to the etched p-GaN layer. The wafer is etched into a multilevel mesa that forms two separate voltage terminals and a ground contact to control the bias between specific semiconductor layers. All junctions share a common ground contact.

[0031] In one or more other embodiments, a two-junction device is provided in which the color emitted by one of the junctions is controlled by varying the voltage at one terminal. For example, increasing the voltage may change the color from red to green. By decreasing the pulse width modulation cycle as the bias voltage increases, the red and green radiances can be matched. Blue emission is controlled by a separate contact terminal to the third (blue) active region. The voltage-induced color change capability is facilitated by a reversed orientation of the pn junction field relative to the InGaN quantum well polarization field.

[0032] In the examples shown in the figures and described in detail below, a separate drive voltage (applied to terminal A in FIGS. 6 and 10) produces blue light. However, alternative implementations are possible in which the red active region is swapped for a blue active region. In these embodiments, red light is emitted with a bias on terminal A, and the magnitude of the bias on terminal B can be used to tune the emission of other colors from green to blue.

[0033] FIG. 1 illustrates a process flow diagram of a method 50 for fabricating a micro light-emitting diode (μLED) array according to one or more embodiments of the present invention. Referring to FIG. 1, in one or more embodiments, the method begins in operation 52 by sequentially forming two or three p-n junctions on the same epitaxial wafer to form an epitaxial stack, the epitaxial stack including at least one n-type layer and at least one p-type layer, with a color active region buried between the at least one n-type layer and the at least one p-type layer. In operation 54, a reflective p-contact electrode is deposited on the epitaxial stack. In operation 56, the epitaxial stack with the reflective p-contact is bonded to a backplane wafer. In operation 58, the epitaxial stack is dry etched to provide access to the n-type layer and form electrical contacts and mesas. In operation 60, a dielectric layer is conformally deposited across the epitaxial wafer on the mesa. In operation 62, a portion of the dielectric layer is removed to form a dielectric opening on top of the mesa, exposing at least one n-type layer. In operation 64, an ohmic contact is deposited in the dielectric opening to form an electrical contact. In operation 66, a conformal reflective metal layer is deposited over a portion of the mesa, forming a gap across the center of the mesa for external light emission. In operation 68, an electrode grid is deposited on top of the LED array.

[0034] Referring to FIG. 5 , the epitaxial growth steps for a first variation 100, variation A, are described. FIG. 5 shows a cross-sectional view of a μLED array 100 according to one or more embodiments. One aspect of the present disclosure relates to a method of fabricating a μLED array. Referring to FIG. 5 , the first variation 100, variation "A," is a three-junction device with first and second pn junctions (of opposite pn deposition order) sharing a common n-type layer connected to one of the electrical terminals. These two junctions are driven in parallel (rather than independently), but the aggregate color of their emission can be controlled by voltage. For example, if red and green active regions are connected in parallel, current flows only through the red region at low voltages. The red active region can be designed so that its emission shifts to green at high voltages and adds to the light emitted by the green active region. Blue emission is controlled by a separate contact terminal to the third (blue) active region.

[0035] 5, μLED array 100 is fabricated by forming multiple III-nitride layers on a substrate 102 and forming three-junction LEDs on the substrate that include color active regions. The color active regions include a first color active region 106a, a second color active region 106b, and a third color active region 106c. Any order in which the different color active regions are stacked is within the scope of this disclosure.

[0036] In some embodiments, the LED array 100 includes three or more p-n junctions. In one or more embodiments, the first light-emitting stack 105a has a first n-type layer 104a formed on the substrate 102, a first color active region 106a formed on the first n-type layer 104a, a first p-type layer 108a formed on the first color active region 106a, and a first tunnel junction 110a formed on the first p-type layer 108a. The first p-n junction includes the first n-type layer 104a and the first p-type layer 108a separated by the first color active region 106a.

[0037] In one or more embodiments, the first color active region 106a is a blue color active region. In the illustrated embodiment, a first tunnel junction 110a is present on the first light-emitting stack, specifically on the first p-type layer 108a. A tunnel junction is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. As the electrons tunnel, holes are left behind in the p-type layer, and carriers are generated in both regions. Therefore, an electronic device such as a diode can pass a large current under reverse bias through the tunnel junction because the leakage current is small under reverse bias. The tunnel junction has a specific alignment of the conduction and valence bands in a pn tunnel junction. This can be achieved by using very high doping (e.g., a p++ / n++ junction). III-nitride materials also have an intrinsic polarization that creates an electric field at the heterointerface between different alloy compositions. In some circumstances, this polarization field can also be utilized to achieve band alignment for tunneling.

[0038] 5, the μLED array 100 further includes a second light-emitting stack 105b on the first light-emitting stack 105a. As will be appreciated by those skilled in the art, the second light-emitting stack 105b need not be a self-contained light-emitting stack. In one or more embodiments, the second color To emit light from the active region 106b, electrons must be injected from layer 104c (which is part of the third group 105c). First tunnel junction 110a the second n-type layer 104b on top, Second n-type layer 104bThe semiconductor device 100 has a second tunnel junction 110b on top of the second junction 110a, a second p-type layer 108b on the second tunnel junction 110b, and a second color active region 106b on the second p-type layer 108b. In one or more embodiments, the second color active region 106b is a red color active region. In the illustrated embodiment, a second tunnel junction 110b is present on the second junction 110a, specifically on the second n-type layer 104b. When the second n-type layer 104b is biased positively relative to the second p-type layer 108b, hole current flows through the second tunnel junction 110b to the second p-type layer 108b. The second tunnel junction 110b is itself a (second) p-n junction, composed of an n-type layer and a p-type layer, not separately shown in the figure. The second p-type layer 108b serves to inject the holes necessary to excite luminescence from the second color active region 106b.

[0039] The third light-emitting stack 105c is formed on the second light-emitting stack 105b and includes a third n-type layer 104c on the second color active region 106b, a third color active region 106c on the third n-type layer 104c, and a third p-type layer 108c on the third color active region 106c. The third n-type layer 104c functions to inject electrons into both the second color active region 106b of the second light-emitting stack and the third color active region 106c of the third light-emitting stack. A third p-n junction includes the third n-type layer 104c and the third p-type layer 108c separated by the third color active region 106c.

[0040] In one or more embodiments, the first n-type layer 104a is formed on a substrate 102. The substrate 102 may be any substrate known to those skilled in the art that is configured for use in forming LED devices. In one or more embodiments, the substrate 102 comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more implementations, the substrate 102 is a transparent substrate. In certain implementations, the substrate 102 comprises sapphire. In one or more embodiments, the substrate 102 is unpatterned prior to the formation of the LED. Thus, in some embodiments, the substrate 102 is unpatterned and can be considered flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0041] In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c may comprise any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In particular embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c comprise gallium nitride (GaN). In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are independently doped with an n-type dopant, such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration is greater than or equal to 1×10 17 From 2 x 10 19 cm 3 The range is.

[0042] In one or more embodiments, the layer of III-nitride material may be deposited by one or more of sputter deposition, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0043] As used herein, "sputter deposition" refers to the physical vapor deposition (PVD) method of depositing thin films by sputtering. In sputter deposition, materials, such as III-nitrides, are ejected from a source target onto a substrate. This technique is based on ion bombardment of the source material target, which produces vapor by a purely physical process, i.e., sputtering of the target material.

[0044] As used in accordance with some embodiments of the present application, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a gas-phase technique used to deposit thin films on a substrate surface. The ALD process involves exposing a substrate surface, or portions of a substrate, to alternating precursors, i.e., two or more reactive compounds, to deposit layers of material on the substrate surface. When the substrate is exposed to the alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate, or portions of the substrate, are exposed to the precursors separately.

[0045] As used in certain embodiments, "chemical vapor deposition" refers to a process in which a film of material is deposited on a substrate surface from the gas phase by decomposition of chemicals. In CVD, the substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. A particular subset of CVD processes commonly used in LED manufacturing uses metal-organic precursor chemistries and is called MOCVD or metalorganic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" refers to either co-flow or when there is a significant overlap in the exposure of multiple precursors.

[0046] "Plasma-enhanced atomic layer deposition (PEALD)," as used in some embodiments, refers to a technique for depositing thin films on a substrate. In some examples of PEALD processes related to thermal ALD processes, materials may be formed from the same chemical precursors, but at higher deposition rates and lower temperatures. In PEALD processes, generally, reactant gases and reactive plasmas are sequentially introduced into a processing chamber containing a substrate. A first reactant gas is pulsed in the processing chamber and adsorbed on the substrate surface. A reactive plasma is then pulsed in the processing chamber and reacts with the first reactant gas to form a deposited material, e.g., a thin film, on the substrate. As with thermal ALD processes, a purge step may be performed between each reactant delivery.

[0047] As used in accordance with one or more embodiments, "plasma-enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing thin films on a substrate. In a PECVD process, a source material in a gas or liquid phase is introduced into a PECVD chamber, such as a gaseous or liquid III-nitride material entrained in a carrier gas. A plasma-initiating gas is also introduced into the chamber. A plasma is generated in the chamber, generating excited radicals. The excited radicals chemically bond to the surface of a substrate placed in the chamber, forming a desired film thereon.

[0048] In one or more embodiments, the μLED array 100 is fabricated by placing the substrate 102 in a metalorganic vapor phase epitaxy (MOVPE) reactor for epitaxial growth of the μLED array layers.

[0049] In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may independently comprise any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N). These are also referred to as III-nitride materials. Thus, in some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0050] In some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently comprise a series of doped p-type layers. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently comprise gallium nitride (GaN) layers. The first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c independently comprise a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0051] In one or more embodiments, the primary differentiator of the epitaxy used between this μLED array and conventional μLED arrays is the aforementioned reverse polarity orientation, and the use of wider than typical quantum wells in applications where a large color shift is intentionally desired. For example, the well width to optimize internal quantum efficiency (IQE) may be 3 nm, although in one or more embodiments, it may be preferable to increase the width to 5 nm. In one or more embodiments, the well width may range from 2 nm to 8 nm.

[0052] FIG. 6 shows a cross-sectional schematic diagram of the first variation 100 after processing it into a micro LED array. Arrows 126, 128, 130 with different line patterns represent recombination paths from which red, green, and blue emissions result. In one or more embodiments, when terminal A 122 has a voltage of about 3 volts and terminal B 124 has a voltage of about 0 volts, blue light 130 results. In one or more embodiments, when terminal A 122 has a voltage of about 0 volts and terminal B 124 has a voltage greater than 3 volts, red light 128 results. In one or more embodiments, when terminal A 122 has a voltage of about 0 volts and terminal B 124 has a voltage greater than or equal to about 5 volts, green light 126 (or red-green light) results. Using a color-shifted red active region similar to that shown in FIG. 4, red emission with a small bias on terminal B 124 and extra green emission with a large bias on terminal B 124 may be generated. As will be appreciated by those skilled in the art, the first variation 100 shown in FIG. 6 is rotated 180 degrees relative to the depiction in FIG.

[0053] Referring to FIG. 6, a micro LED wafer 150 is fabricated with a first step of acceptor activation anneal. A reflective p-contact electrode (p-mirror) 118 is deposited. The reflective p-contact electrode (p-mirror) 118 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the reflective p-contact electrode (p-mirror) 118 comprises one or more of aluminum (Al), platinum (Pt), silver (Ag), etc. In other embodiments, the reflective p-contact electrode (p-mirror) 118 may comprise a bilayer of a reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium tin oxide (ITO), where the ITO is the portion of the bilayer that directly contacts the third p-type layer 108c.

[0054] In one or more embodiments, a reflective p-contact electrode (p-mirror) 118 is then bonded to a backplane wafer 120, which may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 120 includes vias 122 and 124 between the bonding surface and circuitry within or on the opposite side of the backplane wafer 120.

[0055] 6 , in one or more embodiments, first n-type layer 104a, second n-type layer 104b, and third n-type layer 104c are etched, for example, by dry etching, to form openings for electrical contacts 114, separate the pixels, and access vias 124 to backplane terminal B. In one or more embodiments, there are three etch levels 152, 154, and 156 total, which is a more manageable number than conventional μLED arrays.

[0056] In one or more embodiments, a dielectric layer 112 is conformally deposited over the entire wafer 150. As used herein, the term "dielectric" refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes an oxide, such as, but not limited to, silicon oxide (SiO), aluminum oxide (AlO), or a nitride, such as silicon nitride (SiN). In one or more embodiments, the dielectric layer includes silicon nitride (SiN), silicon oxide (SiO), or a multilayer of silicon dioxide (SiO) and silicon nitride (SiN). In some embodiments, the composition of the dielectric layer is non-stoichiometric with respect to an ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g., silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g., silicon oxycarbonitride (SiNCO)).

[0057] In one or more embodiments, the dielectric layer 112 is removed from the electrical contact points using a dry etch. Ohmic contact metal layers 114 are deposited in the dielectric openings to form the ohmic contact metal layers 114. Each of the ohmic contact metal layers 114 contacts the n-type layers 104a, 104b, and 104c and may be the same metal. The ohmic contact metal layers 114 may comprise any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metal layers 114 comprise aluminum (Al).

[0058] Continuing with reference to FIG. 6 , a thick, partially conformal metal layer 116 is deposited over most of the mesa region. As shown in FIGS. 6 and 7 , a gap 132 is left across the center of the mesa to allow light to radiate outward and to electrically isolate terminal B 124 from ground. The partially conformal metal layer 116 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the partially conformal metal layer 116 has high reflectivity and stability. In one or more embodiments, the partially conformal metal layer 116 comprises aluminum (Al) or platinum (Pt). Layer 116 may be comprised of a stack of multiple different metal thin films, for example, a first metal such as Al or silver (Ag) with high reflectivity properties and a second metal with better chemical stability such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au), or Pt. A partially conformal metal layer 116 connects the second n-type layer 104b with a via 124 to backplane terminal B.

[0059] Figure 7 shows a schematic top view of array 150 shown in cross section in Figure 6. The cross section shown in Figure 7 corresponds to the northwest corner of a larger display. In one or more embodiments, an electrode grid 172 of ground lines is deposited on top of the reflective partially conformal metal layer 116 on one side of each pixel, as shown in Figure 7. The electrode grid 172 connects to ground lines around the periphery of the display 150. In one or more embodiments, the electrode grid 172 connects the ground terminal (on the left side of Figure 6) to ground electrodes around the periphery of the display.

[0060] 6 and 7, in one or more embodiments, blue light 130 is emitted when terminal A 174 is biased above ground potential (i.e., +3V) and terminal B 176 is at ground (i.e., 0V). In one or more embodiments, when terminal A 174 is at ground (i.e., 0V), either red light 128 or green light 126 can be generated by biasing terminal B 176, depending on the magnitude of the bias. For example, when the bias on terminal B is in the range of approximately 3V to less than 5V, red light 128 is generated, and when the bias on terminal B 176 is greater than 5V, green light 126 can be generated. Although the first color active region 106a and the second color active region 106b are connected in parallel, they can be designed so that, for small biases, current flows only through the second color (red) active region 106b. Thus, only red light 128 is generated. For a larger bias on terminal B176, current flows through both the red and green active regions, but the color produced may be primarily green due to the higher IQE of the green active region relative to the red, and the natural tendency of red emission to shift toward shorter wavelengths at higher current densities. The color purity of the green may be further enhanced by using a "red" active region, such as that shown in Figure 4, which itself emits green (but not red) light at high current densities. The pulse-width modulation duty cycle may be reduced for the green mode of operation, resulting in a radiance similar to the red mode with a higher duty cycle.

[0061] Figure 8 shows the top view of conformal dielectric layers 182, 184, 186 deposited over the entire surface following the final mesa etch step. In one or more embodiments, the conformal dielectric layers 182, 184, 186 underlie the electrode grid 172 shown in Figure 7. Referring to Figures 6-8, regions 188, 194 indicate where the dielectric layers 182, 184, 186 will be removed in a subsequent etch to access the ohmic contact metal layer 114 over the pixel. The conformal dielectric layers 182, 184, 186 may also be used to access a via 190 connected to terminal B in the backplane, or to access a via 190 connected to terminal A.

[0062] Referring to FIG. 9 , the epitaxial growth steps of a second variant 200, variant B, are shown. Figure 9 illustrates a cross-sectional view of a μLED array 200 according to one or more embodiments. One aspect of the present disclosure relates to a method of fabricating a μLED array. Referring to FIG. 9 , the second variant 200, variant "b," is a two-junction device, where the first and second junctions (with opposite pn deposition order) share a common n-type layer connected to one of the electrical terminals. In one or more embodiments, variant B200 has a simpler epitaxial structure and a simpler mesa surface topography than variant A100. Fabrication of microLEDs is achieved in variant B200 with one less mesa etch level. In variant B200, the first active region itself follows the mechanism illustrated in FIG. 4 and provides both red and green light to terminal B depending on the bias.

[0063] 9, μLED array 200 is fabricated by forming multiple III-nitride layers on a substrate 202 to form two-junction LEDs on the substrate, including color active regions. The color active regions include a first color active region 206a and a second color active region 206b. Any order in which the different color active regions are stacked is within the scope of this disclosure.

[0064] In a particular embodiment, the LED array 200 has a first light-emitting stack 205a having a first n-type layer 204a formed on a substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, a first color active region 206a formed on the first p-type layer 208a, and a second n-type layer 204b on the first color active region 206a.

[0065] In one or more embodiments, the first color active region 206a is a red / green color active region. In the embodiment shown, a tunnel junction 210a exists between the first n-type layer 204a and the first p-type layer 208a. This arrangement allows holes to be injected into the first color active region 206a without direct metal contact to the surface of the p-type layer 208a. Electrons are injected into the first color active region 206a from the second n-type layer 204b.

[0066] Referring further to FIG. 9 , the μLED array 200 further includes a second light-emitting stack 205b on the first light-emitting stack 205a. The second light-emitting stack 205b includes a second n-type layer 204b, a second color active region 206b on the second n-type layer 204b, and a second p-type layer 208b on the second color active region 206b. Note that the second n-type layer 204b is “shared” between both the first and second light-emitting stacks 205a and 205b. In other words, the second n-type layer 204b can be used to inject electrons into both the first active region 206a and the second active region 206b. The second n-type layer 204b may be composed of multiple layers with different n-type doping concentrations. In one or more embodiments, the second color active region 206b is a blue color active region. Optionally, a second tunnel junction 210b and a third n-type layer 204c may be formed on the second p-type layer 208b. These optional layers allow the wafer to be subjected to high temperature processing (e.g., high temperature annealing to activate the buried p-type layer) without damaging the p-type layer 208b.

[0067] In one or more embodiments, a first n-type layer 204a is formed on a substrate 202. The substrate 202 may be any substrate known to those skilled in the art configured for use in forming LED devices. In one or more embodiments, the substrate 202 comprises one or more of the following: sapphire, silicon carbide, silica (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 202 is a transparent substrate. In certain embodiments, the substrate 202 comprises sapphire. In one or more embodiments, the substrate 202 is unpatterned prior to the formation of the LED. Thus, in some embodiments, the substrate 202 is unpatterned and can be considered flat or substantially flat. In other embodiments, the substrate 202 is a patterned substrate.

[0068] In one or more embodiments, first n-type layer 204a, second n-type layer 204b, and optional third n-type layer 204c may comprise any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, first n-type layer 204a, second n-type layer 204b, and third n-type layer 204c independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c comprise gallium nitride (GaN). In one or more embodiments, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c are independently doped with an n-type dopant, such as silicon (Si) or germanium (Ge).

[0069] In one or more embodiments, the layer of III-nitride material may be deposited by one or more of sputter vapor deposition, atomic layer vapor deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma enhanced atomic layer vapor deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD), as previously described.

[0070] In one or more embodiments, the μLED array 200 is fabricated by placing the substrate 202 in a metal organic vapor phase epitaxy (MOVPE) reactor for epitaxial growth of the μLED array layers.

[0071] In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may independently comprise any III-V semiconductor, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as III-nitride materials. Thus, in some embodiments, the first p-type layer 208a and the second p-type layer 208b independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0072] In some embodiments, the first p-type layer 208a and the second p-type layer 208b independently comprise a series of doped p-type layers. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently comprise gallium nitride (GaN) layers. The first p-type layer 208a and the second p-type layer 208b may independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b independently comprise a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0073] In one or more embodiments, the primary differentiator of the epitaxy used between the present μLED array 200 and existing μLED arrays is the aforementioned reverse polarization orientation and the use of wider than typical quantum wells in applications where a large color shift is intentionally desired. For example, while a well width that optimizes internal quantum efficiency (IQE) at high current densities is 3 nm, in one or more embodiments, it may be preferable to increase the width to 5 nm. In one or more embodiments, the well width may range from 2 nm to 8 nm.

[0074] 10 shows a cross-sectional schematic diagram of the second variation 200 after processing into a micro LED array 250. Arrows 226, 228 with different line patterns represent recombination paths from which red, green, and blue emissions result. A color-shifted red active region similar to that of FIG. 4 may be used to generate red emission with a small bias on terminal B and green emission with a large bias on terminal B. As will be appreciated by those skilled in the art, the second variation 200 of FIG. 9 has been rotated 180 degrees to form the micro LED array 250.

[0075] 10 , a micro LED wafer 250 is fabricated by first performing an acceptor activation anneal. A reflective p-contact electrode (p-mirror) 218 ​​is deposited. The reflective p-contact electrode (p-mirror) 218 ​​may comprise any suitable material known to those skilled in the art. In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 ​​comprises one or more of aluminum (Al), platinum (Pt), silver (Ag), etc. In other embodiments, the reflective p-contact electrode (p-mirror) 218 ​​may comprise a bilayer of a reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium tin oxide (ITO), where the ITO is the portion of the bilayer that directly contacts the second p-type layer 208b.

[0076] In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 ​​is then bonded to a backplane wafer 220. This wafer may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 220 has vias 222 and 224 between the bonding surface and circuitry on or in the opposite side of the backplane wafer 220.

[0077] 10 , in one or more embodiments, the first n-type layer 204a and the second n-type layer 204b are etched, for example, by dry etching, to form openings for electrical contacts 214, separating the pixels, and vias 224 to access backplane terminal B. In one or more embodiments, there are a total of two etch levels 252 and 254, which is a more manageable number than in conventional RGB μLED arrays.

[0078] In one or more embodiments, the dielectric layer 212 is conformally deposited across the wafer 250. In one or more embodiments, the dielectric layer 212 includes, but is not limited to, an oxide, such as silicon oxide (SiO), aluminum oxide (AlO), or a nitride, such as silicon nitride (SiN). In one or more embodiments, the dielectric layer 212 includes silicon nitride (SiN), silicon oxide (SiO), or a multilayer of silicon dioxide (SiO) and silicon nitride (SiN). In some embodiments, the composition of the dielectric layer 212 is non-stoichiometric with respect to an ideal molecular formula. For example, but not limited to, in some embodiments, the dielectric layer 212 includes an oxide (e.g., silicon oxide, aluminum oxide), a nitride (e.g., silicon nitride (SiN)), an oxycarbide (e.g., silicon oxycarbide (SiOC)), and an oxynitrocarbide (e.g., silicon oxynitrocarbide (SiNCO)).

[0079] In one or more embodiments, the dielectric layer 212 is removed from the electrical contact points using a dry etch. Ohmic contact metals 214 are deposited to form within the dielectric openings. Each of the ohmic contact metals 214 may be the same metal as the n-type layers 204a and 204b, respectively. The ohmic contact metals 214 may comprise any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metals 214 comprise aluminum (Al).

[0080] 10 , a thick, partially conformal metal layer 216 is deposited over most of the mesa region. A gap 232 is left across the center of the mesa to allow light to be emitted externally and to electrically isolate terminal B 224 from ground. The partially conformal metal layer 216 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the partially conformal metal layer 216 has high reflectivity and stability. In one or more embodiments, the partially conformal metal layer 216 comprises aluminum (Al) or platinum (Pt). The partially conformal metal layer 216 connects the second n-type layer 204b to backplane terminal B through via 224. Layer 216 may be comprised of a stack of multiple different metal thin films, for example, a first metal such as Al or silver (Ag) with high reflectivity properties and a second metal with better chemical stability such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au), or Pt. A partially conformal metal layer 216 connects the second n-type layer 204b to backplane terminal B through via 224.

[0081] In other, not shown, embodiments, a different embodiment of Variation B can be formed, which has a red color active area operated by a fixed current supplied by Terminal A and a green / blue voltage-controlled color switching active area connected to Terminal B.

[0082] Variation A100 of Figures 5 and 6 is more complex than Variation B200 of Figures 9 and 10, but allows for higher system efficiency. In one or more embodiments, a green color active region (Variation A) designed to emit green at higher currents can be optimized to achieve a higher internal quantum efficiency than a red color active region that switches to green emission at high bias voltages. In InGaN red active regions, quantum efficiency tends to peak at very low current densities. Similar arguments apply to the relative IQE of a green / blue switching active region versus an active region specifically designed to emit blue at high current densities.

[0083] Visualization systems such as virtual reality and augmented reality systems are becoming increasingly popular in areas such as entertainment, education, medicine, and business.

[0084] In a virtual reality system, a display can provide a user with a view of a scene, such as a three-dimensional scene. The user can move through the scene by repositioning the user's head or by walking. The virtual reality system can detect the user's movements and change the view of the scene to match the movement. For example, when a user rotates their head, the system can present a view of the scene whose view direction changes to match the user's line of sight. In this way, the virtual reality system can simulate the user's presence in the three-dimensional scene. Additionally, the virtual reality system can receive tactile sensory input, such as from a wearable position sensor, and can provide haptic feedback to the user as needed.

[0085] In an augmented reality system, a display can incorporate elements from a user's surroundings into a view of a scene. For example, an augmented reality system can add text captions and / or visual elements to a user's view of their surroundings. For example, a retailer can use an augmented reality system to show a user how furniture will look in a room in the user's home by incorporating visuals of furniture pieces onto a captured image of the user's surroundings. As the user moves around the user's room, the visualization takes into account the user's movements and changes the appearance of the furniture in a manner consistent with the movements. For example, an augmented reality system can place a virtual chair in a room. The user can stand in the room in front of the virtual chair position and view the front of the chair. The user can move through the room to the area behind the virtual chair position to view the back of the chair. In this way, the augmented reality system can add elements to a dynamic view of the user's surroundings.

[0086] FIG. 11 illustrates a block diagram of an example visualization system 10 using a μLED array according to one or more embodiments. The visualization system 10 can include a wearable housing 12, such as a headset or goggles. The housing 12 can mechanically support and house the following elements: In some examples, one or more of the following elements can be included in one or more additional housings, which can be separate from the wearable housing 12 and coupled to the wearable housing 12 via wireless and / or wired connections. For example, a separate housing can house a battery, radios, and other elements to reduce the weight of the wearable goggles. The housing 12 can include one or more batteries 14 to power any or all of the following elements: The housing 12 can have circuitry and be electrically coupled to an external power source, such as a wall outlet, to recharge the battery 14; and the housing 12 can include one or more radios 16 to wirelessly communicate with a server or network via a suitable protocol, such as Wi-Fi.

[0087] The visualization system 10 may include one or more sensors 18, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyro sensors, time-of-flight sensors, triangulation-based sensors, etc. In some examples, the one or more sensors may sense a user's position, location, and / or orientation. In some examples, one or more of the sensors 18 may generate a sensor signal in response to the sensed location, location, and / or orientation. The sensor signal may have sensor data corresponding to the sensed location, location, and / or orientation. For example, the sensor data may include a depth map of the surroundings. In some examples, such as an augmented reality system, one or more of the sensors 18 may capture real-time video images of the surroundings near the user.

[0088] The visualization system 10 may include one or more video generation processors 20. The one or more video generation processors 20 may receive scene data representing a three-dimensional scene, such as a set of position coordinates of objects in the scene or a depth map of the scene, from a server and / or storage medium. The one or more video generation processors 20 may receive one or more sensor signals from one or more sensors 18. In response to the scene data representing the surroundings and at least one sensor signal representing the user's position and / or orientation relative to the surroundings, the one or more video generation processors 20 may generate at least one video signal corresponding to a view of the scene. In some examples, the one or more video generation processors 20 may generate two video signals, one for each eye of the user, representing views of the scene from the perspectives of the user's left and right eyes, respectively. In some examples, the one or more video generation processors 20 may generate three or more video signals and combine these video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0089] The visualization system 10 may have one or more light sources 22 that may provide light to the display of the visualization system 10. Suitable light sources 22 may include light emitting diodes, monolithic light emitting diodes, multiple light emitting diodes, arrays of light emitting diodes, arrays of light emitting diodes disposed on a common substrate, segmented light emitting diodes, arrays of micro light emitting diodes (microLEDs) disposed on a single substrate and having individually addressable and controllable (and / or controllable in groups and / or subsets) light emitting diode elements, etc.

[0090] The light-emitting diode may be a white light-emitting diode. For example, the white light-emitting diode may emit excitation light, such as blue light or violet light. The white light-emitting diode may include one or more phosphors that absorb some or all of the excitation light and, in response, emit fluorescent light, such as yellow light, having a wavelength longer than that of the excitation light.

[0091] One or more light sources 22 may include light-generating elements having different colors or wavelengths. For example, a light source may include a red light-emitting diode capable of emitting red light, a green light-emitting diode capable of emitting green light, and a blue light-emitting diode capable of emitting blue light. The red, green, and blue light may be combined in specific ratios to produce any suitable visually perceptible color in the visible portion of the electromagnetic spectrum.

[0092] The visualization system 10 can include one or more modulators 24. The modulators 24 can be used in one of at least two configurations.

[0093] In a first configuration, modulator 24 can include circuitry capable of directly modulating light source 22. For example, light source 22 can have an array of light emitting diodes, and modulator 24 can directly modulate the power, voltage, and / or current induced in each light emitting diode in the array to form modulated light. Modulation can be implemented in an analog and / or digital manner. In some examples, light source 22 can have an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and modulator 24 can directly modulate the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes to form modulated light to generate a specified image.

[0094] In a second configuration, the modulator 24 can include a modulation panel, such as a liquid crystal panel. The light source 22 can generate uniform or nearly uniform illumination that illuminates the modulation panel. The modulation panel can include pixels. Each pixel can selectively attenuate a respective portion of the modulation panel area in response to an electrical modulation signal to form the modulated light. In some examples, the modulator 24 can include multiple modulation panels capable of modulating light of different colors. For example, the modulator 24 can include a red modulation panel capable of attenuating red light from a red light source, such as a red light emitting diode, a green modulation panel capable of attenuating green light from a green light source, such as a green light emitting diode, and a blue modulation panel capable of attenuating blue light from a blue light source, such as a blue light emitting diode.

[0095] In some examples of the second configuration, the modulator 24 can receive uniform or nearly uniform white light from a white light source, such as a white light emitting diode. The modulation panel can include a wavelength-selective filter on each pixel of the modulation panel. The panel pixels are arranged in groups (e.g., groups of three or four), and each group can form a pixel of a color image. For example, each group can include panel pixels with red color filters, panel pixels with green color filters, and panel pixels with blue color filters. Other suitable configurations can also be used.

[0096] The visualization system 10 includes one or more modulation processors 26, which can receive video signals, such as from one or more video generation processors 20, and can generate electrical modulation signals in response. In configurations where the modulators 24 directly modulate the light sources 22, the electrical modulation signals can drive the light sources 24. In configurations where the modulators 24 include modulation panels, the electrical modulation signals can drive the modulation panels.

[0097] The visualization system 10 can include one or more beam combiners 28 (also known as beam splitters 28) that can combine light beams of different colors to form a single polychromatic beam. In configurations where the light source 22 can have multiple light emitting diodes of different colors, the visualization system 10 can include one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that can combine light of the different colors to form a single polychromatic beam.

[0098] The visualization system 10 can direct modulated light to the observer's eyes in one of at least two configurations. In a first configuration, the visualization system 10 functions as a projector and has suitable projection optics 30 to project the modulated light onto one or more screens 32. The screens 32 can be positioned at a suitable distance from the user's eyes. The visualization system 10 can optionally have one or more lenses 34 to position the virtual image on the screen 32 at a suitable distance from the eyes, such as a close focal length, such as 500 mm, 750 mm, or another suitable distance. In some examples, the visualization system 10 has a single screen 32, and modulated light can be directed toward both of the user's eyes. In some examples, the visualization system 10 has two screens 32, and modulated light from each screen 32 can be directed toward a respective eye of the user. In some examples, the visualization system 10 can have three or more screens 32. In a second configuration, the visualization system 10 can direct modulated light directly to one or both of the observer's eyes. For example, the projection optics 30 may form an image on the retina of the user's eye, or may form an image on each retina of the user's two eyes.

[0099] In some configurations of an augmented reality system, the visualization system 10 has an at least partially transparent display through which the user can see their surroundings. In such configurations, the augmented reality system can generate modulated light that corresponds to an augmentation of the surroundings rather than the surroundings themselves. For example, in the retailer example displaying chairs, the augmented reality system can direct modulated light toward a screen or the user's eyes that corresponds to the chair but not the rest of the room.

[0100] (Embodiment) Various embodiments are listed below, and it is understood that the embodiments listed below can be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0101] Embodiment (a) A light emitting diode (LED) array, comprising: a first light-emitting stack on a second light-emitting stack; the second light emitting stack is on a third light emitting stack, the third light emitting stack is on a reflective p-contact electrode bonded to a backplane; the first light emitting stack has a first electrical contact on a first n-type layer on a first color active region, the first color active region on a first p-type layer, the first p-type layer on a first tunnel junction; the second light-emitting stack has a second electrical contact on a second n-type layer in contact with the first tunnel junction and on the second tunnel junction, the second tunnel junction is on a second p-type layer, the second p-type layer is on a second color active region; and the third light-emitting stack has a third electrical contact on a third n-type layer in contact with the second color active region and on the third p-type layer.

[0102] Embodiment (b) The LED array of embodiment (a), further comprising a dielectric layer surrounding the first light-emitting stack, the second light-emitting stack, and the third light-emitting stack.

[0103] Embodiment (c) The LED array of embodiment (a) or (b), further comprising a reflective metal layer on the dielectric layer.

[0104] Embodiment (d) The LED array of any one of embodiments (a) to (c), wherein the first light emitting stack and the second light emitting stack share the second n-type layer connected to the second electrical contact.

[0105] Embodiment (e) The LED array of any one of embodiments (a) to (d), wherein the voltage controls the aggregate color of the emission when the first light-emitting stack and the second light-emitting stack are driven in parallel.

[0106] Embodiment (f) The LED array of any one of embodiments (a) to (e), further comprising an electrode grid.

[0107] Embodiment (g) 10. The LED array of claim 9, wherein the first n-type layer, the second n-type layer, and the third n-type layer independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), or the like.

[0108] Embodiment (h) The LED array of any one of embodiments (a) to (g), wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

[0109] Embodiment (i) The LED array of any one of embodiments (a) to (h), wherein the first electrical contact, the second electrical contact, and the third electrical contact independently comprise aluminum.

[0110] Embodiment (j) The LED array of any one of embodiments (a) to (i), wherein the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0111] Embodiment (k) The LED array of any one of embodiments (a) to (j), wherein the reflective p-contact electrode has a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0112] Embodiment (l) 1. A method of manufacturing an LED array, comprising: forming at least three pn junctions successively on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, with a collar active region buried between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access the at least one n-type layer and form electrical contacts and mesas; conformally depositing a dielectric layer over the mesa; removing a portion of the dielectric layer to form a dielectric opening on a top surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer over a portion of the mesa and forming a gap across the center of the mesa to allow light to be emitted externally; depositing an electrode grid on top of the LED array; A method comprising:

[0113] Embodiment (m) The method of embodiment (l), further comprising annealing the epitaxial stack before depositing the reflective p-contact electrode.

[0114] Embodiment (n) The epitaxial stack comprises: a first light emitting stack having a first p-type layer on a first color active region, the first color active region on the first p-type layer, the first p-type layer on a first tunnel junction; a second light emitting stack having a second n-type layer in contact with the first tunnel junction and overlying a second tunnel junction, the second tunnel junction overlying a second p-type layer, the second p-type layer overlying a second color active region; a third light emitting stack in contact with the second color active region and having a third n-type layer on a third p-type layer; The method of any one of embodiments (l) to (m), comprising:

[0115] Embodiment (o) The method of any one of embodiments (1) to (n), wherein the voltage controls the aggregate color of the emission when the first light-emitting stack and the second light-emitting stack are driven in parallel.

[0116] Embodiment (p) The method of any one of embodiments (l) through (o), wherein the first n-type layer, the second n-type layer, and the third n-type layer independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0117] Embodiment (q) The method of any one of embodiments (l) through (p), wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

[0118] Embodiment (r) The method of any one of embodiments (l) to (q), wherein the electrical contact comprises aluminum.

[0119] Embodiment(s) the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag); or The method of any one of embodiments (l) to (r), wherein the reflective p-contact electrode has a bilayer comprising indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0120] Embodiment (t) Battery, radio, sensors, Video generation processing, a light source comprising an LED array according to any one of embodiments (a) to (r); modulator, modulation processor, Beam combiner, projection optical system, screen, and lens A visualization system comprising:

[0121] The use of "a," "an," "the," and similar terms in the context of describing the materials and methods discussed herein (particularly in the context of the claims) should be understood to encompass both the singular and the plural unless otherwise indicated or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if individually set forth in the application. All methods described herein can be performed in any suitable order unless otherwise indicated or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "etc.") provided herein is intended merely to better illustrate the materials and methods and does not pose a limitation on scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods.

[0122] Throughout this application, references to terms such as "first," "second," "third," etc. are used to describe various elements, and these elements are not intended to be limited by these terms. These terms are used to distinguish one element from another.

[0123] Throughout this application, when a layer, region, or substrate is referred to as being "on" or extending "on" another element, it means that it is directly on or extends directly onto the other element, or that intervening elements may be present. When an element is referred to as being "directly on" or extending "directly onto" another element, there may be no intervening elements present. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element and / or may be connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between the element and the other element. It is understood that these terms are intended to encompass different orientations of elements in addition to any orientation depicted in the figures.

[0124] Relative terms such as "lower," "upper," "top," "below," "horizontal," or "vertical" may be used to describe the relationship of one element, layer, or region to another element, layer, or region as depicted in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0125] Throughout this application, the phrases "one embodiment," "an embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this application do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0126] Although the present disclosure has been described with reference to particular embodiments, it is understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A light emitting diode (LED) array comprising: a first light-emitting stack on a second light-emitting stack; the second light emitting stack is on a third light emitting stack, the third light emitting stack is on a reflective p-contact electrode bonded to a backplane; the first light emitting stack has a first electrical contact on a first n-type layer on a first color active region, the first color active region on a first p-type layer, the first p-type layer on a first tunnel junction; the second light emitting stack has a second electrical contact on a second n-type layer in contact with the first tunnel junction and on a second tunnel junction, the second tunnel junction being on a second p-type layer, the second p-type layer being on a second color active region; the third light emitting stack has third electrical contacts on a third n-type layer in contact with the second color active region and on a third p-type layer; The LED array further comprises: a dielectric layer surrounding the first light emitting stack, the second light emitting stack, and the third light emitting stack; a reflective metal layer on the dielectric layer; An LED array having

2. 10. The LED array of claim 1, wherein the first light-emitting stack and the second light-emitting stack share the second n-type layer connected to the second electrical contact.

3. 3. The LED array of claim 2, wherein a voltage controls the aggregate color of the emission when the first light-emitting stack and the second light-emitting stack are driven in parallel.

4. The LED array of claim 1 further comprising an electrode grid.

5. 10. The LED array of claim 1, wherein the first n-type layer, the second n-type layer, and the third n-type layer independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), or the like.

6. 6. The LED array of claim 5, wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

7. 10. The LED array of claim 1, wherein the first electrical contact, the second electrical contact, and the third electrical contact independently comprise aluminum.

8. 10. The LED array of claim 1, wherein the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag).

9. 10. The LED array of claim 1, wherein the reflective p-contact electrode has a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

10. 1. A method of manufacturing an LED array, comprising: forming at least three pn junctions successively on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, with a collar active region buried between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access the at least one n-type layer and form electrical contacts and mesas; conformally depositing a dielectric layer over the mesa surrounding the at least three pn junctions; removing a portion of the dielectric layer to form a dielectric opening on a top surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal reflective metal layer on the dielectric layer over a portion of the mesa and forming a gap across the center of the mesa to allow light to be emitted externally; depositing an electrode grid on top of the LED array; and The epitaxial stack comprises: a first light emitting stack having a first n-type layer on a first color active region, the first color active region on a first p-type layer, the first p-type layer on a first tunnel junction; a second light emitting stack having a second n-type layer in contact with the first tunnel junction and overlying a second tunnel junction, the second tunnel junction overlying a second p-type layer, the second p-type layer overlying a second color active region; a third light emitting stack in contact with the second color active region and having a third n-type layer on a third p-type layer; A method comprising:

11. The method of claim 10 , further comprising annealing the epitaxial stack before depositing the reflective p-contact electrode.

12. 11. The method of claim 10, wherein a voltage controls the aggregate color of the emission when the first light-emitting stack and the second light-emitting stack are driven in parallel.

13. 11. The method of claim 10, wherein the first n-type layer, the second n-type layer, and the third n-type layer independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), or the like.

14. 14. The method of claim 13, wherein the first n-type layer, the second n-type layer, and the third n-type layer comprise gallium nitride (GaN).

15. The method of claim 10 , wherein the electrical contact comprises aluminum.

16. the reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), and silver (Ag); or 11. The method of claim 10, wherein the reflective p-contact electrode comprises a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

17. Battery, radio, sensors, Video generation processing, A light source comprising an LED array according to any one of claims 1 to 9. modulator, modulation processor, Beam combiner, projection optical system, screen, and lens A visualization system comprising:

Images