Quantum computers and computational methods using electron shuttling

Abstract

Provided are: a qubit array chip in which qubits are arranged in an array and integrated, wherein it is possible to suppress an increase in the size of a parameter table that stores operation conditions required for control, while suppressing a decrease in computing accuracy due to characteristic variations within the chip, even with an increased number of qubits are integrated; and a quantum computer using this qubit array chip. This quantum computer comprises a quantum dot array in which quantum dots are two-dimensionally arranged, and performs quantum operations by irradiating the quantum dot array with electromagnetic waves, the quantum computer being characterized in that the quantum dot array is divided into an arithmetic area for performing the quantum operations and memory areas for shuttling the qubits stored in the quantum dots, has a parameter table that stores the control voltage and the control time for each quantum dot during the quantum operations in the arithmetic area, and controls the qubits in the arithmetic area on the basis of the parameter table.

Description

[Technical Field]

[0001] The present invention relates to the configuration of a quantum computer and its operation method, and in particular to a technique that is effective when applied to a quantum computer that uses a quantum bit array chip in which quantum bits are arranged and integrated in an array. [Background technology]

[0002] Quantum computers have been attracting attention in recent years. Quantum computers are computers that process information by utilizing the "quantum" properties of atoms, electrons, and other elements that make up matter (the phenomenon of quantum mechanics). The miniaturization and performance improvements of semiconductor elements, which have supported the advancement of computers to date, are reaching their limits, making it difficult to significantly improve the performance of conventional classical computers. Quantum computers are one attempt to overcome these limitations by using new computational principles and devices. Currently, hardware development is underway with the aim of realizing quantum computers, and various types of quantum bits, the computing elements at the heart of quantum computers, have been proposed, including superconducting, ion-trap, and silicon types.

[0003] The schematic configuration of a silicon quantum computer 1000 is shown in Figure 1. Quantum bits (Qubits) 102, which are quantum operation devices, are arranged in an array and mounted on a quantum bit array chip (QBA) 101, which is fabricated as a silicon chip. The QBA 101 controls the quantum bits for quantum operations and senses the quantum information of the operation results. A cryogenic analog control chip (CAC) 103 supplies the QBA 101 with quantum operation patterns, operation timing, bias voltage, and RF signals. This CAC 103 is controlled by a host computer and a digital control chip (CDC) 104, which has a bridge function, and receives the results of operations performed by the QBA 101.

[0004] To ensure stable operation of the quantum bit (Qubit) 102, the QBA 101 is placed inside the dilution refrigerator DR and operates at an extremely low temperature of about 0.1 K. The CAC 103 that controls it is placed in an environment of about 4 K inside the dilution refrigerator DR. The host computer and CDC 104 operate at room temperature.

[0005] Figure 2A shows a cross-sectional view of the quantum bit (Qubit) array mounted on the QBA101. In this QBA101, the Qubit is the spin S of a single electron confined within a potential barrier PB formed in a silicon channel C of a MOS structure. Figure 2A shows the state in which an electron is trapped directly below the quantum dot control gate (XQ) 201 by increasing the voltage of the quantum dot control gate (XQ) 201 and decreasing the voltage of the interaction control gate (XJ) 202. In other words, the XQ 201 acts as a quantum dot that can trap electrons, and a quantum bit (Qubit) is formed by trapping a single electron within it.

[0006] The operation of a quantum bit (Qubit) is controlled by irradiating it with a high-frequency RF signal, as shown in Figure 2B. A magnetic field B is applied to the Qubits in the array, and the precession frequency f S is set to 20.01 GHz for the selected bits and 20 GHz for the unselected bits. When an RF signal with a frequency of 20.01 GHz is irradiated to the entire array, the spin of only the selected bits, whose precession frequency matches the RF frequency, is rotated, allowing quantum operations to be performed.

[0007] In a quantum bit (Qubit) array, quantum dots are arranged two-dimensionally in the X and Y directions, as shown in Figure 3. The first layer of gate wiring in the MOS structure consists of quantum dot control gate lines (XQ) 2022 and interaction control gates (XJ) 2021 arranged in multiple rows in the X direction, while the second layer of gate wiring consists of quantum dot control gate lines (YQ) 2032 and interaction control gates (YJ) 2031 arranged in multiple rows in the Y direction. To make the structure easier to understand, Figure 3 shows the distance between the first layer of gate wiring and the silicon channel C expanded in the Z direction. This array structure enables large-scale integration of quantum dots and quantum bits (Qubits) while suppressing an increase in the total number of wiring lines.

[0008] As a technology using such quantum bits (Qubits), for example, the technology described in Patent Document 1 is disclosed. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2021 / 251175 Summary of the Invention [Problem to be solved by the invention]

[0010] The issues with the prior art typified by Patent Document 1 will be specifically explained using the circuit diagram of a quantum bit (Qubit) array shown in Figure 4. In this circuit diagram, an initialization region 402 and a sense region 403 are arranged on either side of a central calculation region 401. The array alternates between quantum dot control gate MOSs (with gates connected to XQ or YQ) and interaction control gate MOSs (with gates connected to XJ). The silicon channel C of the SOI structure is connected in the X direction, enabling electron movement and interaction between quantum dots via transfer gates. In addition, an interaction control gate MOS (with gates connected to YJ) is arranged to connect the silicon channel C in the Y direction, enabling electron movement and interaction in the Y direction as well.

[0011] In the calculation region 401, 128 MOS transistors used as quantum dots are arranged in 8 rows x 16 columns. Two and four columns of MOS transistors for quantum dots are arranged in the initialization region 402 and the sense region 403, respectively. One side of the silicon channel C in both the X and Y directions at the end of the array is commonly connected to the reservoir terminal Nres, and the other side is separated as a DOE / DOS terminal. Although not shown as wiring, an RF signal RFQB is arranged on this array by multilayer wiring.

[0012] This chip performs operations on a single quantum bit (Qubit), such as spin rotation around the X axis (Rx) and spin rotation around the Y axis (Ry), which rotate the direction of the spin that holds the quantum information of the Qubit by 90 degrees around the X and Y axes of the Bloch sphere, respectively.

[0013] As an example of control when performing Rx / Ry calculations, control using a dynamic resonant frequency change method is shown in Figures 5A and 5B. Figure 5B shows an example of the operating waveform when operating Qubit qd00 in the array circuit diagram shown in Figure 5A. First, a static magnetic field is applied to the entire chip, setting the resonant frequency of the precession of the electron spins of all Qubits to 20 GHz.

[0014] When performing calculations, V is applied between terminals XJN1 and XJS1, and between terminals XJN2 and XJS2. L1 -V L2 A voltage of 20µA is applied from XJS1 to XJN1 and from XJN2 to XJS2. Furthermore, V is applied between terminals YJW0 and YJE0, and between terminals YJW1 and YJW1. L3 -V L4 A voltage of 1 mA is applied from YJW0 to YJE0 and from YJE1 to YJW1. The local magnetic field generated by this current causes the resonant frequency f of the spin precession of electrons in qd00. qd00 However, it increases from 20GHz in standby mode to 20.01GHz.

[0015] In this state, a 20.01 GHz RF signal RFQB is applied to the entire chip with a period of Rabi oscillation t RB If the RF signal is applied for only a quarter of the time, only the electron spins in qd00 with the same resonance frequency can be selectively rotated by 90°. If the phase of the RF signal is matched to the phase of the spin precession, rotation around the X axis will occur, and if there is a 90° difference, rotation around the Y axis will be realized. Finally, the voltages applied between terminals XJN1 and XJS1, between XJN2 and XJS2, between YJW0 and YJE0, and between YJW1 and YJE1 are inverted, and f qd00 After setting the frequency to 19.99 GHz, the system waits for the same period of time to compensate for the phase change in the spin precession.

[0016] To expand the scale of quantum computing, it is necessary to increase the size of the qubit array on this qubit chip and the number of integrated qubits, which increases the impact of variations in device characteristics due to variations in dimensions and composition during device fabrication and spatial variations in the strength of the irradiated RF signal.

[0017] As an example, the distance between the qubit qd00 and the gate XJN1 in FIG. 5A may be different from the distance between the qubit qd10 and the gate XJN1. In this case, the resonant frequency f of the spin precession of these qubits qd00、 f qd10The optimum value of the current to be applied to XJN1 to achieve 20.01GHz differs from 20uA.

[0018] Furthermore, when an RF signal is applied to the entire chip, the received signal strength may differ for spatially separated qubits in the array of Figure 4. In this case, the Rabi oscillation period t RB Since the time required for applying the RF signal differs depending on the quantum bit, the optimal time for applying the RF signal to rotate the spin of the selected quantum bit by 90° also differs.

[0019] Therefore, an object of the present invention is to provide a quantum bit array chip in which quantum bits are arranged and integrated in an array, which can suppress a decrease in calculation accuracy due to characteristic variations within the chip, even when the number of integrated quantum bits is increased, while suppressing an increase in the size of the parameter table that stores the operating conditions necessary for control, as well as a quantum computer using the same, and a calculation method using electronic shuttling. [Means for solving the problem]

[0020] In order to solve the above problems, the present invention provides a quantum computer that includes a quantum dot array in which quantum dots are arranged two-dimensionally, and performs quantum operations by irradiating the quantum dot array with electromagnetic waves, wherein the quantum dot array is divided into an operation area in which the quantum operations are performed and a memory area in which quantum bits stored in the quantum dots are shuttled, and the quantum computer has a parameter table that stores, for each quantum dot, a control voltage and a control time during the quantum operation in the operation area, and controls the quantum bits in the operation area based on the parameter table.

[0021] The present invention is also characterized by comprising the steps of: (a) rearranging the quantum bits in the memory area to make them adjacent to each other, and then shuttling the quantum bits into the operation area; and (b) controlling the quantum bits in the operation area based on a parameter table that stores, for each quantum dot, the control voltage and control time during quantum operation in the operation area. [Effects of the Invention]

[0022] According to the present invention, it is possible to realize a quantum bit array chip in which quantum bits are arranged and integrated in an array, which can suppress a decrease in calculation accuracy due to characteristic variations within the chip, even when the number of integrated quantum bits is increased, while suppressing an increase in the size of a parameter table that stores operating conditions necessary for control, as well as a quantum computer using the same and a calculation method using electronic shuttling.

[0023] This will enable the quantum bit array chip and the quantum computer using it to have higher performance and higher accuracy.

[0024] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a silicon quantum computer. [Figure 2A] FIG. 1 is a diagram showing a cross-sectional structure of a quantum bit (Qubit) array. [Figure 2B] FIG. 1 is a diagram illustrating a quantum computing method using electromagnetic field irradiation. [Figure 3] FIG. 1 illustrates a silicon qubit array structure. [Figure 4] FIG. 1 is a circuit diagram of a quantum bit array. [Figure 5A] FIG. 10 is an array circuit diagram of a dynamic resonant frequency changing method. [Figure 5B] 10 shows the operating waveforms of a dynamic resonant frequency changing method. [Figure 6] FIG. 1 is a circuit diagram of a quantum bit array according to a first embodiment of the present invention. [Figure 7A] FIG. 7 is a diagram showing a part of the calculation region in FIG. 6. [Figure 7B] FIG. 10 is a diagram showing the operation waveforms of quantum dot unit operation control. [Figure 7C]FIG. 10 is a diagram illustrating an example of a parameter table in the control chip. [Figure 8] FIG. 10 is a diagram illustrating calculation control by electronic shuttling. [Figure 9A] FIG. 10 is a circuit diagram showing the initialization operation of the quantum bit array. [Figure 9B] FIG. 10 is a potential diagram showing the initialization operation of the quantum bit array. [Figure 9C] FIG. 10 is a diagram showing the operating waveforms of the initialization operation of the quantum bit array. [Figure 10A] FIG. 1 is a circuit diagram showing the shuttling operation (control of each column) in a quantum bit array. [Figure 10B] FIG. 1 is a potential diagram showing the shuttling operation (control of each column) in a quantum bit array. [Figure 10C] FIG. 10 is a diagram showing the operating waveforms of the shuttling operation (control of each column) in the quantum bit array. [Figure 11A] FIG. 1 illustrates an example of quantum computation by electron shuttling. [Figure 11B] FIG. 10 is a diagram showing an example of an operation sequence by electronic shuttling. [Figure 12] FIG. 1 illustrates a method for permuting quantum bits by electron shuttling. [Figure 13] FIG. 10 is a diagram illustrating a quantum bit array according to a second embodiment of the present invention. [Figure 14A] FIG. 10 is a circuit diagram showing the spin-charge conversion operation in the sense region. [Figure 14B] FIG. 10 is a potential diagram showing the spin-charge conversion operation in the sense region. [Figure 14C] FIG. 10 is a diagram showing the operating waveforms of the spin-charge conversion operation in the sense region. [Figure 15] FIG. 14 is a circuit diagram of the sense region of FIG. 13. [Figure 16] FIG. 10 is a diagram showing a quantum bit array according to a third embodiment of the present invention. [Figure 17] FIG. 17 is a circuit diagram of the sense area and the initialization area of ​​FIG. 16. [Figure 18A]FIG. 1 is a circuit diagram showing shuttling operation (whole array mode) in a quantum bit array. [Figure 18B] FIG. 1 is a potential diagram showing shuttling operation (whole array mode) in a qubit array. [Figure 18C] FIG. 10 is a diagram showing the operating waveforms of a shuttling operation (whole array mode) in a quantum bit array. [Figure 19] FIG. 1 is a diagram showing the configuration of a quantum bit array chip (QBA). [Figure 20] FIG. 1 is a diagram showing the signal interface between the cryogenic analog control chip (CAC) and the quantum bit array chip (QBA). [Figure 21] FIG. 1 is a diagram showing the block configuration of registers and switches of a quantum bit array chip (QBA). [Figure 22] FIG. 10 is a diagram showing a first switch matrix connected to quantum bit array control signal lines. [Figure 23] FIG. 10 is a diagram showing a second switch matrix connected to quantum bit array control signal lines. [Figure 24] FIG. 10 is a diagram showing a third switch matrix connected to quantum bit array control signal lines. [Figure 25] FIG. 10 is a diagram illustrating a method for controlling the slew rate of the first array control signal line. [Figure 26] FIG. 10 is a diagram showing a method for controlling the slew rate of a second array control signal line. [Figure 27A] FIG. 1 is a diagram showing a cross-sectional structure of a quantum bit (Qubit) array. [Figure 27B] FIG. 1 is a diagram showing the layout of a quantum bit (Qubit) array. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. [Example]

[0027] A quantum bit array chip according to a first embodiment of the present invention, a quantum computer using the same, and a computing method using electron shuttling will be described with reference to FIGS.

[0028] First, the quantum bit (Qubit) array of this embodiment will be specifically described with reference to Fig. 6. Fig. 6 is a circuit diagram of the quantum bit (Qubit) array of this embodiment.

[0029] In the circuit diagram, memory regions are placed on both sides of the central calculation region, with the initialization region on the left and the sense region on the right. In the array, quantum dot control gate MOS (gate connected to XQ) and interaction control gate MOS (gate connected to XJ) are alternately placed in the X direction, and SOI structure silicon channel C is placed in the X direction, enabling electron movement and interaction between quantum dots via the transfer gate.

[0030] In addition, quantum dot control gate MOS (gate connected to YQ) and interaction control gate MOS (gate connected to YJ) are arranged alternately in the Y direction, and SOI structure silicon channel C is arranged in the Y direction, enabling electron movement and interaction between quantum dots via the transfer gate. At the intersection of the X-direction silicon channel C and the Y-direction silicon channel C, a quantum dot control gate MOS (gate connected to YQ) is arranged.

[0031] The calculation area has 16 MOSs used as quantum dots arranged in an 8-row x 2-column array. Quantum operations such as Rx / Ry and Swap are performed in this area. The memory areas on both sides have 8-row x 16-column quantum dot arrays, and 17-row x 1-column quantum dots are arranged at the boundary of the calculation area.

[0032] The initialization region has an 8-row x 2-column quantum dot array, and to its left, there is a 17-row x 1-column quantum dot array. The sense region has an 8-row x 3-column quantum dot array, and to its right, there is a 17-row x 1-column quantum dot array. Note that in Figure 6, elements repeatedly arranged in the X and Y directions are omitted.

[0033] The silicon channel C is connected to the reservoir terminal Nres on one side in both the X and Y directions at the end of the array, and is separated as a DOE / DOS terminal on the other side. Although not shown as wiring, the RF signal RFQB is arranged on this array using multilayer wiring.

[0034] In this way, by dividing the quantum bit array into a memory area and an operation area and performing Rx / Ry and Swap operations only in the operation area, it is possible to limit the scope of quantum bit variation control and make control easier.

[0035] A method of quantum dot-based calculation control will be described using Figures 7A to 7C. Figure 7A is a diagram showing a portion of the calculation area in Figure 6. Figure 7B is a diagram showing the operating waveforms of quantum dot-based calculation control. Figure 7C is a diagram showing an example of a parameter table in the control chip.

[0036] The operations performed on a single quantum bit (qubit) on this chip include spin rotation around the X axis (Rx) and spin rotation around the Y axis (Ry), which rotate the direction of the spin that holds the quantum information of the quantum bit (qubit) by 90 degrees around the X and Y axes of the Bloch sphere, respectively.

[0037] As an example of control when performing Rx / Ry calculations, control using a dynamic resonant frequency change method is shown in Figures 7A to 7C. Figure 7B shows an example of the operating waveform when operating Qubit qd00 using the array circuit diagram shown in Figure 7A. First, a static magnetic field is applied to the entire chip, setting the resonant frequency of the precession of the electron spins of all Qubits to 20 GHz.

[0038] When performing an operation, terminal XJN 17 ,XJS 17 ,XJN 18 ,XJS 18 V L2n ,V L1s ,V L1n ,V L2s Apply a voltage of XJS 17 From XJN 17 Towards, and XJN 18 From XJS 18 A current of about 80uA is applied to the direction of the electron spin precession in the qd00. The local magnetic field generated by this current causes the resonant frequency f qd00 However, it increases from 20GHz in standby mode to 20.01GHz.

[0039] At this time, unlike Figure 5A, the current value is increased in order to control the electron resonance frequency to 20.01 GHz only by the current flowing through the XJ terminal. 17 A similar local magnetic field is applied to other quantum dots connected to the gate. Therefore, by shuttling electrons in advance within the array and placing electrons only in the qd00 quantum dots, selective quantum operations can be performed.

[0040] In this state, a 20.01 GHz RF signal RFQB is applied to the entire chip with a period of Rabi oscillation t RB If the RF signal is applied for only a quarter of the time, only the electron spins in qd00 with the same resonance frequency can be selectively rotated by 90°. In this case, if the phase of the RF signal is matched with the phase of the spin precession, rotation around the X axis will occur, and if there is a 90° difference, rotation around the Y axis will be realized. Finally, the terminal XJN 17 ,XJS 17 Between, XJN 18 ,XJS 18 Reverse the voltage applied between f qd00 After setting the frequency to 19.99 GHz, the system waits for the same period of time to compensate for the phase change in the spin precession.

[0041] In this case, the qubit qd00 and gate XJN in Figure 7A 17The distance between the qubit qd10 and the gate XJN1 may be different from the distance between the qubit qd10 and the gate XJN1. In this case, the resonant frequency f qd00、 f qd10 To make it 20.01GHz, XJN 17 The optimum value of the applied current differs from 80uA.

[0042] Furthermore, when an RF signal is applied to the entire chip, the received signal strength may differ for quantum bits that are spatially separated within the array. In this case, the Rabi oscillation period t RB Since the time required for applying the RF signal differs depending on the quantum bit, the optimal time for applying the RF signal to rotate the spin of the selected quantum bit by 90° also differs.

[0043] Therefore, the optimal applied voltage V when applying current to the gate for each quantum dot is set in the parameter table shown in Figure 7C. L1n ,V L1s ,V L2n ,V L2s and the application time of the electromagnetic wave t RF These voltages and times applied from the control chip can be optimized depending on the location of the quantum dot that performs the quantum operation. The parameter table may be placed on the quantum bit chip or on a different control chip.

[0044] This control allows for the setting of operating conditions for each bit, even if the number of qubits integrated on a qubit array chip increases and the characteristic variability increases, thereby improving the accuracy of calculations. Furthermore, by limiting the qubits that perform quantum calculations, it is possible to suppress an increase in the size of the parameter table that stores the operating conditions required for this control.

[0045] Figure 8 shows a method for controlling calculations using electronic shuttling. Figure 8 shows a schematic diagram of the initialization area, memory area, calculation area, and sense area in the quantum bit array of Figure 6. The memory area contains four quantum bits, A0, B0, C0, and D0, and the example shows a case where calculations are performed using A0 and B0 to obtain A1 and B1.

[0046] In step 1, quantum bits A0 and B0 are moved to the calculation region by shuttling. At this time, C0 and D0 are kept in the memory region. In step 2, quantum operations are selectively performed on A0 and B0 to produce A1 and B1. In step 3, quantum bits A1 and B1 containing the calculation results are sequentially moved to the sense region by shuttling, and the spin information is read out.

[0047] By using this type of calculation method, even if the memory area is expanded to increase the number of quantum bits to be calculated, the calculation area can be limited to a fixed size, which has the advantage that the size of the parameter table to accommodate characteristic variations can be kept constant.

[0048] Furthermore, the operation of the sense region also requires optimum value control similar to that in FIG. 7C, but since the sense region is also limited, there is an advantage in that the size of the parameter table can be kept constant.

[0049] As a method for initializing a quantum bit array, a pumping method is used to fill a quantum dot with a single electron and then transfer it to the edge of the array, as shown in Figures 9A to 9C. The circuit diagram is shown in Figure 9A, the potential diagram for each step is shown in Figure 9B, and the operating waveforms are shown in Figure 9C.

[0050] The reservoir terminal Nres is fixed to the voltage Vres, and the YQW1 terminal is connected to the high voltage V H XJS i0 and XQS i0 The MOS structure, in which the terminal is input to the gate, forms a potential barrier for pumping, and by adjusting the height of the barrier, it is possible to move only one electron at a time. i0 The voltage is low voltage V L and XJS i0 is the intermediate voltage V B0a and V B0b Varies between XJS i0 V B0b At this time, only one electron crosses the barrier, and XJSi1 This is the potential well created under XQS i1 A pulse applied to XJS0 can shuttle electrons to the right of the array.

[0051] This operation is performed simultaneously on MOS transistors whose gates are commonly connected in the X direction, so it is possible to perform the initialization operation on all rows of the array. 15 V L By lowering the voltage to 0 V and blocking electrons, it is possible to perform an initialization operation and inject electrons only in selected rows.

[0052] Figures 10A to 10C show how electrons are moved within the quantum bit array using this method. The circuit diagram is shown in Figure 10A, the potential diagram for each step is shown in Figure 10B, and the operating waveform is shown in Figure 10C. The XQ and XJ wiring are controlled to control all rows simultaneously, but the depths of adjacent potential wells are both V H and electrons are moved from left to right.

[0053] By moving electrons using this shuttling method, electrons can be moved between the calculation area and the memory area, making it possible to perform operations on any quantum bit even when performing quantum operations only in the calculation area.

[0054] 11A and 11B show examples of quantum operations performed by shuttling electrons that serve as quantum bits. The operation example in Fig. 11A shows a case where, for four quantum bits A0, B0, C0, and D0, an operation combining one quantum operation and two quantum operations is performed between A0 and B0 to output A1 and B1, an operation combining one quantum operation and two quantum operations is performed between C0 and D0 to output C1 and D1, and an operation combining one quantum operation and two quantum operations is performed between B1 and C1 to output B2 and C2.

[0055] As shown in the operation step of Figure 11B, quantum bits A0 and B0 are moved to the operation region by shuttling and quantum operations are selectively performed to produce A1 and B1. Next, quantum bits C0 and D0 are moved to the operation region by shuttling and quantum operations are selectively performed to produce C1 and D1. The quantum bits are then rearranged so that quantum bits B1 and C1 are adjacent to each other. Finally, these are moved to the operation region and quantum operations are performed to produce B2 and C2.

[0056] In this way, by swapping adjacent quantum bits by shuttling, quantum operations can be performed on any pair of quantum bits.

[0057] FIG. 12 shows a schematic diagram of a method for shuffling electrons in a quantum dot, i.e., a method for shuffling the order of quantum bits, using a quantum dot with 2 rows and 10 columns.

[0058] In Figure 12, quantum dots in the memory area are shown as light gray hatched areas, and quantum dots in the operation area are shown as dark gray hatched areas. The white areas have no channels, and electrons cannot move through them.

[0059] At time t = 0, four quantum bits A0, B0, C0, and D0 are placed as shown in Figure 12. After A0 and B0 are moved to the operation area by shuttling, quantum operation U1 is performed at time t = 1 to 2. Similarly, after C0 and D0 are moved to the operation area by shuttling, quantum operation U2 is performed at time t = 3 to 4.

[0060] Then, from time t5 to t10, the quantum bits A1, B1, C1, and D1 of the calculation results are rearranged to make B1 and C1 adjacent. At this time, as shown from time t=6 to t=9, A1 is moved to the quantum dot at (X,Y)=(6,0), swapping the order of A1, B1, and C1. Finally, from time t=11 to t=12, quantum operation U3 is performed, and the final calculation results B2 and C2 are obtained.

[0061] As shown in this example, by creating rows such as Y=0, 2 in which no quantum dots are arranged in the quantum bit array, the order of electrons can be easily exchanged. [Example]

[0062] Second Embodiment A quantum bit array chip according to a second embodiment of the present invention, a quantum computer using the same, and a computing method using electron shuttling will be described with reference to FIGS.

[0063] Figure 13 is a diagram showing a quantum bit array according to this embodiment, and illustrates a method for expanding the quantum bit array size. This embodiment shows a method for expanding the array size and increasing the number of quantum bits by arranging multiple memory regions MA, calculation regions PA, initialization regions IA, and sense regions SA. This embodiment shows an example in which the array shown in Figure 6 is inverted in the X direction, with the sense region as the boundary, and expanded in the Y direction by repeating the same configuration.

[0064] The operation of the sense area SA in this quantum bit array is shown in Figures 14A to 14C. The calculation result is read out by sensing the spin information of the electrons that make up the quantum bit (qubit). To do this, the spin direction of the quantum bit (qubit), which stores the quantum information of the calculation result, is first converted into an electric charge (one or two electrons) in the sense area SA, and this electric charge is then shuttled to a comparator outside the array and converted into classical digital information. If the quantum bit (qubit) is in an intermediate state between "0" and "1," either "0" or "1" will be read out with a probability proportional to that state.

[0065] FIG. 14A shows a circuit diagram, and FIG. 14B shows a potential diagram of the quantum dots included in the circuit of FIG. 14A. Also, FIG. 14C shows a case where the gate electrode is an XQN. r0The figure shows the waveform of the operation when converting the spin information of the quantum bit (Qubit) contained in the quantum dot qd0 connected to XQN into a charge. Here, only one row of quantum dots is shown, but the control line is connected to quantum dots in all rows, and the same operation is performed in these quantum dots. r1 and XQN r2 The gate electrodes of the quantum dots qd1 and qd2 connected to r1 , XJN r2 , XJN r3 The transfer gate connected to the gate is used as a barrier.

[0066] When the calculation is completed, the voltage of the control line XJN is V L , control line XQN is V H Held by XJN r1 V H By setting it to and shuttling, the quantum bit (Qubit) in qd0 is moved to qd1. One electron with an up-spin is placed in the quantum dot qd2 beforehand at the time of initialization. XJN r1 is the bias voltage V B0 , XJN r2 is the bias voltage V B1 , XQN r2 is the bias voltage V S2 and the quantum dot qd2 is set to a potential state in which only two electrons can exist.

[0067] Next, XQN r1 is the bias voltage V F Here, these bias voltages are set so that the quantum levels of T(1,1) and S(1,1) in qd1 are between the quantum levels of T(2,0) and S(2,0) in qd1. This creates a spin blockade state in which only electrons with downward spins in qd1 can pass through qd1 and the barrier, and electrons with upward spins cannot enter qd1.

[0068] That is, if the result is "0" and the electron in qd1 has an up-spin, the number of electrons in qd2 remains 1, and if the result is "1" and the electron in qd1 has a down-spin, the number of electrons in qd2 increases to 2. XJN r3 ,XJS r3 V H By switching on the YQE1 gate, this charge is transferred to the quantum dot qd3 in each row, whose gate is controlled by YQE1, and stored as the sense result. This charge is then shuttled out of the array and read out as a classical "0" or "1."

[0069] Figure 15 shows a circuit diagram of the sense region SA in the center of the array in Figure 13. In this array, the number of quantum bits used for calculations can be increased by shuttling electrons from memory region MA01 to memory region MA02. In this case, the upward-spin electrons used for spin blockade in the sense amplifier region are shuttled to a quantum dot controlled by the gate of YQE2, shown by the thick dotted line in Figure 15.

[0070] This operation makes it possible to immediately read out the results when an operation is performed via a plurality of memory areas MA. [Example]

[0071] Third Embodiment A quantum bit array chip according to a third embodiment of the present invention, a quantum computer using the same, and a computing method using electron shuttling will be described with reference to FIGS.

[0072] This example shows a method for expanding the array size and increasing the number of quantum bits by arranging multiple memory areas MA, calculation areas PA, initialization areas IA, and sense areas SA. As shown in Figure 16, this example shows an example in which the array in Figure 6 is expanded by repeating the same configuration in both the X and Y directions.

[0073] Fig. 17 shows a circuit diagram of the sense area SA and initialization area IA in the center of the array in Fig. 16. Fig. 17 is a diagram showing a method of supplying electrons during initialization.

[0074] In this array, the number of quantum bits used for calculations can be increased by shuttling electrons from memory area MA01 to memory area MA02.

[0075] During initialization, electrons are supplied to the initialization area IA via MOS transistors controlled by the YQ and YJ gates in the sense amplifier area. This allows the number of MOS transistors connecting the array in the Y direction to be reduced to one row, thereby reducing the area and control time of the control circuit. [Example]

[0076] Fourth Embodiment A quantum bit array chip according to a fourth embodiment of the present invention, a quantum computer using the same, and a computing method using electron shuttling will be described with reference to FIGS. 18A to 26. FIG.

[0077] In Example 1 (FIGS. 10A to 10C), an example was shown in which shuttling was performed by controlling the control lines of the quantum bit array one by one. In the example of the memory area and calculation area shown in the array in FIG. 6, there are 37 control lines for XJ, 34 for XQ, and 8 for YQ, and it is necessary to set the voltage for each of these lines from outside the chip.

[0078] Figures 18A to 18C show the operation when shuttling is performed simultaneously across the entire array. As shown in the circuit diagram of Figure 18A, two XJ gates and two XQ gates form one group, which holds one quantum bit. Correspondingly, all of the array control signal lines are divided into four groups. The even-numbered XJ gates are grouped as CG0 and connected together. The odd-numbered XJ gates are grouped as CG2 and connected together. The even-numbered XQ gates are grouped as CG1 and connected together. Additionally, the odd-numbered XQ gates are grouped as CG3 and connected together.

[0079] The potential diagram created by these gates is shown in FIG. 18B, and the operational waveforms are shown in FIG. 18C. H and low voltage VL By controlling the potential between the qubits in common, it is possible to control the potential and shuttling the qubits to the right simultaneously across the entire array.

[0080] In this case, the voltages for these four groups can be set from outside the chip, which makes shuttling control easier and shortens the time required for shuttling.

[0081] In order to explain the configuration of the switch matrix and switch control register connected to the array control signal lines, the configuration of the quantum bit array chip (QBA) is shown in FIG.

[0082] A cryogenic analog control chip (CAC: 103 in Figure 1) supplies 50 types of array bias voltages V_DAC to a quantum bit array chip (QBA) 1901. A bias pattern signal BSPT and a bias pattern strobe signal BSTR are input to QBA 1901 to control how these bias voltages are applied to each quantum bit array control signal line in quantum bit (Qubit) array 1902.

[0083] Inside the QBA1901, the combination of quantum bit array control signal lines and control voltages is specified by a 9-bit signal consisting of a 6-bit control line address SID and a 3-bit control line voltage SWNO. The bias pattern signal BSPT allows three control line information to be input simultaneously using a total of 27 signals in three groups, X, Y, and S, indicated by the control line address SID of the quantum bit array control signal lines.

[0084] These pieces of information are decoded by decoders 1903a and 1903b, respectively, and then stored in switch control register 1904. Based on the state of switch control register 1904, switch matrix 1905 is switched to output the desired bias voltage to the quantum bit array control signal line. This timing is defined by control signal enable SWEN.

[0085] The RF signal for quantum operation is input via RF and then propagates through the wiring on the quantum bit (Qubit) array 1902. The result of the quantum operation performed by the Qubit array 1902 is converted into classical digital information by the sense amplifier 1906 and output to the cryogenic analog control chip (CAC) 103 via the EXRT.

[0086] In order to explain the interface method of signals that define the operation of the quantum bit array chip (QBA) 1901, an example of a timing chart is shown in FIG.

[0087] The cryogenic analog control chip (CAC) 103 outputs a bias pattern signal BSPT in synchronization with the system clock CLK, and also outputs a bias pattern strobe signal BSTR that controls the output timing of the bias pattern. In QBA1901, the bias pattern signal BSPT is latched and decoded at the falling edge of the bias pattern strobe signal BSTR, and then stored in a switch control register 1904 within QBA1901. In switch matrix 1905, which is an analog matrix switch, a voltage selected from the bias voltage V_DAC is connected to the quantum bit array control signal line, and the timing of this connection is determined by a control signal enable SWEN.

[0088] Here, pattern 1 input at clock 2 is output to switch control register 1904 (reference numeral 2001 in FIG. 20), and is output as an array control signal at clock 3 (reference numeral 2002 in FIG. 20). At this time, for quantum bit array control signal lines to which no information has been input at the timing when bias pattern strobe signal BSTR is input, the previously set bias voltage continues to be output from switch matrix 1905.

[0089] In this embodiment, a maximum of three sets of control signal patterns can be input in one cycle, and to change three or more control signals, the switch control register 1904 must be updated over multiple cycles. Here, control patterns 2 and 3 input at clocks 6 and 8 are output as array control signals by the control signal enable SWEN activated at clock 9 (reference number 2003 in Figure 20). The control signal enable SWEN can also be used to transition control signals at timing independent of the system clock. An example is shown in which control pattern 4 input at clock 12 is output as an array control signal at finely adjusted timing (reference number 2004 in Figure 20).

[0090] In this way, by supplying information about bias voltages to be applied to a large number of quantum bit array control signal lines to the QBA1901 in a time-division manner, the number of input signals to the QBA1901 can be limited.

[0091] In addition, by inputting the bias pattern strobe signal BSTR and the control signal enable SWEN, which determine the operation timing of the internal circuits of the QBA1901, from the CAC103, it is possible to omit the timing generation circuit within the QBA1901, thereby reducing the power consumption of the QBA1901.

[0092] The RF signal is applied from RF signal RFQB at a timing specified in CAC 103 and is used for arithmetic processing of quantum bit (Qubit) 102. By inputting sense amplifier control signal pattern 6-9 to clock 20-32, the arithmetic result is read out from data output terminal EXRT (reference numeral 2005 in FIG. 20).

[0093] The main circuits used in the quantum bit array chip (QBA) 1901 are shown in Figure 21. The circuit shown in Figure 21 is configured as a register-switch block 2101 having switch control registers 1904 for generating array control signals and a switch matrix 1905. The switch control registers 1904 and switch matrix 1905 are grouped by signal and arranged around the Qubit array 1902 and sense amplifiers 1906.

[0094] The bias pattern signal BSPT is divided into Groups X, Y, and S, and input to the corresponding register groups.

[0095] The Group X signals are supplied to switch control registers 1904 (switch control registers 1904X1, 1904X2, 1904X3) corresponding to a switch (Group X-1) that outputs array signal XQ, a switch (Group X-2) that outputs array signal XJN, and a switch (Group X-3) that outputs array signal XJS.

[0096] The signals of Group Y are supplied to switch control registers 1904 (switch control registers 1904Y1, 1904Y2, 1904Y3) corresponding to a switch (Group Y-1) that outputs array signal YQW, a switch (Group Y-2) that outputs array signals DOS and DOE, a switch (Group Y-3) that outputs array signal YJW, and a switch (Group Y-4) that outputs array signal YJE.

[0097] The signals of Group S are supplied to switch control registers 1904 (switch control registers 1904S1, 1904S2, 1904S3) corresponding to switches (Group S-1, Group S-2) that output control signals and switches (Group S-3) that output sensing signals.

[0098] In this way, grouping and distributing the quantum bit array control signal lines facilitates the connection between switch matrix 1905 and the array control signals. Also, by dividing the bias pattern signals BSPT into three groups, X, Y, and S, it is possible to simultaneously update the information on three sets of quantum bit array control signal lines, thereby shortening the time required to set the bias voltage.

[0099] The configuration of the first switch control register and switch matrix when shutting down the entire array is shown in Figure 22. In the upper half of the block, V H ,V L A 3-to-1 switch matrix is ​​configured to connect the two bias voltages and the common terminal of CG1. Also, for XQN

[18] , V H ,V L ,V S1 A 4-to-1 switch matrix is ​​formed that connects the three types of bias voltages and the common terminal of CG1.

[0100] In the lower half of the block, V is set for the odd-numbered array control signal lines XQS[1,3, …15] and XQN[21,23 …35]. H ,V L A 3-to-1 switch matrix is ​​configured to connect the two bias voltages and the common terminal of CG3. Also, for XQN

[17] , V H ,V L ,V S1 A 4-to-1 switch matrix is ​​formed that connects the three types of bias voltages and the common terminal of CG3.

[0101] When the bias pattern signal BSPT is input from CAC103 and taken into QBA1901 by the bias pattern strobe signal BSTR, the control line address SID and control line voltage SWNO corresponding to each of Groups X, Y, and S are decoded, and the bit of the bias voltage to be output is held in the register of the corresponding array control signal line.

[0102] When the control signal enable SWEN is input from the CAC 103, the contents of the register are output to the switch matrix, the switch of the corresponding control line is switched, and a predetermined bias voltage is output to the array control signal.

[0103] When shuttling the entire array, as shown in FIG. 22, connect XQS and XQN to CG1 in the upper half of the block, and connect XQS and XQN to CG3 in the lower half of the block.

[0104] The configuration of the second switch control register and switch matrix is ​​shown in Figure 23. In the upper half block, V H ,V L A 3-to-1 switch matrix is ​​configured to connect the two types of bias voltages and the common terminal of CG0. Also, V H ,V L ,V VL5 L ,V VL5 ,V X A 6-to-1 switch matrix is ​​formed that connects the five types of bias voltages and the common terminal of CG0.

[0105] In the lower half of the block, V is set for the odd-numbered array control signal lines XJS[1,3, …15] and XJN[21,23 …35]. H ,V L A 3-to-1 switch matrix is ​​configured to connect the two types of bias voltages and the common terminal of CG2. Also, V H ,V L ,V VL5 L ,V VL5 ,V X A 6-to-1 switch matrix is ​​formed that connects the five types of bias voltages and the common terminal of CG2.

[0106] When shuttling the entire array, as shown in FIG. 23, connect XJS and XJN to CG0 in the upper half of the block, and connect arrays XJS and XJN to CG2 in the lower half of the block.

[0107] The configuration of the third switch control register and switch matrix is ​​shown in Figure 24. In the upper half block, V H ,V L A 3-to-1 switch matrix is ​​formed that connects the two types of bias voltages and the common terminal of CG1.

[0108] In the lower half of the block, V is set for the odd-numbered array control signal lines of YQE[0,1, …15]. H ,V L A 3-to-1 switch matrix is ​​formed that connects the two types of bias voltages and the common terminal of CG3.

[0109] When shuttling the entire array, as shown in FIG. 24, connect YQWN to CG1 in the upper half of the block, and connect array YQE to CG3 in the lower half of the block.

[0110] 25 shows a first signal driving method for shutting down the entire array. In this embodiment, the common terminals CG0 to CG3 are external terminals of the QBA chip and are connected to DA converters DAC0 to DAC3 on the cryogenic analog control chip (CAC) 103. When shutting down, the DA converters directly transition the voltage of the common terminals between VL and VH.

[0111] It is known that if the transition time is too short, the fidelity of the quantum state in the quantum bit will deteriorate. For this reason, the degradation of fidelity can be suppressed by controlling the signal transition time with a DA converter. In this way, when the voltage is controlled from outside the chip, the configuration of the quantum bit array chip (QBA) 1901 can be simplified.

[0112] 26 shows a second signal driving method for shutting down the entire array. In this example, V L or V H A switch matrix and a switch control register are provided to apply the voltages to CG0 to CG3. The switch control register specifies the voltages to be applied to CG0 to CG3 according to the phases PH0 to PH3. By controlling the phase register values ​​from CAC103 in the order PH0 to PH3, the voltages required to shut down the entire array can be generated for CG0 to CG3.

[0113] Here, variable load capacitances for slew rate control are connected to CG0 to CG3, and the magnitude of the load capacitance is changed to control the slew rate of the signal by switching the value of register SR between 0 and 3. When the voltage is controlled inside the quantum bit array chip (QBA) as in this embodiment, there is an advantage that the slew rate can be accurately controlled because the influence of parasitic capacitance can be reduced.

[0114] In this way, when shutting, the array control signal lines are divided into four groups, connected together, and controlled collectively. This means that it is only necessary to set the voltage for these four groups from outside the chip, which simplifies shuttling control and reduces the time required for shutting.

[0115] Furthermore, since the change time of the control signal can be controlled, it is possible to suppress the deterioration of fidelity of the quantum bit when shuttling is performed. [Example]

[0116] A quantum bit array chip according to a fifth embodiment of the present invention, a quantum computer using the same, and a computing method using electron shuttling will be described with reference to FIGS. 27A and 27B.

[0117] 27A and 27B are diagrams showing a second selection method (quantum operation method using a local magnetic field) of quantum bits that perform operations on the quantum bit array chip (QBA) 101. Fig. 27A shows the cross-sectional structure of the quantum bit (Qubit) array, and Fig. 27B shows the layout of the quantum bit (Qubit) array.

[0118] In the quantum bit array chip (QBA) 101 of this embodiment, the spin S of a single electron confined within a potential barrier PB formed in a silicon channel C of a MOS structure is used as a quantum bit (Qubit).

[0119] FIG. 27A shows a state in which electrons are trapped directly below the quantum dot control gate (XQ) 201 by increasing the voltage of the quantum dot control gate (XQ) 201 and decreasing the voltage of the interaction control gate (XJ) 202. In other words, the quantum dot control gate (XQ) 201 acts as a quantum dot that can trap electrons, and a quantum bit (Qubit) is formed by trapping one electron therein. Furthermore, as shown in the layout of FIG. 27B, in the operation region, a ferromagnetic film ML is placed above the MOS structure, and the magnetic field B L An external magnetic field B is applied to the entire qubit array chip. EX When the magnetic field strength in the calculation area is applied, B L +B EX and the magnetic field strength of the memory area is B EX This becomes:

[0120] In this way, by creating a difference in magnetic field strength between the operation area and the memory area, the frequency of precession of electrons in the quantum dots in the operation area, f S is set to 20.01 GHz, and the frequency of the precession of electrons in the quantum dots in the memory region is set to 20 GHz.

[0121] When the entire array is irradiated with an RF signal with a frequency of 20.01 GHz, the spins of only the electrons in the quantum dots in the calculation region, whose precession frequency matches the RF frequency, are rotated, allowing quantum calculations to be performed.

[0122] As another calculation method, in the structures of FIGS. 27A and 27B, no external magnetic field is applied, and electrons are normally placed in the memory calculation region, and only the electrons of the selected quantum bit are shuttled and moved to the calculation region, thereby reducing the local magnetic field B L It is also possible to rotate the electron spin S by applying

[0123] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0124] 101, 1901... Quantum bit array chip (QBA), 102... Quantum bit (Qubit), 103... Cryogenic analog control chip (CAC), 104... Digital control chip (CDC), 201, 2022, 2032... Quantum dot control gate (XQ, XQN, XQS, YQ, YQE, YQW), 202, 2021, 2031... Interaction control gate (XJ, XJN, XJS, YJ, YJW, YJE), 1000... Silicon quantum computer, 401... Computation area, 402... Initialization area, 403... Sense area, 1902... Quantum bit Qubit array, 1903a, 1903b...decoder, 1904...switch control register, 1905...switch matrix, 1906...sense amplifier, 2001, 2002, 2003, 2004, 2005...output, 2101...register switch block, DR...dilution refrigerator, C...silicon channel, PB...potential barrier, S...electron spin, MA...memory area, PA...arithmetic area, IA...initialization area, SA...sense area, CX...X system control circuit, CY...Y system control circuit, CS...sense system control circuit, ML...ferromagnetic film, f S …spin precession frequency, fRF、 f MW ...RF signal frequency, t RF ...RF signal application time, V L1 ,V L2 ,V B0 ,V B1 …bias voltage, t RB ...Rabi oscillation period, V_DAC...bias voltage, BSPT...bias pattern signal, SID...control line address, SWNO...control line voltage, BSTR...bias pattern strobe signal, SWEN...control signal enable, EXRT...arithmetic result output (data output terminal), DAC...digital-analog converter, CG...common gate, PH...phase

Claims

1. A quantum dot array is provided in which quantum dots are arranged two-dimensionally, A quantum computer that performs quantum operations by irradiating the quantum dot array with electromagnetic waves, The quantum dot array is divided into an operation area for performing the quantum operation and a memory area for shuttling quantum bits stored in the quantum dots, a parameter table storing a control voltage and a control time for the quantum operation in the operation region for each quantum dot; A quantum computer that controls the quantum bits in the operation area based on the parameter table.

2. 2. The quantum computer according to claim 1, A quantum computer characterized in that the quantum bits are rearranged in the memory area so as to be adjacent to each other, and then the quantum bits are shuttled into the operation area to perform the quantum operation.

3. 3. The quantum computer according to claim 2, the quantum dot array comprises a sense region; A quantum computer characterized in that the operation result of the quantum operation is output by moving the quantum bit to the sense region and reading it out.

4. 4. The quantum computer according to claim 3, the quantum dot array is configured by repeatedly arranging a plurality of initialization regions, memory regions, and calculation regions; A quantum computer characterized by performing calculations by moving quantum bits between a plurality of said memory areas.

5. 5. The quantum computer according to claim 4, a plurality of array control signal lines in the quantum dot array are commonly connected to a first group to a fourth group via a switch; A quantum computer characterized in that periodic control voltage waveforms of the same shape are applied to the first to fourth groups with a fixed time difference.

6. 6. The quantum computer according to claim 5, A quantum computer characterized in that a variable load capacitance for controlling the rate of change of the voltage of the array control signal line is connected to the common terminal side of the switch.

7. 5. The quantum computer according to claim 4, The quantum dot array comprises a semiconductor layer and an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes disposed on the insulating layer, the first gate electrodes trapping electrons of a predetermined spin state in the semiconductor layer when a voltage is applied thereto; a plurality of second gate electrodes arranged alternately with the first gate electrodes, the second gate electrodes being adjacent to the first gate electrodes when a current for forming a magnetic field acting on the electrons is passed in an extension direction of the first gate electrodes in the case of changing the spin state of the electrons; A quantum computer characterized in that, when the spin state of electrons trapped in the first gate electrode is changed, a current is controlled to flow through the second gate electrode.

8. 5. The quantum computer according to claim 4, The quantum dot array comprises a semiconductor layer and an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes disposed on the insulating layer, the first gate electrodes trapping electrons of a predetermined spin state in the semiconductor layer when a voltage is applied thereto; a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes; In the operation region, a ferromagnetic film is disposed on the first gate electrode, A quantum computer characterized in that, when performing the quantum operation, the frequency of the precession of electron spins in the quantum dots in the operation region is different from the frequency of the precession of electron spins in the quantum dots in the memory region.

9. A method of computing using electronic shuttling comprising the steps of: (a) shuffling the quantum bits in a memory region so that they are adjacent to each other, and then shuttling the quantum bits in a computation region; (b) controlling the quantum bit in the operation region based on a parameter table storing, for each quantum dot, a control voltage and a control time during quantum operation in the operation region;

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