Logic analyzer circuit, integrated circuit, integrated circuit system and method

Abstract

This logic analyzer circuit comprises: a trace capture circuit that acquires N signals to be observed when a change occurs in at least one of the N signals from a circuit to be observed; and a buffer that stores signal data acquired by the trace capture circuit. The signal data has a timestamp of an M bit width indicating the time of acquisition, and state change data of N bit widths corresponding to respective values of the N signals to be observed. The signal data is binary-format data of an (M+N)-bit fixed length.

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to integrated circuits, and more particularly to logic analyzer circuits that monitor signals within integrated circuits. [Background technology]

[0002] As integrated circuits become larger, their internal logic configurations become more complex, making it more difficult to determine the cause of malfunctions. Malfunctions that could not be detected through theoretical logic verification often occur during testing on an actual device, making analysis difficult. Therefore, there is a demand for more efficient verification by selecting and monitoring multiple desired signals within an integrated circuit. Therefore, a monitoring circuit is implemented to acquire desired signals from the user circuit, and a mechanism is provided to acquire internal signals and output them externally. This monitoring circuit is called a logic analyzer circuit.

[0003] This logic analyzer circuit is a logic-synthesizable circuit that is independent of the device on which it is implemented, allowing it to be implemented and verified together with a user circuit block without relying on an ASIC, FPGA, or the like (see, for example, Patent Document 1). The user circuit to be monitored and the logic analyzer circuit are implemented within an integrated circuit, and state changes in the monitored signal are recorded along with a timestamp. Patent Document 1 reduces the data size of the acquired signal by sampling only state changes rather than continuously sampling the value of the probed signal according to the system clock. An example of a file format is an encoding format using ASCII (American Standard Code for Information Interchange), such as VCD (Value Change Dump) that complies with the IEEE (Institute of Electrical and Electronics Engineers) standard. A programmable processor within the integrated circuit reads the file, converts it into a waveform, and outputs it in real time to a display or the like via a video output port. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2020-529064 Summary of the Invention [Problem to be solved by the invention]

[0005] On the other hand, the VCD format described in Patent Document 1 records a timestamp value for each state change, and the identifier and value of the signal that has changed, in ASCII format. Therefore, when monitoring multiple signals, the data size may increase in proportion to the number of signals that have changed per timestamp.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a logic analyzer circuit, an integrated circuit, and an integrated circuit system that are capable of reducing the data size of a signal to be monitored. [Means for solving the problem]

[0007] A logic analyzer circuit according to one disclosure includes a trace capture circuit that captures N signals to be observed from a circuit to be observed when a change occurs in at least one of the N signals, and a buffer that stores signal data captured by the trace capture circuit. The signal data includes an M-bit timestamp indicating the time of acquisition and N-bit state change data corresponding to the values ​​of the N signals to be observed. The signal data is binary data with a fixed length of (M+N) bits. [Effects of the Invention]

[0008] The logic analyzer circuit, integrated circuit, and integrated circuit system of the present disclosure are capable of reducing the data size of a monitored signal. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of an integrated circuit 1 according to a first embodiment. [Figure 2] 3 is a diagram illustrating the format of signal data stored in a buffer 105 according to the first embodiment. FIG. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of an external system 109 connected to an integrated circuit 1 according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating details of a signal data set stored in a buffer 105 according to the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating a conventional signal data acquisition format as a comparative example. [Figure 6] FIG. 10 is a diagram illustrating the data size in the method according to the first embodiment and the data size in the method of the comparative example. [Figure 7] FIG. 10 is a schematic diagram of an integrated circuit 1# according to a second embodiment. [Figure 8] FIG. 1 is an image diagram of division of multiple signal data sets. [Figure 9] FIG. 11 is a flowchart illustrating processing for performing compression of blocks in a plurality of patterns in a compression circuit 606 according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating the data size in a method according to a second embodiment and the data size in a method according to a comparative example. [Figure 11] FIG. 10 is a diagram illustrating the internal configuration of a compression circuit 606 according to the third embodiment. [Figure 12] FIG. 11 is a schematic diagram illustrating a scanning method of an input data scanning unit 1101 for each block of divided signal data. [Figure 13] FIG. 11 is a flowchart illustrating a compression process of each block in a compression circuit 606 according to the third embodiment. [Figure 14] FIG. 11 is a diagram illustrating a case where compression processing according to the third embodiment is performed in parallel. [Figure 15] FIG. 10 is a timing chart showing an overview of the compressed code generation process for a plurality of blocks. [Figure 16] FIG. 10 is a schematic diagram illustrating a Huffman table update processing method in the Huffman table update phase. [Figure 17] 13 illustrates a specific example of a Huffman table according to the third embodiment. [Figure 18] FIG. 10 illustrates an integrated circuit according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, identical parts are designated by the same reference numerals. Since the names and functions of these parts are also the same, detailed description thereof will not be repeated.

[0011] Embodiment 1 FIG. 1 is a schematic diagram of an integrated circuit 1 according to the first embodiment.

[0012] Referring to FIG. 1, an integrated circuit 1 includes an observation target circuit 101, a logic analyzer circuit 103 that monitors an observation target signal 102 of the observation target circuit 101, a processor bus 108, and a processor 107 that can execute a program.

[0013] The integrated circuit 1 is also connected to an external system 109 via an external bus 110 . The logic analyzer circuit 103 includes a trace capture circuit 104 and a buffer 105. The trace capture circuit 104 captures the signal when a change occurs in the observation target signal 102. The buffer 105 temporarily stores the captured signal data.

[0014] The processor 107 acquires the signal data temporarily stored in the buffer 105 via a processor bus 108. The processor 107 also transmits the signal data to an external system 109 via an external bus 110.

[0015] FIG. 2 is a diagram illustrating the format of signal data stored in the buffer 105 according to the first embodiment.

[0016] 2, the trace capture circuit 104 captures a signal when there is a change in the observation target signal 102. The buffer 105 stores one signal data set 201 captured by the trace capture circuit 104.

[0017] The signal data set 201 has a timestamp 202 located at the beginning and state change data 203. The timestamp 202 may have any bit width necessary to enable measurement of the time until the next change in the signal 102 under observation.

[0018] When the timestamp 202 overflows, even if there is no signal change, the timestamp 202 at the time of overflow and the state change data 203 are recorded to clearly indicate that an overflow has occurred.

[0019] The state change data 203 may be assigned a bit width necessary to include the desired observation target signal.

[0020] In this example, the signal data set 201 is a fixed-length binary data set that combines a timestamp 202 and state change data 203 .

[0021] The buffer 105 stores a plurality of signal data sets 201 in order from the oldest to the newest.

[0022] FIG. 3 is a diagram illustrating an example of the configuration of an external system 109 connected to the integrated circuit 1 according to the first embodiment.

[0023] Referring to FIG. 3, the external system 109 includes a debugger 2, a PC (Personal Computer) 3, and a display 5.

[0024] Signal data sent from the integrated circuit 1 is input to the debugger 2 via an external bus 110 connected to the integrated circuit 1 .

[0025] The debugger 2 converts the data format of the signal data into a format compatible with the bus of the PC 3 and transmits it to the PC 3.

[0026] The PC 3 has software for displaying the signal data on the display 5, and uses this software to decode the signal data in a predetermined procedure, reconstruct it into a waveform, and display it on the display 5.

[0027] FIG. 4 is a diagram illustrating details of the signal data set stored in the buffer 105 according to the first embodiment.

[0028] 4, in the data recording method according to the first embodiment, a timestamp 202 indicating the data acquisition time is placed on the MSB (Most Significant Bit) side. As an example, 8 bits are allocated to the timestamp 202.

[0029] Next, for example, a monitored signal 502 consisting of 120 signals is treated as 1-bit binary data per signal, and 120 of these signals are combined from the MSB (Most Significant Bit) side to the LSB (Least Significant Bit) side to generate 120-bit state change data 203.

[0030] One piece of signal data is 128-bit fixed-length binary data that combines an 8-bit timestamp 202 and 120-bit state change data 203 .

[0031] As a result, even if the values ​​of multiple signals among the monitored signals change at the same time, the size of the signal data will always be a fixed length of 128 bits (16 bytes) and will never exceed this.

[0032] FIG. 5 is a diagram for explaining a conventional signal data acquisition format as a comparative example. The signal data acquisition format when using the VCD format will be described with reference to Fig. 5. In the VCD format, definitions 401 of character strings corresponding to all signals to be monitored are placed at the beginning of the file.

[0033] Then, as shown in FIG. 5, if there is a change in the signal being monitored, the value 403 after the change in the signal whose state has changed and the corresponding signal identification string 404 are recorded, each on a separate line following the timestamp 402.

[0034] Here, the data size of a timestamp with Nd decimal digits is 1 byte for the first character <#> + 1 byte for the line feed character + Nd bytes for the timestamp = 2 + Nd bytes.

[0035] The data size for each signal that has changed is 3 bytes (1 byte for the change value + 1 byte for the signal identification character string 404 + 1 byte for the line feed character).

[0036] At this point, when the number of changed signals is Nc, the data size per timestamp is 2+Nd+3×Nc bytes.

[0037] Therefore, the data size increases in proportion to the number of changed signals. As an example, assume that the number of signals to be monitored is large, for example, that the number of signals Nc is 120.

[0038] FIG. 6 is a diagram illustrating the data size according to the method of the first embodiment and the data size according to the method of the comparative example.

[0039] Referring to FIG. 6, in this example, the data size relative to the number of state change signals per timestamp of signal data when the VCD format is used is shown.

[0040] For example, the data size of the time stamp is set to Nd = 4. When the number of signals is Nc > 3, the data size of the signal data exceeds 16 bytes.

[0041] On the other hand, when the fixed-length binary format according to the first embodiment is used, the data size relative to the number of state change signals per timestamp of the signal data remains constant even when the number of signals increases.

[0042] Therefore, by using a fixed-length binary format as the transfer format according to the first embodiment, the data size can be significantly reduced even when a large number of state change signals occur per timestamp.

[0043] Embodiment 2 FIG. 7 is a schematic diagram of an integrated circuit 1# according to the second embodiment.

[0044] 7, integrated circuit 1# differs from integrated circuit 1 in that it is replaced by logic analyzer circuit 603#. As the other configurations are the same as those described in FIG. 1, detailed description thereof will not be repeated.

[0045] Compared to logic analyzer circuit 103, logic analyzer circuit 603# further includes compression circuit 606.

[0046] The compression circuit 606 reads out the data group (plurality of signal data sets) stored in the buffer 105 and compresses it.

[0047] Specifically, the data may be compressed into a predetermined binary format using a run-length method as a compression algorithm.

[0048] An example of a predetermined binary format is a header that lists each value of the signal being observed at the start of signal acquisition, followed by the number of times the signal has consecutively taken the same value along the time axis for each change in the signal value. Applying this compression algorithm can achieve a high compression rate when the frequency of signal changes is low.

[0049] The data group may be divided into a number of blocks, and a compression algorithm may be applied to each block.

[0050] Alternatively, the number of blocks to be divided may be changed to perform compression of the blocks in a plurality of patterns, and the compression that results in the smallest data size may be selected.

[0051] FIG. 8 is a conceptual diagram of division of multiple signal data sets. FIG. 8A is an image diagram showing division in the data arrangement direction.

[0052] Referring to FIG. 8(B), this is an image diagram showing a case where data is further divided in the time direction.

[0053] FIG. 9 is a flowchart illustrating processing for performing compression of blocks in a plurality of patterns in compression circuit 606 according to the second embodiment.

[0054] Referring to FIG. 9, compression circuit 606 acquires signal data from buffer 105 and determines whether signal data up to a predetermined size has been acquired (step S1).

[0055] The compression circuit 606 waits until the signal data has been acquired up to a predetermined size (NO in step S1), and if it determines that the signal data has been acquired up to the predetermined size (YES in step S1), it divides the signal data set into N blocks in the data arrangement direction as described in Figure 8(A) (step S2).

[0056] Next, the compression circuit 606 performs a predetermined compression process on the data of the divided N blocks (step S3).

[0057] Next, the compression circuit 606 determines whether or not the compression process for all N divided blocks has been completed (step S4). The compression circuit 606 repeats the predetermined compression process of step S3 until the compression process for all N divided blocks has been completed, and if completed, proceeds to the next step.

[0058] Furthermore, the compression circuit 606 further divides each of the N blocks into two (step S5). Specifically, the blocks are further divided in the time direction as will be described with reference to FIG. 8(B).

[0059] Next, the compression circuit 606 performs a predetermined compression process on the data of the divided 2N blocks (step S6).

[0060] Next, the compression circuit 606 determines whether or not the compression process for all 2N divided blocks has been completed (step S7). The compression circuit 606 repeats the predetermined compression process of step S6 until the compression process for all 2N divided blocks has been completed, and if completed, proceeds to the next step.

[0061] Furthermore, the compression circuit 606 further divides each of the N blocks into four (step S8). Specifically, the blocks are further divided into two in the time direction in the same manner as described in FIG. 8(B).

[0062] Next, the compression circuit 606 performs a predetermined compression process on the data of the divided 4N blocks (step S9).

[0063] Next, the compression circuit 606 determines whether or not the compression process for all 4N divided blocks has been completed (step S10). The compression circuit 606 repeats the predetermined compression process of step S6 until the compression process for all 4N divided blocks has been completed, and if completed, proceeds to the next step.

[0064] Next, the compression circuit 606 selects the uncompressed data and the compression method that provides the smallest data size among the three types of compression methods (step S11).

[0065] Then, the compression circuit 606 ends the process (END). According to the above method, data of the method with the smallest data size is selected from among the plurality of compression patterns, and the selected data is sent to the processor 107.

[0066] This allows even large amounts of signal data to be compressed and transferred efficiently, and also enables high-speed, real-time waveform display.

[0067] In addition, the algorithm for the specified compression process may be a widely used lossless compression algorithm such as ZIP or GZIP, other than the run length algorithm mentioned above, or another lossless compression algorithm that is easy to implement in an integrated circuit.

[0068] FIG. 10 is a diagram illustrating the data size of the method according to the second embodiment and the data size of the method according to the comparative example.

[0069] Referring to FIG. 10, a graph of data size versus the number of state change signals per timestamp when compression processing is performed for every 128 data sets using run-length format is shown.

[0070] When the number of state change signals per timestamp is four or less, the data size can be reduced to 40% or less, making it possible to reduce the data size compared to the VCD format.

[0071] Embodiment 3 The following describes the case where Huffman coding is used as the compression algorithm.

[0072] FIG. 11 is a diagram illustrating the internal configuration of compression circuit 606 according to the third embodiment.

[0073] Referring to FIG. 11, the compression circuit 606 includes an input data scanning unit 1101, an original data SRAM (Static Random Access Memory) 1102, a compressed data SRAM 1106, a write data control unit 1104, a Huffman table SRAM 1103, a read data control unit 1105, a data output control unit 1107, and selectors 1108 and 1109.

[0074] The original data SRAM 1102 temporarily stores one block of signal data from the buffer 105 before compression, and has a two-side bank configuration of side A and side B, with the bank side being switched according to the processing pipeline stage described below.

[0075] The Huffman table SRAM 1103 stores Huffman tables. The write data control unit 1104 creates statistical information such as a decision tree and a histogram from the signal data to be compressed, and updates the Huffman table.

[0076] A read data control unit 1105 reads out a compressed code from the Huffman table SRAM 1103 based on the signal data to be compressed, and outputs the Huffman table data to the processor bus 108 when updating the Huffman table.

[0077] The compressed data SRAM 1106 stores compressed codes and has a two-plane bank configuration of plane A and plane B, and the bank plane is switched according to the processing pipeline stage described later.

[0078] The data output control unit 1107 calculates the amount of compressed data for one block and determines the output data.

[0079] The selector 1108 selects between the original data SRAM 1102 and the compressed data SRAM 1106 as the data to be output to the processor bus 108 .

[0080] A selector 1109 selects the data to be output to the processor bus 108 between the output of the selector 1108 and the Huffman table data.

[0081] Regarding the data compression method of the signal data compression circuit 606 based on the third embodiment, a method of compressing data of each block when the data is divided into N blocks of 8 bits in the division method in the data arrangement direction shown in FIG. 8(A) will be described.

[0082] The division method does not need to be limited to 8-bit units, and division may be performed in units of 4 bits, 16 bits, or other numbers of bits.

[0083] FIG. 12 is a schematic diagram illustrating a method for scanning each block of divided signal data by the input data scanning unit 1101.

[0084] Referring to FIG. 12, each block has a configuration in which an 8-bit data array is arranged for L rows in the time axis direction.

[0085] The input data scanning unit 1101 sequentially takes in 8 bits at a time in L times from top (old data) to bottom (new data) along the time axis, and executes compression processing.

[0086] FIG. 13 is a flowchart illustrating the compression process of each block in compression circuit 606 according to the third embodiment.

[0087] Referring to FIG. 13, when the compression process starts, input data scanning unit 1101 determines whether or not the current block is the first block of the data to be compressed (step S20).

[0088] Next, if the input data scanning unit 1101 determines that the block is the first block (YES in step S20), it instructs the write data control unit 1104 to store an initial Huffman table in the Huffman table SRAM 1103 (step S22).

[0089] On the other hand, if the input data scanning unit 1101 determines that the block is not the first block (NO in step S20), it skips step S22 and proceeds to the next step S24.

[0090] In step S 24 , the input data scanning unit 1101 starts scanning one block of signal data, and stores the signal data before compression in the original data SRAM 1102 .

[0091] Next, the input data scanning unit 1101 determines whether all eight bits of the scanned data are 0 (step S26).

[0092] If the input data scanning unit 1101 determines that all 8 bits are 0 (YES in step S26), it adds +1 to the built-in 0 data counter in the read data control unit 1105 (step S28).

[0093] On the other hand, if the input data scanning unit 1101 determines that not all eight bits are 0 (NO in step S26), it skips step S28 and proceeds to the next step S30.

[0094] Next, in step S30, the write data control unit 1104 updates statistical information such as a histogram based on the scanned 8-bit data.

[0095] Next, the read data control unit 1105 performs a read access using the scanned 8-bit data from the Huffman table SRAM 1103 as an address, and reads out the compressed code (step S32).

[0096] Next, the data output control unit 1107 packs and writes the compressed code output from the read data control unit 1105 into the compressed data SRAM 1106 (step S34).

[0097] Next, the input data scanning unit 1101 determines whether or not scanning of 8-bit signal data has been completed L times (step S36).

[0098] If the input data scanning unit 1101 determines that scanning of 8-bit signal data has not been completed L times (NO in step S36), the process proceeds to step S54, where the input data scanning unit 1101 scans the next 8-bit data sequence, and then proceeds to step S26.

[0099] If the input data scanning unit 1101 determines that it has completed scanning the signal data of 8 bits each up to L times (YES in step S36), it swaps the write and read sides of the two bank surfaces (A / B) of the original data SRAM 1102 and the compressed data SRAM 1106, and adds +1 to the block counter built into the read data control unit 1105 (step S37).

[0100] Next, the read data control unit 1105 determines whether the value of the built-in 0 data counter matches L (step S38).

[0101] If the read data control unit 1105 determines that the value of the 0 data counter matches L (YES in step S38), it outputs the all 0 flag as ON ("1").

[0102] Then, the read data control unit 1105 instructs the data output control unit 1107 to discard one block of compressed data stored in the compressed data SRAM 1106 (step S52), and then the process proceeds to the next step S48.

[0103] On the other hand, if the read data control unit 1105 determines that the value of the built-in 0 data counter does not match L (NO in step S38), it outputs the all 0 flag as OFF ("0") (step S40).

[0104] Next, the data output control unit 1107 determines whether the size of one block of compressed data stored in the compressed data SRAM 1106 is equal to or larger than the size of the signal data before compression (8×L bits) (step S42).

[0105] If the size of one block of compressed data is equal to or larger than the size of the signal data before compression (YES in step S42), the data output control unit 1107 outputs the compression flag as OFF ("0"), and then selects data on the original data SRAM 1102 side according to the selector 1108 and outputs it to the processor bus 108 (step S46).

[0106] On the other hand, if the size of one block of compressed data is less than the size of the signal data before compression (8×L bits) (NO in step S42), the data output control unit 1107 outputs the compression flag as ON ("1"), and accordingly selects data on the compressed data SRAM 1106 side according to the selector 1108, and outputs it to the processor bus 108 (step S44).

[0107] Next, the read data control unit 1105 determines whether the value of the built-in block counter has reached P (step S48). For example, if the data is divided into N units of 8 bits, P=N is set.

[0108] If the read data control unit 1105 determines that the value of the block counter has reached P times (YES in step S48), the write data control unit 1104 updates the Huffman table information stored in the Huffman table SRAM 1103 based on statistical information such as the calculated histogram, outputs the Huffman table data to the processor bus 108 via the selector 1109, and resets the block counter to 0 (step S50).

[0109] On the other hand, if the value of the block counter has not reached P (NO in step S48), the process returns to step S20 and the above processing is repeated, thereby repeatedly executing the compression processing for each block.

[0110] In this example, we have explained the case where an 8-bit data array is divided into N units as an example, but this is not limited to this and the same applies to cases where N blocks are further divided into 2 or 4 blocks.

[0111] FIG. 14 is a diagram illustrating a case where parallel processing is performed on the compression processing according to the third embodiment.

[0112] 14, a case where the process is divided into two pipeline stages for speedup is shown. Specifically, a timing chart for processing consecutive blocks in parallel is shown.

[0113] Specifically, the case where the process of generating compressed codes and the process of outputting data are performed separately in parallel is shown.

[0114] In the first processing time period (between time T1 and time T2), the compressed code generation process of stage 1 is performed on the Mth block.

[0115] First, L pieces of 8-bit data (where L corresponds to the number of rows in the scan shown in FIG. 12) of signal data D-1 to DL are input in accordance with the clock cycle.

[0116] By reading the Huffman table SRAM 1103 using this data as an address, compressed codes H-1 to HL are read out after one cycle.

[0117] Reading of the last compressed code is completed in the (L+1)th cycle of phase M. In the next cycle (L+2 cycle), bank switching is performed, in the next cycle (L+3 cycle), all 0 determination is performed, and in the next cycle (L+4 cycle), compressed data size determination is performed.

[0118] As described above, the number of cycles required for the compressed code generation process is L+4 cycles. In the next processing time period (between time T2 and time T3), the compressed code generation process of stage 1 is performed on the (M+1)th block, and the data output process of stage 2 is performed on the Mth block.

[0119] In stage 2, during the L+4 cycles, a process is executed in which, based on the determination result, compressed data or original data is output to the processor bus 108, or no data is output at all due to an all-0 determination.

[0120] FIG. 15 is a timing chart showing an overview of the compressed code generation process for a plurality of blocks.

[0121] Referring to Figure 15, after the compressed code generation in stage 1 and the data output processing in stage 2 are performed on the Mth block to the M+(P-1)th block (i.e., P blocks), the Huffman table update phase is entered.

[0122] Here, the Huffman table information is updated and output to the processor bus 108. When the Huffman table update phase is completed, the compressed code generation in Stage 1 and the data output process in Stage 2 are repeated for the (M+P)th block to the (M+(2P-1))th block (i.e., P blocks).

[0123] FIG. 16 is a schematic diagram illustrating a Huffman table update processing method in the Huffman table update phase.

[0124] Referring to FIG. 16(A), during P compressed code generation phases, +1 is voted for nodes corresponding to 256 types of signal data corresponding to 8 bits each time the data matches the data input by the input data scanning unit 1101.

[0125] Next, after completing the P compressed code generation phases, the process moves to the Huffman table update phase, where the number of votes for each of the 256 nodes is divided by the total number of votes L x P and converted into an occurrence probability (%).

[0126] Referring to FIG. 16(B), the occurrence probabilities are sorted in descending order. Referring to FIG. 16(C), a Huffman tree is generated based on the sorted data, and a compressed code is generated for each node.

[0127] The generated compressed code is written to the Huffman table SRAM 1103 using the original data corresponding to the corresponding node as an address, and is also output to the processor bus 108 so that the compressed data can be decompressed on the external system side or processor side.

[0128] 17 shows a specific example of a Huffman table according to the third embodiment. The left column shows the original 8-bit data, and the right column shows the probability of occurrence. This example shows a case where 11 types of 8-bit data exist in a given block to be compressed.

[0129] 17, the center column shows the Huffman codes derived by calculating a decision tree based on the occurrence probability of each element. Codes are assigned in descending order of occurrence probability: 0, 10, 110, ...

[0130] The code compression rate when using the Huffman table is S i (bit), the occurrence probability of the i-th bit is P i (%), it can be expressed by the following formula: where N is the total number of types of 8-bit data that appear.

[0131]

number

[0132] The compression ratio in the case of the Huffman table shown in FIG. 17 is calculated as follows using the above formula:

[0133] (1×40.0%+2×25.0%+3×17.0%+4×8.5%+5×5.0%+6×2.0%+7×1.0%+8×0.7%+9×0.5%+10×0.2%+10×0.1%) / 8=29.03% From the above calculation results, it is possible to compress the data to approximately 29% of the original data size by using Huffman coding.

[0134] The Huffman table SRAM 1103 that stores the Huffman tables only needs to reserve 256 addresses, so it does not need to be placed in external memory and can be implemented in a small area as SRAM on the LSI. Implementing it in the LSI's built-in SRAM also enables cycle-based reference, which reduces access latency and enables high-speed Huffman encoding compared to implementing the Huffman tables in external memory such as DRAM.

[0135] FIG. 18 is a diagram illustrating an integrated circuit according to another embodiment. 18, integrated circuit 2 differs from integrated circuit 1# in that it additionally includes a second buffer 1801. As the other configurations are similar to those described in FIG. 7, detailed description thereof will not be repeated.

[0136] Logic analyzer circuit 1802 further includes a second buffer 1801 for temporarily holding the compressed data compared with logic analyzer circuit 603#.

[0137] Compression circuit 606 reads out the data group (multiple signal data sets) stored in buffer 105# at an earlier timing and stores the compressed data in second buffer 1801 before a read request is issued from the processor. This allows the size of buffer 105# to be smaller than that of logic analyzer circuit 603#, and because second buffer 1801 stores compressed data, the size of second buffer 1801 can also be reduced. The combined size of buffer 105# and second buffer 1801 can be smaller than the size of buffer 105 of logic analyzer circuit 603#, making it possible to efficiently use the size of memory used for buffers.

[0138] Furthermore, the data compressed by the compression circuit 606 may be decompressed by the processor 107 built into the integrated circuit 2, converted into a general-purpose data format such as VCD (Value Change Dump), and supplied to the external system 109 via the external bus 110. This method reduces the amount of data transferred on the processor bus and enables data to be supplied to the external system in a general-purpose data format.

[0139] The configurations exemplified as the above-described embodiments are examples of the configurations of the present disclosure, and may be combined with other known technologies, or may be modified, such as by omitting some parts, within the scope of the gist of the present disclosure. Furthermore, the above-described embodiments may be implemented by appropriately adopting the processes and configurations described in other embodiments.

[0140] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0141] 1 Integrated circuit, 2 Debugger, 5 Display, 101 Observed circuit, 102 Observed signal, 103, 1802 Logic analyzer circuit, 104 Trace capture circuit, 105 Buffer, 107 Processor, 108 Processor bus, 109 External system, 110 External bus, 201 Signal data set, 202, 402 Time stamp, 203 State change data, 606 Compression circuit, 1101 Input data scan unit, 1102 Original data SRAM, 1103 Huffman table SRAM, 1104 Write data control unit, 1105 Read data control unit, 1106 Compressed data SRAM, 1107 Data output control unit, 1108, 1109 Selector, 1801 Second buffer.

Claims

1. a trace capture circuit that acquires N signals to be observed from the circuit to be observed when a change occurs in at least one of the N signals to be observed; a buffer for storing signal data acquired by the trace capture circuit; a compression circuit for compressing the plurality of pieces of signal data stored in the buffer; The signal data is A timestamp of M bits in width indicating the time of acquisition; N-bit width state change data respectively corresponding to the values ​​of the N observation target signals, the signal data is binary format data with a fixed length of (M+N) bits, The compression circuit divides the signal data into a plurality of blocks, compresses each block of data obtained by the division into a plurality of patterns, selects a compression with a small data size from the compression process results of the plurality of patterns, and processes the compression process and the output process of the selected compressed data in parallel.

2. The compression circuit a first memory for storing signal data of each block obtained by division; an input data scanning unit that scans the signal data; Huffman tables, a write data control unit that initializes and updates the Huffman table; a read data control unit that reads a compressed code from the Huffman table based on the signal data; a second memory for storing the compressed code; a data output control unit that outputs data from either the first or second memory; 2. The logic analyzer circuit according to claim 1, wherein said first and second memories are configured as a plurality of banks, and the bank planes are switched every predetermined cycle to execute the processing of the compressed code generation stage and the processing of the data output processing stage.

3. 3. The logic analyzer circuit of claim 2, wherein the Huffman table is implemented using static random access memory (SRAM).

4. 3. The logic analyzer circuit according to claim 2, wherein said write data control unit creates statistical information of a decision tree or a histogram obtained as a result of scanning said signal data by said input data scanning unit, and updates said Huffman table.

5. the read data control unit determines whether the signal data of each block is all 0; the data output control unit does not output the data when the signal data is all 0 as a result of the determination by the read data control unit, 3. The logic analyzer circuit according to claim 2, wherein said data output control unit calculates the amount of data of said compressed code corresponding to each of said blocks when said signal data is not all 0 as a result of determination by said read data control unit, and outputs data of either said first or second memory based on the calculation result.

6. 2. The logic analyzer circuit of claim 1, further comprising another buffer for storing the signal data compressed by said compression circuit.

7. 10. An integrated circuit comprising: a logic analyzer circuit according to claim 1; and a processor for decompressing the compressed signal data output by the compression circuit of the logic analyzer circuit.

8. a circuit to be observed; a logic analyzer circuit for monitoring a target signal of the target circuit; a processor connected to the logic analyzer circuit and configured to transfer data to an external device; The logic analyzer circuit a trace capture circuit for acquiring N signals to be observed when a change occurs in at least one of the N signals to be observed from the circuit to be observed; a buffer for storing signal data acquired by the trace capture circuit; a compression circuit for compressing the plurality of pieces of signal data stored in the buffer, The signal data is A timestamp of M bits in width indicating the time of acquisition; N-bit state change data indicating the value of the observation target signal; the signal data is binary format data with a fixed length of (M+N) bits, The compression circuit is an integrated circuit that divides the signal data into a plurality of blocks, compresses each block of data obtained by the division into a plurality of patterns, selects a compression with a small data size from the compression process results of the plurality of patterns, and processes the compression process and the output process of the selected compressed data in parallel.

9. 9. The integrated circuit according to claim 8, further comprising a processor bus for transmitting and receiving data between the logic analyzer circuit and the processor.

10. an integrated circuit; an external bus for connecting to the integrated circuit; an external device that transmits and receives data to and from the integrated circuit via the external bus; The integrated circuit comprises: a circuit to be observed; a logic analyzer circuit for monitoring a target signal of the target circuit; a processor connected to the logic analyzer circuit and configured to transfer data to the external device via the external bus; The logic analyzer circuit a trace capture circuit for acquiring N signals to be observed when a change occurs in at least one of the N signals to be observed from the circuit to be observed; a buffer for storing signal data acquired by the trace capture circuit; a compression circuit for compressing the plurality of pieces of signal data stored in the buffer; The signal data is A timestamp of M bits in width indicating the time of acquisition; N-bit state change data indicating the value of the observation target signal; the signal data is binary format data with a fixed length of (M+N) bits, The compression circuit divides the signal data into a plurality of blocks, compresses each of the block data obtained by the division into a plurality of patterns, selects a compression with a small data size from the compression process results of the plurality of patterns, and performs the compression process and the output process of the selected compressed data in parallel.

11. acquiring N signals to be observed from the circuit to be observed when a change occurs in at least one of the N signals to be observed; storing the acquired signal data; and compressing the stored signal data. The signal data is A timestamp of M bits in width indicating the time of acquisition; N-bit width state change data respectively corresponding to the values ​​of the N observation target signals, the signal data is binary format data with a fixed length of (M+N) bits, The compressing step includes: Dividing the signal data into a plurality of pieces; a step of compressing each block data obtained by the division into a plurality of patterns of numbers; selecting a compression with a small data size from among the plurality of patterns of compression processing results, The method further comprises the step of performing the compression process and the output process of the selected compressed data in parallel.

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