Integrated circuit and power supply circuit

Abstract

To provide an integrated circuit that appropriately controls a transistor of a power supply circuit depending on a load state.SOLUTION: An integrated circuit 32 drives a transistor of a power supply circuit, the power supply circuit generating a predetermined level of output voltage to a load from an input voltage and including a transformer that includes a primary coil, a secondary coil, and an auxiliary coil and the transistor that controls a current flowing through the primary coil. The integrated circuit comprises: a first determination circuit (a control circuit 40) that determines whether the load is heavy or light; a second determination circuit that determines whether a mode is a continuous mode in which a current of the secondary coil does not become zero or a discontinuous mode in which the current of the secondary coil becomes zero when the transistor is in an off-state; an oscillation circuit 43; and a switching control circuit 44. The switching control circuit, when the load is in a light-load state, controls switching of the transistor on the basis of the determination result of the second determination circuit and an oscillation signal, and when the load is in a heavy-load state, controls switching of the transistor on the basis of the oscillation signal irrespective of the determination result of the second determination circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power supply circuit. [Background technology]

[0002] There are integrated circuits that control a flyback AC-DC converter based on an inductor current and a feedback voltage corresponding to an output voltage (for example, Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5601158 [Patent Document 2] U.S. Patent No. 10,056,842 [Patent Document 3] U.S. Patent No. 10,355,606 [Patent Document 4] Patent No. 3412624 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, an AC-DC converter is provided with a control circuit that controls the operation of the AC-DC converter. The control circuit is required to appropriately control the transistors of the AC-DC converter according to the load state.

[0005] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide an integrated circuit that appropriately controls transistors in a power supply circuit according to the load state. [Means for solving the problem]

[0006] The integrated circuit of a first aspect of the present invention that solves the above-mentioned problems includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls the current flowing through the primary coil, and is an integrated circuit that drives the transistor of a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, and is equipped with a first determination circuit that determines whether the load state is heavy load or light load, a second determination circuit that determines whether the load state is a continuous mode in which the current in the secondary coil does not become zero when the transistor is off, or a discontinuous mode in which the current in the secondary coil becomes zero when the transistor is off, an oscillation circuit that outputs an oscillation signal, and a switching control circuit that, when the load state is light load, controls the switching of the transistor based on the determination result of the second determination circuit and the oscillation signal, and when the load state is heavy load, controls the switching of the transistor based on the oscillation signal regardless of the determination result of the second determination circuit.

[0007] The integrated circuit of a second aspect of the present invention that solves the above-mentioned problems includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls a current flowing through the primary coil, and is an integrated circuit that drives the transistor of a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, and includes a first comparison circuit that compares a first voltage corresponding to a voltage on the high potential side of the transistor with a second voltage, an oscillation circuit that outputs an oscillation signal, and a switching control circuit that controls switching of the transistor, and the switching control circuit controls the secondary coil when the transistor is off. an on-signal output circuit that outputs an on-signal for turning on the transistor after the oscillation signal is input and the first number of times at which the first voltage becomes the second voltage becomes a reference number when the current through the load is zero, an off-signal output circuit that outputs an off-signal for turning off the transistor based on the current flowing through the transistor, a first holding circuit that holds the reference number of times, and an adjustment circuit that increases the reference number of times under a first condition when the load current flowing through the load decreases and decreases the reference number of times under a second condition that is stricter than the first condition when the load current increases.

[0008] A first aspect of the power supply circuit of the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, and includes: a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor that controls the current flowing through the primary coil; and an integrated circuit that drives the transistor. The integrated circuit includes a first determination circuit that determines whether the load state is heavy or light; a second determination circuit that determines whether the load state is a continuous mode in which the current in the secondary coil does not become zero when the transistor is off, or a discontinuous mode in which the current in the secondary coil becomes zero when the transistor is off; an oscillation circuit that outputs an oscillation signal; and a switching control circuit that, when the load state is light, controls the switching of the transistor based on the determination result of the second determination circuit and the oscillation signal, and when the load state is heavy, controls the switching of the transistor based on the oscillation signal regardless of the determination result of the second determination circuit.

[0009] A power supply circuit according to a second aspect of the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, and includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, a transistor that controls a current flowing through the primary coil, and an integrated circuit that drives the transistor, wherein the integrated circuit includes a first comparison circuit that compares a first voltage corresponding to a voltage on the high potential side of the transistor with a second voltage, an oscillation circuit that outputs an oscillation signal, and a switching control circuit that controls switching of the transistor, and wherein the switching control circuit The inverter includes an on signal output circuit that outputs an on signal to turn on the transistor after the oscillation signal is input and the first number of times the first voltage becomes the second voltage becomes a reference number when the current in the secondary coil is zero, an off signal output circuit that outputs an off signal to turn off the transistor based on the current flowing through the transistor, a first holding circuit that holds the reference number, and an adjustment circuit that increases the reference number under a first condition when the load current flowing through the load decreases and decreases the reference number under a second condition that is stricter than the first condition when the load current increases. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that appropriately controls transistors in a power supply circuit according to the load state. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an example of the configuration of an AC-DC converter 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 32. [Figure 3] 4 is a diagram for explaining control of a bottom switch circuit 50 by a control circuit 40. FIG. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of an oscillator circuit 43. [Figure 5]10 is a diagram showing an example of the relationship between a feedback voltage Vfb, a bias current Ib, and an oscillation frequency Fsw. FIG. [Figure 6] 10 is a diagram showing an example of a timing chart illustrating the operation of the AC-DC converter 10 and the control IC 32 when they are continuously operating in a "disconnected state." [Figure 7] 10 is a diagram showing an example of a timing chart illustrating the operation of the AC-DC converter 10 when it operates discontinuously in a "disconnected state." [Figure 8] 2 is a diagram illustrating an example of the configuration of an AC-DC converter 12. FIG. [Figure 9] FIG. 10 is a diagram showing an example of a timing chart illustrating the operations of the AC-DC converter 12 and the control IC 32 in "continuous operation." [Figure 10] 10 is a diagram showing an example of a timing chart illustrating a malfunction of the overcurrent protection circuit 54. FIG. [Figure 11] 10 is a diagram showing an example of a timing chart illustrating an operation of suppressing a malfunction of the overcurrent protection circuit 54 by the timer 55. FIG. [Figure 12] 10 is a diagram showing an example of a timing chart illustrating an operation of suppressing a malfunction of the overcurrent protection circuit 54 by the timer 55. FIG. [Figure 13] FIG. 2 is a diagram showing an example of the configuration of a bottom switch circuit 50. [Figure 14] FIG. 2 is a diagram showing an example of the configuration of a bottom controller 93. [Figure 15] 10 is a diagram showing the timing at which the output circuit 111 outputs the signal out0. FIG. [Figure 16] FIG. 10 is a diagram showing an example of a timing chart illustrating the operation of AC-DC converter 12 in "discontinuous operation." [Figure 17] FIG. 10 is a timing chart showing an example of the operation of the control IC 32 when the oscillation frequency Fsw decreases in "discontinuous operation." [Figure 18] FIG. 10 is a timing chart showing an example of the operation of the control IC 32 when the oscillation frequency Fsw increases in the "discontinuous operation." [Figure 19]It is a diagram showing an example of the configuration of the generation circuit 114. [Figure 20] It is a diagram showing an example of the configuration of the timers 121 and 122. [Figure 21] It is a diagram showing an example of a timing chart illustrating the operation of the generation circuit 114 when the bottom can be detected in "discontinuous operation". [Figure 22] It is a diagram showing an example of a timing chart illustrating the operation of the generation circuit 114 when the bottom cannot be detected in "discontinuous operation".

Embodiments for Carrying Out the Invention

[0012] From the description in this specification and the attached drawings, at least the following matters become clear. =====This Embodiment===== FIG. 1 is a diagram showing an example of the configuration of an AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a flyback power supply circuit that generates an output voltage Vout of a predetermined level from the AC voltage Vac of a commercial power supply.

[0013] <<<Overview of the AC-DC Converter 10>>> The AC-DC converter 10 includes a full-wave rectifier circuit 20, capacitors 21 and 25, a transformer 22, a control block 23, diodes 24 and D1, a constant voltage circuit 26, a light-emitting diode 27, a resistor R1, and a capacitor C1. And the AC-DC converter 10 supplies power to the load 11.

[0014] The full-wave rectifier circuit 20 full-wave rectifies a predetermined AC voltage Vac, which is the input voltage, and outputs it as a voltage Vrec to the primary coil L1 of the transformer 22 and the capacitor 21. Also, the capacitor 21 smoothes the voltage Vrec. Note that the AC voltage Vac is, for example, a voltage with an effective value of 100 to 240V and a frequency of 50 to 60Hz.

[0015] The transformer 22 has a primary coil L1 provided on the input side, and a secondary coil L2 and an auxiliary coil L3 magnetically coupled to the primary coil L1. The secondary coil L2 and the auxiliary coil L3 are wound so that the voltage generated in the secondary coil L2 and the auxiliary coil L3 has the opposite polarity to the voltage generated in the primary coil L1. The primary coil L1 and the auxiliary coil L3 are provided on the input side (primary side), and the secondary coil L2 is provided on the output side (secondary side).

[0016] The control block 23 controls the voltage generated in the secondary coil L2 on the secondary side of the transformer 22 by controlling the inductor current IL1 flowing through the primary coil L1 on the primary side of the transformer 22. As a result, an output voltage Vout of a target level is generated on the secondary side of the transformer 22.

[0017] The diode 24 rectifies the inductor current IL2 from the secondary coil L2 of the transformer 22 and supplies the rectified current to the capacitor 25. The capacitor 25 is charged by the current from the diode 24, and an output voltage Vout is generated across the terminals of the capacitor 25.

[0018] The constant voltage circuit 26 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

[0019] The light-emitting diode 27 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 26, and forms a photocoupler together with a phototransistor 39, which will be described later. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light emitted from the light-emitting diode 27 increases.

[0020] The resistor R1, capacitor C1, and diode D1 constitute a snubber circuit. The snubber circuit suppresses surge voltages generated by leakage inductance of the primary coil L1 when the power transistor 30 is turned off, thereby preventing breakdown of the power transistor 30. The snubber circuit is connected in parallel with the primary coil L1. The anode of the diode D1 is connected to the high-potential side of the power transistor 30 (described later), and the cathode is connected to the resistor R1. The capacitor C1 is connected in parallel with the resistor R1.

[0021] The load 11 is a load connected to the AC-DC converter 10, and the output voltage Vout is applied to the load 11. The current flowing through the load 11 is referred to as a load current Iout.

[0022] <<<Overview of Control Block 23>>> The control block 23 is a circuit block for controlling the AC-DC converter 10. The control block 23 includes a power transistor 30, resistors 31, 34, and 37, a control IC 32, capacitors 33, 35, and 38, a diode 36, and a phototransistor 39.

[0023] The power transistor 30 is an NMOS transistor for controlling the power supplied to the load 11. In this embodiment, the power transistor 30 is a MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. The power transistor 30 may be, for example, a bipolar transistor, etc., as long as it is a transistor that can control power. Furthermore, the voltage on the high potential side of the power transistor 30 is defined as voltage Vx.

[0024] The resistor 31 is a resistor for detecting an inductor current IL1 (i.e., a current flowing through the power transistor 30) that flows through the primary coil L1 when the power transistor 30 is on. One end of the resistor 31 is connected to the source electrode of the power transistor 30, and the other end is grounded.

[0025] The control IC 32 is an integrated circuit that controls the switching of the power transistor 30 so that the level of the output voltage Vout becomes a target level. Specifically, the control IC 32 drives the power transistor 30 based on the inductor current IL1 and the output voltage Vout.

[0026] The control IC 32 is provided with terminals CS, FB, OUT, and VCC, the details of which will be described later. The gate electrode of the power transistor 30 is connected to the terminal OUT, and the power transistor 30 is driven by a drive voltage Vg. The actual control IC 32 is also provided with other terminals, but these are omitted for convenience of explanation.

[0027] Capacitor 33 is provided between terminal CS and ground, and the voltage across resistor 31 generated by the flow of inductor current IL1 is applied via resistor 34. Capacitor 33 and resistor 34 form a low-pass filter, stabilizing voltage Vcs at terminal CS.

[0028] A capacitor 38 is provided between the terminal FB and ground to stabilize the voltage Vfb at the terminal FB. The voltage Vfb is a feedback voltage corresponding to the output voltage Vout and is applied to the terminal FB. As will be described in detail later, the control IC 32 turns on the power transistor 30 at a frequency corresponding to the voltage Vfb. If the voltage Vcs exceeds the voltage Vfb while the power transistor 30 is on, the control IC 32 turns off the power transistor 30.

[0029] In reality, the control IC 32 turns off the power transistor 30 when the voltage Vcs exceeds k times the voltage Vfb (where k is 1 or less). Hereinafter, the same applies to the parts where it has been explained that the voltage Vcs exceeds the voltage Vfb or that the voltage Vcs becomes the voltage Vfb.

[0030] The phototransistor 39 is provided between the terminal FB and ground and receives light from the light-emitting diode 27. Furthermore, when the intensity of the light emitted by the light-emitting diode 27 increases, the phototransistor 39 causes a larger sink current Ia to flow through the terminal FB.

[0031] The capacitor 35 is provided between the terminal VCC and the ground. The anode of the diode 36 is connected to the auxiliary coil L3, and the cathode is connected via the resistor 37 to the terminal VCC.

[0032] Furthermore, the voltage Va generated in the auxiliary coil L3 is applied to the capacitor 35 via the diode 36 and resistor 37, and the voltage of the capacitor 35 becomes the power supply voltage Vcc of the control IC 32. When the power transistor 30 is off, a voltage corresponding to the voltage Va of the auxiliary coil L3 is generated in the capacitor 35 at the terminal VCC, and the voltage of the capacitor 35 is applied as the power supply voltage Vcc.

[0033] <<<Control IC32 Configuration>>> 2 is a diagram showing an example of the configuration of the control IC 32. The control IC 32 includes a control circuit 40, a hysteresis comparator 41, a resistor 42, an oscillation circuit 43, and a switching control circuit 44.

[0034] <<<Control Circuit 40 and Bottom Switch Circuit 50>>> A bottom switch circuit 50 (described later) outputs a pulse signal pwm_s that turns on the power transistor 30 based on a signal output from the control circuit 40 and an output from the hysteresis comparator 41 .

[0035] As will be described in detail later, the internal state of the bottom switch circuit 50 is reset based on the signal crst0 from the control circuit 40. Furthermore, the bottom switch circuit 50 changes the mode in which it outputs a pulse signal pwm_s having a predetermined minimum on-width based on the signals btm_cmp and crst1. Note that here, a detailed circuit configuration of the bottom switch circuit 50 will be described below, giving an overview of the operation of the bottom switch circuit 50.

[0036] The control circuit 40, together with the hysteresis comparator 41, controls the bottom switch circuit 50 as shown in Fig. 3. In this embodiment, the operation of the bottom switch circuit 50 is divided into an operation when conditions A1 to A3 are met and an operation when condition A4 is met. The cases where conditions A1 to A4 are met will be described in detail below.

[0037] <<Condition A1>> Condition A1 is met when the AC-DC converter 10 and a later-described AC-DC converter 12 are started up. At this time, a soft start circuit (SS) described later outputs a signal ss_end at an “L” level, and the hysteresis comparator 41 always outputs a signal btm_cmp at an “L” level.

[0038] In this case, since the AC-DC converters 10 and 12 are in operation, the bottom switch circuit 50 outputs the pulse signal pwm_s when the pulse signal osc_out is input.

[0039] <<Condition A2>> Condition A2 is satisfied when the AC-DC converter 10 is in a steady state with no external circuit connected to the terminal CS. In this state, the soft start circuit outputs a high-level signal ss_end, but the hysteresis comparator 41 always outputs a low-level signal btm_cmp.

[0040] In this case, the hysteresis comparator 41 does not detect oscillation of the voltage Vcs, and therefore, similarly to the case of condition A1, the bottom switch circuit 50 outputs the pulse signal pwm_s when the pulse signal osc_out is input.

[0041] <<Condition A3>> Condition A3 is also satisfied when the load 11 is heavy during steady-state operation of the AC-DC converter 12 (described later) with a predetermined external circuit connected to the terminal CS. In this case, when the power transistor 30 is on, the hysteresis comparator 41 outputs the signal btm_cmp at an "L" level. On the other hand, when the power transistor 30 is off, the hysteresis comparator 41 always outputs the signal btm_cmp at an "H" level.

[0042] As will be described in more detail later, in this embodiment, even in this case, the hysteresis comparator 41 does not detect oscillations in the voltage Vcs, so that the bottom switch circuit 50 outputs a pulse signal pwm_s when the pulse signal osc_out is input, as in the case of condition A2.

[0043] <<Condition A4>> Condition A4 is also satisfied when the load 11 is lightly loaded during steady state operation of the AC-DC converter 12 (described later) with a predetermined external circuit connected to the terminal CS. In this case, when the power transistor 30 is off, the hysteresis comparator 41 outputs the signal btm_cmp at an “H” level.

[0044] In this case, the hysteresis comparator 41 may detect oscillations in the voltage Vcs. Therefore, unlike the cases of conditions A1 to A3, the bottom switch circuit 50 may not immediately output the pulse signal pwm_s even if the pulse signal osc_out is input. In other words, the bottom switch circuit 50 may output the pulse signal pwm_s in response to oscillations in the voltage Vcs.

[0045] That is, under condition A4, the operation of the bottom switch circuit 50 may differ depending on the operation of the AC-DC converter 12. Specifically, if the AC-DC converter 12 is operating continuously, the bottom switch circuit 50 outputs a pulse signal pwm_s when the pulse signal osc_out is input. In this case, when the power transistor 30 is on, the hysteresis comparator 41 outputs a signal btm_cmp at an "L" level. On the other hand, when the power transistor 30 is off, the hysteresis comparator 41 always outputs a signal btm_cmp at an "H" level.

[0046] On the other hand, if the AC-DC converter 12 is operating discontinuously, the bottom switch circuit 50 outputs the signal btm_cmp at "L" level after the pulse signal osc_out is input, and then outputs pwm_s at a predetermined timing. In this case, when the power transistor 30 is on, the hysteresis comparator 41 outputs the signal btm_cmp at "L" level. When the power transistor 30 is off, the hysteresis comparator 41 outputs the signal btm_cmp at "H" level or "L" level depending on the fluctuation of the voltage Vcs.

[0047] Next, the operation of the control circuit 40 will be described. The control circuit 40 changes the signals crst0 and crst1 in accordance with the signals ss_end, Vpg, and voltage Vfb. Specifically, the control circuit 40 outputs the signal crst0 that resets the internal circuit of the bottom switch circuit 50 in order to control the bottom switch circuit 50, as described above.

[0048] In addition, when the load 11 is in a heavy load state, as in the case of condition A3, and the pulse signal osc_out is input, the control circuit 40 outputs an “H” level signal crst1 that causes the bottom switch circuit 50 to output a pulse signal pwm_s.

[0049] On the other hand, when the load 11 is in a light load state, as in the case of condition A4, the control circuit 40 outputs an “L” level signal crst1 that causes the bottom switch circuit 50 to output a pulse signal pwm_s in accordance with the operation of the AC-DC converter 12.

[0050] As a result, when the load 11 is in a heavy load state, the oscillation circuit 43 outputs the pulse signal osc_out, and the bottom switch circuit 50 can turn on the power transistor 30 regardless of the voltage Vx. The bottom switch circuit 50 changes its operating state depending on the logic level of the input signal, and the detailed circuit configuration of the bottom switch circuit 50 will be described later. The control circuit 40 corresponds to a "first determination circuit."

[0051] <<<Hysteresis Comparator 41>>> The hysteresis comparator 41, together with some circuits of the bottom switch circuit 50 described later, detects whether a predetermined external circuit is connected between the terminal CS and the auxiliary coil L3. Specifically, the hysteresis comparator 41 detects whether the above-mentioned predetermined external circuit (described in detail later) is being used by detecting the voltage Vcs when the power transistor 30 is turned off.

[0052] Furthermore, when a predetermined external circuit is used, the hysteresis comparator 41 is used to detect whether the current flowing through the primary coil L1 and the secondary coil L2 is continuous or discontinuous. As will be described in detail later, the hysteresis comparator 41 detects the voltage Vcs when the power transistor 30 is turned off, thereby detecting that oscillations corresponding to the voltage Vx occur in the voltage Vcs when the current is discontinuous. The hysteresis comparator 41 generates, from a reference voltage Vref0, a threshold voltage VrefH for detecting whether a predetermined external circuit is connected and a voltage VrefL for detecting whether the current is continuous or discontinuous. In this embodiment, the threshold voltage VrefH is higher than the threshold voltage VrefL.

[0053] Specifically, the hysteresis comparator 41 operates when the control circuit 40 (described later) outputs a signal crst0 at an "L" level while the power transistor 30 is off.

[0054] Furthermore, if a predetermined external circuit is connected to the terminal CS of the control IC 32, the voltage Vcs becomes higher than the threshold voltage VrefH when the power transistor 30 is off. Therefore, when the voltage Vcs is higher than the threshold voltage VrefH, the hysteresis comparator 41 outputs the signal btm_cmp at an "H" level. At this time, the hysteresis comparator 41 can detect that a predetermined external circuit is connected to the terminal CS.

[0055] On the other hand, when the control IC 32 is used in the AC-DC converter 10 and a predetermined external circuit is not connected to the terminal CS, the voltage Vcs becomes the ground voltage when the power transistor 30 is off. Therefore, when the voltage Vcs is lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level. At this time, the hysteresis comparator 41 can detect that the control IC 32 is used in the AC-DC converter 10. Note that when the signal crst0 is at the "H" level, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level.

[0056] Furthermore, as will be described in detail later, when a predetermined external circuit is connected to the terminal CS and, for example, the current in the secondary coil L2 becomes discontinuous (zero), the voltage Vcs oscillates in accordance with the oscillation of the voltage Vx. At this time, the hysteresis comparator 41 detects that the voltage Vcs falls below the threshold voltage VrefL and can detect that the voltage Vx is oscillating. This allows the hysteresis comparator 41 to detect whether the voltage Vcs oscillates while the power transistor 30 is off. Furthermore, how the control IC 32 operates depending on whether oscillation of the voltage Vcs is detected will be described later.

[0057] The hysteresis comparator 41 corresponds to a “comparison circuit” or a “first comparison circuit,” the voltage Vcs corresponds to a “first voltage,” and the threshold voltage VrefL corresponds to a “second voltage.” Furthermore, the signal btm_cmp corresponds to a “comparison result.”

[0058] Furthermore, as will be described in detail later, when the control IC 32 is used in an AC-DC converter 12 (described later) including an external circuit, the hysteresis comparator 41 outputs a signal btm_cmp of "H" level and the control IC 32 operates in a "connected state." On the other hand, when the control IC 32 is used in the AC-DC converter 10 of Fig. 1, the hysteresis comparator 41 outputs a signal btm_cmp of "L" level and the control IC 32 operates in a "disconnected state."

[0059] This allows the control IC 32 to determine, based on the detection result of the hysteresis comparator 41, whether the control IC 32 operates in a "disconnected state" in which a specified external circuit is not connected to the terminal CS, or whether the control IC 32 operates in a "connected state" in which a specified external circuit is connected to the terminal CS.

[0060] When the control IC 32 is used in the AC-DC converter 10, the control IC 32 operates in a "disconnected state." Here, the "disconnected state" refers to a state in which the voltage Vcs does not change according to the voltage Vx when the power transistor 30 is off. The "connected state" will be described in detail later.

[0061] The resistor 42 is provided between the node to which the internal voltage Vdd generated from the power supply voltage Vcc is applied and the terminal FB, and generates a voltage Vfb corresponding to the sink current Ia flowing from the phototransistor 39.

[0062] In this embodiment, when the load 11 is in a heavy load state and the output voltage Vout decreases, the sink current Ia decreases. As a result, the voltage Vfb increases. On the other hand, when the load 11 is in a light load state and the output voltage Vout increases, the sink current Ia increases. As a result, the voltage Vfb decreases. Note that "the load 11 is in a heavy load state" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is greater than a predetermined value (for example, 5 A). Note also that "the load 11 is in a light load state" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is smaller than a predetermined value (for example, 5 A).

[0063] <<<Configuration and Operation of Oscillator Circuit 43>>> The oscillator circuit 43 outputs a pulse signal оsc_out having a frequency Fsw according to the voltage Vfb. Specifically, the oscillator circuit 43 outputs a pulse signal оsc_out having a frequency ranging from Fsw0 to Fsw1, which is higher than the frequency Fsw0, according to the voltage Vfb. The pulse signal osc_out corresponds to an "oscillation signal."

[0064] As will be described in detail later, when a pulse signal pwm_s that turns on the power transistor 30 is input, the oscillator circuit 43 outputs a pulse signal osc_out at a timing when an oscillation period corresponding to the frequency Fsw has elapsed since the input of the pulse signal pwm_s. The oscillation period corresponds to "a period corresponding to the frequency of the oscillation signal."

[0065] 4 is a diagram showing an example of the configuration of the oscillator circuit 43, and FIG. 5 is a diagram showing an example of the relationship between the feedback voltage Vfb, the current Ib, and the oscillation frequency Fsw. The oscillator circuit 43 is configured to include current sources 70 and 71, switches 72 and 73, a capacitor 74, a comparator 75, a delay circuit 76, an OR element 77, and an inverter 78.

[0066] Current source 70 receives the internal voltage Vdd and supplies a constant current Ib0. Current source 71 also receives the internal voltage Vdd and supplies a current Ibx corresponding to the voltage Vfb. Note that current Ib is the sum of constant current Ib0 and current Ibx.

[0067] When the voltage Vfb is lower than Vfba, the current source 71 does not supply the current Ibx. When the voltage Vfb is higher than Vfba but lower than Vfbb, the current source 71 supplies the current Ibx that increases according to the voltage Vfb. When the voltage Vfb is higher than Vfbb, the current source 71 supplies a predetermined current as the current Ibx.

[0068] Therefore, as shown in FIG. 5, when the voltage Vfb is lower than Vfba, the current Ib becomes a constant current Ib0, and when the voltage Vfb is higher than Vfba and lower than Vfbb, the current Ibx increases according to the voltage Vfb, thereby increasing the current Ibx.

[0069] Furthermore, when the voltage Vfb becomes higher than Vfbb, the current Ib becomes a current Ib1, which is a constant current value, as the current Ibx becomes a predetermined current.

[0070] Switching between switches 72 and 73 charges and discharges capacitor 74. When switch 72 is turned on, capacitor 74 is charged with current Ib. On the other hand, when switch 73 is turned on, capacitor 74 is discharged.

[0071] The comparator 75 operates to output a pulse signal оsc_оut by comparing the voltage saw of the capacitor 74 with a reference voltage Vref1. Specifically, when the switch 72 is turned on, the capacitor 74 is charged with a current Ib, and the voltage saw rises. When the voltage saw reaches the reference voltage Vref1, the comparator 75 outputs an "H" level signal.

[0072] The delay circuit 76 then delays the signal from the comparator 75 by a predetermined time and outputs the delayed signal. Therefore, when the comparator 75 outputs an "H" level signal, the delay circuit 76 outputs an "H" level signal after a predetermined time.

[0073] The OR element 77 performs a logical OR operation on the signal from the delay circuit 76 and the pulse signal pwm_s, and switches the switch 73. Specifically, when the delay circuit 76 outputs an "H" level signal, the OR element 77 turns on the switch 73 and discharges the capacitor 74. At this time, the switch 72 turns off. Therefore, the voltage saw becomes the ground voltage.

[0074] When the voltage saw drops and becomes lower than the reference voltage Vref1, the comparator 75 outputs a signal at the “L” level. Therefore, when the switch 72 is turned on and an oscillation period has elapsed, that is, when the voltage saw becomes the reference voltage Vref1, the comparator 75 outputs a pulse signal osc_out that becomes the “H” level for a certain period of time.

[0075] As a result, the oscillator circuit 43 outputs a pulse signal оsc_оut having an oscillation frequency corresponding to the oscillation period, i.e., the voltage Vfb. When the comparator 75 outputs the pulse signal оsc_оut at the "L" level, the signal from the delay circuit 76 becomes "L" level and the inverter 78 outputs a "H" level signal, turning the switch 72 on.

[0076] Furthermore, when the pulse signal pwm_s is input, the OR element 77 turns on the switch 73 and discharges the capacitor 74. At this time, the switch 72 remains on. Therefore, the voltage saw temporarily reaches the ground voltage and then rises. Therefore, the oscillator circuit 43 synchronizes and restarts measurement of the oscillation period every time the power transistor 30 turns on before the oscillation period has elapsed. That is, when the pulse signal pwm_s is input, the oscillator circuit 43 outputs the pulse signal osc_out at the timing when the oscillation period corresponding to the frequency Fsw has elapsed since the pulse signal pwm_s was input.

[0077] The oscillation period of the oscillation circuit 43 is the period from when the switch 72 is turned on until the comparator 75 outputs the high-level pulse signal оsc_оut, and is determined by the value of the current Ib according to the voltage Vfb. That is, the oscillation period becomes shorter as the current Ib increases, and becomes longer as the current Ib decreases.

[0078] Therefore, when the load 11 is in a heavy load state, the oscillation period becomes shorter, and when the load 11 is in a light load state, the oscillation period becomes longer. Here, when the load 11 is in a heavy load state, the load current Iout is larger than a predetermined value, whereas when the load 11 is in a light load state, the load current Iout is smaller than the predetermined value.

[0079] From the above, as shown in FIG. 5, when the voltage Vfb becomes lower than Vfba, the current Ib becomes the current Ib0, the oscillation period becomes constant, and the oscillation circuit 43 outputs the pulse signal оsc_out having the oscillation frequency Fsw0.

[0080] Furthermore, when voltage Vfb becomes higher than Vfba and lower than Vfbb, current Ib increases as voltage Vfb increases. As current Ib increases, the oscillation period gradually shortens, and therefore oscillator circuit 43 outputs pulse signal оsc_out having an oscillation frequency that increases from frequency Fsw0 to Fsw1.

[0081] Furthermore, when the voltage Vfb becomes higher than Vfbb, the current Ib becomes Ib1 regardless of the voltage Vfb, and the oscillation period becomes constant, so that the oscillation circuit 43 outputs a pulse signal оsc_out having an oscillation frequency Fsw1. Note that the comparator 75 corresponds to an "oscillation signal output circuit," and the other circuits in the oscillation circuit 43 correspond to a "first timing circuit."

[0082] <<<Details of the switching control circuit 44>>> The switching control circuit 44 includes a bottom switch circuit 50, an SR flip-flop 51, OR elements 52 and 57, a comparator 53, an overcurrent protection circuit (OCP) 54, a timer 55, an AND element 56, a buffer 58, an undervoltage lockout (UVLO) 59, and a soft start circuit (SS) 60. For convenience of explanation, the switching control circuit 44 includes the bottom switch circuit 50, but a part of the bottom switch circuit 50 is included in the "second determination circuit."

[0083] <<<SRフリップフロップ51> >> The SR flip-flop 51 outputs a signal Vq1 that switches the power transistor 30. Specifically, when the bottom switch circuit 50 outputs a pulse signal pwm_s, the SR flip-flop 51 outputs a signal Vq1 of "H" level. On the other hand, when an OR element 57 (described later) outputs a signal pwm_r of "H" level, the SR flip-flop 51 outputs a signal Vq1 of "L" level.

[0084] The OR element 52 is configured to output an "H" level signal Vpg while an "H" level pulse pwm_s having a minimum on-width is being input. Specifically, even if the SR flip-flop 51 outputs a signal Vq1 having a pulse width shorter than the minimum on-width of the signal pwm_s, the OR element 52 performs a logical OR operation of the signals pwm_s and Vq1 to output the signal Vpg having the minimum pulse width, i.e., to output a drive signal Vg having the minimum pulse width to a buffer 58 (described later). As a result, the power transistor 30 is always turned on for at least the minimum on-width.

[0085] <<<Comparator 53>>> The comparator 53 generates the timing to turn off the power transistor 30. Specifically, when the AC-DC converter 10 starts up, a soft-start circuit 60 (described later) outputs a voltage Vss that gradually increases in steps. Then, while the power transistor 30 is on, if the voltage Vcs exceeds the lower of the voltage Vss and the voltage Vfb, the comparator 53 outputs an "H" level signal Vr.

[0086] That is, at startup, when the voltage Vcs exceeds the voltage Vss, the comparator 53 outputs a signal Vr at an "H" level. This turns off the power transistor 30. Therefore, as the voltage Vss rises, the on-period of the power transistor 30 gradually becomes longer. As a result, the output voltage Vout also gradually rises. Note that after the so-called soft start period has elapsed, the voltage Vss becomes higher than the voltage Vfb. As a result, during steady state operation, the comparator 53 compares the voltage Vcs with the voltage Vfb.

[0087] In reality, when the voltage Vcs exceeds k times the voltage Vfb, the comparator 53 outputs an “H” level signal Vr that turns off the power transistor 30. Hereinafter, the same applies to the parts where it has been explained that the voltage Vcs exceeds the voltage Vfb or that the voltage Vcs becomes the voltage Vfb.

[0088] When the voltage Vcs becomes higher than the voltage Vfb, the comparator 53 outputs a signal Vr at an "H" level, which turns off the power transistor 30.

[0089] Furthermore, during either startup or steady-state operation, the comparator 53 outputs an "L" level signal Vr when the voltage Vcs is lower than the lower of the voltages Vss and Vfb. The comparator 53 corresponds to a "first off signal output circuit," and the signal Vr corresponds to an "off signal."

[0090] <<<Overcurrent protection circuit (OCP)54>>> When the overcurrent protection circuit (OCP) 54 detects that an excessive inductor current IL1 is flowing through the power transistor 30, it turns off the power transistor 30. Specifically, the overcurrent protection circuit 54 operates while the comparator 53 is operating, and when the voltage Vcs exceeds the reference voltage Vref2, it determines that an excessive inductor current IL1 is flowing through the power transistor 30 and outputs an “H” level signal ocp_o. Therefore, the overcurrent protection circuit 54 turns off the power transistor 30.

[0091] On the other hand, when the voltage Vcs is lower than the reference voltage Vref2, the overcurrent protection circuit 54 outputs the signal ocp_o at the "L" level. Moreover, the overcurrent protection circuit 54 outputs the signal ocp_o at the "L" level while the power transistor 30 is off (i.e., while the signal Vpg is at the "L" level). The overcurrent protection circuit 54 corresponds to an "overcurrent detection circuit."

[0092] <<<Timer 55 and logic circuit>>> The timer 55 prevents malfunction of the overcurrent protection circuit 54. When the timer 55 outputs a high-level signal mask, the AND element 56 outputs the signal ocp_o as the signal sw_off. When the timer 55 outputs a low-level signal mask, the AND element 56 outputs a low-level signal sw_off. Details of the operation of the timer 55 will be described later. The timer 55 and the AND element 56 correspond to a second off signal output circuit, and the signal sw_off corresponds to an off signal.

[0093] The OR element 57 performs a logical OR operation on the signal Vr and the signal sw_off, and outputs the result as a signal pwm_r. Specifically, when the OR element 57 receives the signal Vr at an “H” level or the signal sw_off at an “H” level, it outputs the signal pwm_r at an “H” level.

[0094] On the other hand, when the signal Vr and the signal sw_off are at the “L” level, the OR element 57 outputs the signal pwm_r at the “L” level. The comparator 53, the overcurrent protection circuit 54, the timer 55, the AND element 56, and the OR element 57 correspond to an “off signal output circuit.”

[0095] <<<Buffer 58>>> The buffer 58 amplifies the signal Vpg and outputs it as the drive signal Vg. Specifically, when the SR flip-flop 51 outputs the signal Vpg at an "H" level, the buffer 58 outputs the drive signal Vg at an "H" level. On the other hand, when the SR flip-flop 51 outputs the signal Vpg at an "L" level, the buffer 58 outputs the drive signal Vg at an "L" level.

[0096] <<<Low Voltage Protection Circuit (UVLO)59>>> When the power supply voltage Vcc is low, the undervoltage lockout (UVLO) circuit 59 resets the control IC 32 and stops the operation of the control IC 32. Specifically, when the power supply voltage Vcc is lower than a predetermined voltage, the undervoltage lockout (UVLO) circuit 59 outputs an “H” level signal rst.

[0097] On the other hand, when the power supply voltage Vcc exceeds a predetermined voltage, the low voltage protection circuit 59 outputs a signal rst of "L" level. The signal rst is output to various circuits within the control IC 32, and the various circuits are reset when a signal rst of "H" level is input, and start operating when a signal rst of "L" level is input.

[0098] <<<Soft start circuit (SS) 60>>> The soft start circuit (SS) 60 gradually increases the output voltage Vout at the start of the AC-DC converter 10, transitioning the AC-DC converter 10 to a steady state. Specifically, when the low voltage protection circuit 59 outputs an "L" level signal rst, the soft start circuit 60 gradually increases the voltage Vss in a stepwise manner.

[0099] The soft-start circuit 60 outputs the signal ss_end at the "L" level from when the low-voltage protection circuit 59 outputs the signal rst at the "L" level until the soft-start period has elapsed, and then outputs the signal ss_end at the "H" level after the soft-start period has elapsed. The soft-start period corresponds to the period from when the AC-DC converter 10 starts up until when it transitions to a steady state.

[0100] <<<<Operation of AC-DC Converter 10 and Control IC 32 During Continuous Operation in the "Disconnected State">>> Fig. 6 is a timing chart showing an example of the operation of the AC-DC converter 10 and the control IC 32 during continuous operation in the "disconnected state." Note that Fig. 6 corresponds to condition A2 in Fig. 3, so the bottom switch circuit 50 operates regardless of the operation of the hysteresis comparator 41 and the control circuit 40. Also, in Fig. 6, it is assumed that the AC-DC converter 10 operates continuously, with either the inductor current IL1 or IL2 always flowing.

[0101] At time t0, the control IC 32 outputs a high-level (hereinafter referred to as "H" level) drive signal Vg, turning on the power transistor 30. When the power transistor 30 turns on, the inductor current IL1 flowing through the primary coil L1 increases at a predetermined gradient.

[0102] As a result, the voltage Vcs generated by the inductor current IL1 flowing through the resistor 31 also increases at a predetermined gradient.

[0103] Furthermore, as described above, when the power transistor 30 is on, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level regardless of the voltage Vcs. Here, since the control circuit 40 outputs the signal crst0 at the "H" level, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level.

[0104] Furthermore, the secondary-side coil L2 is electromagnetically coupled with the primary-side coil L1 with opposite polarity, and the diode 24 is turned off. Therefore, the inductor current IL2 that flows through the secondary-side coil L2 does not flow when the power transistor 30 is on, and energy is stored in the transformer 22. When the power transistor 30 is turned on, the voltage Vx becomes a voltage corresponding to the inductor current IL1. However, since the on-resistance of the power transistor 30 and the resistor 31 are sufficiently small, in FIG. 6, for convenience, the voltage Vx is depicted as being approximately the ground voltage.

[0105] Similarly, since no current corresponding to the inductor current IL2 flows in the auxiliary coil L3, the voltage Va of the auxiliary coil L3 becomes the ground voltage.

[0106] Furthermore, the capacitor 74 is charged, and the voltage saw rises, causing the oscillator circuit 43 to start measuring the oscillation period.

[0107] At time t1, when voltage Vcs exceeds voltage Vfb, comparator 53 outputs high-level signal Vr. This causes OR element 57 to output high-level signal pwm_r, and SR flip-flop 51 to output low-level signal Vq1. As a result, control IC 32 outputs low-level drive signal Vg, turning off power transistor 30.

[0108] When the power transistor 30 is turned off, the inductor current IL1 decreases rapidly. At this time, the power transistor 30 is turned off, and the voltage Vcs becomes the ground voltage.

[0109] Furthermore, the signal Vpg becomes "L" level, and the control circuit 40 outputs the signal crst0 at "L" level. As a result, the hysteresis comparator 41 starts operating. However, in the AC-DC converter 10 shown in FIG. 1, no external circuit is connected between the auxiliary coil L3 and the terminal CS, and as described above, the voltage Vcs at the terminal CS is the ground voltage. Therefore, since the voltage Vcs does not exceed the threshold voltage VrefH, the hysteresis comparator 41 continues to output the signal btm_cmp at "L" level.

[0110] Furthermore, when the power transistor 30 is turned off, the energy stored in the transformer 22 is output from the secondary-side coil L2 via the diode 24. At this time, the inductor current IL2 flows while decreasing at a predetermined slope. Here, since the inductor current IL1 is zero, the voltage Vx is a voltage corresponding to the rectified voltage Vrec, and the voltage Va of the auxiliary coil L3 electromagnetically coupled to the coil L2 is a voltage corresponding to the inductor current IL2 of the coil L2.

[0111] At time t2, when the voltage saw exceeds the reference voltage Vref1, the oscillation circuit 43 outputs a pulse signal osc_out. Then, as described above, the bottom switch circuit 50 outputs a pulse signal pwm_s based on the pulse signal osc_out. As a result, the SR flip-flop 51 outputs a high-level signal Vq1. Then, the buffer 58 outputs a high-level drive signal Vg, turning on the power transistor 30. Furthermore, in the oscillation circuit 43, the capacitor 74 discharges, so that the voltage saw becomes the ground voltage.

[0112] Here, at time t2, the inductor current IL2 has not yet become 0, and after the power transistor 30 turns on and the inductor current IL1 flows, the inductor current IL2 becomes 0. After time t2, the same operation as from time t0 to t1 is repeated.

[0113] Therefore, during continuous operation, the AC-DC converter 10 operates without the inductor current IL1 becoming zero when the power transistor 30 is turned on. During continuous operation, either the inductor current IL1 or the inductor current IL2 flows at any instant between time t0 and time t2.

[0114] <<<<Operation of AC-DC Converter 10 During Discontinuous Operation in the "Disconnected State">>> Fig. 7 is a diagram showing an example of a timing chart illustrating the operation of the AC-DC converter 10 when it operates discontinuously in the "disconnected state". In Fig. 7, it is assumed that the AC-DC converter 10 is operating in a steady state, and that the voltage Vfb is lower than the voltage Vfbb.

[0115] 7 is the same as that of the control IC 32 in Fig. 6, so a description of the operation of the control IC 32 will be omitted. In Fig. 6, the AC-DC converter 10 is assumed to be operating in a discontinuous mode having a period in which neither of the inductor currents IL1 and IL2 flows.

[0116] At time t10, the control IC 32 outputs an "H" level drive signal Vg to turn on the power transistor 30. When the power transistor 30 turns on, the inductor current IL1 flowing through the primary coil L1 increases from zero.

[0117] In this way, when the AC-DC converter 10 operates discontinuously, the inductor current IL1 increases from its full flow state (i.e., from zero), and the voltage Vcs generated by the inductor current IL1 flowing through the resistor 31 also increases from the ground voltage (zero) in the same way as the inductor current IL1.

[0118] On the other hand, the secondary-side coil L2 is electromagnetically coupled with the reverse polarity, and the diode 24 is turned off, so that the inductor current IL2 that flows through the secondary-side coil L2 does not flow when the power transistor 30 is turned on, and energy is stored in the transformer 22. Also, when the power transistor 30 is turned on, the voltage Vx becomes a voltage corresponding to the inductor current IL1. However, since the on-resistance of the power transistor 30 and the resistor 31 are sufficiently small, in FIG. 6, for convenience, the voltage Vx is depicted as being approximately the ground voltage.

[0119] Similarly, since no current corresponding to the inductor current IL2 flows in the auxiliary coil L3, the voltage Va of the auxiliary coil L3 becomes the ground voltage.

[0120] At time t11, when the voltage Vcs exceeds the voltage Vfb, the control IC 32 outputs the drive signal Vg at the "L" level to turn the power transistor 30 off.

[0121] When the power transistor 30 is turned off, the voltage Vx rises to approximately the rectified voltage Vrec, causing the inductor current IL1 to decrease rapidly and the voltage Vcs to become the ground voltage. As a result, the energy stored in the transformer 22 is output from the secondary coil L2 via the diode 24. At this time, the inductor current IL2 flows while decreasing at a constant rate. At this time, the voltage Va becomes a voltage corresponding to the inductor current IL2.

[0122] At time t12, the inductor current IL2 stops flowing. At this time, the voltage Vx starts to oscillate according to the resonant frequency of the LC circuit formed by the primary coil L1 and the parasitic capacitance between the drain and source of the power transistor 30.

[0123] When the voltage Vx starts to oscillate, the voltage Va generated in the primary coil L1 and the auxiliary coil L3 magnetically coupled to the secondary coil L2 also starts to oscillate similarly around the voltage level of the ground voltage.

[0124] Then, at time t13, which is the period of the pulse signal osc_out of the oscillation circuit 43 that has elapsed since time t10, the control IC 32 outputs the drive signal Vg at an “H” level to turn on the power transistor 30. When the power transistor 30 is turned on again, as at time t10, the inductor current IL2 does not flow because the AC-DC converter 10 is operating discontinuously.

[0125] Furthermore, the same operation is repeated after time t13. Therefore, during discontinuous operation, the AC-DC converter 10 operates so that the inductor current IL1 becomes zero when the power transistor 30 is turned on. During discontinuous operation, there is a period, such as between time t12 and time t13, during which almost neither the inductor current IL1 nor the inductor current IL2 flows.

[0126] When the AC-DC converter 10 is operating discontinuously, ringing (oscillation) occurs in the drain-source voltage (voltage Vx) of the power transistor 30, as shown in FIG. 7 . When the power transistor 30 is turned on while the voltage Vx is at a high level, the efficiency of the AC-DC converter 10 deteriorates. Specifically, for example, if a capacitor (not shown) is connected between the drain and source of the power transistor 30 as a noise countermeasure, when the level of the voltage Vx increases, charge is stored in the combined capacitance of the parasitic capacitance between the drain and source of the power transistor 30 and the capacitor (not shown). When the power transistor 30 is turned on, the charge stored in the combined capacitance flows to ground via the power transistor 30 and resistor 31, and the efficiency of the AC-DC converter 10 deteriorates by the amount of charge stored in the combined capacitance.

[0127] 7, the timing (for example, t10, t13) at which the power transistor 30 turns on is determined based on the cycle of the pulse signal osc_out of the oscillation circuit 43. Therefore, as described above, the power transistor 30 turns on at a timing when the level of the voltage Vx is high, which may result in a decrease in efficiency.

[0128] Therefore, in order for the power transistor 30 to be turned on at the point where the level of the ringing voltage Vx becomes minimum (hereinafter referred to as "bottom"), the switching of the power transistor 30 is controlled using the voltage Va. Hereinafter, such an AC-DC converter 12 will be described with reference to FIG. 8.

[0129] <<<Overview of AC-DC Converter 12>>> FIG. 8 is a diagram showing an example of the configuration of an AC-DC converter 12 according to an embodiment of the present invention. The AC-DC converter 12 is a circuit that can turn on the power transistor 30 at the timing of the bottom of the voltage Vx during so-called discontinuous operation.

[0130] The control block 28 of the AC-DC converter 12 of the present embodiment includes a diode 80 and a resistor 81 for detecting the voltage of the auxiliary coil L3. Since the blocks with the same reference numerals in FIGS. 1 and 8 are the same, here, mainly the diode 80 and the resistor 81 will be described.

[0131] The anode of the diode 80 is connected to the auxiliary coil L3, and the cathode is connected to the terminal CS via the resistor 81. Further, when a high voltage is generated in the auxiliary coil L3 and the diode 80 is turned on, the voltage Va is applied to the capacitor 33 via the diode 80 and the resistor 81.

[0132] When the power transistor 30 is turned on, the voltage generated in the resistor 31 is applied to the terminal CS. On the other hand, when the power transistor 30 is turned off, a voltage corresponding to the voltage Va of the auxiliary coil L3 is applied to the terminal CS. Details will be described later, but thereby, the hysteresis comparator 41 can detect that the diode 80 and the resistor 81 are connected to the terminal CS. The diode 80 and the resistor 81 correspond to a "detection circuit".

[0133] The capacitor 33 is discharged via a first path via the resistors 31 and 34, and a second path via the capacitance between the terminals of the diode 80, the resistor 81, and the auxiliary coil L3. In the second path, the capacitor 33 may be discharged by a reverse recovery current of the diode 80 that occurs when the voltage Va becomes negative.

[0134] Furthermore, when the power transistor 30 is turned on, the inductor current IL1 starts to flow through the resistor 31. Therefore, a voltage according to the inductor current IL1 is applied to the voltage Vcs.

[0135] On the other hand, when the power transistor 30 is turned off, the inductor current IL2 starts to flow. Then, when the inductor current IL2 starts to flow, the voltage Va generated in the auxiliary coil L3 is applied to the voltage Vcs.

[0136] Similarly to the AC-DC converter 10, the AC-DC converter 12 operates continuously or discontinuously. When the control IC 32 is in a "connected state," if the AC-DC converter 12 operates continuously, the control IC 32 operates in "continuous operation." When the AC-DC converter 12 operates discontinuously, the control IC 32 operates in "discontinuous operation." The continuous operation of the AC-DC converter 12 is referred to as "continuous mode," and the discontinuous operation of the AC-DC converter 12 is referred to as "discontinuous mode." The case where the control IC 32 is used in the AC-DC converter 10 (e.g., the case of condition A2 in FIG. 3 ) corresponds to the "first case." When the control IC 32 is used in the AC-DC converter 12, the case where the control IC 32 is in "continuous mode" (the case where the control IC 32 is in "continuous mode" under condition A4 in FIG. 3 ) corresponds to the "second case," and the case where the control IC 32 is in "discontinuous mode" (the case where the control IC 32 is in "discontinuous mode" under condition A4 in FIG. 3 ) corresponds to the "third case."

[0137] When the power transistor 30 is turned off and the inductor current IL2 becomes discontinuous, as described above, the voltage Va generated in the auxiliary coil L3 oscillates around the voltage level of the ground voltage. Although the voltage Va oscillates around the ground voltage, only the positive voltage of the oscillating voltage Va is applied to the terminal CS because the diode 80 is provided between the terminal CS and the auxiliary coil L3. The control IC 32, which operates based on the voltage Vcs, will be described in detail below.

[0138] <<<Control IC32 operation during "continuous operation">>> Fig. 9 is a diagram showing an example of a timing chart illustrating the operation of the AC-DC converter 12 and the control IC 32 in "continuous operation." Fig. 9 corresponds to condition A4 in Fig. 3. Also, the AC-DC converter 12 is designed so that the voltage Vcs corresponding to the voltage Va when the power transistor 30 is turned off is higher than the threshold voltage VrefH of the hysteresis comparator 41.

[0139] 6 is different from the operation of the AC-DC converter 12 in the voltage Vcs, the operation related to the voltage Vcs will be described in detail below. Note that the control IC 32 of the AC-DC converter 12 is the same as the control IC 32 of FIG. 1, and therefore FIG. 2 will be referred to as appropriate.

[0140] At time t20, when the control IC 32 outputs a drive signal Vg at an "H" level, the power transistor 30 turns on. When the power transistor 30 turns on, an inductor current IL1 flows. At this time, a voltage generated across the resistor 31 by the inductor current IL1 is applied to the terminal CS. Then, the voltage Vcs rises at a predetermined slope.

[0141] 2 outputs a high-level signal crst0. The hysteresis comparator 41 outputs a low-level signal btm_cmp because the high-level signal crst0.

[0142] At time t21, when voltage Vcs exceeds voltage Vfb, control IC 32 outputs "L" level drive signal Vg, turning off power transistor 30. At this time, voltage Va corresponding to inductor current IL2 is generated in auxiliary coil L3, and a voltage corresponding to voltage Va generated in auxiliary coil L3 is applied to terminal CS.

[0143] Furthermore, the control circuit 40 outputs the signal crst0 at the “L” level. Then, the hysteresis comparator 41 outputs the signal btm_cmp at the “H” level because the signal crst0 is at the “L” level and the voltage Vcs is higher than the threshold voltage VrefH.

[0144] This also enables the control IC 32 to determine whether the auxiliary coil L3 is connected to the terminal CS based on the signal btm_cmp. That is, the control IC 32 can detect that the AC-DC converter 12 is operating in the "connected state."

[0145] At time t22, when the oscillator circuit 43 outputs the pulse signal оsc_оut, the control IC 32 outputs a drive signal Vg at a high level, turning on the power transistor 30. When the power transistor 30 turns on, the control circuit 40 outputs a signal crst0 at a high level. Furthermore, since the signal crst0 is at a high level, the hysteresis comparator 41 outputs a signal btm_cmp at a low level. The same operation is then repeated from time t22 onwards.

[0146] <<<Malfunction of the overcurrent protection circuit 54>>> When the control IC 32 outputs a drive signal Vg at an "H" level and the power transistor 30 is turned on, the application of the voltage Va to the auxiliary coil L3 is stopped and the capacitor 33 is discharged via the first path or the second path. Therefore, when the power transistor 30 is turned on, the voltage Vcs temporarily drops to the ground voltage and then rises according to the inductor current IL1.

[0147] However, as shown in Fig. 10, there are cases where the voltage Vcs does not become lower than the reference voltage Vref2 even when the power transistor 30 is turned on due to some factor (for example, when the reverse recovery current of the diode 80 included in the second path does not flow). Such a case will be described with reference to Fig. 10.

[0148] At time t30, the voltage Vcs becomes voltage Vfb, and the comparator 53 in FIG. 2 outputs a high-level signal Vr. This causes the control IC 32 to output a low-level drive signal Vg, turning off the power transistor 30. When the power transistor 30 turns off, the control circuit 40 outputs a low-level signal crst0, as described above. Then, as the voltage Va from the auxiliary coil L3 increases, the voltage Vcs becomes higher than the reference voltage VrefH, causing the hysteresis comparator 41 to output a high-level signal btm_cmp. Furthermore, the overcurrent protection circuit 54 outputs a low-level signal ocp_o because the drive signal Vg also becomes low due to the low-level signal Vpg. Therefore, the OR element 57 outputs a low-level pwm_r after the power transistor 30 turns off.

[0149] Then, at time t31, when the oscillator circuit 43 outputs the pulse signal osc_out and the bottom switch circuit 50 outputs the pulse signal pwm_s, the control IC 32 outputs the drive signal Vg at the "H" level. However, the voltage Vcs remains higher than the reference voltage Vref2, and the overcurrent protection circuit 54 outputs the signal ocp_o at the "H" level, so the OR element 57 outputs the signal pwm_r at the "H" level.

[0150] Therefore, at time t32, when the minimum on-width period of the pulse signal pwm_s has elapsed since time t31, the SR flip-flop 51 outputs a low-level signal Vq1, and the control IC 32 outputs a low-level drive signal Vg. As a result, the power transistor 30 turns off immediately after turning on. Furthermore, because the signal Vpg is low, the overcurrent protection circuit 54 outputs a low-level signal ocp_o.

[0151] In this way, if there were no circuit to invalidate the overcurrent determination by the overcurrent protection circuit 54 immediately after the power transistor 30 was turned on, the power transistor 30 would be turned off immediately after being turned on.

[0152] At time t33, when the oscillator circuit 43 outputs the pulse signal osc_out and the bottom switch circuit 50 outputs the pulse signal pwm_s, the control IC 32 outputs a high-level drive signal Vg. At this time, when the voltage Vcs falls below the reference voltage Vref2, the overcurrent protection circuit 54 outputs a low-level signal ocp_o. Thereafter, when the voltage Vcs falls below the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp.

[0153] In this embodiment, in order to suppress such malfunction of the overcurrent protection circuit 54, a timer 55 is provided in the control IC 32. Specifically, when the signal btm_cmp remains at the “H” level after the pulse signal pwm_s is input, the timer 55 outputs the “L” level signal mask until the signal btm_cmp becomes the “L” level or until a predetermined period P has elapsed, whichever is shorter.

[0154] On the other hand, after the pulse signal pwm_s is input, the timer 55 outputs a signal mask at an "H" level when the signal btm_cmp becomes "L" level or when a predetermined period P has elapsed.

[0155] <<<Timer 55 Operation>>> [When the period from when the power transistor 30 is turned on until the voltage Vcs reaches the threshold voltage VrefL is shorter than the predetermined period P] 11 and 12 are diagrams showing examples of timing charts illustrating the operation of suppressing malfunction of the overcurrent protection circuit 54 by the timer 55. Fig. 11 is also an example of a timing chart in the case where the period from when the power transistor 30 is turned on until the voltage Vcs reaches the threshold voltage VrefL is shorter than the predetermined period P.

[0156] 11, it is assumed that the voltage Vcs becomes smaller than the reference voltage Vref2 after a predetermined period P has elapsed at most after the power transistor 30 is turned on. That is, it is assumed that the overcurrent protection circuit 54 outputs the signal ocp_o at the “L” level before the predetermined period P has elapsed at most after the power transistor 30 is turned on.

[0157] Also, in this embodiment, as in the case of FIG. 10, for convenience of explanation, the comparator 53 outputs a signal Vr at an “H” level when the voltage Vcs becomes the voltage Vfb, and then outputs a signal Vr at an “L” level.

[0158] At time t40, when the voltage Vcs reaches voltage Vfb and the comparator 53 in FIG. 2 outputs a high-level signal Vr, the control IC 32 outputs a low-level signal Vg to turn off the power transistor 30. Then, as the voltage Va from the auxiliary coil L3 increases, the voltage Vcs becomes higher than the reference voltage VrefH, causing the hysteresis comparator 41 to output a high-level signal btm_cmp. Furthermore, the overcurrent protection circuit 54 outputs a low-level signal ocp_o because the drive signal Vg also becomes low due to the low level signal Vpg. At this time, the timer 55 is outputting a high-level signal mask, and the OR element 57 outputs a low-level signal pwm_r after the power transistor 30 is turned off.

[0159] 2 outputs the pulse signal osc_out and the bottom switch circuit 50 outputs the pulse signal pwm_s, the control IC 32 outputs the signal Vg at an “H” level to turn on the power transistor 30. At this time, the voltage Vcs is still higher than the reference voltage Vref2, so the overcurrent protection circuit 54 outputs the signal ocp_o at an “H” level.

[0160] However, since the timer 55 outputs the signal mask at an "L" level, the AND element 56 outputs the signal sw_off at an "L" level, and therefore the OR element 57 outputs the signal pwm_r at an "L" level.

[0161] As a result, the control IC 32 can prevent the overcurrent protection circuit 54 from malfunctioning because the voltage Vcs is higher than the reference voltage Vref2. Furthermore, after the power transistor 30 is turned on, the timer 55 outputs the “H” level signal mask before the predetermined period P has elapsed, so the control IC 32 can use the overcurrent protection function early.

[0162] At time t42 when the voltage Vcs drops below the reference voltage Vref2, the overcurrent protection circuit 54 outputs the signal ocp_o at the "L" level.

[0163] At time t43, when the voltage Vcs further decreases and falls below the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp, and the timer 55 outputs a high-level signal mask. At this time, the overcurrent protection circuit 54 outputs a low-level signal ocp_o, so the AND gate 56 outputs a low-level signal sw_off. As a result, the OR gate 57 outputs a low-level signal pwm_r.

[0164] At time t44 when the voltage Vcs becomes the voltage Vfb, the comparator 53 outputs the signal Vr at the "H" level. Then, after the power transistor 30 is turned off, the OR element 57 outputs the signal pwm_r at the "L" level.

[0165] [When the period from when the power transistor 30 is turned on until the voltage Vcs reaches the threshold voltage VrefL is longer than the predetermined period P] 12 is an example of a timing chart in which the period from when the power transistor 30 is turned on until the voltage Vcs reaches the threshold voltage VrefL is longer than the predetermined period P. In FIG. 12, as in FIG. 11, the overcurrent protection circuit 54 outputs the signal ocp_o at the “L” level after the power transistor 30 is turned on, before the predetermined period P has elapsed at most.

[0166] 11, the comparator 53 outputs an "H" level signal Vr. In addition, in Fig. 12, the operation from time t50 to t51 is the same as the operation from time t40 to t41 in Fig. 11, and therefore a description thereof will be omitted.

[0167] After the control IC 32 outputs the signal Vg at "H" level, at time t52 when the voltage Vcs falls below the reference voltage Vref2, the overcurrent protection circuit 54 outputs the signal ocp_o at "L" level.

[0168] At time t53, when a predetermined period P has elapsed since time t51, the timer 55 outputs a high-level signal mask. However, at time t52, the overcurrent protection circuit 54 outputs a low-level signal ocp_o, so the AND element 56 outputs a low-level signal sw_off, and therefore the OR element 57 outputs a low-level signal pwm_r.

[0169] As a result, the control IC 32 can prevent the overcurrent protection circuit 54 from malfunctioning because the voltage Vcs is higher than the reference voltage Vref2. Furthermore, when a predetermined period P has elapsed after the power transistor 30 is turned on, the timer 55 outputs an “H” level signal mask, so the control IC 32 can use the overcurrent protection function once the predetermined period P has elapsed at most.

[0170] At time t54 when the voltage Vcs decreases and falls below the threshold voltage VrefL, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level.

[0171] At time t55 when the voltage Vcs becomes the voltage Vfb, the comparator 53 outputs the signal Vr at the “H” level. Then, after the power transistor 30 is turned off, the OR element 57 outputs the signal pwm_r at the “L” level.

[0172] 11 and 12, the overcurrent protection circuit 54 has been described as outputting the signal ocp_o at the "L" level after the power transistor 30 has been turned on and at most the predetermined period P has elapsed. However, if the overcurrent protection circuit 54 continues to output the signal ocp_o at the "H" level even after the predetermined period P has elapsed, the power transistor 30 turns off after the predetermined period P has elapsed.

[0173] As a result, even if an overcurrent actually flows through the power transistor 30 for some reason, if the state in which the overcurrent flows continues longer than the maximum predetermined period P, the control IC 32 can turn off and protect the power transistor 30. Note that the predetermined period P corresponds to the "predetermined period."

[0174] <<<Configuration of Bottom Switch Circuit 50>>> 13 is a diagram showing an example of the configuration of the bottom switch circuit 50. The bottom switch circuit 50 outputs a pulse signal pwm_s that turns on the power transistor 30. Specifically, when the control IC 32 operates in the "disconnected state" or "continuous operation," the bottom switch circuit 50 outputs the pulse signal pwm_s when the oscillator circuit 43 outputs the pulse signal osc_out.

[0175] On the other hand, the bottom switch circuit 50 outputs a pulse signal pwm_s based on the outputs of the hysteresis comparator 41 and the control circuit 40. Specifically, when the control IC 32 operates in "discontinuous operation", the bottom switch circuit 50 outputs a pulse signal pwm_s based on the pulse signal osc_out and the outputs of an up-counter 90 and an up-down counter 91, which will be described later.

[0176] The bottom switch circuit 50 includes an up-counter 90, an up-down counter 91, a data hold 92, and a bottom controller 93. The up-counter 90 and the up-down counter 91 operate when the voltage Vcs oscillates while the control IC 32 is operating in "discontinuous operation."

[0177] The up-counter 90 counts the number of oscillations that occur in the voltage Vcs (i.e., the number of times that bottoms occur (the number of bottoms)). Specifically, when the control circuit 40 outputs the signal crst0 at an "L" level, the up-counter 90 counts up each time the hysteresis comparator 41 outputs the signal btm_cmp at an "L" level.

[0178] The count value counted up by the up-counter 90 is output as a signal uc_out. This allows a determination circuit 110 (described later) to determine whether the control IC 32 operates in "continuous operation" or "discontinuous operation" based on whether the signal uc_out is zero at the timing when the pulse signal osc_out is input.

[0179] The up-counter 90 is reset when the control circuit 40 outputs a high-level signal crst0. Here, "bottom" refers to the timing at which the voltage Vx oscillates and reaches its lower limit during discontinuous operation (see FIG. 16), and the "bottom count" refers to the number of times this timing has occurred. The up-counter 90 corresponds to a "counter." The value of the signal uc_out of the up-counter 90 corresponds to the "first count."

[0180] The up / down counter 91 holds a reference number of times based on the bottom number of times, which is the reference for turning on the power transistor 30. When the control circuit 40 outputs a signal crst1 at an "L" level, the up / down counter 91 operates, and when the control circuit 40 outputs a signal crst1 at an "H" level, the reference number of times stored as a count value is reset.

[0181] Specifically, when a signal up_down from a bottom controller 93 (described later) is at the "H" level instructing up counting and a clock signal udc_clk is input, the up / down counter 91 takes in a signal uc_out as a reference number of times (count value), which it then outputs as a signal udc_out.

[0182] On the other hand, when the signal up_down of the up-down counter 91 is at the "L" level indicating downcounting and the clock signal udc_clk is input, the up-down counter 91 counts down a reference number of times (count value) and outputs the result as the signal udc_out. The up-down counter 91 corresponds to a "first holding circuit." The condition under which the up-down counter 91 takes in the reference number of times corresponds to a "first condition." The condition under which the up-down counter 91 counts down corresponds to a "second condition."

[0183] The data hold 92 holds the signal uc_out from the up counter 90, which indicates the number of bottoms, at the timing when the pulse signal osc_out is input. Specifically, when the control circuit 40 outputs the signal crst0 at the "L" level to release the reset of the data hold 92 and the oscillator circuit 43 outputs the pulse signal osc_out, the data hold 92 captures the signal uc_out and outputs it as the signal dh_out. On the other hand, when the control circuit 40 outputs the signal crst0 at the "H" level, the data hold 92 is reset. The data hold 92 corresponds to a "second holding circuit." The value of the signal dh_out of the data hold 92 corresponds to the "second number of times."

[0184] The bottom controller 93 outputs a pulse signal pwm_s for turning on the power transistor 30, and a clock signal udc_clk and a signal up_down for controlling the bottom switch circuit 50. Specifically, the bottom controller 93 changes the timing at which it outputs the pulse signal pwm_s depending on whether the control IC 32 operates in a "disconnected state," "continuous operation," or "discontinuous operation."

[0185] 14, the bottom controller 93 includes a signal generation circuit 100 and an adjustment circuit 101. The signal generation circuit 100 outputs a pulse signal pwm_s in response to the signal btm_cmp output by the hysteresis comparator 41. Specifically, when the control IC 32 operates in the "disconnected state" or "continuous operation," the signal generation circuit 100 outputs the pulse signal pwm_s when the oscillator circuit 43 outputs the pulse signal osc_out, as shown in FIG.

[0186] Furthermore, when the control IC 32 operates in "discontinuous operation," when the signal btm_cmp changes in accordance with the oscillation of the voltage Vcs, the signal generating circuit 100 outputs a pulse signal pwm_s in accordance with the change in the signal btm_cmp. On the other hand, when the oscillation of the voltage Vcs disappears and the signal btm_cmp does not change, the signal generating circuit 100 outputs a pulse signal pwm_s after a predetermined time has elapsed. Note that the signal generating circuit 100 corresponds to an "ON signal output circuit," and the signal pwm_s corresponds to an "ON signal."

[0187] 14, the signal generation circuit 100 includes a determination circuit 110, an output circuit 111, an OR element 112, a D flip-flop 113, and a generation circuit 114. The determination circuit 110 determines whether the control IC 32 operates in "continuous operation" or "discontinuous operation."

[0188] Specifically, when the oscillator circuit 43 outputs the pulse signal osc_out, if the signal uc_out from the up-counter 90 (i.e., the count value of the up-counter 90) is zero, the determination circuit 110 determines that the control IC 32 operates in "continuous operation" and outputs an "L" level signal mode. On the other hand, when the oscillator circuit 43 outputs the pulse signal osc_out, if the signal uc_out from the up-counter 90 is not zero, the determination circuit 110 determines that the control IC 32 operates in "discontinuous operation" and outputs an "H" level signal mode.

[0189] This allows the determination circuit 110 to determine whether the control IC 32 is operating in "continuous operation" or "discontinuous operation" based on whether the signal uc_out is zero at the timing when the pulse signal osc_out is input. When the control IC 32 operates in a "disconnected state," the voltage Vcs does not oscillate and the signal uc_out from the up-counter 90 is zero, so the determination circuit 110 outputs a signal mode at an "L" level. The signal mode corresponds to the "determination result."

[0190] As shown in FIG. 15, the output circuit 111 changes the timing at which it outputs the pulse signal out0 depending on whether the control IC 32 operates in the "disconnected state" and "continuous operation" or "discontinuous operation."

[0191] 15, when the control IC 32 operates in the "disconnected state" or "continuous operation" when the "mode" signal is at the "L" level, the output circuit 111 outputs the pulse signal out0 when the oscillator circuit 43 outputs the pulse signal osc_out. At this time, the switching frequency Ftr of the power transistor 30 is equal to the oscillation frequency Fsw.

[0192] 15, when the "H" level signal "mode" is input, the control IC 32 operates in "discontinuous operation," so that the output circuit 111 outputs the pulse signal "out0" at a predetermined timing after the oscillator circuit 43 outputs the pulse signal "osc_out." At this time, the switching frequency Ftr is lower than the oscillation frequency Fsw.

[0193] The following describes in detail how the output circuit 111 determines the predetermined timing. The output circuit 111 changes the predetermined timing after the oscillator circuit 43 outputs the pulse signal osc_out, depending on the logic level of the signal up_down.

[0194] Specifically, first, a description will be given of condition B2 when the signal up_down is at the “H” level, i.e., when the oscillation frequency Fsw decreases and the up / down counter 91 counts up. When the oscillation circuit 43 outputs the pulse signal osc_out, the signals uc_out and udc_out match, and then the hysteresis comparator 41 outputs the “L” level signal btm_cmp, the output circuit 111 outputs the signal out0 after a predetermined delay.

[0195] Next, a description will be given of condition B3 when the signal up_down is at the "L" level, i.e., when the oscillation frequency Fsw increases and the up / down counter 91 counts down. When the oscillation circuit 43 outputs the pulse signal osc_out and the signal uc_out is smaller than the signal udc_out, the output circuit 111 waits until the signal uc_out matches the signal udc_out, and after a predetermined delay, outputs the signal out0.

[0196] As a result, when the load 11 is in a light load state, the control IC 32 can quickly respond to fluctuations in the load 11 state and quickly change the switching frequency Ftr. Furthermore, when the load 11 is in a heavy load state, the control IC 32 suppresses abrupt changes in the switching frequency Ftr and suppresses abrupt changes in the inductor currents IL1 and IL2. Furthermore, the control IC 32 suppresses the occurrence of audible noise in the transformer 22.

[0197] The OR element 112 performs a logical OR operation on the signal out0 from the output circuit 111 and a signal out1 from a generating circuit 114 (described later), and outputs the result as a pulse signal pwm_s.

[0198] When the control circuit 40 outputs the signal crst0 at the "L" level and the hysteresis comparator 41 outputs the signal btm_cmp at the "H" level, the D flip-flop 113 outputs the signal en at the "H" level. On the other hand, when the control circuit 40 outputs the signal crst0 at the "H" level, the D flip-flop 113 is reset. The signal en is used in the generation circuit 114 and the clock generation circuit 117 as a signal indicating whether the control IC 32 operates in "continuous operation" or "discontinuous operation."

[0199] The generation circuit 114 generates the timing to turn on the power transistor 30 when the oscillation of the voltage Vcs becomes too small to be detected. Specifically, when the oscillation of the voltage Vcs becomes smaller than normal due to some factor, the hysteresis comparator 41 can no longer detect the voltage Vcs signal, and a predetermined time has passed, the generation circuit 114 outputs the pulse signal out1. Details of the generation circuit 114 will be described later.

[0200] The adjustment circuit 101 changes the reference number of times in accordance with the load current Iout flowing through the load 11. The adjustment circuit 101 includes comparators 115 and 116 and a clock generation circuit 117.

[0201] The comparator 115 compares the current bottom count with the reference count by comparing the count value of the up-counter 90 with the count value of the up-down counter 91. Specifically, if the signal uc_out and the signal udc_out match, that is, if the current bottom count matches the reference count, the comparator 115 outputs a signal cnt_cmp at an "H" level, and if the signal uc_out and the signal udc_out do not match, that is, if the current bottom count does not match the reference count, the comparator 115 outputs a signal cnt_cmp at an "L" level.

[0202] The comparator 116 outputs a signal up_down that indicates whether the up / down counter 91 should count up or count down in accordance with the signal udc_clk input to the up / down counter 91. Specifically, the comparator 116 outputs an “L” level signal up_down when the count value indicated by the signal udc_out is greater than the count value indicated by the signal dh_out plus 1 (i.e., when the oscillation period of the oscillator circuit 43 in FIG. 2 becomes shorter).

[0203] On the other hand, when the count value indicated by the signal udc_out is equal to or less than the count value indicated by the signal dh_out plus 1 (i.e., when the oscillation period of the oscillation circuit 43 becomes longer), the comparator 116 outputs the signal up_down at an "H" level. Note that when the signal dh_out is zero (i.e., when the pulse signal osc_out has not been input after the data hold 92 is reset), the comparator 116 does not perform the comparison and outputs the signal up_down at the same logical level as the logical level it has been outputting previously. Furthermore, when the signal udc_out is zero (i.e., when the up / down counter 91 is reset), the comparator 116 outputs the signal up_down at an "H" level.

[0204] The clock generation circuit 117 generates a pulse signal udc_clk that indicates the timing at which the up / down counter 91 updates the reference count. Specifically, the clock generation circuit 117 operates when the signal en is at "H" level. Then, when the comparator 116 outputs the signal up_down at "H" level, the clock generation circuit 117 outputs the pulse signal udc_clk when the signal cnt_cmp becomes "L" level.

[0205] When the up / down counter 91 receives the pulse signal udc_clk, it receives the signal uc_out and outputs it as the signal udc_out. As a result, when the oscillation frequency Fsw decreases and the control IC 32 decreases the switching frequency Ftr of the power transistor 30, the control IC 32 immediately increases the maximum bottom count based on the decrease in oscillation frequency Fsw. That is, when the load 11 becomes light, the control IC 32 immediately decreases the switching frequency Ftr.

[0206] On the other hand, after the pulse signal osc_out is input, the clock generation circuit 117 outputs the pulse signal udc_clk when the comparator 116 outputs the signal up_down at the "L" level a predetermined number of times in succession.

[0207] Below, we will explain the operation when the signal up_down goes to the “L” level, including circuits other than the clock generation circuit 117. First, when the oscillation circuit 43 outputs the pulse signal osc_out, the data hold 92 takes in the signal uc_out and outputs it as the signal dh_out.

[0208] Next, the comparator 116 outputs a signal up_down at an "L" level when the count value indicated by the signal udc_out is greater than the count value indicated by the signal dh_out plus 1. Then, when the pulse signal osc_out is input a predetermined number of times and this operation is repeated, the clock generation circuit 117 outputs a pulse signal udc_clk.

[0209] When the up / down counter 91 receives the pulse signal udc_clk, it counts down the count value and outputs the result as the signal udc_out. This causes the control IC 32 to gradually decrease the reference number of times. In this way, the conditions under which the up / down counter 91 counts down are stricter than the conditions under which the up / down counter 91 counts up.

[0210] As a result, when the oscillation frequency Fsw increases and the switching frequency Ftr of the power transistor 30 increases, the control IC 32 gradually increases the switching frequency Ftr. That is, even if the load 11 becomes a heavy load, the control IC 32 does not immediately change the switching frequency Ftr, but gradually increases the switching frequency Ftr. As a result, the control IC 32 can suppress abrupt changes in the switching frequency Ftr and suppress audible noise from occurring in the transformer 22.

[0211] The determination circuit 110 corresponds to the "mode determination circuit," the comparator 115 corresponds to the "second comparison circuit," and the comparator 116 corresponds to the "third comparison circuit." Therefore, the hysteresis comparator 41, the up-counter 90, and the determination circuit 110 correspond to the "second determination circuit." Furthermore, the clock generation circuit 117 corresponds to the "update circuit."

[0212] <<<Operation of AC-DC converter 12 during discontinuous operation>>> FIG. 16 is a diagram illustrating an example of the operation of the AC-DC converter 12 during discontinuous operation. In the AC-DC converter 12 of FIG. 8, a diode 80 and a resistor 81 are added to the AC-DC converter 10 of FIG. 1 so that a voltage corresponding to the voltage Va of the auxiliary coil L3 is applied to the terminal Vcs when the power transistor 30 is off. Therefore, FIG. 16 differs from FIG. 7, illustrating the discontinuous operation of the AC-DC converter 10, only in the change in the voltage Vcs. Therefore, the change in the voltage Vcs will be described below using FIG. 16. Times t60 to t63 in FIG. 16 correspond to times t10 to t13 in FIG. 7. In FIG. 16, to facilitate understanding of the definition of "bottom" described above, the timing at which the voltage Vx oscillates and reaches its lower limit during discontinuous operation is highlighted by a dotted line.

[0213] At time t60, when the power transistor 30 is turned on, the inductor current IL1 flowing through the primary coil L1 increases because the AC-DC converter 12 is operating discontinuously. Therefore, the voltage Vcs temporarily drops to the ground voltage and then rises in the same manner as the inductor current IL1. Therefore, the voltage Vcs also increases from zero.

[0214] At time t61, when the voltage Vcs exceeds the voltage Vfb, the control IC 32 outputs the drive signal Vg at the "L" level to turn the power transistor 30 off.

[0215] Furthermore, the voltage Vx is a voltage that corresponds to the rectified voltage Vrec, and the voltage Va is a voltage that corresponds to the inductor current IL2. At this time, the voltage Vcs is a voltage that corresponds to the voltage Va.

[0216] At time t62, voltage Va begins to oscillate around the voltage level of the ground voltage. As a result, voltage Vcs also begins to oscillate. Note that because voltage Va is applied to terminal CS via diode 80 and resistor 81, when voltage Va becomes negative, voltage Vcs becomes a negative voltage that is lower than ground voltage by approximately the forward voltage of diode 80.

[0217] At time t63, the control IC 32 outputs a drive signal Vg of "H" level to turn on the power transistor 30. At this time, the voltage Vcs becomes the voltage generated across the resistor 31. Furthermore, the same operation is repeated from time t63 onwards.

[0218] <<<<Operation when the oscillation frequency Fsw decreases during "discontinuous operation">>> 17 is a timing chart showing an example of the operation of the control IC 32 when the load 11 is in a light load state during "discontinuous operation" and the oscillation frequency Fsw drops. Note that FIG. 17 corresponds to condition A4 in FIG. 3. Also, times t70, t76, and t83 in FIG. 17 correspond to times t60 and t63 in FIG. 16. Also, times t71 and t77 in FIG. 17 correspond to time t61 in FIG. 16. Furthermore, times t72 and t78 in FIG. 17 correspond to time t62 in FIG. 16.

[0219] The changes in the signals btm_cmp, crst0, crst1, pwm_r, saw, and osc_out have been explained so far and will not be explained in detail. Also, it is assumed that the up / down counter 91 has already been reset and has output a count value of "0" as the signal udc_out before time t70.

[0220] At time t70, the control IC 32 outputs a drive signal Vg at an "H" level to turn on the power transistor 30. When the power transistor 30 turns on, the voltage Vcs increases. At this time, the control circuit 40 outputs a signal crst0 at an "H" level, and the up-counter 90 is reset. As a result, the count value (signal uc_out) of the up-counter 90 becomes "0."

[0221] At time t71 when the voltage Vcs increases to voltage Vfb, the comparator 53 outputs a high-level signal Vr, and the OR element 57 outputs a high-level signal pwm_r, turning off the power transistor 30. When the power transistor 30 turns off, the voltage Vcs rises in response to the voltage Va from the auxiliary coil L3. When the voltage Vcs exceeds the threshold voltage VrefH, the hysteresis comparator 41 outputs a high-level signal btm_cmp.

[0222] At time t72 when the voltage Vcs drops below the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. The up-counter 90 then counts up based on the low-level signal btm_cmp. As a result, the count value (signal uc_out) of the up-counter 90 becomes 1.

[0223] When the up-counter 90 counts up and the signal uc_out becomes "1," the signal uc_out becomes greater than the signal udc_out, causing the clock generation circuit 117 to output the pulse signal udc_clk. At this time, the signal udc_out is equal to the signal dh_out, so the comparator 116 outputs the signal up_down at "H" level. Therefore, the up / down counter 91 takes in the signal uc_out as the signal udc_out and sets the count value (signal udc_out) to "1." After that, the voltage Vcs starts to oscillate (ring).

[0224] At time t73 when the voltage Vcs oscillates and falls below the threshold voltage VrefL, the hysteresis comparator 41 operates in the same manner as at time t72, causing the up-counter 90 to change the signal uc_out from "1" to "2." As a result, when the signal udc_clk is input, the up-down counter 91 changes the signal udc_out from "1" to "2."

[0225] At time t74 when the oscillator circuit 43 outputs the pulse signal osc_out, the data hold 92 captures the signal uc_out of the up-counter 90 and outputs it as the signal dh_out. At this time, the signals uc_out and udc_out match. That is, the count value of the up-down counter 91, which is the reference number for determining the timing of turning on, is equal to the number indicated by the signal dh_out when the pulse signal osc_out is input.

[0226] Then, at time t75 when the voltage Vcs oscillates and falls below the threshold voltage VrefL, the hysteresis comparator 41 operates, as at time t72, and the up-counter 90 sets the signal uc_out to "3". After that, when the signal udc_clk is input, the up-down counter 91 changes the signal udc_out from "2" to "3".

[0227] When the pulse signal osc_out is input at time t74, the signals uc_out and udc_out match, so at time t76 after the waiting period has elapsed, the bottom controller 93 outputs the pulse signal pwm_s, turning on the power transistor 30. Then, because the pulse signal pwm_s is input, the oscillator circuit 43 subsequently outputs the pulse signal osc_out at a timing when an oscillation period corresponding to the frequency Fsw has elapsed since the pulse signal pwm_s was input.

[0228] As a result, the oscillator circuit 43 measures the oscillation period every time the power transistor 30 is turned on, and therefore, even when the power transistor 30 is turned on in accordance with the voltage Vx, a delay in the switching frequency Ftr can be prevented.

[0229] After time t76, the operation from time t70 to time t76 is repeated. However, after time t76, the signal udc_out, which is the count value of up / down counter 91 and indicates the reference number of times, is "3." Here, if the load current Iout of load 11 becomes even smaller after time t76, the period during which voltage Vcs is higher than threshold voltage VrefH (from time t77 to t78) becomes shorter than the period from time t71 to t72.

[0230] In this case, the number of times that the voltage Vcs oscillates increases. As a result, at time t82, when the up-counter 90 outputs the signal uc_out that is "4," the up-down counter 91 changes the signal udc_out from "3" to "4" because the signal udc_clk is input.

[0231] Then, at time t83, a standby period after time t82, the signals uc_out and udc_out matched when the pulse signal osc_out was input at time t81, so the bottom controller 93 outputs the pulse signal pwm_s.

[0232] In this way, as shown between times t77 and t78, when the load current lout decreases, the number of oscillations of the voltage Vcs increases. In such a case, if the signal udc_out, which is the count value of the up / down counter 91 and indicates the reference number of oscillations, does not change from "3," the pulse signal pwm_s is output after time t80, and the period of the pulse signal pwm_s changes significantly.

[0233] In this embodiment, when the load current Iout decreases, the reference number of times also increases, so that the period of the pulse signal pwm_s can be kept substantially constant. As a result, for example, it is possible to prevent audible noise from occurring in the primary coil L1 or the like due to a sudden change in the period of the pulse signal pwm_s.

[0234] <<<<Operation when the oscillation frequency Fsw increases during "discontinuous operation">>> 18 is a timing chart showing an example of the operation of the control IC 32 when the load 11 becomes a heavy load state during "discontinuous operation" and the oscillation frequency Fsw increases. Note that FIG. 18 corresponds to condition A4 in FIG. 3. Also, times t90, t96, t102, and t107 in FIG. 18 correspond to times t60 and t63 in FIG. 16. Also, times t91, t97, and t103 in FIG. 18 correspond to time t61 in FIG. 16. Furthermore, times t92, t98, and t104 in FIG. 18 correspond to time t62 in FIG. 16.

[0235] Furthermore, the changes in the signals btm_cmp, crst0, crst1, pwm_r, saw, and osc_out have been explained so far, so they will not be explained in detail. Furthermore, it is assumed that the up / down counter 91 outputs a count value of "3" as the signal udc_out (reference number of times) before time t90. Furthermore, it is assumed that the comparator 116 outputs the signal up_down at an "L" level before time t90, because the signal udc_out is greater than the value obtained by adding 1 to the signal dh_out.

[0236] The operation of the control IC 32 from time t90 to time t91 is the same as the operation of the control IC 32 from time t70 to time t71 in FIG. 17, and therefore will not be described again.

[0237] At time t92 when the voltage Vcs drops below the threshold voltage VrefL, the hysteresis comparator 41 outputs the signal btm_cmp at the "L" level. The up-counter 90 then counts up based on the signal btm_cmp at the "L" level, changing the signal uc_out from "0" to "1."

[0238] At this time, the signal udc_out is greater than the value of the signal dh_out plus 1, so the comparator 116 outputs the signal up_down at the "L" level. Furthermore, when the signal osc_out is input, the signal up_down does not become "L" level for a predetermined number of consecutive times (three times in this example). Therefore, the clock generation circuit 117 does not output the pulse signal udc_clk. As a result, the up / down counter 91 does not count down, and the signal udc_out remains at "3." After that, the voltage Vcs begins to oscillate.

[0239] At time t93 when the oscillator circuit 43 outputs the pulse signal osc_out, the data hold circuit 92 captures the signal uc_out and outputs it as the signal dh_out. At this time, the signal udc_out is greater than the value of the signal dh_out plus 1, so the comparator 116 outputs the signal up_down at the “L” level.

[0240] Furthermore, when the signal osc_out is input, the signal up_down does not remain at the "L" level for the predetermined number of times. Therefore, the clock generation circuit 117 does not output the pulse signal udc_clk. As a result, the up / down counter 91 does not count down, and the signal udc_out remains at "3."

[0241] At time t94 when the voltage Vcs oscillates and falls below the threshold voltage VrefL, the hysteresis comparator 41 operates in the same manner as at time t92, causing the up-counter 90 to change the signal uc_out from “1” to “2.” Then, since the signal udc_clk is not input to the up-down counter 91, the signal udc_out remains at “3.”

[0242] At time t95 when the voltage Vcs oscillates and falls below the threshold voltage VrefL, the hysteresis comparator 41 operates in the same manner as at time t92, causing the up-counter 90 to set the signal uc_out to "3." Then, since the signal udc_clk is not input to the up-down counter 91, the signal udc_out remains at "3."

[0243] At this time, the pulse signal osc_out has already been input, and the signals uc_out and udc_out match, so at time t96, after a waiting period has elapsed since time t95, the bottom controller 93 outputs the pulse signal pwm_s, and the power transistor 30 turns on.

[0244] The "standby period" is the period from time t95 when the voltage Vcs reaches the threshold VrefL to the next bottom (not shown) of the oscillation (ringing). In other words, the "standby period" is approximately ¼ of the ringing period. As a result, the bottom controller 93 can turn on the power transistor 30 at a timing when the drain-source voltage of the power transistor 30 is small.

[0245] Then, since the pulse signal pwm_s is input, the oscillator circuit 43 outputs the pulse signal osc_out at a timing when an oscillation period corresponding to the frequency Fsw has elapsed since the pulse signal pwm_s was input. Note that, from time t96 to time t102, the operation from time t90 to time t96 is repeated.

[0246] From time t102 to time t105, the operation from time t90 to time t93 is repeated.

[0247] However, at time t105, when the pulse signal osc_out was input, the state in which the signal udc_out was greater than the value of the signal dh_out plus 1 continued a predetermined number of times (for example, three times in the case of FIG. 18). That is, after the pulse signal osc_out was input, the comparator 116 output the signal up_down at the "L" level continued a predetermined number of times.

[0248] Therefore, at time t106, the clock generation circuit 117 outputs the pulse signal udc_clk. At this time, the up / down counter 91 counts down the count value from "3" to "2" and outputs the count value as the signal udc_out. Then, the comparator 116 outputs the signal up_down at the "H" level because the signal udc_out becomes equal to the value obtained by adding 1 to the signal dh_out.

[0249] As described above, when the load 11 approaches a heavy load state and the oscillation frequency Fsw increases, the control IC 32 decreases the reference count. In this case, the control IC 32 counts down the reference count, i.e., the signal udc_out, when the condition for decreasing the reference count is met a predetermined number of times. This allows the control IC 32 to prevent a sudden increase in the switching frequency Ftr and suppress audible noise from occurring in the transformer 22.

[0250] Then, at time t106, the voltage Vcs decreases and falls below the threshold voltage VrefL, causing the up-counter 90 to output the signal uc_out which is "2."

[0251] At time t107, when a waiting period has elapsed since time t106, pulse signal osc_out has already been input, and signal uc_out and signal udc_out match, so the bottom controller 93 outputs pulse signal pwm_s, turning on the power transistor 30. Then, because pulse signal pwm_s has been input, the oscillator circuit 43 subsequently outputs pulse signal osc_out at a timing when an oscillation period corresponding to frequency Fsw has elapsed since pulse signal pwm_s was input.

[0252] <<<When the voltage Vcs oscillation becomes smaller>>> However, when the control IC 32 operates in "discontinuous operation," the oscillation of the voltage Vcs may become weak for some reason, and the hysteresis comparator 41 may not be able to detect the oscillation of the voltage Vcs. In this case, the output circuit 111 cannot output the pulse signal out0. Therefore, the power transistor 30 does not turn on. In such a case, by using the generation circuit 114 shown in FIG. 20, it is possible to turn on the power transistor 30 even when the oscillation of the voltage Vcs is small.

[0253] Specifically, if the generation circuit 114 cannot detect any oscillation of the voltage Vcs at all after a predetermined period has elapsed, it generates a pulse signal out1. If it detects oscillation of the voltage Vcs even once, it generates a pulse signal out1 according to the period of the oscillation of the voltage Vcs. On the other hand, if the generation circuit 114 continues to detect oscillation of the voltage Vcs, it does not generate the pulse signal out1. Furthermore, the generation circuit 114 operates when the D flip-flop 113 outputs a signal en at an "H" level. The predetermined period corresponds to the "first period."

[0254] <<<Details of the generation circuit 114>>> The generation circuit 114 is configured to include a trigger circuit 120, timers 121 and 122, an OR element 123, and an output circuit 124. The trigger circuit 120 outputs signals that trigger the timers 121 and 122. Specifically, when no oscillation of the voltage Vcs is detected, the trigger circuit 120 outputs signals Vg1 and Vg2 that trigger the timer 121 that outputs a signal outa that is the basis of the pulse signal out1. Furthermore, when the trigger circuit 120 detects oscillation of the voltage Vcs even once, it outputs signals Vg3 and Vg4 that trigger the timer 122 that outputs a signal outb that is the basis of the pulse signal out1.

[0255] <<Trigger circuit 120>> The trigger circuit 120 includes D flip-flops 130, 133, and 135, one-shot circuits 131 and 132, AND elements 134 and 136, and a selector 137. The circuit configuration of the trigger circuit 120 will be described first with reference to Fig. 19. Then, the timers 121 and 122, the OR element 123, and the output circuit 124 will be described, followed by a description of how the generation circuit 114 operates in response to signals Vg1 to Vg4.

[0256] The D flip-flop 130 operates to generate signals Vg1 to Vg4 in response to the oscillation of the voltage Vcs. Specifically, the D flip-flop 130 is reset when the signal en is at the "L" level. Furthermore, when the signal en goes to the "H" level and the signal btm_cmp goes to the "L" level due to the oscillation of the voltage Vcs, the D flip-flop 130 outputs the "H" level signal Vg1 from its Q output.

[0257] Thereafter, each time the voltage Vcs oscillates and the signal btm_cmp becomes "L" level, the D flip-flop 130 inverts the Q output. The Q output of the D flip-flop 130 becomes the signal Vg1. As a result, the timer 121 (described later) does not output the pulse signal outa while it can detect oscillations in the voltage Vcs.

[0258] Furthermore, the one-shot circuit 131 outputs a pulse signal Vg1_osh at the rising edge of the Q output of the D flip-flop 130. The Q-bar output of the D flip-flop is set as a signal Vg1_b. The one-shot circuit 132 outputs a pulse signal Vg2 at the rising edge of the signal Vg1_b.

[0259] The D flip-flop 133 is reset when the signal en is at the “L” level. When the reset is released and the “H” level signal btm_cmp is input, the D flip-flop 133 outputs the signal en as the signal en1.

[0260] Furthermore, the AND element 134 performs a logical AND operation on the signal en1 and the pulse signal Vg1_b. The AND element 134 outputs the signal Vg3. The signal Vg3 has a logical level opposite to that of the signal Vg1 while the signal en1 is at the "H" level. As a result, similar to the case of the timer 121, the timer 122 (described later) does not output the pulse signal outb while it can detect oscillations in the voltage Vcs.

[0261] The D flip-flop 135 is reset when the signal en is at the “L” level. When the reset is released and the “H” level signal btm_cmp is input, the D flip-flop 135 outputs the signal en1 as the signal en2.

[0262] Furthermore, the AND element 136 performs a logical AND operation on the signal Vg1_b and a signal obtained by inverting the signal Vg3, and outputs the result to the selector 137. When the signal en2 is at the "L" level, the selector 137 outputs the output of the AND element 136 as the signal Vg4. On the other hand, when the signal en2 is at the "H" level, the selector 137 outputs the signal Vg1_osh as the signal Vg4.

[0263] <<Details of Timers 121 and 122>> The timer 121 starts timing when the voltage Vcs reaches the threshold voltage VrefL, and thereafter, if no oscillation of the voltage Vcs is detected at all, it outputs a pulse signal outa that is the basis of the pulse signal out1. Furthermore, if the timer 122 detects an oscillation of the voltage Vcs even once, it times a period corresponding to the oscillation period of the voltage Vcs and outputs a pulse signal outb that is the basis of the pulse signal out1. The circuits of the timers 121 and 122 will be described first with reference to FIG. 20. Then, the operation of the generation circuit 114 including the timers 121 and 122 will be described with reference to FIGS. 21 and 22. The trigger circuit 120 corresponds to a "measurement circuit," the timer 121 corresponds to a "first timer," and the timer 122 corresponds to a "second timer."

[0264] 20 is a diagram showing an example of the configuration of the timers 121 and 122. The timers 121 and 122 output a signal OUTX in response to the signals In1 and In2. Note that, since the timers 121 and 122 have the same configuration, the following description will be given taking the timer 121 as an example.

[0265] The timer 121 includes constant current sources 140 and 143, a PMOS transistor 141, NMOS transistors 142 and 145, a capacitor 144, Zener diodes 146 and 147, and a comparator 148.

[0266] When a low-level signal In1 is input to the constant current source 140, the constant current source 140 charges the capacitor 144 with a current Ic via the PMOS transistor 141. On the other hand, when a high-level signal In1 is input to the constant current source 140, the PMOS transistor 141 is turned off, and the capacitor 144 is not charged with the current Ic. The voltage generated across the capacitor 144 is referred to as a voltage Vy.

[0267] When a high-level signal In1 is input, the constant current source 143 discharges the capacitor 144 at a current Ic / 2 via the NMOS transistor 142. On the other hand, when a low-level signal In1 is input, the NMOS transistor 142 is turned off, and the constant current source 143 does not discharge the capacitor 144 at a current Ic / 2. The "capacitance value of the capacitor 144" is determined so that the voltage Vy becomes lower than the reference voltage Vref3 when a predetermined period of time has elapsed since the high-level signal In1 was input.

[0268] When an "H" level signal In2 is input, the NMOS transistor 145 turns on and clamps the voltage Vy generated across the capacitor 144 to the voltage Vzda. The voltage Vzda is the voltage clamped by the Zener diode 146. On the other hand, when an "L" level signal In2 is input, the NMOS transistor 145 turns off and does not clamp the voltage Vy to the voltage Vzda. The Zener diode 147 clamps the voltage Vy to the voltage Vzdb.

[0269] The comparator 148 compares the voltage Vy with the reference voltage Vref3 and outputs a signal OUTX. Specifically, when the signal In1 is at the “H” level, the capacitor 144 is discharged, and the voltage Vy becomes lower than the reference voltage Vref3, the comparator 148 outputs the “H” level signal OUTX.

[0270] On the other hand, when the signal In1 is at the "L" level, the capacitor 144 is charged, and the voltage Vy is higher than the voltage Vref3, the comparator 148 outputs the "L" level signal OUTX. Note that here, the voltage Vzdb>the voltage Vzda>the reference voltage Vref3.

[0271] As described above, the timers 121 and 122 discharge the capacitor 144 with a current Ic / 2 while the signal In1 is at an "H" level, and charge the capacitor 144 with a current Ic while the signal In1 is at an "L" level. At this time, if the voltage Vy exceeds the voltage Vzdb, the voltage Vy is clamped to the voltage Vzdb by the Zener diode 147. Furthermore, the timers 121 and 122 clamp the voltage Vy to the voltage Vzda while or when the signal In2 is at an "H" level. Furthermore, while the signal In2 is at an "L" level, the timers 121 and 122 clamp the voltage Vy to the voltage Vzdb if the voltage Vy exceeds the voltage Vzdb.

[0272] 19, the generation circuit 114 will be described again. The OR element 123 performs a logical OR on the pulse signal outa from the timer 121 and the pulse signal outb from the timer 122, and outputs the result as a pulse signal outc.

[0273] When the control circuit 40 outputs the signal crst0 at the "L" level, the pulse signal outc is input, and then the pulse signal osc_out is input, the output circuit 124 outputs the pulse signal out1.

[0274] On the other hand, when the control circuit 40 outputs the signal crst0 at the "L" level and the pulse signal outc is input, if the pulse signal osc_out has already been input, the output circuit 124 outputs the pulse signal out1.

[0275] Each time the control circuit 40 outputs the signal crst0 at "H" level, the output circuit 124 is reset and outputs the pulse signal out1 at "L" level.

[0276] From the above, when the trigger circuit 120 continues to output the signal Vg1 at the "H" level for a predetermined period, the timer 121 outputs the pulse signal outa. However, if the D flip-flop 130 is able to detect oscillations in the voltage Vcs, it inverts the logic level of the signal Vg1 each time the signal btm_cmp goes to the "L" level. As a result, the timer 121 does not output the pulse signal outa while it is able to detect oscillations in the voltage Vcs at a cycle shorter than the predetermined period. Note that the predetermined period corresponds to the "first period."

[0277] Similarly to the timer 121, when the trigger circuit 120 continues to output a high-level signal Vg3 for a predetermined period, the timer 122 outputs a pulse signal outb. If the trigger circuit 120 detects even one oscillation of the voltage Vcs, it outputs a signal Vg4 so that the timer 122 can output a pulse signal outb in accordance with the oscillation period. While or when the high-level signal Vg4 is being input, the voltage Vy of the timer 122 is clamped to the voltage Vzda. The operation of the timer 122 will be described in detail later.

[0278] <<<Operation of the Generation Circuit 114 When Oscillation of the Voltage Vcs is Continually Detected>>> FIG. 21 is a timing chart showing an example of the operation of the generation circuit 114 when a bottom exists in "discontinuous operation." In this case, the generation circuit 114 does not output the pulse signal out1. However, in this case, the output circuit 111 of FIG. 14 outputs the signal out0. In FIG. 21, the voltages Vzd1 and Vzd3 correspond to the voltage Vzda, and the voltages Vzd2 and Vzd4 correspond to the voltage Vzdb. The voltage Va corresponds to the voltage Vy in the timer 121, and the voltage Vb corresponds to the voltage Vy in the timer 122.

[0279] At time t110, the control IC 32 outputs a drive signal Vg at an "H" level, turning on the power transistor 30. When the power transistor 30 is turned on, the voltage Vcs rises. While the power transistor 30 is on, the control circuit 40 outputs a signal crst0 at an "H" level.

[0280] 19 outputs a signal Vg1 of a low level and a signal Vg1_b of a high level, and the one-shot circuit 132 outputs a signal Vg2 of a low level. Therefore, the voltage Va is clamped to the voltage Vzd2.

[0281] Furthermore, the AND element 134 outputs a signal Vg3 of "L" level. At this time, the selector 137 outputs a signal Vg4 of "H" level. Therefore, the voltage Vb is clamped to the voltage Vzd3.

[0282] At time t111, when the voltage Vcs reaches the voltage Vfb, the control IC 32 outputs a drive signal Vg at an "L" level, and the power transistor 30 turns off. When the power transistor 30 turns off, the voltage Vcs exceeds the threshold voltage VrefH, and the hysteresis comparator 41 outputs a signal btm_cmp at an "H" level. Furthermore, when the power transistor 30 turns off, the control circuit 40 outputs a signal crst0 at an "L" level.

[0283] When the control circuit 40 outputs the signal crst0 at the "L" level, the signal btm_cmp is at the "H" level, so the D flip-flop 113 outputs the signal en at the "H" level. Then, the D flip-flop 130 outputs the signal Vg1 at the "L" level and the signal Vg1_b at the "H" level.

[0284] At time t112, when the voltage Vcs becomes lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. At this time, the D flip-flop 130 outputs a high-level signal Vg1 and a low-level signal Vg1_b. The one-shot circuit 131 also outputs a pulse signal Vg1_osh.

[0285] Furthermore, since the D flip-flop 133 outputs the signal en1 at the "L" level, the AND element 134 outputs the signal Vg3 at the "L" level. Furthermore, since the D flip-flop 135 outputs the signal en2 at the "L" level, the selector 137 outputs the signal Vg4 at the "L" level.

[0286] At this time, the signal Vg1 goes high, causing the voltage Va to drop. Similarly, the signal Vg4 goes low, causing the voltage Vb to rise.

[0287] At time t113, when the voltage Vcs oscillates and exceeds the threshold voltage VrefH, the hysteresis comparator 41 outputs a high-level signal btm_cmp. When the high-level signal btm_cmp is input, the D flip-flop 133 outputs a high-level signal en as the signal en1. At this time, the D flip-flop 130 is outputting a low-level signal Vg1_b, so the AND element 134 continues to output a low-level signal Vg3.

[0288] At time t114, when the voltage Vcs becomes lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. At this time, the D flip-flop 130 outputs a low-level signal Vg1 and a high-level signal Vg1_b. The one-shot circuit 132 outputs a pulse signal Vg2. The timer 121 receives the pulse signal Vg2 and sets the voltage Va to the voltage Vzd1.

[0289] Furthermore, since the signal en1 and the signal Vg1_b are at the "H" level, the AND element 134 outputs the "H" level Vg3, which causes the timer 122 to reduce the voltage Vb that had been increasing.

[0290] At time t115, when the voltage Vcs oscillates and exceeds the threshold voltage VrefH, the hysteresis comparator 41 outputs an “H” level signal btm_cmp. When the “H” level signal btm_cmp is input, the D flip-flop 135 outputs an “H” level signal en1 as the signal en2.

[0291] At time t116, when the voltage Vcs becomes lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. At this time, the D flip-flop 130 outputs a high-level signal Vg1 and a low-level signal Vg1_b. The high-level signal Vg1 input to the timer 121 reduces the voltage Va. Since the signal Vg1 becomes high, the one-shot circuit 131 outputs a pulse signal Vg1_osh.

[0292] Furthermore, since the signal Vg1_b is at the “L” level, the AND element 134 outputs the “L” level signal Vg3. Furthermore, since the signal en2 is at the “H” level, the selector 137 outputs the pulse signal Vg1_osh as the signal Vg4.

[0293] The operation of the generation circuit 114 between time t117 and time t123 is the same as the operation of the generation circuit 114 between time t110 and time t116, and therefore will not be described.

[0294] At time t124, when the voltage Vcs oscillates and exceeds the threshold voltage VrefH, the hysteresis comparator 41 outputs the signal btm_cmp at the “H” level.

[0295] At time t125, when the voltage Vcs becomes lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. At this time, the D flip-flop 130 outputs a low-level signal Vg1 and a high-level signal Vg1_b. Furthermore, since the signal Vg1_b becomes high, the one-shot circuit 132 outputs a pulse signal Vg2. Furthermore, when the pulse signal Vg2 is output, the timer 121 sets the voltage Va to the voltage Vzd1.

[0296] Furthermore, since the signal en1 is at the "H" level, the AND element 134 outputs the "H" level signal Vg1_b as the signal Vg3, causing the timer 122 to decrease the voltage Vb.

[0297] At time t126, the control IC 32 outputs an "H" level drive signal Vg, turning on the power transistor 30. When the power transistor 30 turns on, the control circuit 40 outputs an "H" level signal crst0, and the generation circuit 114 is reset.

[0298] From the above, from time t110 to time t126, neither of the voltages Va nor Vb drops below the reference voltage Vref3, and therefore the pulse signals outa, outb, and outc are not output. As a result, when oscillation of the voltage Vcs is detected, the generation circuit 114 does not output the pulse signal out1. Therefore, when oscillation of the voltage Vcs is detected, the output circuit 111 in FIG. 14 turns on the power transistor 30 at an appropriate timing.

[0299] <<<<Operation of the Generation Circuit 114 When Oscillation of the Voltage Vcs Cannot Be Detected or When It Becomes Undetectable Halfway Through>>> FIG. 22 is a timing chart showing an example of the operation of the generation circuit 114 when the bottom disappears in "discontinuous operation." In this case, the generation circuit 114 outputs a pulse signal out1. In FIG. 22, voltages Vzd1 and Vzd3 correspond to voltage Vzda, and voltages Vzd2 and Vzd4 correspond to voltage Vzdb. Voltage Va corresponds to voltage Vy in timer 121, and voltage Vb corresponds to voltage Vy in timer 122.

[0300] [Operation of the generation circuit 114 when oscillation of the voltage Vcs cannot be detected] First, in order to explain the operations of trigger circuit 120 and timer 121, the operation of generation circuit 114 between time t130 and time t134 will be explained.

[0301] The operation of the generation circuit 114 between time t130 and time t132 is the same as the operation of the generation circuit 114 between time t110 and time t112 in FIG. 21, and therefore will not be described.

[0302] At time t133, a predetermined period has elapsed since the D flip-flop 130 output the “H” level signal Vg1 at time t132. Furthermore, since no oscillation in the voltage Vcs has been detected up to that point, the voltage Va falls below the reference voltage Vref3, and the timer 121 outputs the “H” level pulse signal outa.

[0303] At time t134, when the oscillator circuit 43 outputs the pulse signal osc_out, since the pulse signal outa has already been output, the generator circuit 114 outputs the pulse signal out1, turning on the power transistor 30. When the power transistor 30 turns on, the control circuit 40 outputs the signal crst0 at an “H” level, so that the generator circuit 114 is reset.

[0304] [Operation of the generation circuit 114 when oscillation of the voltage Vcs becomes undetectable midway] Next, in order to explain the operations of the trigger circuit 120 and the timer 122, the operation of the generation circuit 114 between time t134 and time t140 will be explained.

[0305] The operation of the generation circuit 114 between time t134 and time t136 is the same as the operation of the generation circuit 114 between time t110 and time t112 in FIG. 21, and therefore will not be described.

[0306] At time t137, when the voltage Vcs oscillates and exceeds the threshold voltage VrefH, the hysteresis comparator 41 outputs the signal btm_cmp at the “H” level. At this time, the D flip-flop 133 outputs the signal en at the “H” level as the signal en1.

[0307] At time t138, when the voltage Vcs becomes lower than the threshold voltage VrefL, the hysteresis comparator 41 outputs a low-level signal btm_cmp. At this time, the D flip-flop 130 outputs a low-level signal Vg1 and a high-level signal Vg1_b. Furthermore, since the signal Vg1_b becomes high, the one-shot circuit 132 outputs a pulse signal Vg2. Furthermore, when the pulse signal Vg2 is output, the timer 121 sets the voltage Va to the voltage Vzd1.

[0308] Furthermore, since the signal en1 is at the “H” level, the AND element 134 outputs the “H” level signal Vg1_b as the signal Vg3. When the “H” level signal Vg3 is input, the timer 122 reduces the voltage Vb.

[0309] At time t139, a predetermined period elapses after the AND element 134 outputs the "H" level signal Vg3. At this time, the voltage Vb becomes lower than the reference voltage Vref3. Therefore, the timer 122 outputs the "H" level signal outb.

[0310] At time t140, when the oscillator circuit 43 outputs the pulse signal osc_out, since the pulse signal outb has already been output, the generator circuit 114 outputs the pulse signal out1, turning on the power transistor 30. When the power transistor 30 turns on, the control circuit 40 outputs the signal crst0 at an “H” level, so that the generator circuit 114 is reset.

[0311] As a result, the timer 122 charges the capacitor 144 with the current Ic and discharges the capacitor 144 with the current Ic / 2. Therefore, the period from time t138 to time t139 is approximately twice the period from time t136 to time t138. This allows the timer 122 to output the pulse signal outb in accordance with the oscillation period of the voltage Vcs. The period from time t138 to time t139 corresponds to the "second period."

[0312] === Variations === The hysteresis comparator 41 has a hysteresis characteristic that changes the output depending on the threshold voltages VrefH and VrefL. However, the comparator for detecting the voltage Vcs does not necessarily have to have a hysteresis characteristic.

[0313] Although the hysteresis comparator 41 detects the voltage Vcs in the above embodiment, it may also detect the voltage Vcc at the terminal VCC instead of the voltage Vcs. Furthermore, the hysteresis comparator 41 may detect a voltage that changes in accordance with the voltage Vx of the high-potential side electrode of the power transistor 30 (for example, a voltage in accordance with the inductor current IL1).

[0314] Although the up counter 90 is used to detect whether the AC-DC converter 12 is operating discontinuously, the circuit that stores the number of bottoms in response to the oscillation of the voltage Vcs is not limited to an up counter. For example, the circuit that stores the number of bottoms may be an up-down counter, a down counter, or the like.

[0315] ===Summary=== (1) The AC-DC converters 10 and 12 of this embodiment have been described above. The control IC 32 includes a control circuit 40, a second determination circuit consisting of a hysteresis comparator 41, an up-counter 90, and a determination circuit 110, an oscillation circuit 43, and a switching control circuit 44. The control circuit 40 and the second determination circuit enable the control IC 32 to switch the power transistor 30 in accordance with the state of the load 11. This makes it possible to provide an integrated circuit that appropriately controls the AC-DC converter in accordance with the state of the load.

[0316] (2) The switching control circuit 44 also includes a signal generating circuit 100 and an OFF signal output circuit including a comparator 53, an overcurrent protection circuit 54, a timer 55, an AND element 56, and an OR element 57. This allows the control IC 32 to switch the power transistor 30 according to the state of the load 11 and the operating state of the AC-DC converter 12.

[0317] (3) Furthermore, the oscillator circuit 43 outputs a pulse signal osc_out whose frequency increases as the load current Iout increases, thereby enabling the AC-DC converters 10 and 12 to supply power to the load 11 according to the state of the load 11.

[0318] (4) Furthermore, the control circuit 40 detects the state of the load 11 based on the voltage Vfb corresponding to the output voltage Vout, and the oscillation circuit 43 changes the frequency of the pulse signal osc_out based on the voltage Vfb. This allows the control IC 32 to control the AC-DC converter 10 or the AC-DC converter 12 according to the state of the load 11.

[0319] (5) Furthermore, if the pulse signal pwm_s is input to the oscillator circuit 43 before the oscillation period has elapsed since the pulse signal osc_out was output, the oscillator circuit 43 measures the oscillation period again and outputs the pulse signal osc_out, so that the switching frequency Ftr of the power transistor 30 becomes approximately the same as the oscillation frequency Fsw.

[0320] (6) Furthermore, the oscillation circuit 43 is realized by the circuit shown in Fig. 4. This makes it possible to output a pulse signal osc_out having an oscillation frequency Fsw according to the voltage Vfb, that is, the state of the load 11.

[0321] (7) The second determination circuit includes a hysteresis comparator 41, an up-counter 90, and a determination circuit 110. This allows the control IC 32 to determine, with a simple circuit, whether the AC-DC converter 12 is operating discontinuously or continuously.

[0322] (8) The signal generating circuit 100 also includes a timer 121. This allows the control IC 32 to turn on the power transistor 30 after a predetermined period has elapsed, even if the control IC 32 cannot detect any oscillation in the voltage Vcs.

[0323] (9) The signal generating circuit 100 also includes a trigger circuit 120 and a timer 122. As a result, if the control IC 32 detects a bottom even once while the power transistor 30 is off, it turns on the power transistor 30 at a timing based on the cycle of the bottom.

[0324] (10) The control IC 32 also includes a hysteresis comparator 41, an oscillator circuit 43, a comparator 53, an overcurrent protection circuit 54, a timer 55, an OFF signal output circuit including an AND element 56 and an OR element 57, an up / down counter 91, and an adjustment circuit 101. This allows the control IC 32 to differentiate between the first condition and the second condition, preventing a sudden increase in the switching frequency Ftr. This makes it possible to suppress audible noise generated in the transformer 22.

[0325] (11) The control IC 32 also includes an up-counter 90 and a data hold 92. This allows the control IC 32 to determine whether to increase or decrease the switching frequency Ftr based on the timing at which the pulse signal osc_out is input.

[0326] (12) Furthermore, the signal generating circuit 100 includes a determination circuit 110, and the adjustment circuit 101 includes a comparator 115. This allows the control IC 32 to detect the operating state of the AC-DC converter 12 and determine the timing to turn on the power transistor 30.

[0327] (13) The adjustment circuit 101 also includes a comparator 116 and a clock generation circuit 117. This allows the control IC 32 to appropriately control the up / down counter 91 that holds the reference number of times, and change the switching frequency Ftr according to the state of the load 11.

[0328] (14) Furthermore, the signal generating circuit 100 outputs a pulse signal pwm_s based on the comparison results of the comparators 115 and 116 and the pulse signal osc_out. This allows the control IC 32 to prevent a sudden change in the switching frequency Ftr even if the oscillation frequency Fsw changes suddenly. This suppresses audible noise from the transformer 22.

[0329] (15) Furthermore, if the pulse signal pwm_s is input to the oscillator circuit 43 before the oscillation period has elapsed since the pulse signal osc_out was output, the oscillator circuit 43 measures the oscillation period again and outputs the pulse signal osc_out, thereby making the switching frequency Ftr of the power transistor 30 substantially equal to the oscillation frequency Fsw.

[0330] (16) The oscillator circuit 43 is realized by the circuit shown in Fig. 4. This makes it possible to output a pulse signal osc_out having an oscillation frequency Fsw according to the voltage Vfb, that is, the state of the load 11.

[0331] (17) The signal generating circuit 100 also includes a timer 121. This allows the control IC 32 to turn on the power transistor 30 after a predetermined period has elapsed, even if the control IC 32 cannot detect any oscillation in the voltage Vcs.

[0332] (18) The signal generating circuit 100 also includes a trigger circuit 120 and a timer 122. As a result, if the control IC 32 detects a bottom even once while the power transistor 30 is off, it turns on the power transistor 30 at a timing based on the cycle of the bottom.

[0333] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0334] 10,12 AC-DC converter 11 Load 20 Full wave rectifier circuit 21, 25, 33, 35, 38, 74, 144 capacitors 22 Transformer 23,28 Control Blocks 24,36,80 diodes 26 Constant voltage circuit 27 Light-emitting diode 30 Power transistor 31, 34, 37, 42, 81 Resistance 39 Phototransistor 40 Control circuit 41 Hysteresis Comparator 43 Oscillator Circuit 44 Switching control circuit 50 Bottom switch circuit 51 SR Flip-Flop 53,75,148 Comparator 54 Overcurrent protection circuit 55,121,122 Timer 56,134,136 AND elements 52, 57, 77, 112, 123 OR elements 58 buffers 59 Low voltage protection circuit 60 Soft start circuit 70,71 current source 72,73 Switch 76 Delay Circuit 78 Inverter 90 Up Counter 91 Up / Down Counter 92 Data Hold 93 Bottom Controller 100 Signal generation circuit 101 Adjustment circuit 110 Judgment circuit 111,124 Output circuit 113,130,133,135 D flip-flops 114 Generation circuit 115,116 Comparator 117 Clock Generation Circuit 120 Trigger Circuit 131,132 One-shot circuit 137 Selector 140,143 constant current source 141 PMOS transistor 142,145 NMOS transistors 146,147 Zener diode

Claims

1. An integrated circuit for driving a transistor of a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, the power supply circuit including a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls a current flowing through the primary coil, a first determination circuit that determines whether the load state is a heavy load or a light load; a second determination circuit that determines whether the mode is a continuous mode in which the current in the secondary coil does not become zero when the transistor is off, or a discontinuous mode in which the current in the secondary coil becomes zero when the transistor is off; an oscillation circuit that outputs an oscillation signal; a switching control circuit that controls switching of the transistor based on the determination result of the second determination circuit and the oscillation signal when the load state is a light load, and controls switching of the transistor based on the oscillation signal when the load state is a heavy load regardless of the determination result of the second determination circuit; Equipped with The oscillator circuit comprises: When an on signal for turning on the transistor is input within a period corresponding to the frequency of the oscillation signal after the oscillation signal is output, the oscillation signal is output at a timing when the period has elapsed since the on signal was input. Integrated circuit.

2. 10. The integrated circuit of claim 1, The switching control circuit an on-signal output circuit that outputs an on-signal for turning on the transistor based on the oscillation signal in a first case where the load state is a light load and the current in the secondary coil is in the continuous mode, or in a second case where the load state is a heavy load, and outputs the on-signal based on the oscillation signal and a first voltage corresponding to the voltage on the high potential side of the transistor in a third case where the load state is a light load and the current in the secondary coil is in the discontinuous mode; an off signal output circuit that outputs an off signal for turning off the transistor based on a current flowing through the transistor; An integrated circuit comprising:

3. 3. An integrated circuit according to claim 2, the oscillation circuit outputs the oscillation signal whose frequency increases as the load current flowing through the load increases. Integrated circuit.

4. 4. An integrated circuit according to claim 3, the first determination circuit determines, based on a feedback voltage corresponding to the output voltage and a predetermined voltage, that the load state is a heavy load when a load current flowing through the load is greater than a predetermined value, and determines that the load state is a light load when the load current is smaller than the predetermined value; the oscillation circuit changes the frequency of the oscillation signal based on the feedback voltage. Integrated circuit.

5. The integrated circuit according to any one of claims 2 to 4, The oscillator circuit comprises: a first timing circuit that starts timing based on the oscillation signal or the ON signal; an oscillation signal output circuit that outputs the oscillation signal when the first timing circuit has timed a period corresponding to the frequency of the oscillation signal; An integrated circuit comprising:

6. An integrated circuit according to any one of claims 2 to 5, The second determination circuit a comparison circuit that compares the first voltage corresponding to the voltage on the high potential side of the transistor when the transistor is off with a second voltage; a counter that counts the number of times the first voltage becomes the second voltage; a mode determination circuit that determines whether the current in the secondary coil is in the continuous mode or the discontinuous mode based on the count value of the counter when the oscillation signal is input; Including, The on signal output circuit is In the third case, the oscillation signal is input, and the ON signal is output after the count value of the counter reaches a predetermined value. An integrated circuit comprising:

7. 7. An integrated circuit according to claim 6, The on signal output circuit is a first timer that outputs the on signal when a first period has elapsed after the first voltage has become the second voltage; Integrated circuit.

8. 8. An integrated circuit according to claim 6 or claim 7, The on signal output circuit is a measurement circuit that measures a period during which the first voltage becomes the second voltage; a second timer that outputs the on signal when a second period corresponding to the measured cycle has elapsed after the first voltage has become the second voltage; An integrated circuit comprising:

9. A power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor for controlling a current flowing through the primary coil; an integrated circuit that drives the transistor; Equipped with The integrated circuit comprises: a first determination circuit that determines whether the load state is a heavy load or a light load; a second determination circuit that determines whether the mode is a continuous mode in which the current in the secondary coil does not become zero when the transistor is off, or a discontinuous mode in which the current in the secondary coil becomes zero when the transistor is off; an oscillation circuit that outputs an oscillation signal; a switching control circuit that controls switching of the transistor based on the determination result of the second determination circuit and the oscillation signal when the load state is a light load, and controls switching of the transistor based on the oscillation signal when the load state is a heavy load regardless of the determination result of the second determination circuit; Equipped with The oscillator circuit comprises: When an on signal for turning on the transistor is input within a period corresponding to the frequency of the oscillation signal after the oscillation signal is output, the oscillation signal is output at a timing when the period has elapsed since the on signal was input. power circuit.

10. An integrated circuit for driving a transistor of a power supply circuit that generates an output voltage of a predetermined level from an input voltage to a load, the power supply circuit including a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a transistor that controls a current flowing through the primary coil, a first determination circuit that determines whether the load state is a heavy load or a light load; a second determination circuit that determines whether the mode is a continuous mode in which the current in the secondary coil does not become zero when the transistor is off, or a discontinuous mode in which the current in the secondary coil becomes zero when the transistor is off; an oscillation circuit that outputs an oscillation signal; a switching control circuit that controls switching of the transistor based on the determination result of the second determination circuit and the oscillation signal when the load state is a light load, and controls switching of the transistor based on the oscillation signal when the load state is a heavy load regardless of the determination result of the second determination circuit; The first determination circuit comprises: An integrated circuit that determines, based on a feedback voltage corresponding to the output voltage and a predetermined voltage, that the load state is a heavy load when the load current flowing through the load is greater than a predetermined value, and that the load state is a light load when the load current is smaller than the predetermined value.

11. 11. The integrated circuit of claim 10, The switching control circuit an on-signal output circuit that outputs an on-signal for turning on the transistor based on the oscillation signal in a first case where the load state is a light load and the current in the secondary coil is in the continuous mode, or in a second case where the load state is a heavy load, and outputs the on-signal based on the oscillation signal and a first voltage corresponding to the voltage on the high potential side of the transistor in a third case where the load state is a light load and the current in the secondary coil is in the discontinuous mode; an off signal output circuit that outputs an off signal for turning off the transistor based on a current flowing through the transistor; An integrated circuit comprising:

12. 12. The integrated circuit of claim 11, the oscillation circuit outputs the oscillation signal whose frequency increases as the load current increases. Integrated circuit.

13. 11. The integrated circuit of claim 10, a predetermined terminal to which a voltage corresponding to a current flowing through the transistor is applied; further comprising a comparator for detecting a voltage at the predetermined terminal; the comparator determines whether or not a predetermined external circuit is connected to the predetermined terminal by comparing the voltage of the predetermined terminal with a predetermined threshold value of the comparator at the moment the transistor is turned off; when it is determined that the predetermined external circuit is connected to the predetermined terminal, switching of the transistor is controlled based on the determination result of the second determination circuit and the oscillation signal; when it is determined that the predetermined external circuit is not connected to the predetermined terminal, the second determination circuit cannot determine whether the mode is the continuous mode or the discontinuous mode, and the switching of the transistor is controlled based on the oscillation signal; the oscillation circuit changes the frequency of the oscillation signal based on the feedback voltage. Integrated circuit.

14. The integrated circuit according to any one of claims 11 to 12, The oscillator circuit comprises: When the on signal is input within a period corresponding to the frequency of the oscillation signal after the oscillation signal is output, the oscillation signal is output at a timing when the period has elapsed since the on signal was input. Integrated circuit.

15. The integrated circuit according to any one of claims 11 to 12, The oscillator circuit comprises: a first timing circuit that starts timing based on the oscillation signal or the ON signal; an oscillation signal output circuit that outputs the oscillation signal when the first timing circuit has timed a period corresponding to the frequency of the oscillation signal; An integrated circuit comprising:

16. 16. An integrated circuit according to any one of claims 11 to 12 or 14 to 15, The second determination circuit a comparison circuit that compares the first voltage corresponding to the voltage on the high potential side of the transistor when the transistor is off with a second voltage; a counter that counts the number of times the first voltage becomes the second voltage; a mode determination circuit that determines whether the current in the secondary coil is in the continuous mode or the discontinuous mode based on the count value of the counter when the oscillation signal is input; Including, The on signal output circuit is In the third case, the oscillation signal is input, and the ON signal is output after the count value of the counter reaches a predetermined value. An integrated circuit comprising:

17. 17. An integrated circuit according to claim 16, comprising: The on signal output circuit is a first timer that outputs the on signal when a first period has elapsed after the first voltage has become the second voltage; Integrated circuit.

18. 18. An integrated circuit according to claim 16 or claim 17, The on signal output circuit is a measurement circuit that measures a period during which the first voltage becomes the second voltage; a second timer that outputs the on signal when a second period corresponding to the measured cycle has elapsed after the first voltage has become the second voltage; An integrated circuit comprising:

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