Semiconductor substrate and manufacturing method thereof

Abstract

To enhance the manufacturing efficiency of a semiconductor device.SOLUTION: A semiconductor substrate includes a base substrate; a template substrate having a first seed area and first selection growth area arranged in a first direction and having a first convex body in the first selection growth area; and a first nitride semiconductor part positioned on the first seed area and the first selection growth area, having a longitudinal shape extended in a second direction orthogonal to the first direction and including a constriction part contacting the outer peripheral surface of the first convex body.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor substrates and methods for manufacturing the same. [Background technology]

[0002] BACKGROUND ART Conventionally, a method is known in which a semiconductor device is formed by forming a layered structure of nitride semiconductors on a gallium nitride (GaN) substrate, and then cleaving and dividing the GaN substrate and the layered structure.

[0003] Patent Document 1 discloses a technique for improving the yield of cleavage by inducing cleavage of a GaN substrate and a laminated structure in a predetermined direction along a line on which a plurality of cleavage inducing members are arranged. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2006 / 041134 Summary of the Invention [Problem to be solved by the invention]

[0005] Improve the manufacturing efficiency of semiconductor devices. [Means for solving the problem]

[0006] In one embodiment of the present disclosure, a semiconductor substrate includes a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, with a first convex body provided in the first selective growth region, and a first nitride semiconductor portion located on the first seed region and the first selective growth region, having an elongated shape extending in a second direction perpendicular to the first direction, and having a constricted portion in contact with the outer peripheral surface of the first convex body.

[0007] A method for manufacturing a semiconductor substrate in one aspect of the present disclosure includes the steps of: preparing a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, with a first convex body provided in the first selective growth region; and stopping the growth of a first nitride semiconductor portion having an elongated shape extending in a second direction perpendicular to the first direction, the first nitride semiconductor portion growing from on the first seed region onto the first selective growth region, and contacting an outer peripheral surface of the first convex body, after a constricted portion contacting the outer peripheral surface is formed in the first nitride semiconductor portion. [Effects of the Invention]

[0008] The manufacturing efficiency of semiconductor devices can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view schematically illustrating a configuration of a semiconductor substrate according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along the line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. [Figure 4] 3 is a partially enlarged view of FIG. 2, showing the semiconductor substrate in a state having a stress concentration portion before cracks occur in the first nitride semiconductor portion. FIG. [Figure 5] FIG. 10 is a plan view schematically illustrating a configuration of a semiconductor substrate according to another embodiment. [Figure 6] FIG. 3 is an enlarged plan view showing the periphery of a first convex body, illustrating an example of the shape of the first convex body. [Figure 7] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. [Figure 8] 1 is a block diagram illustrating an example of a semiconductor substrate manufacturing apparatus according to an embodiment of the present disclosure. [Figure 9] 1 is a plan view schematically illustrating a configuration of a semiconductor substrate in Example 1. FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX in FIG. 9. [Figure 11] FIG. 2 is a cross-sectional view showing an example of the configuration of a template substrate. [Figure 12] 3 is an enlarged cross-sectional view showing a first protrusion of a semiconductor substrate in Example 1. FIG. [Figure 13] 3 is an enlarged plan view showing a first protrusion of the semiconductor substrate in Example 1. FIG. [Figure 14] 1A to 1C are cross-sectional views schematically showing a method for manufacturing a template substrate included in a semiconductor substrate in Example 1. [Figure 15] 2 is a cross-sectional view showing an example of lateral growth of a nitride semiconductor portion included in a semiconductor substrate in Example 1. FIG. [Figure 16] 1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 17] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] 1 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. FIG. [Figure 19] FIG. 2 is a perspective view showing another configuration of the semiconductor device obtained in Example 1. [Figure 20] 10 is a plan view showing a method for manufacturing a semiconductor substrate and a semiconductor device using the semiconductor substrate in Example 2. [Figure 21] FIG. 10 is a perspective view showing the configuration of a semiconductor device obtained in Example 2. [Figure 22] FIG. 10 is a perspective view showing a structural example of a semiconductor device according to a second embodiment. [Figure 23] 10A to 10C are cross-sectional views showing a method for manufacturing a template substrate included in a semiconductor substrate in Example 3. [Figure 24] 10 is a diagram for explaining the stress state of a first nitride semiconductor portion in which a crack is formed in a semiconductor substrate in Example 4. FIG. [Figure 25] 10 is a diagram for explaining the stress state of a first nitride semiconductor portion in which no cracks are formed, of a semiconductor substrate in Example 4. FIG. [Figure 26]25 is an image showing the stress measurement results of the diagram indicated by reference numeral 2502 in FIG. 25 with the scale of the color bar changed. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, the following description is intended to provide a better understanding of the gist of the present disclosure and does not limit the present disclosure unless otherwise specified. The shapes and dimensions (length, width, etc.) of the configurations shown in the drawings in this application do not necessarily reflect the actual shapes and dimensions, and have been changed as appropriate for the clarity and simplification of the drawings.

[0011] [Semiconductor substrate] FIG. 1 is a cross-sectional view schematically illustrating the configuration of a semiconductor substrate according to an embodiment of the present disclosure. FIG. 2 is a plan view schematically illustrating the configuration of a semiconductor substrate according to an embodiment of the present disclosure. FIG. 1 shows a cross-sectional view taken along line II in FIG. 2. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. As in FIG. 2 and other figures in the present disclosure, hatching may be applied to each component in the plan view for clarity of illustration. This also applies to the other figures described below.

[0012] As shown in FIGS. 1 to 3, a semiconductor substrate 10 according to an embodiment of the present disclosure includes a template substrate 7 and a first nitride semiconductor portion 8F. The template substrate 7 includes a base substrate BS and has a first seed region 4F and a first selective growth region 6F aligned in a first direction (X direction). The template substrate 7 has a first protruding body 21P provided in the first selective growth region 6F. The first nitride semiconductor portion 8F is located on the first seed region 4F and the first selective growth region 6F of the template substrate 7, and has an elongated shape extending in a second direction (Y direction) perpendicular to the first direction. The first nitride semiconductor portion 8F has a constricted portion CP in contact with an outer peripheral surface 21S of the first protruding body 21P. The first nitride semiconductor portion 8F may be a nitride semiconductor layer (e.g., a nitride semiconductor crystal).

[0013] The template substrate 7 has a selective growth portion (deposition suppression portion) 20 on the base substrate BS, and the first nitride semiconductor portion 8F can be selectively grown by this selective growth portion 20. The selective growth portion 20 includes a first thin portion 21T, a first convex body 21P, and an opening K.

[0014] The first thin portion 21T is formed from a material on which a nitride semiconductor is difficult to deposit, and functions as a selective growth mask for lateral growth of the first nitride semiconductor portion 8F. The first protrusion 21P has a convex shape that protrudes upward from the base substrate BS or the first thin portion 21T, and the thickness (height) of the first protrusion 21P may be greater than the thickness of the first nitride semiconductor portion 8F. The first protrusion 21P is formed from a material on which a nitride semiconductor is difficult to deposit.

[0015] The opening K may have a longitudinal shape extending in the second direction (Y direction). A portion of the upper surface of the base substrate BS that overlaps with the opening K may be a first seed region 4F. First thin portion 21T and first convex body 21P may be located above at least a part of the portion of the upper surface of the base substrate BS other than the first seed region 4F.

[0016] The first nitride semiconductor portion 8F grows laterally on the first thin portion 21T, starting from the first seed region 4F. Then, after the first nitride semiconductor portion 8F grows laterally to a position where it contacts the outer peripheral surface 21S of the first protrusion 21P, it continues to grow along the outer peripheral surface 21S of the first protrusion 21P. As a result, a constricted portion CP may be formed in at least a part of the first nitride semiconductor portion 8F.

[0017] The first protrusion 21P may have any structure that allows the constricted portion CP to be formed in the first nitride semiconductor portion 8F, and the specific structure of the first protrusion 21P is not particularly limited. For example, the first protrusion 21P may have a core portion that serves as a central core and a surface layer portion that covers the core portion, and the surface layer portion may be provided continuously (integrally) with the first thin portion 21T. The core portion may be formed on the base substrate BS, and may be made of any material that can be covered by the surface layer portion to form the first protrusion 21P. The specific material of the core portion is not limited. Alternatively, the first protrusion 21P may be provided separately on the first thin portion 21T.

[0018] The outer peripheral surface 21S of the first protrusion 21P includes a first end face EF that contacts the constricted portion CP. The constricted portion CP of the first nitride semiconductor portion 8F may have a shape that follows the shape of the first end face EF. The first nitride semiconductor portion 8F may include a crack C that extends in the first direction (X direction) and reaches the constricted portion CP.

[0019] Furthermore, in the semiconductor substrate 10 of this embodiment, the selective growth portion 20 may have opposing first thin portions 21TA and opposing first protrusions 21PA located on opposite sides in the first direction (X direction) across the opening K, so as to correspond to the first thin portions 21T and the first protrusions 21P, respectively. A detailed description of the opposing first thin portions 21TA and opposing first protrusions 21PA corresponding to the first thin portions 21T and the first protrusions 21P, respectively, will not be repeated.

[0020] The first nitride semiconductor portion 8F includes a nitride semiconductor as a main material (main component). The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0021] The first nitride semiconductor portion 8F may be doped (for example, n-type including donors) or non-doped. The semiconductor substrate means a substrate including a nitride semiconductor, and the base substrate BS may include a semiconductor other than a nitride semiconductor (for example, a silicon-based semiconductor) or a non-semiconductor (for example, an insulator).

[0022] The first nitride semiconductor portion 8F can be formed by an ELO (Epitaxial Lateral Overgrowth) method, starting from the first seed region 4F (the upper surface of the base substrate BS exposed at the opening K). The first nitride semiconductor portion 8F may be formed by the ELO method, for example, using a template substrate 7 including a base substrate BS and a mask pattern (described later) on the base substrate BS. The first nitride semiconductor portion 8F may be formed by the ELO method using a template substrate 7 having a growth-inhibiting region (for example, a region that inhibits crystal growth in the c-axis direction) and a seed region corresponding to the opening K. The first seed region 4F may be any region that serves as a starting point for growth of the first nitride semiconductor portion 8F. The template substrate 7 may have, for example, the first seed region 4F and a first selective growth region 6F on the upper surface of the base substrate BS, in which case the template substrate 7 may not have a first thin portion 21T.

[0023] In FIG. 1 and other figures, the <11-20> direction of the nitride semiconductor is the X direction, the <1-100> direction of the nitride semiconductor is the Y direction, and <0001> The first direction may be the m-axis direction (<11-20> direction) of the first nitride semiconductor portion 8F, and the second direction may be the a-axis direction (<1-100> direction) of the first nitride semiconductor portion 8F. The Z direction (thickness direction) may be the c-axis direction (<11-20> direction) of the first nitride semiconductor portion 8F. <0001> In the following description of this specification, the X, Y, and Z directions are similarly defined, and the X, Y, and Z axes (arrows are used to refer to the directions) are appropriately illustrated in the drawings. In the semiconductor substrate 10, the direction from the base substrate BS to the first nitride semiconductor portion 8F is referred to as "upward." In addition, in this specification, viewing a certain component from the Z direction, in other words, viewing the component from a line of sight parallel to the normal direction of the top surface of a substantially flat component (e.g., the semiconductor substrate 10) (including perspective views), may be referred to as "planar view." This also applies to the following description, and a repeated explanation will be omitted.

[0024] In the ELO method, a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used as the base substrate BS or a main substrate (not shown) included in the base substrate BS. The first nitride semiconductor portion 8F can be laterally grown using a template substrate 7 including the heterogeneous substrate. Examples of the heterogeneous substrate include a single-crystal silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate.

[0025] Generally, when the material of the growth substrate used in the ELO method is different from the material of the semiconductor layer grown on the growth substrate by the ELO method, the following problem can occur: When a semiconductor substrate obtained by depositing a semiconductor layer on a growth substrate under high temperature conditions is cooled to room temperature, internal stress (compressive stress or tensile stress) occurs in the semiconductor layer due to the difference in thermal expansion coefficient between the growth substrate and the semiconductor layer.

[0026] For example, a semiconductor substrate in which a GaN layer is grown on a sapphire substrate by the ELO method will have a curved shape with upward warping when cooled to room temperature. Also, a semiconductor substrate in which a GaN layer is grown on a Si substrate or SiC substrate by the ELO method will have a curved shape with downward warping when cooled to room temperature. The curvature of the semiconductor substrate can cause unwanted cracks in the semiconductor layer and make it difficult to perform lithography processes in later processes.

[0027] As a result of extensive research, the present inventors have obtained new knowledge, which will be explained below with reference to FIG.

[0028] Fig. 4 is a partially enlarged view of Fig. 2, showing the state before cracks C (see Fig. 2) occur in the first nitride semiconductor portion 8F. In Fig. 4, arrows are used to schematically indicate the stress directions of internal stresses occurring in the first nitride semiconductor portion 8F.

[0029] When the base substrate BS includes, for example, a silicon substrate, the following can be said. That is, when the semiconductor substrate 10 on which the first nitride semiconductor portion 8F has been formed under high-temperature conditions is cooled to room temperature, the first nitride semiconductor portion 8F and the base substrate BS contract as the temperature decreases. The first nitride semiconductor portion 8F contracts to a greater extent than the base substrate BS. In the semiconductor substrate 10 of this embodiment, the first convex body 21P forms a constricted portion CP in the first nitride semiconductor portion 8F. In this case, as shown in FIG. 4, a stress concentration portion SP occurs near the constricted portion CP.

[0030] The tip of first protrusion 21P on the side of first end facet EF in the first direction in plan view is referred to as first end 21X. Stress concentrating portion SP may be located at a portion where first protrusion 21P and first nitride semiconductor portion 8F are in contact, or may be located in a peripheral portion of first end 21X. At least a portion of first nitride semiconductor portion 8F is bonded and fixed in position on template substrate 7. Therefore, in response to contraction of first nitride semiconductor portion 8F including a nitride semiconductor, tensile stress may be generated in first nitride semiconductor portion 8F from base substrate BS including a silicon substrate.

[0031] The compressive stress and tensile stress described above tend to cause cracks C to form near the first end 21X of the constricted portion CP. By causing cracks C to form in the first nitride semiconductor portion 8F, the semiconductor substrate 10 can relieve the internal stress that has occurred in the first nitride semiconductor portion 8F. For example, by generating strong internal stress in the stress concentration portion SP, cracks C are spontaneously formed in the first nitride semiconductor portion 8F when the temperature is lowered to room temperature after film formation, and as a result, the internal stress in the first nitride semiconductor portion 8F can be relieved.

[0032] It is also possible to generate a relatively weak internal stress in the stress concentration portion SP to the extent that cracks C do not spontaneously form, and in this case, the semiconductor substrate 10 can be subjected to a subsequent process in a state in which cracks C have not been formed. Then, cracks C can be easily formed by applying an external force at a desired time (timing) in the subsequent process, and as a result, the internal stress of the first nitride semiconductor portion 8F can be alleviated.

[0033] The strength of the internal stress generated in the stress concentration portion SP when the temperature is lowered to room temperature after film formation can be adjusted by various methods. For example, the internal stress generated in the stress concentration portion SP can be weakened by reducing the thickness of the first nitride semiconductor portion 8F or increasing the thickness of the base substrate BS. Furthermore, the shape of the first convex body 21P and the shape of the constricted portion CP can adjust the strength of the internal stress generated in the stress concentration portion SP and change the strength of the internal stress required for the spontaneous formation of cracks C.

[0034] The portion of the first end face EF that contacts the constricted portion CP is referred to as the abutment region AR1. In a plan view, the length L1 of the abutment region AR1 in the first direction may be 15% or more of the length L2 of the first end face EF in the first direction, thereby providing the constricted portion CP with a shape that facilitates the effective formation of the stress concentration portion SP. The length L1 may be the same as the length L2, and the first nitride semiconductor portion 8F may be formed to extend further in the X direction than the position of the first protrusion 21P that contacts the first end face EF.

[0035] The first end face EF of the first protrusion 21P may be the face of the outer peripheral surface 21S that forms the first end 21X and faces the first seed region 4F in plan view (in other words, the normal to the face passes through the first seed region 4F in plan view). The same explanation for the first protrusion 21P may also be applied to the opposing first protrusion 21PA, and repeated explanation will be omitted. However, the size of the abutment region AR1, i.e., the length L1, of the first protrusion 21P and the opposing first protrusion 21PA may be different from each other.

[0036] According to the semiconductor substrate 10 of this embodiment, the first convex body 21P allows the formation of a constricted portion CP in the first nitride semiconductor portion 8F. The preferential formation of cracks C in the stress concentration portion SP located near the constricted portion CP reduces the possibility of unintended and unnecessary cracking in the first nitride semiconductor portion 8F and the occurrence of slip lines. Furthermore, the internal stress of the first nitride semiconductor portion 8F is relieved, which facilitates the reduction of warpage of the semiconductor substrate 10. Furthermore, the spontaneous formation of cracks C simplifies the manufacturing process of semiconductor devices. Furthermore, the semiconductor substrate 10 can be designed so that cracks C do not spontaneously form. In this case, a subsequent process of forming cracks C by breaking to relieve stress can be appropriately performed. Due to the various effects described above, the use of the semiconductor substrate 10 can improve the manufacturing efficiency of semiconductor devices.

[0037] The present inventors have confirmed that the internal stress generated in the stress concentration portion SP and the stress relaxation due to the formation of cracks C can be evaluated by stress measurement using Raman spectroscopy (see Example 4 described later).

[0038] Specific examples of semiconductor devices include light emitters (LED chips, semiconductor laser chips, etc.), light emitting elements with submounted light emitters, and light emitting modules with packaged light emitting elements. The semiconductor device is not limited to light emitting semiconductor devices, and may be, for example, a photodiode. When the semiconductor substrate 10 is used to manufacture a photodiode, the same effects as when it is used to manufacture a light emitting semiconductor device can be obtained.

[0039] [Another configuration example] Fig. 5 is a plan view schematically showing the configuration of a semiconductor substrate 10 according to another embodiment. As shown by reference numeral 5001 in Fig. 5, the semiconductor substrate 10 may have a first protrusion 21P but may not have an opposing first protrusion 21PA. Even in this case, the presence of a constricted portion CP in the first nitride semiconductor portion 8F can make it easier for cracks C to form.

[0040] Furthermore, the semiconductor substrate 10 may include a second nitride semiconductor portion 8S in contact with the outer peripheral surface 21S of the first protrusion 21P (see the examples described later). The second nitride semiconductor portion 8S may be located on the first selective growth region 6F, and may grow laterally on the first thin portion 21T from another seed region (not shown) as a starting point, and may be in contact with the first protrusion 21P.

[0041] First protrusion 21P may have a shape with the first direction as its longitudinal direction, for example. First protrusion 21P may include, on outer peripheral surface 21S, second end face ES that contacts second nitride semiconductor portion 8S. First protrusion 21P may have symmetrical shapes of first end face EF and second end face ES. Semiconductor substrate 10 may have cracks C that reach first protrusion 21P in both first nitride semiconductor portion 8F and second nitride semiconductor portion 8S.

[0042] 5, the semiconductor substrate 10 may have a first protruding body 21P in contact with the first nitride semiconductor portion 8F and a second protruding body 22P in contact with the second nitride semiconductor portion 8S. In this example, the first protruding body 21P does not have to be in contact with the second nitride semiconductor portion 8S. Like the first protruding body 21P, the second protruding body 22P has an outer peripheral surface 22S shaped to guide the lateral growth of the second nitride semiconductor portion 8S so as to have a constricted portion CP. The second protruding body 22P may include a third end face ET in the outer peripheral surface 22S in contact with the constricted portion CP of the second nitride semiconductor portion 8S.

[0043] By making the sizes of the first convex body 21P and the second convex body 22P relatively small, it is possible to reduce the influence on the flow (e.g., flow rate) of the source gas during film formation of the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S. Furthermore, by providing a gap between the first convex body 21P and the second convex body 22P, it is also possible to effectively reduce the influence on the flow of the source gas. This makes it easier to improve the uniformity of the crystal growth of the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S.

[0044] In the semiconductor substrate 10, the first protrusions 21P and the second protrusions 22P may be aligned in the first direction (X direction), or the positions of the first protrusions 21P and the second protrusions 22P in the second direction (Y direction) may be different from each other, as shown by reference numeral 5002 in FIG. 5. This can reduce the influence of the first protrusions 21P and the second protrusions 22P on the flow of the source gas. As a result, the uniformity of the crystal growth of the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S can be improved.

[0045] [Examples of convex shapes] An example of the shape of the convex body of the semiconductor substrate 10 in one embodiment of the present disclosure will be described below with reference to Fig. 6. Although the first convex body 21P will be described below as an example, the following description can be applied to each of the multiple convex bodies of the semiconductor substrate 10. Furthermore, each of the multiple convex bodies of the semiconductor substrate 10 may have a different shape.

[0046] FIG. 6 is an enlarged plan view of the periphery of the first convex body 21P, illustrating an example of the shape of the first convex body 21P. For clarity, FIG. 6 simply illustrates the shape of the first convex body 21P in plan view. However, typically, the first convex body 21P may have a shape such that the cross-sectional area of ​​the first convex body 21P, when cut along a cross section parallel to the XY plane, expands from the upper surface to the lower surface (e.g., the connection surface with the first thin portion 21T). In other words, the outer peripheral surface 22S of the first convex body 21P may have a shape that is inclined in the thickness direction. This can be easily understood with reference to the manufacturing method of the semiconductor substrate 10 described in the examples below. For the first convex body 21P, it is important that the shape of the outer peripheral surface 21S generates a constricted portion CP associated with the stress concentration portion SP. FIG. 6 is a schematic diagram illustrating an example of the shape of the first convex body 21P. It goes without saying that the overall appearance of the first convex body 21P in plan view is not limited to the example shown in FIG. 6.

[0047] As shown in the diagram indicated by reference numeral 6001 in Fig. 6, an example of the first convex body 21P may have a quadrangular shape in plan view. As shown in the diagram indicated by reference numeral 6002 in Fig. 6, an example of the first convex body 21P may have a triangular shape in plan view. The first convex body 21P may have a polygonal shape with five or more corners in plan view. The first convex body 21P may have a first end face EF formed by two surfaces that form a corner, in which case it is possible to easily increase the internal stress generated in the stress concentration portion SP.

[0048] As shown in the diagram indicated by reference numeral 6003 in FIG. 6, an example of the first convex body 21P may have an elliptical shape in a plan view. The first convex body 21P may have a circular shape in a plan view. As shown in the diagram indicated by reference numeral 6004 in FIG. 6, an example of the first convex body 21P may have a bullet shape in a plan view. As shown in the diagram indicated by reference numeral 6005 in FIG. 6, an example of the first convex body 21P may have a rounded triangular shape in a plan view, but is not limited thereto and may have a rounded polygonal shape. The first convex body 21P may have a first end face EF formed by a curved surface, in which case it is relatively easy to reduce the internal stress generated in the stress concentration portion SP.

[0049] [Manufacturing of semiconductor substrates] FIG. 7 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate 10 according to an embodiment of the present disclosure. As illustrated in FIG. 7, the method for manufacturing a semiconductor substrate 10 includes a step (S10) of preparing a template substrate 7 including a base substrate BS, having a first seed region 4F and a first selective growth region 6F aligned in a first direction, with a first protruding body 21P provided in the first selective growth region 6F. The method for manufacturing a semiconductor substrate 10 also includes a step (S20) of stopping the growth of a first nitride semiconductor portion 8F after the first nitride semiconductor portion 8F, which has grown from the first seed region 4F onto the first selective growth region 6F and has a longitudinal shape extending in a second direction perpendicular to the first direction, contacts the outer peripheral surface 21S of the first protruding body 21P and forms a constricted portion CP in the first nitride semiconductor portion 8F, contacting the outer peripheral surface 21S. Because a stress concentration portion SP is generated in the constricted portion CP, cracks C are likely to form in the stress concentration portion SP. Manufacturing semiconductor devices using such a semiconductor substrate 10 can improve the manufacturing efficiency of semiconductor devices.

[0050] In the method for manufacturing the semiconductor substrate 10 according to the embodiment, after the growth of the first nitride semiconductor portion 8F is stopped, cracks C extending in the first direction and reaching the constricted portions CP may be naturally formed in the first nitride semiconductor portion 8F. Since the cracks C are naturally formed by the stress concentration portions SP generated in the constricted portions CP, it is not necessary to perform a separate step of forming the cracks C.

[0051] In one embodiment, in a method for manufacturing a semiconductor substrate 10, after stopping the growth of the first nitride semiconductor portion 8F, external stress may be applied to the first nitride semiconductor portion 8F to form a crack C in the first nitride semiconductor portion 8F that extends in the first direction and reaches the constricted portion CP. After the semiconductor substrate 10 is formed in a state in which the internal stress is concentrated to an extent that the crack C does not naturally form, and the stress concentration portion SP is provided, the crack C can be generated by performing, for example, a breaking step at an appropriate time. Generally, breaking can cause chipping or dust generation. By performing the breaking step at an appropriate time in a subsequent process, the effect on the semiconductor substrate 10, if chipping or dust generation occurs, can be limited.

[0052] Fig. 8 is a block diagram showing an example of an apparatus for manufacturing a semiconductor substrate 10 according to an embodiment of the present disclosure. The apparatus 50 for manufacturing a semiconductor substrate 10 shown in Fig. 8 includes an apparatus A10 that performs the step S10 described above, an apparatus A20 that performs the step S20 described above, and an apparatus A50 that controls the apparatus A10 and the apparatus A20.

[0053] The apparatus A10 and the apparatus A20 may include processing devices (film forming devices) such as an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus. The apparatus A50 may include a processor and memory. The apparatus A50 may be configured to control the apparatus A10 and the apparatus A20 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0054] Example 1 (Overall composition) 9 is a plan view schematically showing the configuration of the semiconductor substrate 10 in Example 1. FIG. 10 is a cross-sectional view taken along line XX shown in FIG.

[0055] As shown in FIGS. 9 and 10 , the semiconductor substrate 10 in Example 1 includes a template substrate 7, a first nitride semiconductor portion 8F, and a second nitride semiconductor portion 8S. The template substrate 7 includes a base substrate BS and a mask pattern 6 located on the base substrate BS. The mask pattern 6 includes a first opening K1 corresponding to the first seed region 4F and a first mask portion 5F corresponding to the first selective growth region 6F. The template substrate 7 also includes a plurality of protruding nuclei (nuclei) CR on the base substrate BS, each having a shape that protrudes upward. The first convex body 21P may include a protruding nuclei CR and a first mask portion 5F that covers the surface of the protruding nuclei CR. The protruding nuclei CR and the mask pattern 6 correspond to the selective growth portion 20 in the above-described embodiment.

[0056] The template substrate 7 may have a second seed region 4S, with a first selective growth region 6F located between the first seed region 4F and the second seed region 4S. The second nitride semiconductor portion 8S may be located on the second seed region 4S and the first selective growth region 6F, and may be in contact with the outer peripheral surface 21S of the first protrusion 21P. The outer peripheral surface 21S of the first protrusion 21P may be formed by the surface of the first mask portion 5F, and the surface of the first mask portion 5F may be the first selective growth region 6F.

[0057] The template substrate 7 may have a second selective growth region 6S provided with a second protrusion 22P, and the second seed region 4S may be located between the first selective growth region 6F and the second selective growth region 6S. The template substrate 7 may have the first protrusion 21P and the second protrusion 22P aligned in the first direction (X direction). The mask pattern 6 may include a second opening K2 corresponding to the second seed region 4S and a second mask portion 5S corresponding to the second selective growth region 6S. The second protrusion 22P may have a protruding core portion CR and a second mask portion 5S covering the surface of the protruding core portion CR. The outer peripheral surface 22S of the second protrusion 22P may be formed by the surface of the second mask portion 5S, and the surface of the second mask portion 5S may be the second selective growth region 6S.

[0058] The pitch (spacing) of the first protrusions 21P and the second protrusions 22P in the first direction may be equal to the pitch of the first seed regions 4F and the second seed regions 4S in the semiconductor substrate 10. The pitch of the first protrusions 21P and the second protrusions 22P may be the distance between the centers of the first protrusions 21P and the second protrusions 21P in a cross-sectional view orthogonal to the second direction (Y direction).

[0059] A protrusion group PG including the first protrusion 21P and the second protrusion 22P may be arranged side by side at a constant pitch in the first direction on the template substrate 7. On the semiconductor substrate 10, a third protrusion 23P may be provided in the first selective growth region 6F, and the first protrusion 21P and the third protrusion 23P may be arranged side by side in the second direction.

[0060] Hereinafter, the openings of mask pattern 6, including first and second openings K1 and K2, will be collectively referred to as openings K, and the nitride semiconductor portions, including first and second nitride semiconductor portions 8F and 8S, will be collectively referred to as nitride semiconductor portions 8. Furthermore, the seed regions, including first and second seed regions 4F and 4S, will be collectively referred to as seed regions J, and the mask portions, including first and second mask portions 5F and 5S, will be collectively referred to as mask portions 5. Mask pattern 6 may be a mask layer, and nitride semiconductor portions 8 may be a nitride semiconductor layer.

[0061] (template substrate) The mask pattern 6 on the template substrate 7 has a plurality of openings K and mask portions 5 above the base substrate BS. The openings K may have an elongated shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the length direction. The mask portions 5 may have an elongated shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the length direction in a plan view. The template substrate 7 may have a convex group PG formed by the mask portions 5 covering the plurality of protruding core portions CR in accordance with the arrangement of the plurality of protruding core portions CR.

[0062] Fig. 11 is a cross-sectional view showing an example of the configuration of the template substrate 7. Fig. 11 shows the periphery of an opening K in the template substrate 7. The protruding core portion CR, which is not shown in Fig. 11, can be located on the main substrate 1, the base substrate BS, or the mask portion 5, regardless of the basic configuration of the template substrate 7.

[0063] 11, the template substrate 7 may have a configuration in which a seed portion 3 and a mask pattern 6 are formed in this order on a main substrate 1, or a configuration in which a multilayered base portion 4 (including a buffer portion 2 and a seed portion 3) and a mask pattern 6 are formed in this order on a main substrate 1. The seed portion 3 may be formed locally (e.g., in a stripe shape) so as to overlap with an opening K of the mask pattern 6 in a plan view. The seed portion 3 may include a nitride semiconductor formed at a low temperature of 600°C or less. This can reduce warping of the semiconductor substrate 10 (template substrate 7 and nitride semiconductor portion 8) caused by stress from the seed portion 3.

[0064] The seed portion 3 is a growth starting point for the nitride semiconductor portion 8 and can function as a seed region J. The seed region J may overlap the opening K in a plan view and may have a shape with its longitudinal direction in the second direction (Y direction). The seed portion 3 is bonded to the nitride semiconductor portion 8. The seed portion 3 may be made of a GaN-based semiconductor, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. The seed portion 3 may be made of a material containing at least Al and N. The material of the seed portion 3 may be a nitride semiconductor containing aluminum. The silicon carbide used for the seed portion 3 may be hexagonal 6H-SiC or 4H-SiC.

[0065] For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, the two (main substrate and seed portion) melt together, so by providing a buffer portion 2 including at least one of an AlN layer and a SiC (silicon carbide) layer, for example, melting can be reduced. When a main substrate 1 that does not melt together with the seed portion 3 is used, it is possible to configure without providing the buffer portion 2. Also, when a seed portion 3 that is less reactive with the main substrate 1 is used, it is possible to configure without providing the buffer portion 2.

[0066] The buffer section 2 can be made of, for example, a GaN-based semiconductor containing Al, aluminum nitride (AlN), or silicon carbide (SiC). The silicon carbide used in the buffer section 2 can be hexagonal (6H-SiC, 4H-SiC) or cubic (4C-SiC). The buffer section 2 can include a strain relaxation layer. Examples of the strain relaxation layer include an AlGaN superlattice structure and a graded structure in which the Al composition of AlGaN changes stepwise. When the buffer section 2 includes a strain relaxation layer, the longitudinal stress of the ELO semiconductor layer 8 can be relaxed.

[0067] The seed portion 3 can also be formed using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). Using a sputtering device has the advantages of low-temperature film formation, large-area film formation, and cost reduction. As shown in FIG. 11, the template substrate 7 may have a configuration in which a mask pattern 6 is formed on a main substrate 1 (e.g., a SiC bulk crystal substrate).

[0068] In one example, the base substrate BS may include a silicon substrate or a silicon carbide substrate, and the nitride semiconductor portion 8 may include a GaN-based semiconductor. The base substrate BS may include at least a main substrate 1, and may include the main substrate 1 and a seed portion 3 located on the main substrate 1.

[0069] The main substrate 1 may be a substrate whose main component is a material other than a nitride semiconductor. The main substrate 1 may have a thermal expansion coefficient at 1000°C smaller than that of the nitride semiconductor portion 8. The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and the main substrate 1 may be made of any material and have any surface orientation that allows the nitride semiconductor portion 8 to be grown by the ELO method. The main substrate 1 may also be a SiC (bulk crystal) substrate or an AlN (bulk crystal) substrate. "Bulk crystal" means polycrystalline.

[0070] The mask portion 5 may be a selective growth mask for laterally growing the nitride semiconductor portion 8. As the mask portion 5, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN or the like), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (for example, 1000 degrees or higher) (for example, a film of platinum, rhodium, iridium, ruthenium, osmium, tungsten, molybdenum, or the like), or a laminated film including at least two of these may be used.

[0071] The width direction of the opening K may be, for example, the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8 which is a nitride semiconductor crystal, and the length direction may be the m-axis direction. In the mask pattern 6, a plurality of openings K may be arranged in the a-axis direction (X direction) of the nitride semiconductor portion 8. The openings K may have a tapered shape (a shape in which the width narrows downward).

[0072] Fig. 12 is an enlarged cross-sectional view showing the first convex body 21P of the semiconductor substrate 10 in Example 1. Fig. 13 is an enlarged plan view showing the first convex body 21P of the semiconductor substrate 10 in Example 1. Here, the first convex body 21P will be described as an example, but what will be described below also applies to the other convex bodies included in the convex body group PG.

[0073] As shown in Figures 12 and 13, the first convex body 21P may have a protruding core portion CR and a first mask portion 5F that covers the surface of the protruding core portion CR, in which case the first mask portion 5F (mask portion 5) and the surface of the first convex body 21P are made of the same material.

[0074] First protrusion 21P may have a shape whose longitudinal direction is the first direction (X direction). Outer circumferential surface 21S of first protrusion 21P includes a first end face EF in contact with first nitride semiconductor portion 8F and a second end face ES in contact with second nitride semiconductor portion 8S, and the first end face EF and second end face ES may have symmetrical shapes.

[0075] The first protrusion 21P may have a first end 21X, which is a tip end on the first end face EF side in the first direction, and a second end 21Y, which is a tip end on the second end face ES side in the first direction. The surfaces of the first end 21X and the second end 21Y may be curved. The first end face EF and the second end face ES may have a curved surface and a flat surface.

[0076] The constricted portion CP of the first nitride semiconductor portion 8F and the constricted portion CP of the second nitride semiconductor portion 8S do not have to have symmetrical shapes. The shape of the constricted portion CP can change due to various influences. The first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S may each have a crack C that extends in the first direction (X direction) and reaches the constricted portion CP.

[0077] The protruding core portion CR may be made of any material as long as it can form the first protrusion 21P, and there is no particular limitation on the specific material. The first protrusion 21P is required to be heat-resistant at the film-forming temperature of the nitride semiconductor portion 8 (for example, approximately 1200°C). If the mask portion 5 and the protruding core portion CR are made of a material that is easily removed in a subsequent process, the first protrusion 21P can be easily removed in a process after the nitride semiconductor portion 8 is formed. The protruding core portion CR may be a silicon dioxide (SiO2) film (hereinafter referred to as a "TEOS film") formed using TEOS (Si(OC2H5)4). The mask portion 5 and the protruding core portion CR that cover the surface of the protruding core portion CR may be made of the same material or different materials. For example, the mask portion 5 may include a silicon nitride film, and the protruding core portion CR may include a TEOS film. Furthermore, the mask portion 5 and the protruding core portion CR may be made of the same material but different raw materials, for example, the mask portion 5 may be a silicon oxide film formed by sputtering, and the protruding core portion CR may be a TEOS film.

[0078] The first protrusions 21P may contain at least one of an oxide and a nitride. The first protrusions 21P may include a TEOS film. Without being limited to the above example, the first protrusions 21P may have at least a part of the protruding core portion CR exposed, in which case the protruding core portion CR may be formed of a material on which a nitride semiconductor is difficult to deposit. Alternatively, the protruding core portion CR may not be covered by the mask portion 5, and the protruding core portion CR may be the first protrusions 21P. In this case, the protruding core portion CR may be formed of a material that is difficult to adhere to the nitride semiconductor portion 8.

[0079] The thickness H2 of the protruding core portion CR of the first protruding body 21P may be greater than the thickness H1 of the nitride semiconductor portion 8. Here, if the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S have different thicknesses, the thickness H1 of the nitride semiconductor portion 8 is the larger of the thicknesses of the first nitride semiconductor portion 8F and the second nitride semiconductor portion 8S. Furthermore, the thickness H3 of the first protruding body 21P may be greater than the thickness H1 of the nitride semiconductor portion 8. This effectively reduces the possibility that the nitride semiconductor portion 8 will grow onto the upper surface of the first protruding body 21P. This makes it easier to form the constricted portion CP. The thickness H3 of the first protruding body 21P may be the sum of the thickness H2 of the protruding core portion CR and the thickness of the mask portion 5.

[0080] (Nitride Semiconductor Department) The nitride semiconductor portion 8 can be formed by the ELO method, starting from the portions (first seed region 4F, second seed region 4S) where the base substrate BS is exposed by the opening K. Vapor phase growth such as metal organic vapor phase epitaxy, hydride vapor phase epitaxy, and molecular beam vapor phase epitaxy can be used for the ELO method.

[0081] In the ELO method of this embodiment, the growth of crystals growing in opposite directions (a-axis directions) on the mask portion 5 is stopped before they meet, thereby forming a plurality of striped nitride semiconductor portions 8. The mask portion 5 may be located below the gap G between adjacent nitride semiconductor portions 8.

[0082] Of the nitride semiconductor portion 8 (8F-8S), the portion located above the seed region J becomes a dislocation inherited portion HD with many threading dislocations, and the portion located above the first selective growth region 6F (the wing portion above the mask portion 5) can become a low-defect portion SD with a lower threading dislocation density than the dislocation inherited portion HD. The dislocation inherited portion HD and the low-defect portion SD will be described later.

[0083] (Manufacturing of template substrate) FIG. 14 is a cross-sectional view that schematically shows a method for manufacturing the template substrate 7 included in the semiconductor substrate 10 in Example 1. In the method for manufacturing the template substrate 7 in Example 1, as shown in FIG. 14, first, a base substrate BS is prepared. Next, protruding core portions CR are patterned on the base substrate BS. The method for forming the protruding core portions CR is not particularly limited. For example, the protruding core portions CR can be formed by forming an SiO2 film made of TEOS on the entire surface of the base substrate BS, and then removing part of the SiO2 film by dry etching. Alternatively, the protruding core portions CR may be formed by removing part of the SiO2 film by wet etching.

[0084] Next, a mask portion 5 is formed on the base substrate BS and the protruding core portion CR using, for example, a sputtering method. After applying a resist, the resist is patterned using photolithography, and a plurality of openings K are formed by removing portions of the mask portion 5 using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF). This allows the formation of a template substrate 7 having a convex group PG and a mask pattern 6.

[0085] (Specific example of template substrate) A base substrate BS having a main substrate 1 and an underlayer 4 was used. The main substrate 1 was a silicon substrate having a (111) plane, and the buffer portion 2 of the underlayer 4 was an AlN layer (for example, 30 nm). The seed portion 3 of the underlayer 4 was a first layer of Al 0.6 Ga 0.4 A graded layer was formed in which an N layer (for example, 2.4 μm thick) and a GaN layer (for example, 1.9 μm thick) as a second layer were formed in this order.

[0086] A TEOS film (for example, 10 μm thick) was used for the protruding core CR. The length of the TEOS film in the first direction (longitudinal direction) was, for example, 21 μm, and the length in the second direction (transverse direction) was, for example, 8 μm.

[0087] A silicon nitride film (SiN) was used for the mask pattern 6. The thickness of the silicon nitride film was, for example, 100 nm. The silicon nitride film was formed by plasma-enhanced chemical vapor deposition (CVD). The width of the mask portion 5 was, for example, 50 μm, and the width of the opening K was, for example, 5 μm.

[0088] (Deposition of nitride semiconductor film) FIG. 15 is a cross-sectional view showing an example of lateral growth of the nitride semiconductor portion 8 included in the semiconductor substrate 10 in Example 1. As shown in FIG. 15, in the ELO method, for example, an initial growth layer SL is first formed in the seed region J that overlaps with the opening K in a planar view using the template substrate 7 described above. Thereafter, the nitride semiconductor portion 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL is the starting point for the lateral growth of the nitride semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the nitride semiconductor portion 8 to either the Z direction (c-axis direction) or the X direction (a-axis direction).

[0089] Here, the ELO deposition conditions may be controlled as follows. That is, deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rises above the upper surface of the mask portion 5 (the stage where it contacts the upper end of the side surface of the mask portion 5) or just after it rises above the upper surface of the mask portion 5. In other words, at the above timing, the ELO deposition conditions are switched from the c-axis deposition conditions to the a-axis deposition conditions. In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that material is less likely to be consumed in the thickness direction growth of the nitride semiconductor portion 8, and the nitride semiconductor portion 8 can grow laterally at a high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm to 3.0 μm.

[0090] In Example 1, the nitride semiconductor portion 8 was an n-type GaN layer, and an MOCVD apparatus was used to perform ELO deposition of Si-doped GaN (gallium nitride) on the template substrate 7. Examples of ELO deposition conditions that can be used are: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, and V / III=6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0091] Then, the first nitride semiconductor portion 8F growing laterally on the mask portion 5 contacts the outer peripheral surface 21S of the first convex body 21P, and after a constricted portion CP contacting the outer peripheral surface 21S is formed in the first nitride semiconductor portion 8F, the growth of the first nitride semiconductor portion 8F is stopped.

[0092] The first nitride semiconductor portion 8F may have a dislocation inheritance portion HD located above the opening K, and a low-defect portion SD located above the mask portion 5. The low-defect portion SD may have a lower density of threading dislocations extending in the thickness direction (Z direction) (threading dislocation density) than the dislocation inheritance portion HD. When an active portion (for example, a region where electrons and holes recombine) is included above the nitride semiconductor portion 8, the active portion can be provided at a position overlapping the low-defect portion SD in plan view.

[0093] In the first nitride semiconductor portion 8F, lateral growth from the initial growth layer SL can increase the number of non-threading dislocations inside the low defect portion SD. This can reduce the threading dislocation density on the surface of the low defect portion SD. Furthermore, the distribution of impurity concentrations (e.g., silicon, oxygen) inside the low defect portion SD can be controlled. Threading dislocations can be observed by, for example, performing CL (Cathode Luminescence) measurement on the surface (c-plane) of the nitride semiconductor portion 8 or a cross section parallel to the surface. Non-threading dislocations are dislocations that are measured by CL on a cross section taken along a plane parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.

[0094] The low defect portion SD may have a threading dislocation density of 1 / 5 or less of that of the dislocation inheritance portion HD. 6 / cm2 It may be the following:

[0095] The first nitride semiconductor portion 8F had a width of 53 μm and a thickness of 5 μm in the portion other than the constricted portion CP. The width (size in the X direction) of the low defect portion SD was 24 μm. The aspect ratio of the first nitride semiconductor portion 8F was 53 μm / 5 μm=10.6, which is a high aspect ratio.

[0096] The first nitride semiconductor portion 8F has a constricted portion CP. Therefore, when the ELO film is formed using an MOCVD apparatus and then cooled to room temperature, a crack C extending in the first direction may be spontaneously formed in the stress concentrated portion SP (see FIG. 4).

[0097] (Device structure formation) Fig. 16 is a plan view showing the method for manufacturing a semiconductor device in Example 1. Fig. 17 is a cross-sectional view showing the method for manufacturing a semiconductor device in Example 1. The last drawing in Fig. 16 shows a plan view seen through the support substrate SK.

[0098] 16 and 17 , the mask portion 5 and the protruding core portion CR in the semiconductor substrate 10 are removed by wet etching or the like. Then, a plurality of trenches TR are formed to divide the nitride semiconductor portion 8 into a plurality of base semiconductor portions 8B. At least one of the plurality of trenches TR formed in the nitride semiconductor portion 8 may remove the joint portion between the base semiconductor portion 8B and the seed region J (the portion exposed from the opening K). In this case, an anchor film AF may be formed after the formation of the plurality of trenches TR so that the plurality of island-shaped base semiconductor portions 8B do not become scattered on the template substrate 7.

[0099] Thereafter, a compound semiconductor portion 9 including an active portion can be formed in an island shape above each base semiconductor portion 8 B. Then, a device portion (device stack) DS including the base semiconductor portion 8 B and the compound semiconductor portion 9 can be formed.

[0100] The compound semiconductor portion 9 can be formed by, for example, MOCVD. The compound semiconductor portion 9 may have a layered structure of, for example, an n-GaN layer, an MQW (Multi-Quantum Well) as an active portion, a p-AlGaN layer, and a p-GaN layer. The base semiconductor portion 8B may be a base semiconductor layer, and the compound semiconductor portion 9 may be a compound semiconductor layer.

[0101] The anchor film AF contacts the side surface of the base semiconductor portion 8B and the mask portion 5, and anchors the base semiconductor portion 8B to the template substrate 7. As the anchor film AF, a dielectric film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, a silicon oxynitride film, an aluminum oxide-silicon film, an aluminum oxynitride film, a zirconium oxide film, a titanium oxide film, or a tantalum oxide film can be used.

[0102] The compound semiconductor portion 9 may include a nitride semiconductor (e.g., a GaN-based semiconductor). By using a silicon oxide film, a silicon nitride film, an aluminum oxide-silicon film, a silicon oxynitride film, a titanium nitride film, or the like for the anchor film AF, the nitride semiconductor of the compound semiconductor portion 9 does not grow on the anchor film AF, and therefore the compound semiconductor portion 9 can be formed in an island shape. During the transfer of the element portion DS, at least a portion of the anchor film AF may remain on the template substrate 7 or may be attached to the element portion DS. By using a material with low conductivity for the anchor film AF, there is no risk of electrical leakage or the like occurring even if the anchor film AF remains in the final semiconductor device.

[0103] For example, a trench TR is formed by dry etching using a resist mask, an anchor film AF is formed over the entire surface by sputtering or EB (Electron Beam Deposition), and then the resist mask is removed to lift off unnecessary portions of the anchor film AF.

[0104] The first electrode E1, which is an anode, may be formed so as to overlap the low defect portion SD in plan view and to be in contact with the compound semiconductor portion 9. When the nitride semiconductor of the base semiconductor portion 8B is an n-type, the second electrode E2, which is a cathode, can be formed so as to be in contact with the base semiconductor portion 8B.

[0105] The first electrode E1 (anode) and the second electrode E2 (cathode) may have a single-layer structure or a multi-layer structure containing at least one of Al, Ag, Cr, Pd, Pt, Au, Ni, Ti, V, W, Cu, Zn, Sn, and In, or may include an alloy layer. At least one of the first and second electrodes E1 and E2 may have a laminated structure of a translucent conductive film (such as ITO (indium tin oxide)) and a light-reflective metal film (such as Ag, Al, or Ti).

[0106] A semiconductor device can be obtained by transferring the element portion DS to a support substrate SK and dividing the support substrate SK. The second electrode E2 may be connected to the support substrate SK via a second bonding portion A2, which makes it easier to transfer the element portion DS to the support substrate SK even when the heights of the first and second electrodes E1 and E2 are different.

[0107] FIG. 18 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. Using a semiconductor substrate 10, for example, a light emitter (LED chip) 21 shown in FIG. 18 can be obtained. An n-type portion 9N, an active portion 9K, and a p-type portion 9P may be formed in this order as the compound semiconductor portion 9 on the base semiconductor portion 8B. By making the n-type portion 9N an n-GaN layer, making the active portion 9K including the light emitting portion an MQW (multi-quantum well) including an InGaN layer and a GaN layer, and making the p-type portion 9P a stacked structure of a p-AlGaN layer and a p-GaN layer, the element portion DS can be an LED (light emitting diode).

[0108] (Another configuration example) FIG. 19 is a perspective view showing another configuration of the semiconductor device obtained in Example 1. In the example shown in FIG. 18 described above, after forming the trench TR, a first electrode E1 is formed on the compound semiconductor portion 9 located at least partially above the base semiconductor portion 8B, and a second electrode E2 is formed on the base semiconductor portion 8B, with the first and second electrodes E1 and E2 aligned in the second direction (Y direction). This is not limited to this; after forming the trench TR, the compound semiconductor portion 9 and the first electrode E1 may be formed above the base semiconductor portion 8B, and the element portion DS may be transferred to the support substrate SK. Then, a second electrode E2 can be formed on the back surface of the base semiconductor portion 8B. This allows, for example, a light emitter (LED chip) 21 shown in FIG. 19 to be obtained.

[0109] Furthermore, in Example 1, the trenches TR are formed after removing the mask pattern 6, but this is not limiting. As long as the element portion DS can be transferred to the support substrate SK, the timing of removing the mask pattern 6 and the timing of forming the trenches TR are not particularly limited. Furthermore, the transfer may be performed without removing the mask pattern 6, or may be performed without forming the trenches TR. For example, the trenches TR may be formed in conjunction with the step of removing the convex body group PG.

[0110] Example 2 FIG. 20 is a plan view showing a semiconductor substrate 10 according to the second embodiment and a method for manufacturing a semiconductor device using the same.

[0111] In Example 1, a semiconductor device was manufactured using a semiconductor substrate 10 in which a crack C was formed in a nitride semiconductor portion 8. In contrast, in Example 2, after the nitride semiconductor portion 8 was formed on a template substrate 7, a compound semiconductor portion 9 was formed on the nitride semiconductor portion 8 before the crack C was generated.

[0112] 20, for example, after the nitride semiconductor portion 8 is formed in an MOCVD apparatus, the compound semiconductor portion 9 may be formed without cooling to lower the temperature. Alternatively, the internal stress generated in the stress concentration portion SP in the vicinity of the constricted portion CP may be made relatively weak, thereby making it difficult for the crack C to spontaneously form in the nitride semiconductor portion 8.

[0113] After the compound semiconductor portion 9 is formed, cracks C may occur in the nitride semiconductor portion 8 by cooling it to room temperature, and in this case, the cracks C propagate to the compound semiconductor portion 9 as well as the nitride semiconductor portion 8. The cracks C may also be formed by applying an external force to the nitride semiconductor portion 8 and the compound semiconductor portion 9.

[0114] The projection group PG may be removed by forming a trench TR extending in the first direction (X direction). In Example 2, without removing the mask pattern 6, a first electrode E1 is formed on the compound semiconductor portion 9 located at least partially above the base semiconductor portion 8B, and a second electrode E2 is formed on the base semiconductor portion 8B. The first and second electrodes E1 and E2 are positioned to be aligned in the first direction (X direction). Then, the element portion DS may be selectively transferred to a support substrate SK.

[0115] 21 is a perspective view showing the configuration of a semiconductor device obtained in Example 2. Using the semiconductor substrate 10, for example, a light emitter (LED chip) 21 shown in FIG.

[0116] FIG. 22 is a perspective view showing an example of the structure of a semiconductor device in Example 2. As shown in FIG. 22, the element portion DS may be selectively transferred to a support substrate SK, and a two-dimensionally arranged light-emitting substrate 22 may be formed by selective transfer. In the light-emitting substrate 22, for example, the first electrode E1 may be connected to the first pad portion P1 via the first bonding portion A1, and the second electrode E2 may be connected to the second pad portion P2 via the second bonding portion A2. The thickness of the second bonding portion A2 is greater than the thickness of the first bonding portion A1, and the difference in thickness between the first bonding portion A1 and the second bonding portion A2 is equal to or greater than the thickness of the second semiconductor portion S2. This enables connection between the first and second electrodes E1 and E2 and the first and second pad portions P1 and P2 located on the same plane.

[0117] In the second embodiment, for example, the support substrate SK may be formed as follows. That is, a 4-inch Si substrate is used as the substrate main body BS, and the first pad portion P1 and the second pad portion P2 are formed by a wafer process using photolithography technology. A plurality of recesses HL (rectangular in plan view) can be formed in a matrix pattern with a depth of 100 μm by reactive ion etching (RIE) or the like. Then, the first bonding portion A1 and the second bonding portion A2 are formed. The first pad portion P1 and the second pad portion P2 may each be a multilayer film formed from a 10-nm-thick Cr film, a 25-nm-thick Pt film, and a 100-nm-thick Au film in this order from the substrate main body BS side. The first bonding portion A1 and the second bonding portion A2 may each be an AuSn bonding layer formed from a 3000-nm-thick AuSn film and a 100-nm-thick Au film in this order from the substrate main body BS side. For the first joint portion A1 and the second joint portion A2, a solder other than AuSn can be used.

[0118] (Another configuration example) The element portion DS may be a semiconductor laser chip, in which case the cleavage planes formed by the cracks C can be used as cavity end faces. The compound semiconductor portion 9 can be formed so as to include an optical cavity in the active portion 9K. The optical cavity can have, for example, the second direction (Y direction) as its cavity length direction.

[0119] Example 3 23 is a cross-sectional view showing a manufacturing method of the template substrate 7 included in the semiconductor substrate 10 in Example 3. As shown in Fig. 23, for example, first, a main substrate 1, which is a single crystal silicon substrate, is prepared. The main substrate 1 can be etched to form the protruding core portions CR, and in this case, the main substrate 1 and the protruding core portions CR may be made of the same material.

[0120] Next, for example, the mask portion 5 of the mask pattern 6 is formed over the entire surface of the main substrate 1. The resist RZ is patterned by photolithography, and an opening K is formed in the mask portion 5. To form the opening K, a portion of the mask portion 5 may be removed and the main substrate 1 may be dug. Alternatively, only a portion of the mask portion 5 may be removed without dug into the main substrate 1.

[0121] Next, while leaving the resist RZ, a laminate 4x (e.g., an aluminum nitride layer and a gallium nitride layer) is formed using a sputtering method or the like. When forming the laminate 4x while leaving the resist RZ, it is preferable to perform the film formation at a low temperature, since the resist will be burned if the film formation is performed at a high temperature exceeding 200 degrees. Then, the resist RZ is removed (by lifting it off, the base portion 4 is left only in the opening K). This allows the template substrate 7 to be formed.

[0122] Using the template substrate 7 manufactured in this manner, the nitride semiconductor portion 8 is deposited by the ELO method starting from the base portion 4 formed in the opening K, thereby manufacturing the semiconductor substrate 10.

[0123] Example 4 The following describes the results of stress measurement using Raman spectroscopy for the semiconductor substrate 10 in the above-described Example 1. Hereinafter, the end face located at the tip portion in the X direction of the convex body group PG on the template substrate 7 will be referred to as the tip face EG.

[0124] Fig. 24 is a diagram for explaining the stress state of the first nitride semiconductor portion 8F in which the crack C is formed of the semiconductor substrate 10 in Example 4. The diagram designated by reference numeral 2401 in Fig. 24 is a microscope image showing an enlarged view of the portion of the first nitride semiconductor portion 8F in which the crack C is formed, and the diagram designated by reference numeral 2402 in Fig. 24 is an image showing the results of stress measurement performed by using Raman spectroscopy on the portion designated by reference numeral 2401. In Fig. 24, a part of the tip surface EG of the convex body group PG is schematically shown by a dotted line for ease of understanding.

[0125] 24, the first nitride semiconductor portion 8F has a relatively large tensile stress, but has a stress relaxation portion RP in the peripheral portion of the crack C. It can be seen that the tensile stress is more relaxed in the stress relaxation portion RP than in the portion positioned away from the crack C in the Y direction.

[0126] Fig. 25 is a diagram for explaining the stress state of the first nitride semiconductor portion 8F in which no cracks C are formed of the semiconductor substrate 10 in Example 4. The view designated by reference numeral 2501 in Fig. 25 is a microscope image showing an enlarged view of the portion of the first nitride semiconductor portion 8F in which no cracks C are formed, and the view designated by reference numeral 2502 in Fig. 25 is an image showing the results of stress measurement performed by using Raman spectroscopy on the portion designated by reference numeral 2501. In Fig. 25, as in Fig. 24, a part of the tip surface EG of the convex body group PG is schematically shown by a dotted line for ease of understanding.

[0127] As shown in FIG. 25, it can be seen that the first nitride semiconductor portion 8F has a relatively large tensile stress overall when no cracks C are formed.

[0128] Fig. 26 is an image showing the stress measurement results of the diagram indicated by reference numeral 2502 in Fig. 25, with the scale of the color bar changed. As shown in Fig. 26, it can be seen that a stress concentration portion SP occurs near the front end face EG of the first nitride semiconductor portion 8F, in other words, near the constricted portion CP.

[0129] (summary) The semiconductor substrate in aspect 1 of the present disclosure comprises a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, with a first convex body provided in the first selective growth region, and a first nitride semiconductor portion located on the first seed region and the first selective growth region, having an elongated shape extending in a second direction perpendicular to the first direction, and having a constricted portion in contact with the outer peripheral surface of the first convex body.

[0130] A semiconductor substrate according to a second aspect of the present disclosure is the semiconductor substrate according to the first aspect, wherein the first nitride semiconductor portion includes a crack extending in the first direction and reaching the constricted portion.

[0131] A semiconductor substrate according to a third aspect of the present disclosure is the semiconductor substrate according to the first or second aspect, wherein the first nitride semiconductor portion has a stress concentration portion in the vicinity of the constricted portion.

[0132] The semiconductor substrate in aspect 4 of the present disclosure is any one of aspects 1 to 3, wherein the outer peripheral surface includes a first end face that contacts the constricted portion, and the constricted portion has a shape that follows the shape of the first end face.

[0133] A semiconductor substrate according to a fifth aspect of the present disclosure is the semiconductor substrate according to the fourth aspect, wherein the first end face is formed of two surfaces that form an angle or a curved surface.

[0134] A sixth aspect of the present disclosure relates to a semiconductor substrate according to any one of the first to fifth aspects, wherein the first protrusion is thicker than the first nitride semiconductor portion.

[0135] A semiconductor substrate according to a seventh aspect of the present disclosure is the semiconductor substrate according to any one of the first to sixth aspects, wherein the first protrusions have a shape whose longitudinal direction is in the first direction.

[0136] The semiconductor substrate in aspect 8 of the present disclosure is any one of aspects 1 to 7, wherein the first seed region has the second direction as its longitudinal direction, and the first direction is the <11-20> direction of the first nitride semiconductor portion.

[0137] The semiconductor substrate in aspect 9 of the present disclosure is any one of aspects 1 to 8, wherein the template substrate has a mask pattern located on a base substrate, and the mask pattern includes an opening corresponding to the first seed region and a mask portion corresponding to the first selective growth region.

[0138] The semiconductor substrate according to a tenth aspect of the present disclosure is the same as that according to the ninth aspect, wherein the mask portion and the surface of the first convex body are made of the same material.

[0139] In an eleventh aspect of the present disclosure, in the semiconductor substrate of any one of the first to tenth aspects, the base wafer includes a main substrate and a seed portion located on the main substrate.

[0140] A semiconductor substrate according to a twelfth aspect of the present disclosure is the semiconductor substrate according to the eleventh aspect, wherein the main substrate is mainly composed of a material that is not a nitride semiconductor.

[0141] A thirteenth aspect of the present disclosure provides a semiconductor substrate according to the twelfth aspect, wherein the main substrate has a thermal expansion coefficient at 1000° C. that is smaller than that of the first nitride semiconductor portion.

[0142] A semiconductor substrate according to a fourteenth aspect of the present disclosure is any one of the eleventh to thirteenth aspects, wherein the material of the seed portion is a nitride semiconductor containing aluminum.

[0143] The semiconductor substrate in aspect 15 of the present disclosure is any one of aspects 1 to 14, wherein the template substrate has a second seed region, the first selective growth region is located between the first seed region and the second seed region, and a second nitride semiconductor portion is located on the second seed region and the first selective growth region and in contact with the outer peripheral surface of the first convex body.

[0144] The semiconductor substrate in aspect 16 of the present disclosure is the same as aspect 15, except that the outer peripheral surface includes a first end face in contact with the first nitride semiconductor portion and a second end face in contact with the second nitride semiconductor portion, and the first end face and the second end face are symmetrical in shape.

[0145] In aspect 17 of the present disclosure, the semiconductor substrate is the same as in aspect 15 or 16, wherein the template substrate has a second selective growth region in which a second protrusion is provided, the second seed region is located between the first selective growth region and the second selective growth region, and the first protrusion and the second protrusion are aligned in the first direction.

[0146] In an eighteenth aspect of the present disclosure, in the semiconductor substrate of the seventeenth aspect, the pitch between the first convex bodies and the second convex bodies is equal to the pitch between the first seed regions and the second seed regions.

[0147] In a nineteenth aspect of the present disclosure, in the semiconductor substrate of the seventeenth or eighteenth aspect, a group of protrusions including the first protrusions and the second protrusions is arranged on the template substrate at a constant pitch in the first direction.

[0148] A semiconductor substrate according to a twentieth aspect of the present disclosure is any one of the seventeenth to nineteenth aspects, wherein a third protrusion is provided in the first selective growth region, and the first protrusion and the third protrusion are aligned in the second direction.

[0149] A twenty-first aspect of the present disclosure provides a semiconductor substrate according to any one of the first to twentieth aspects, wherein the first protrusion includes at least one of an oxide and a nitride.

[0150] A semiconductor substrate according to a twenty-second aspect of the present disclosure is the twenty-first aspect, wherein the first protrusion includes a TEOS film.

[0151] A twenty-third aspect of the present disclosure provides a semiconductor substrate according to any one of the first to twenty-second aspects, wherein the base substrate includes a silicon substrate or a silicon carbide substrate, and the first nitride semiconductor portion includes a GaN-based semiconductor.

[0152] A method for manufacturing a semiconductor substrate in one aspect of the present disclosure includes the steps of: preparing a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, with a first convex body provided in the first selective growth region; and stopping the growth of a first nitride semiconductor portion having an elongated shape extending in a second direction perpendicular to the first direction, the first nitride semiconductor portion growing from on the first seed region onto the first selective growth region, and contacting an outer peripheral surface of the first convex body, after a constricted portion contacting the outer peripheral surface is formed in the first nitride semiconductor portion.

[0153] In the method for manufacturing a semiconductor substrate in aspect 25 of the present disclosure, in aspect 24, after stopping the growth of the first nitride semiconductor portion, a crack naturally forms in the first nitride semiconductor portion, extending in the first direction and reaching the constricted portion.

[0154] In the method for manufacturing a semiconductor substrate in aspect 26 of the present disclosure, in aspect 24, after stopping the growth of the first nitride semiconductor portion, an external stress is applied to the first nitride semiconductor portion to form a crack in the first nitride semiconductor portion that extends in the first direction and reaches the constricted portion.

[0155] [Additional notes] The invention according to the present disclosure has been described above based on various drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0156] 7 Template substrate 10. Semiconductor substrate 21P 1st convex body 4F 1st Seed Area 6F First Selected Growth Area 8F 1st Nitride Semiconductor Department BS base board CP constricted part K opening

Claims

1. a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, and a first protrusion provided in the first selective growth region; a first nitride semiconductor portion located on the first seed region and the first selective growth region, having an elongated shape extending in a second direction perpendicular to the first direction, and having a constricted portion in contact with an outer peripheral surface of the first protrusion.

2. The semiconductor substrate according to claim 1 , wherein the first nitride semiconductor portion includes a crack extending in the first direction and reaching the constricted portion.

3. The semiconductor substrate according to claim 1 , wherein the first nitride semiconductor portion has a stress concentration portion in the vicinity of the constricted portion.

4. the outer peripheral surface includes a first end surface in contact with the constricted portion, The semiconductor substrate according to claim 1 , wherein the constricted portion has a shape that conforms to the shape of the first end face.

5. The semiconductor substrate according to claim 4 , wherein the first end face is composed of two surfaces forming an angle or a curved surface.

6. The semiconductor substrate according to claim 1 , wherein the first protrusion is thicker than the first nitride semiconductor portion.

7. The semiconductor substrate according to claim 1 , wherein the first protrusion has a shape whose longitudinal direction is in the first direction.

8. the first seed region has a longitudinal direction in the second direction, 8. The semiconductor substrate according to claim 1, wherein the first direction is a <11-20> direction of the first nitride semiconductor portion.

9. the template substrate has a mask pattern positioned on a base substrate; The semiconductor substrate according to claim 1 , wherein the mask pattern includes an opening corresponding to the first seed region and a mask portion corresponding to the first selective growth region.

10. The semiconductor substrate according to claim 9 , wherein the mask portion and the surface of the first convex body are made of the same material.

11. The semiconductor substrate of claim 1 , wherein the base substrate includes a main substrate and a seed portion located on the main substrate.

12. The semiconductor substrate according to claim 11 , wherein the main substrate is primarily made of a material that is not a nitride semiconductor.

13. The semiconductor substrate according to claim 12 , wherein the main substrate has a thermal expansion coefficient at 1000° C. that is smaller than that of the first nitride semiconductor portion.

14. The semiconductor substrate according to claim 11 , wherein the material of the seed portion is a nitride semiconductor containing aluminum.

15. the template substrate has a second seed region; the first selective growth region is located between the first seed region and the second seed region; The semiconductor substrate according to claim 1 , further comprising a second nitride semiconductor portion located on the second seed region and the first selective growth region and in contact with an outer circumferential surface of the first protrusion.

16. 16. The semiconductor substrate of claim 15, wherein the outer peripheral surface includes a first end face in contact with the first nitride semiconductor portion and a second end face in contact with the second nitride semiconductor portion, and the first end face and the second end face have symmetrical shapes.

17. the template substrate has a second selective growth region in which a second protrusion is provided; the second seed region is located between the first selective growth region and the second selective growth region; The semiconductor substrate according to claim 15 , wherein the first protrusions and the second protrusions are aligned in the first direction.

18. The semiconductor substrate of claim 17 , wherein a pitch between the first protrusions and the second protrusions is equal to a pitch between the first seed regions and the second seed regions.

19. The semiconductor substrate according to claim 17 , wherein a group of protrusions including the first protrusions and the second protrusions are arranged at a constant pitch in the first direction on the template substrate.

20. a third protrusion is provided in the first selective growth region; The semiconductor substrate according to claim 17 , wherein the first protrusions and the third protrusions are aligned in the second direction.

21. The semiconductor substrate according to claim 1 , wherein the first protrusion includes at least one of an oxide and a nitride.

22. The semiconductor substrate according to claim 21 , wherein the first protrusion includes a TEOS film.

23. the base substrate comprises a silicon substrate or a silicon carbide substrate; The semiconductor substrate according to claim 1 , wherein the first nitride semiconductor portion includes a GaN-based semiconductor.

24. preparing a template substrate including a base substrate, having a first seed region and a first selective growth region aligned in a first direction, and a first protrusion provided in the first selective growth region; a step of stopping the growth of a first nitride semiconductor portion after the first nitride semiconductor portion has grown from on the first seed region onto the first selective growth region, the first nitride semiconductor portion having an elongated shape extending in a second direction perpendicular to the first direction, and contacting an outer peripheral surface of the first convex body, and a constricted portion contacting the outer peripheral surface is formed in the first nitride semiconductor portion.

25. 25 . The method for manufacturing a semiconductor substrate according to claim 24 , wherein, after growth of the first nitride semiconductor portion is stopped, a crack extending in the first direction and reaching the constricted portion is naturally formed in the first nitride semiconductor portion.

26. 25. The method for manufacturing a semiconductor substrate according to claim 24, further comprising: applying an external stress to the first nitride semiconductor portion after stopping the growth of the first nitride semiconductor portion, thereby forming a crack in the first nitride semiconductor portion that extends in the first direction and reaches the constricted portion.

27. A semiconductor substrate manufacturing apparatus that performs each step according to claim 24.

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