thermal printer

Abstract

To keep common mode noise low.SOLUTION: A thermal printer comprises a thermal head, a drive data generation part, a clock generation part, and a drive data feed part. The thermal head loads thereon many heat generation elements divided into a plurality of blocks, and inputs drive data for driving many heat generation elements in parallel in synchronization with a plurality of first clock signals which are respectively different for the plurality of blocks. The drive data generation part generates a plurality of drive data pieces for the plurality of blocks from print data, and outputs the plurality of drive data pieces in synchronization with a plurality of second clock signals. The clock generation part generates the plurality of first clock signals which mutually deviate in phases. The drive data feed part captures the plurality of drive data pieces outputted from the generation part in synchronization with the plurality of second clock signals, and feeds the same to the thermal head in synchronization with the plurality of the first clock signals.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a thermal printer. [Background technology]

[0002] A thermal head is known in which a large number of mounted heating elements are divided into blocks and drive data is input in parallel for each block. In a thermal printer using a thermal head of this configuration, drive data for driving the heat generating elements of each block is input to the thermal head in synchronization with the same clock signal. This can cause the timing of changes in multiple pieces of drive data supplied to the thermal head to coincide, increasing common mode noise and potentially causing problems with EMI (electromagnetic interference). For these reasons, it was desirable to be able to keep common-mode noise to a minimum. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-279683 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a thermal printer that can reduce common mode noise. [Means for solving the problem]

[0005] A thermal printer according to an embodiment includes a thermal head, a drive data generation unit, a clock generation unit, and a drive data supply unit. The thermal head includes a large number of heating elements divided into multiple blocks, and receives drive data for driving the large number of heating elements in parallel, synchronized with multiple first clock signals, each of which is different for each of the multiple blocks. The drive data generation unit generates multiple drive data for each of the multiple blocks from print data and outputs the multiple drive data in synchronization with multiple second clock signals. The clock generation unit generates multiple clock signals that are out of phase with each other as first clock signals. The drive data supply unit receives the multiple drive data output from the drive data generation unit in synchronization with the multiple second clock signals, and supplies the drive data to the thermal head in synchronization with the multiple first clock signals generated by the clock generation unit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the main circuit configuration of a thermal printer according to an embodiment. [Figure 2] Timing diagram of the output of the CPLD in Figure 1. [Figure 3] 5A and 5B are diagrams showing fluctuations in power supply current accompanying fluctuations in a clock signal in this embodiment. [Figure 4] FIG. 10 is a diagram showing how power supply current fluctuates when clock signals fluctuate at the same timing. DETAILED DESCRIPTION OF THE INVENTION

[0007] An example of an embodiment will be described below with reference to the drawings. FIG. 1 is a block diagram showing the main circuit configuration of a thermal printer 1 according to this embodiment. The thermal printer 1 includes a thermal head 10, a group of motors 20, a motor driver 30, a group of sensor elements 40, a sensor circuit 50, a clock generation circuit 60, an input port 70, a central processing unit (CPU) 80, a read-only memory (ROM) 90, a random-access memory (RAM) 100, and a complex programmable logic device (CPLD) 110.

[0008] The thermal head 10 includes a large number of heating elements 11 and four drive circuits 12. Each of the large number of heating elements 11 generates heat when energized. The large number of heating elements 11 are arranged, for example, in a single row at equal intervals. However, the large number of heating elements 11 may also be arranged in multiple rows or in a staggered pattern. The large number of heating elements 11 are divided into four groups. The four drive circuits 12 correspond to the four groups of heating elements 11, respectively. The drive circuits 12 are connected to the heating elements 11 belonging to the corresponding groups. The drive circuits 12 control the energization of each of the heating elements 11 belonging to the corresponding group.

[0009] The motor group 20 includes a plurality of motors. The motors included in the motor group 20 are power sources for transporting print paper and the like. The motor driver 30 drives the motors included in the motor group 20 under the control of the CPU 80.

[0010] The sensor element group 40 includes various sensor elements for detecting the operating state of the thermal printer 1. The sensor circuit 50 determines the operating state of the thermal printer 1 based on the state of each of the sensor elements included in the sensor element group 40.

[0011] The clock generation circuit 60 generates a system clock signal CA that is the basis for the operation timing of the thermal printer 1. The input port 70 is a port to which a host device is connected and through which print data sent from the host device is input. As an example, it is assumed that a well-known communication device conforming to the USB (universal serial bus) is used as the input port 70.

[0012] The CPU 80 generates four pieces of drive data DBA, DBB, DBC, and DBD for driving the thermal head 10 from the print data input via the input port 70. The CPU 80 outputs the drive data DBA, DBB, DBC, and DBD together with clock signals CBA, CBB, CBC, and CBD, each of which has a different timing, in synchronization with the clock signals CBA, CBB, CBC, and CBD. These pieces of drive data DBA, DBB, DBC, and DBD correspond to four groups of heating elements 11, respectively, and are supplied via the CPLD 110 to the drive circuits 12 corresponding to the same groups. The CPU 80 outputs to each of the four drive circuits 12 a latch signal LAT for indicating the timing for latching the drive data DBA, DBB, DBC, and DBD in each of the drive circuits 12, and a strobe signal STB for indicating the timing for energizing the heating element 11. The CPU 80 references the operating state determined by the sensor circuit 50 and outputs drive data DBA, DBB, DBC, DBD, latch signal LAT and strobe signal STB, and controls the motor driver 30 to perform the required printing operation.

[0013] The ROM 90 stores various software programs describing the processing procedures of the CPU 80, and various data that the CPU 80 refers to when executing various information processes. The RAM 100 temporarily stores data used when the CPU 80 executes various information processes. The CPLD 110 is programmed to form a logic circuit that generates clock signals CCA, CCB, CCC, and CCD as described below, and supplies drive data DBA, DBB, DBC, and DBD to the thermal head 10 in synchronization with these signals.

[0014] Next, the operation of the thermal printer 1 configured as above will be described. The operation of printing an image using the thermal printer 1 may be basically the same as that of other existing thermal printers of the same type. However, the operation of the thermal printer 1 that differs from other existing thermal printers is the supply of drive data DBA, DBB, DBC, and DBD to the thermal head 10, which will be described below.

[0015] FIG. 2 is a timing diagram of the output of the CPLD 110. The CPLD 110 generates clock signals CCA, CCB, CCC, and CCD, which are shifted in phase by 90° from one another as shown in FIG. 2, based on the system clock signal CA. The CPLD 110 then takes in the drive data DBA output from the CPU 80 in synchronization with the clock signal CBA, buffers it, and outputs it in synchronization with the clock signal CCA to one of the drive circuits 12. The drive circuit 12 that receives the drive data DBA and the clock signal CCA takes in the drive data DBA in synchronization with the clock signal CCA.

[0016] The CPLD 110 takes in the drive data DBB output from the CPU 80 in synchronization with the clock signal CBB, buffers it, and then outputs it in synchronization with the clock signal CCB to one of the drive circuits 12. The drive circuit 12 that receives the drive data DBB and the clock signal CCB takes in the drive data DBB in synchronization with the clock signal CCB.

[0017] The CPLD 110 takes in the drive data DBC output from the CPU 80 in synchronization with the clock signal CBC, buffers it, and then outputs it in synchronization with the clock signal CCC to one of the drive circuits 12. The drive circuit 12 that receives the drive data DBC and the clock signal CCC takes in the drive data DBC in synchronization with the clock signal CCC.

[0018] The CPLD 110 takes in the drive data DBD output from the CPU 80 in synchronization with the clock signal CBD, buffers it, and then outputs it in synchronization with the clock signal CCD to one of the drive circuits 12. The drive circuit 12 that receives the drive data DBD and the clock signal CCD takes in the drive data DBD in synchronization with the clock signal CCD. Each of the four drive circuits 12 latches the captured drive data in synchronization with the latch signal LAT, and then controls the energization of the corresponding heating element 11 in synchronization with the strobe signal STB based on the latched drive data.

[0019] As described above, the clock signals CBA, CBB, CBC, and CBD correspond to a plurality of first clock signals, and the clock signals CCA, CCB, CCC, and CCD correspond to a plurality of second clock signals. The CPU 80 functions as a drive data generator. The CPLD 110 functions as both a clock generator and a drive data supplier.

[0020] 3 is a diagram showing the fluctuations in power supply current due to fluctuations in clock signals CCA, CCB, CCC, and CCD. However, the fluctuations in power supply current shown in FIG. 3 only show an outline of the fluctuation trends, and minute fluctuations are not shown. The fluctuation of the power supply current due to fluctuations in the clock signal CCA is shown as the current CUA in Figure 3. The fluctuation of the power supply current due to fluctuations in the clock signal CCB is shown as the current CUB in Figure 3. The fluctuation of the power supply current due to fluctuations in the clock signal CCC is shown as the current CUC in Figure 3. The fluctuation of the power supply current due to fluctuations in the clock signal CCD is shown as the current CUD in Figure 3. However, the actual fluctuation of the power supply current CUX is the combination of these currents CUA, CUB, CUC, and CUD, and theoretically is zero, as shown in Figure 3. However, in reality, due to errors in the change timing and signal levels of the clock signals CCA, CCB, CCC, and CCD, the power supply current CUX does not become completely zero, but it can be kept sufficiently small.

[0021] 4 is a diagram showing how the power supply current fluctuates when the clock signals CCA, CCB, CCC, and CCD fluctuate at the same timing. However, the power supply current fluctuation shown in FIG. 4 shows only a rough outline of the fluctuation tendency, and minute fluctuations are not shown. As shown in FIG. 4, when the clock signals CCA, CCB, CCC, and CCD fluctuate at the same timing, the fluctuation of the power supply current CUX becomes very large, whereas the embodiment of the present application can significantly reduce the fluctuation of the power supply current CUX.

[0022] Thus, the thermal printer 1 makes it possible to keep common mode noise to a minimum. In addition, in the thermal printer 1, the phase difference between the clock signals CCA, CCB, CCC, and CCD is set to 90°, which is calculated as 4 / 360 because there are four groups of heating elements 11. As a result, as described above, the fluctuations in the power supply current CUX can be theoretically reduced to zero, and common mode noise can be minimized.

[0023] This embodiment can be modified in various ways as follows. The number of groups of heating elements 11 may be any integer equal to or greater than two.

[0024] As in the above embodiment, where n is the number of groups of heating elements 11, it is desirable that the phase difference between the n clock signals be an angle calculated by n / 360. However, since it is possible to suppress common-mode noise compared to when there is no phase difference by giving the n clock signals a phase difference, it is also acceptable to give them a phase difference of an angle other than that calculated by n / 360.

[0025] Some or all of the functions realized by the CPLD 110 can also be realized by hardware that executes processes not based on a program, such as a logic circuit.

[0026] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0027] 1...thermal printer, 10...thermal head, 11...heating element, 12...drive circuit, 20...motor group, 30...motor driver, 40...sensor element group, 50...sensor circuit, 60...clock generation circuit, 70...input port, 80...CPU, 90...ROM, 100...RAM, 110...CPLD.

Claims

1. a thermal head having a large number of heating elements divided into a plurality of blocks, and inputting drive data for driving the large number of heating elements in parallel in synchronization with a plurality of first clock signals which are different for each of the plurality of blocks; a drive data generating unit that generates a plurality of drive data for each of the plurality of blocks from print data and outputs the plurality of drive data in synchronization with a plurality of second clock signals; a clock generating unit that generates a plurality of clock signals that are out of phase with each other as the first clock signal; a drive data supply unit that receives the plurality of drive data output from the drive data generation unit in synchronization with the plurality of second clock signals and supplies the plurality of drive data to the thermal head in synchronization with the plurality of first clock signals generated by the clock generation unit; A thermal printer comprising:

2. The thermal head has the multiple heating elements divided into n blocks (n is an integer), the clock generating unit generates n first clock signals whose phases differ by 360 / n degrees; 2. The thermal printer according to claim 1.

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