Feedback amplifier circuit

Abstract

To provide a feedback amplifier circuit that obtains a large feedback inductance as an inductance to eliminate parasitic capacitance between a gate terminal and a drain terminal.SOLUTION: The feedback amplifier circuit includes a transistor 5 whose source terminal is grounded, a first interdigital capacitor 11 connected to a drain terminal of the transistor 5, and a second interdigital capacitor 12 that is connected to a gate terminal of the transistor 5 and electrically coupled to the first interdigital capacitor 11.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a feedback amplifier circuit.

Background Art

[0002] For example, there is a feedback amplifier circuit including a transistor that amplifies a signal in a frequency band exceeding 100 GHz (see, for example, Non-Patent Document 1). In this feedback amplifier circuit, an inductor is connected between the gate terminal and the drain terminal of the transistor in order to cancel the parasitic capacitance between the gate terminal and the drain terminal of the transistor.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The self-resonant frequency of an inductor with a spiral layout is generally 100 GHz or less. Therefore, an inductor with a spiral layout cannot obtain a positive inductance in a frequency band exceeding 100 GHz. For this reason, when obtaining inductance in a frequency band exceeding 100 GHz, a transmission line is often used as the inductor. However, the transmission line has a physical line length dependency in that it has a maximum inductance at a line length of one-quarter wavelength and becomes zero at a line length of one-half wavelength. Also, in a frequency band exceeding 100 GHz, the wavelength is short. Therefore, in a frequency band exceeding 100 GHz, the inductance obtained by the transmission line may be small. Therefore, the feedback amplifier circuit disclosed in Non-Patent Document 1 had the problem that, when a transmission line was used as the inductor, it was sometimes not possible to obtain the inductance necessary to eliminate the parasitic capacitance between the gate terminal and the drain terminal.

[0005] This disclosure was made to solve the above-mentioned problems, and aims to provide a feedback amplifier circuit that can obtain a larger inductance than the feedback amplifier circuit disclosed in Non-Patent Document 1 as the inductance for eliminating parasitic capacitance between the gate terminal and the drain terminal. [Means for solving the problem]

[0006] The feedback amplifier circuit according to this disclosure comprises a transistor whose source terminal is grounded, a first interdigital capacitor connected to the drain terminal of the transistor, and a second interdigital capacitor connected to the gate terminal of the transistor and electrically coupled to the first interdigital capacitor. The device comprises a first DC blocking capacitor with one end connected to the gate terminal of a transistor, a second DC blocking capacitor with one end connected to the drain terminal of a transistor, a first quarter-wavelength transmission line with one end connected to the drain terminal of a transistor, and a second quarter-wavelength transmission line with one end connected to the gate terminal of a transistor, wherein the first interdigital capacitor and the second interdigital capacitor are connected in series, and the frequency of the signal to be amplified applied to the other end of the first DC blocking capacitor is higher than the respective capacitive self-resonant frequencies of the first interdigital capacitor and the second interdigital capacitor. [Effects of the Invention]

[0007] According to this disclosure, a larger inductance can be obtained as the inductance for eliminating parasitic capacitance between the gate terminal and the drain terminal than that of the feedback amplifier circuit disclosed in Non-Patent Document 1. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram showing the feedback amplifier circuit according to Embodiment 1. [Figure 2] This is an explanatory diagram showing the physical line length dependence of transmission lines. [Figure 3] This is an explanatory diagram showing the oblique projection structure of the first interdigital capacitor 11 and the oblique projection structure of the second interdigital capacitor 12. [Figure 4] This is an equivalent circuit diagram showing the first interdigital capacitor 11. [Figure 5]This is an explanatory diagram showing the frequency characteristics of the capacitance and inductance of the first interdigital capacitor 11. [Figure 6] This diagram illustrates the frequency characteristics of capacitance and inductance when two interdigital capacitors are connected in series but are not coupled to each other. [Figure 7] This is an equivalent circuit diagram when the first interdigital capacitor 11 and the second interdigital capacitor 12 are coupled together. [Figure 8] This diagram illustrates the frequency characteristics of capacitance and inductance when two interdigital capacitors are connected in series while being mutually coupled. [Figure 9] This is a diagram showing the feedback amplifier circuit according to Embodiment 2. [Figure 10] This is a diagram showing the feedback amplifier circuit according to Embodiment 3. [Figure 11] This is an equivalent circuit diagram when the first interdigital capacitor 11, the second interdigital capacitor 12, and the third interdigital capacitor 14 are coupled together. [Modes for carrying out the invention]

[0009] To provide a more detailed explanation of this disclosure, the forms for implementing this disclosure will be described below with reference to the attached drawings.

[0010] Embodiment 1. Figure 1 is a diagram showing the configuration of a feedback amplifier circuit according to Embodiment 1. The feedback amplifier circuit shown in Figure 1 has a signal input terminal 1, a signal output terminal 2, a drain power supply terminal 3, and a gate power supply terminal 4. The signal to be amplified is supplied to signal input terminal 1. The signal to be amplified is, for example, a signal in the frequency band above 100 GHz. Signal output terminal 2 is a terminal for outputting the signal after it has been amplified by the feedback amplifier circuit. A DC drain voltage is applied to the drain power supply terminal 3, and a DC gate voltage is applied to the gate power supply terminal 4.

[0011] The feedback amplifier circuit shown in FIG. 1 includes a transistor 5, a first DC blocking capacitor 6, a second DC blocking capacitor 7, a first quarter-wavelength transmission line (hereinafter referred to as "first λ / 4 transmission line") 8, a second quarter-wavelength transmission line (hereinafter referred to as "second λ / 4 transmission line") 9, and a feedback circuit 10.

[0012] The transistor 5 is realized by an N-type transistor. Examples of the N-type transistor include an N-type MOSFET (Metal Oxide Semiconductor Field Efect Transistor). The source terminal of the transistor 5 is grounded. When a signal to be amplified is applied to the gate terminal of the transistor 5, the transistor 5 outputs an amplified signal from the drain terminal. In the feedback amplifier circuit shown in FIG. 1, the transistor 5 is realized by an N-type transistor. However, the transistor 5 is not limited to being realized by an N-type transistor, and may be realized by, for example, a P-type transistor.

[0013] One end of the first DC blocking capacitor 6 is connected to the gate terminal of the transistor 5. The other end of the first DC blocking capacitor 6 is connected to the signal input terminal 1. The first DC blocking capacitor 6 is for blocking the DC component included in the signal to be amplified applied to the signal input terminal 1 and passing the desired signal included in the signal to be amplified. One end of the second DC blocking capacitor 7 is connected to the drain terminal of the transistor 5. The other end of the second DC blocking capacitor 7 is connected to the signal output terminal 2. The second DC blocking capacitor 7 is for blocking the DC component included in the amplified signal and passing the desired signal included in the amplified signal.

[0014] One end of the first λ / 4 transmission line 8 is connected to the drain terminal of transistor 5. The other end of the first λ / 4 transmission line 8 is connected to the drain power supply terminal 3. The first λ / 4 transmission line 8 is a line with a length of 1 / 4 wavelength in which the impedance becomes very high at the frequency of the signal to be amplified. The first λ / 4 transmission line 8 is used to supply the DC drain voltage applied to the drain power supply terminal 3 to the drain terminal of the transistor 5.

[0015] One end of the second λ / 4 transmission line 9 is connected to the gate terminal of transistor 5. The other end of the second λ / 4 transmission line 9 is connected to the gate power supply terminal 4. The second λ / 4 transmission line 9 is a line with a length of 1 / 4 wavelength in which the impedance becomes very high at the frequency of the signal to be amplified. The second λ / 4 transmission line 9 is used to supply the DC gate voltage applied to the gate power supply terminal 4 to the gate terminal of the transistor 5.

[0016] One end of the feedback circuit 10 is connected to the drain terminal of transistor 5. The other end of the feedback circuit 10 is connected to the gate terminal of transistor 5. The feedback circuit 10 includes a first interdigital capacitor 11 and a second interdigital capacitor 12. The first interdigital capacitor 11 is connected to the drain terminal of the transistor 5. The second interdigital capacitor 12 is connected to the gate terminal of transistor 5. The first interdigital capacitor 11 and the second interdigital capacitor 12 are electrically coupled with a coupling degree M. Specifically, the first interdigital capacitor 11 and the second interdigital capacitor 12 are connected via either a substrate or a conductor. The substrate is, for example, a silicon substrate.

[0017] Figure 2 is an explanatory diagram showing the dependence of a transmission line on its physical line length. As shown in Figure 2, transmission lines exhibit a physical dependence on line length, with maximum inductance at a line length of one-quarter wavelength and zero at a line length of half wavelength. Furthermore, wavelengths are shorter in the frequency band above 100 GHz. Therefore, the inductance obtained by the transmission line may be smaller in the frequency band above 100 GHz. Therefore, in the feedback amplifier circuit shown in Figure 1, the feedback circuit 10 includes a first interdigital capacitor 11 and a second interdigital capacitor 12 instead of an inductor realized by a transmission line.

[0018] Figure 3 is an explanatory diagram showing the oblique projection structure of the first interdigital capacitor 11 and the oblique projection structure of the second interdigital capacitor 12. The first interdigital capacitor 11 has multiple needle-shaped elongated electrodes 11a and multiple needle-shaped elongated electrodes 11b, and the second interdigital capacitor 12 has multiple needle-shaped elongated electrodes 12a and multiple needle-shaped elongated electrodes 12b. Each electrode 11a and each electrode 11b of the first interdigital capacitor 11 are arranged alternately in close proximity to each other so as to interlock. Furthermore, the electrodes 12a and 12b of the second interdigital capacitor 12 are arranged alternately in close proximity to each other so as to interlock. Terminal (1) in Figure 3 is connected to the drain terminal of transistor 5. Terminal (2) is connected to the gate terminal of transistor 5. The connection point in Figure 3 is the connection point between the first interdigital capacitor 11 and the second interdigital capacitor 12. For example, in a fine semiconductor process, the thickness of the wiring layer that makes up the first interdigital capacitor 11 and the second interdigital capacitor 12 is predetermined. Therefore, the capacitance and inductance of the feedback circuit 10 are determined by the lengths L of electrodes 11a, 11b, 12a, and 12b, the spacing d between electrodes 11a and 11b, the spacing d between electrodes 12a and 12b, and the number of electrodes 11a, 11b, 12a, and 12b. In the example shown in Figure 3, the bottom surfaces of the first interdigital capacitor 11 and the second interdigital capacitor 12 are located at a height h from the substrate.

[0019] Figure 4 is an equivalent circuit diagram showing the first interdigital capacitor 11. The equivalent circuit of the second interdigital capacitor 12 is the same as that of the first interdigital capacitor 11, and the equivalent circuit showing the second interdigital capacitor 12 is also shown in Figure 4. In the first interdigital capacitor 11 shown in Figure 4, terminal 51 corresponds to terminal (1) shown in Figure 3, and terminal 52 corresponds to the connection part shown in Figure 3. In the second interdigital capacitor 12, terminal 51 corresponds to the connection part shown in Figure 3, and terminal 52 corresponds to terminal (2) shown in Figure 3. Terminal 53 corresponds to either a substrate or a conductor, located at a distance h from the bottom surface of the first interdigital capacitor 11. Each of the first interdigital capacitor 11 and the second interdigital capacitor 12 corresponds to a device comprising a series circuit provided between terminals 51 and 52, and a capacitor connected in parallel with the series circuit. The series circuit is a circuit in which a resistor, an inductor, and a capacitor are connected in series.

[0020] Figure 5 is an explanatory diagram showing the frequency characteristics of capacitance and inductance of the first interdigital capacitor 11. The frequency characteristics of capacitance and inductance of the second interdigital capacitor 12 are the same as those of the first interdigital capacitor 11, and Figure 5 is also an explanatory diagram showing the frequency characteristics of capacitance and inductance of the second interdigital capacitor 12. In Figure 5, the horizontal axis represents frequency, and the vertical axis represents capacitance or inductance. The signal frequency 62 is generally set to a frequency band lower than the capacitive self-resonant frequency 61, where the capacitance is positive. This is because if the signal frequency 62 is higher than the capacitive self-resonant frequency 61, the inductance component becomes positive and the capacitance becomes negative. Unlike parallel plate capacitors, the first interdigital capacitor 11 can obtain inductance in a frequency band higher than the capacitive self-resonant frequency 61 by appropriately determining the length L of electrodes 11a and 11b, the distance between electrodes 11a and 11b, and the number of electrodes 11a and 11b. This inductance is approximately 10 pH.

[0021] When two interdigital capacitors are connected in series without being coupled to each other, an inductance in a frequency band higher than the capacitive self-resonant frequency 61 can be added to the feedback circuit 10, as shown in Figure 6. Figure 6 is an explanatory diagram showing the frequency characteristics of capacitance and inductance when two interdigital capacitors are connected in series but are not coupled to each other. In Figure 6, the horizontal axis represents frequency, and the vertical axis represents capacitance or inductance. As shown in Figure 6, by connecting two interdigital capacitors in series without being coupled to each other, it is possible to achieve an inductance of 20 pH to 30 pH. Furthermore, by inserting these two interdigital capacitors into a transmission line, it is possible to add the inductance of the transmission line.

[0022] When the first interdigital capacitor 11 and the second interdigital capacitor 12 are placed in close proximity to each other, such that they are closer than approximately one-eighth of a wavelength of the signal frequency, the first interdigital capacitor 11 and the second interdigital capacitor 12 are coupled via either a substrate or a conductor, as shown in Figure 7. Figure 7 is an equivalent circuit diagram when the first interdigital capacitor 11 and the second interdigital capacitor 12 are coupled together. When the distance between the first interdigital capacitor 11 and the second interdigital capacitor 12 is, for example, within tens of micrometers, strong mutual coupling occurs between the first interdigital capacitor 11 and the second interdigital capacitor 12.

[0023] As shown in Figure 8, a strong mutual coupling occurs between the first interdigital capacitor 11 and the second interdigital capacitor 12, resulting in the generation of an inductive self-resonant frequency 93. Furthermore, the inductive self-resonant frequency 93 occurs in a higher frequency range than the capacitive self-resonant frequency 91. As shown in Figures 5 and 6, when mutual coupling does not occur between the first interdigital capacitor 11 and the second interdigital capacitor 12, no inductive self-resonant frequency is generated. Figure 8 is an explanatory diagram showing the frequency characteristics of capacitance and inductance when two interdigital capacitors are connected in series while being mutually coupled. The occurrence of an inductive self-resonant frequency 93 means that inductances at frequencies higher than the capacitive self-resonant frequency 91 tend to increase as they approach the inductive self-resonant frequency 93. By utilizing this property, the signal frequency 92 is set between the capacitive self-resonant frequency 91 and the inductive self-resonant frequency 93, thereby enabling a large inductance that would not be possible in a configuration where an inductor is realized by the transmission line, or in a configuration where two interdigital capacitors are connected in series without being coupled to each other.

[0024] In silicon processes, transmission lines generally use a coplanar structure. A coplanar structure has signal lines, side-grounded conductors, and bottom-grounded conductors. The signal line width is approximately 10 μm, the distance between the signal line and the side grounding conductor is approximately 15 μm, and the width of the side grounding conductor is approximately 5 μm. Therefore, the width of the transmission line in a coplanar structure is approximately 50 μm. Consequently, the width of transmission lines in a coplanar structure tends to be wide. For example, a quarter-wavelength signal at 300 GHz requires a relatively short actual line length because it is surrounded by SiO2, the insulating layer of the wiring, but it still requires a length of about 100 μm. In contrast, when realizing inductance using two strongly coupled interdigital capacitors, only two interdigital capacitors with a width of about 10 μm and a length of about 30 μm need to be connected in series. Therefore, inductance from two strongly coupled interdigital capacitors can be implemented in a smaller area than a coplanar transmission line.

[0025] In the above embodiment 1, the feedback amplifier circuit is configured to include a transistor 5 whose source terminal is grounded, a first interdigital capacitor 11 connected to the drain terminal of transistor 5, and a second interdigital capacitor 12 connected to the gate terminal of transistor 5 and electrically coupled to the first interdigital capacitor 11. Therefore, the feedback amplifier circuit can obtain a larger inductance than the feedback amplifier circuit disclosed in Non-Patent Document 1 as the inductance for eliminating parasitic capacitance between the gate terminal and the drain terminal.

[0026] Embodiment 2. Embodiment 2 describes a feedback amplifier circuit that includes a passive element 13 connected in series with the first interdigital capacitor 11 and the second interdigital capacitor 12, respectively.

[0027] Figure 9 is a diagram showing a feedback amplifier circuit according to Embodiment 2. In Figure 9, the same reference numerals as in Figure 1 indicate the same or corresponding parts, so their explanation is omitted. The feedback amplifier circuit shown in Figure 9 comprises a transistor 5, a first DC blocking capacitor 6, a second DC blocking capacitor 7, a first λ / 4 transmission line 8, a second λ / 4 transmission line 9, and a feedback circuit 10a. The feedback circuit 10a includes a first interdigital capacitor 11, a second interdigital capacitor 12, and a passive element 13. The passive element 13 is implemented, for example, by an inductor. One end of the passive element 13 is connected to the gate terminal of the transistor 5. The other end of the passive element 13 is connected to the second interdigital capacitor 12.

[0028] In the feedback amplifier circuit shown in Figure 9, the passive element 13 is connected between the gate terminal of transistor 5 and the second interdigital capacitor 12. However, this is just one example; for example, the passive element 13 may be connected between the drain terminal of transistor 5 and the first interdigital capacitor 11.

[0029] The passive element 13 is not coupled to the first interdigital capacitor 11 and is not coupled to the second interdigital capacitor 12. In this state, the inductance of the passive element 13 is added to the inductance of the feedback circuit 10a. In other words, the presence of the passive element 13 in the feedback circuit 10a increases the inductance of the feedback circuit 10a. Also, the resistance of the passive element 13 is added to the resistance of the feedback circuit 10a. In other words, the presence of the passive element 13 in the feedback circuit 10a increases the resistance of the feedback circuit 10a.

[0030] Embodiment 3. Embodiment 3 describes a feedback amplifier circuit comprising a third interdigital capacitor 14 that is electrically coupled to the first interdigital capacitor 11 and the second interdigital capacitor 12, respectively.

[0031] Figure 10 is a configuration diagram showing a feedback amplifier circuit according to Embodiment 3. In Figure 10, the same reference numerals as in Figure 1 indicate the same or corresponding parts, so their explanation is omitted. The feedback amplifier circuit shown in Figure 10 comprises a transistor 5, a first DC blocking capacitor 6, a second DC blocking capacitor 7, a first λ / 4 transmission line 8, a second λ / 4 transmission line 9, and a feedback circuit 10b. The feedback circuit 10b includes a first interdigital capacitor 11, a second interdigital capacitor 12, and a third interdigital capacitor 14.

[0032] The third interdigital capacitor 14 is connected to the gate terminal of transistor 5. The third interdigital capacitor 14 is electrically coupled to the second interdigital capacitor 12 with a coupling degree N, and is electrically coupled to the first interdigital capacitor 11 with a coupling degree P. Specifically, the first interdigital capacitor 11, the second interdigital capacitor 12, and the third interdigital capacitor 14 are connected via either a substrate or a conductor.

[0033] Figure 11 is an equivalent circuit diagram when the first interdigital capacitor 11, the second interdigital capacitor 12, and the third interdigital capacitor 14 are coupled together. By coupling the first interdigital capacitor 11, the second interdigital capacitor 12, and the third interdigital capacitor 14, the feedback circuit 10b can obtain a larger inductance than the feedback circuit 10 shown in Figure 1. Furthermore, the feedback circuit 10b can set its inductive self-resonant frequency 93 to a lower frequency band than the feedback circuit 10 shown in Figure 1.

[0034] Furthermore, this disclosure allows for free combination of each embodiment, modification of any component in each embodiment, or omission of any component in each embodiment. [Explanation of Symbols]

[0035] 1 Signal input terminal, 2 Signal output terminal, 3 Drain power supply terminal, 4 Gate power supply terminal, 5 Transistor, 6 First DC blocking capacitor, 7 Second DC blocking capacitor, 8 First λ / 4 transmission line, 9 Second λ / 4 transmission line, 10, 10a, 10b Feedback circuit, 11 First interdigital capacitor, 11a, 11b electrodes, 12 Second interdigital capacitor, 12a, 12b electrodes, 13 Passive element, 14 Third interdigital capacitor, 51, 52, 53 Terminals, 61 Capacitive self-resonant frequency, 62 Signal frequency, 91 Capacitive self-resonant frequency, 92 Signal frequency, 93 Inductive self-resonant frequency.

Claims

1. A transistor with its source terminal grounded, A first interdigital capacitor connected to the drain terminal of the transistor, A second interdigital capacitor is connected to the gate terminal of the transistor and electrically coupled to the first interdigital capacitor, A first DC blocking capacitor, one end of which is connected to the gate terminal of the transistor, A second DC blocking capacitor, one end of which is connected to the drain terminal of the transistor, A first quarter-wavelength transmission line, one end of which is connected to the drain terminal of the transistor, The system comprises a second quarter-wavelength transmission line to which one end is connected to the gate terminal of the transistor, The first interdigital capacitor and the second interdigital capacitor are connected in series. The frequency of the signal to be amplified applied to the other end of the first DC blocking capacitor is higher than the capacitive self-resonant frequencies of the first interdigital capacitor and the second interdigital capacitor, respectively. A feedback amplifier circuit characterized by the following features.

2. The feedback amplifier circuit according to claim 1, characterized in that the first interdigital capacitor and the second interdigital capacitor are coupled via either a substrate or a conductor.

3. The feedback amplifier circuit according to claim 1, characterized by comprising a passive element connected in series with each of the first interdigital capacitor and the second interdigital capacitor.

4. The system comprises a third interdigital capacitor electrically coupled to the first interdigital capacitor and the second interdigital capacitor, respectively. The third interdigital capacitor is connected in series with the first interdigital capacitor and the second interdigital capacitor, respectively. The feedback amplifier circuit according to claim 1, characterized in that it is as described above.

5. The feedback amplifier circuit according to claim 4, characterized in that the first interdigital capacitor, the second interdigital capacitor, and the third interdigital capacitor are coupled via either a substrate or a conductor.

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