Pixel driving circuit and its driving method, display panel

Abstract

The pixel driving circuit (100) includes a data writing circuit (1), a light emission control circuit (2), and a light emitting diode chip (3). The data writing circuit (1) is electrically connected to a first scanning signal terminal (Gate1), a data signal terminal (Data), and a first node (N1). The light emission control circuit (2) is electrically connected to the first node (N1), an enable signal terminal (EM), a first voltage signal terminal (VDD), and a second node (N2). The light emission control circuit (2) is configured to transmit a first voltage signal received at the first voltage signal terminal (VDD) to the second node (N2). The light emitting diode chip (3) is electrically connected to the second node (N2) and a second voltage signal terminal (VSS). Here, the light emitting diode chip (3) includes a plurality of light emitting units (32). The light-emitting diode chip (3) is configured to drive a plurality of light-emitting units (32) included therein to emit light for different periods of time, or to drive at least two light-emitting units (32) to emit light for the same period of time, in cooperation with a first voltage signal from the second node (N2) and a second voltage signal received at the second voltage signal terminal (VSS).

Description

Cross-reference of related applications

[0001] This application claims priority to a Chinese patent application filed on May 31, 2021, with application number 202110605113.4, the entirety of which is incorporated into this application by reference. [Technical Field]

[0002] This disclosure relates to the field of display technology, and more particularly to pixel driving circuits and methods for driving the same, and to display panels. [Background technology]

[0003] Light-emitting diodes (LEDs) offer many advantages, including high efficiency, high brightness, high reliability, energy saving, and fast response speed, and are therefore widely used in fields such as conventional displays, near-eye displays, 3D (3-dimensional) displays, and transparent displays. [Overview of the Initiative] [Means for solving the problem]

[0004] In one embodiment, a pixel driving circuit is provided. The pixel driving circuit includes a data writing circuit, a light emission control circuit, and a light-emitting diode chip. The data writing circuit is electrically connected to a first scan signal terminal, a data signal terminal, and a first node. The data writing circuit is configured to transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal. The light emission control circuit is electrically connected to the first node, an enable signal terminal, a first voltage signal terminal, and a second node. The light emission control circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the second node under the control of the voltage at the first node and the enable signal transmitted by the enable signal terminal. The light-emitting diode chip is electrically connected to the second node and a second voltage signal terminal. , multiple It includes a number of light-emitting units. The light-emitting diode chip is driven to cause the multiple light-emitting units to emit light for different periods of time in cooperation with a first voltage signal from the second node and a second voltage signal received at the second voltage signal terminal, or Among the plurality of light-emitting parts It is configured to drive at least two light-emitting units to emit light during the same period of time.

[0005] In some embodiments, the plurality of light-emitting units include at least one first light-emitting unit and at least one second light-emitting unit. Of the at least one first light-emitting part The first bonding electrode of the first light-emitting unit is electrically connected to the second node, and the second bonding electrode of the first light-emitting unit is electrically connected to the second voltage signal terminal. Of the at least one second light-emitting part The first bonding electrode of the second light-emitting unit is electrically connected to the second voltage signal terminal, and the second bonding electrode of the second light-emitting unit is electrically connected to the second node.

[0006] In some embodiments, the light emission control circuit includes a first transistor and a second transistor. The control electrode of the first transistor is electrically connected to the enable signal terminal, the first electrode of the first transistor is electrically connected to the first voltage signal terminal, and the second electrode of the first transistor is electrically connected to a third node. The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the second node.

[0007] In some embodiments, the pixel drive circuit further includes a first reset compensation circuit. The first reset compensation circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the first node, the second node, the third node, and the second voltage signal terminal. The first reset compensation circuit is configured to reset the pixel drive circuit and compensate the threshold voltage of the second transistor under the control of the first scan signal and the second scan signal received at the second scan signal terminal.

[0008] In some embodiments, the first reset compensation circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. The control electrode of the third transistor is electrically connected to the first scan signal terminal, the first electrode of the third transistor is electrically connected to the second voltage signal terminal, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the second scan signal terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the fifth transistor is electrically connected to the second scan signal terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the fifth node. The control electrode of the sixth transistor is electrically connected to the first scan signal terminal, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the fifth node.

[0009] In some embodiments, the pixel driving circuit further includes a plurality of switching transistors. Of the plurality of light-emitting parts The first bonding electrode of the light-emitting section is Of the multiple switching transistors The second node is electrically connected via at least one switching transistor. And / or, the second bonding electrode of the light-emitting part is Of the multiple switching transistors at least one other It is electrically connected to the second voltage signal terminal via a switching transistor.

[0010] In some embodiments, the number of the plurality of light-emitting units is equal to the number of the plurality of switching transistors. The first bonding electrode of the light-emitting unit is electrically connected to the second node. directlyis connected, and the second bonding electrode of the light-emitting unit is electrically connected to the second voltage signal terminal via one switching transistor.

[0011] In some embodiments, the multiple number of the light-emitting units is less than the number of the plurality of switching transistors. Of the plurality of light-emitting parts One The the first bonding electrode of the light-emitting unit is electrically directly connected to the second node, Of the multiple switching transistors and is electrically connected to the first bonding electrode of another Of the plurality of light-emitting parts light-emitting unit via at least one switching transistor. The the first bonding electrode of the light-emitting unit is electrically connected to the first bonding electrode of another Among the plurality of light-emitting parts One The the second bonding electrode of the light-emitting unit is Of the multiple switching transistors electrically connected to the second voltage signal terminal via at least one other switching transistor, and is electrically connected to the first bonding electrode of another Of the multiple switching transistors light-emitting unit via at least one Furthermore, other switching transistor and is electrically connected to the first bonding electrode of another The aforementioned light-emitting unit via at least one The switching transistor. The aforementioned The second bonding electrode of another light-emitting unit is electrically directly connected to the second voltage signal terminal.

[0012] In some embodiments, the light-emitting control circuit includes a seventh transistor and an eighth transistor. The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the first voltage signal terminal, and the second electrode of the seventh transistor is electrically connected to the sixth node. The control electrode of the eighth transistor is electrically connected to the enable signal terminal, the first electrode of the eighth transistor is electrically connected to the sixth node, and the second electrode of the eighth transistor is electrically connected to the second node.

[0013] In some embodiments, the pixel driving circuit further includes a second reset compensation circuit. The second reset compensation circuit is electrically connected to the first scan signal terminal, the first node, and the sixth node. The second reset compensation circuit is configured to compensate the threshold voltage of the seventh transistor in response to the first scan signal. The second reset compensation circuit is further connected to the initial signal terminal and , at least one of the third scan signal terminal and the fourth scan signal terminal and The second reset compensation circuit is further configured to transmit an initial signal received at the initial signal terminal to the first node in response to a third scan signal received at the third scan signal terminal or a fourth scan signal received at the fourth scan signal terminal, thereby resetting the first node.

[0014] In some embodiments, the second reset compensation circuit includes an eleventh transistor and a second capacitor. The control electrode of the eleventh transistor is electrically connected to the first scanning signal terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the sixth node. The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the seventh node. Here, the control electrode of the seventh transistor is electrically connected to the first node via the second capacitor. The second reset compensation circuit is connected to the third scanning signal terminal ni When electrically connected, the second reset compensation circuit further includes a ninth transistor. The control electrode of the ninth transistor is electrically connected to the third scanning signal terminal, the first electrode of the ninth transistor is electrically connected to the initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node. The second reset compensation circuit is connected to the fourth scanning signal terminal niWhen electrically connected, the second reset compensation circuit further includes a tenth transistor. The control electrode of the tenth transistor is electrically connected to the fourth scanning signal terminal, the first electrode of the tenth transistor is electrically connected to the initial signal terminal, and the second electrode of the tenth transistor is electrically connected to the first node.

[0015] In some embodiments, the data writing circuit includes a 12th transistor. The control electrode of the 12th transistor is electrically connected to the first scan signal terminal, the first electrode of the 12th transistor is electrically connected to the data signal terminal, and the second electrode of the 12th transistor is electrically connected to the first node.

[0016] In another embodiment, a method for driving a pixel driving circuit as described in any of the above embodiments is provided. The driving method includes a data writing step and a light emission step. In the data writing step, in response to a first scan signal received at a first scan signal terminal, the data writing circuit is turned on and transmits the data signal received at the data signal terminal to a first node. In the light emission step, under the control of the voltage of the first node and an enable signal received at an enable signal terminal, the light emission control circuit is turned on and transmits the first voltage signal received at a first voltage signal terminal to a second node. In cooperation with the first voltage signal from the second node and the second voltage signal received at a second voltage signal terminal, a plurality of light-emitting parts in a light-emitting diode chip are made to emit light for different periods, or at least two light-emitting parts are made to emit light for the same period.

[0017] In yet another embodiment, a display substrate is provided. The display substrate includes a substrate and a pixel driving circuit as described in any of the plurality of embodiments described above. The plurality of pixel driving circuits are provided on one side of the substrate. Of the plurality of light-emitting units included in the light-emitting diode chip in the pixel driving circuit, each light-emitting unit includes a sequentially stacked first semiconductor layer, a quantum well layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer have different doping types. Here, the light-emitting unit further includes at least one of a first bonding electrode and a second bonding electrode. The first bonding electrode is electrically connected to the first semiconductor layer of the light-emitting unit. The second bonding electrode is electrically connected to the second semiconductor layer of the light-emitting unit.

[0018] In some embodiments, the light-emitting diode chip further includes a base. Multiple light-emitting portions included in the light-emitting diode chip are located on the same side of the base.

[0019] In some embodiments, the light-emitting portion includes a first bonding electrode and a second bonding electrode. Different light-emitting portions have different first bonding electrodes, and different light-emitting portions have different second bonding electrodes.

[0020] In some embodiments, the light-emitting unit includes a plurality of sub-light-emitting units arranged in series. Each sub-light-emitting unit includes a first sub-semiconductor layer, a first sub-quantum well layer, and a second sub-semiconductor layer, which are sequentially stacked. In the same light-emitting section one no sa The first sub-semiconductor layer of the light-emitting section is the same as above identical It is electrically connected to the first bonding electrode of the light-emitting section. In the same light-emitting section others no sa The second sub-semiconductor layer of the light-emitting section is the same as above identical It is electrically connected to the second bonding electrode of the light-emitting section.

[0021] In some embodiments, when the plurality of light-emitting units include at least one first light-emitting unit and at least one second light-emitting unit, the first semiconductor layer of the first light-emitting unit and the second semiconductor layer of the second light-emitting unit are electrically connected to one second bonding electrode, and the second semiconductor layer of the first light-emitting unit and the first semiconductor layer of the second light-emitting unit are electrically connected to another second bonding electrode.

[0022] In some embodiments, the light-emitting diode chip further includes a plurality of connection portions. The first semiconductor layer of the first light-emitting portion is Of the multiple connection parts The second semiconductor layer of the second light-emitting part is electrically connected via a single connector. The first semiconductor layer of the second light-emitting part is Among the multiple connection parts mentioned above, the other The first light-emitting section is electrically connected to the second semiconductor layer via a connecting portion.

[0023] In some embodiments, the first light-emitting unit includes a plurality of first sub-light-emitting units arranged in series, and the second light-emitting unit includes a plurality of second sub-light-emitting units arranged in series. Each first sub-light-emitting unit includes a sequentially stacked third sub-semiconductor layer, a second sub-quantum well layer, and a fourth sub-semiconductor layer. Each second sub-light-emitting unit includes a sequentially stacked fifth sub-semiconductor layer, a third sub-quantum well layer, and a sixth sub-semiconductor layer. Of the plurality of first sub-light-emitting units The third sub-semiconductor layer of one first sub-light-emitting section is electrically connected to the one second bonding electrode, and Of the plurality of second sub-light-emitting units It is electrically connected to the sixth sub-semiconductor layer of one of the second sub-light-emitting sections. Among the plurality of second sub-light-emitting units, the other The fifth sub-semiconductor layer of the second sub-light-emitting section is electrically connected to the other second bonding electrode, and Among the plurality of first sub-light-emitting units, It is electrically connected to the fourth sub-semiconductor layer of the first sub-light-emitting section.

[0024] In some embodiments, at least two of the first semiconductor layers of the light-emitting portion are integrally structured and electrically connected to the same first bonding electrode. [Brief explanation of the drawing]

[0025] To provide a clearer explanation of the technical concepts related to this disclosure, the drawings used to describe some embodiments of this disclosure will be briefly described below. However, it will be clear that the drawings in the following description are only those for some embodiments of this disclosure. Those skilled in the art can obtain other drawings from these. Furthermore, the drawings in the following description can be considered schematic diagrams and do not limit the actual dimensions of the products, the actual processes of the methods, the actual timing of the signals, etc., related to the embodiments of this disclosure.

[0026] [Figure 1] This diagram shows the relationship between current density and luminous efficiency of an LED according to one embodiment.

[0027] [Figure 2] This is a structural diagram of a display substrate according to some embodiments of the present disclosure.

[0028] [Figure 3] This is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] [Figure 4] This is a structural diagram of another pixel driving circuit according to some embodiments of the present disclosure.

[0030] [Figure 5] This is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.

[0031] [Figure 6] Figure 5 shows the equivalent circuit diagram of the pixel driving circuit during light emission.

[0032] [Figure 7] Figure 5 shows another equivalent circuit diagram of the pixel driving circuit during light emission.

[0033] [Figure 8] This is a timing control diagram corresponding to the pixel driving circuit shown in Figure 5, according to some embodiments of the present disclosure.

[0034] [Figure 9] This is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.

[0035] [Figure 10] This is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.

[0036] [Figure 11] This is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.

[0037] [Figure 12] This is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.

[0038] [Figure 13] These are timing control diagrams corresponding to the pixel driving circuits shown in Figures 10 to 11, according to some embodiments of this disclosure.

[0039] [Figure 14] This is a structural diagram of a light-emitting diode chip according to some embodiments of the present disclosure.

[0040] [Figure 15] This is a structural diagram of another light-emitting diode chip according to some embodiments of the present disclosure.

[0041] [Figure 16] Figure 15 is a cross-sectional view of the light-emitting diode chip along the line A-A'.

[0042] [Figure 17] This is a structural diagram of yet another light-emitting diode chip according to some embodiments of the present disclosure.

[0043] [Figure 18] Figure 17 is a cross-sectional view of the light-emitting diode chip along the line B-B'.

[0044] [Figure 19] This is a structural diagram of yet another light-emitting diode chip according to some embodiments of the present disclosure.

[0045] [Figure 20] Figure 19 is a cross-sectional view of the light-emitting diode chip along the C-C' line.

[0046] [Figure 21] This is a structural diagram of yet another light-emitting diode chip according to some embodiments of the present disclosure.

[0047] [Figure 22] This is a structural diagram of yet another light-emitting diode chip according to some embodiments of the present disclosure.

[0048] [Figure 23] Figure 22 is a cross-sectional view of the light-emitting diode chip along the D-D' line. [Modes for carrying out the invention]

[0049] The following describes, with reference to the drawings, some of the technical concepts of the embodiments of this disclosure clearly and completely. Of course, the embodiments described herein should be understood to be only a selection of the embodiments of this disclosure, and not all of them. All other embodiments that a person skilled in the art may obtain based on the embodiments of this disclosure are included in the claims of this disclosure.

[0050] Unless otherwise required by context, throughout this specification and the claims, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted as having an open, inclusive meaning, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties related to this embodiment or example are included in at least one embodiment or example of this disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any specific features, structures, materials, or properties described may be included in any one or more embodiments or examples in any suitable manner.

[0051] In the following, the terms “first” and “second” are merely for illustrative purposes and should not be understood as indicating or implying the relative importance of any technical feature or the number of such features. Accordingly, features limited by “first” and “second” may explicitly or implicitly include one or more such features. In the description of the embodiments of this disclosure, “multiple” means two or more unless otherwise specified.

[0052] In describing some embodiments, the term “connection” and related expressions may be used. For example, in describing some embodiments, the term “connection” may be used to indicate that two or more components have direct physical or electrical contact with one another. The embodiments disclosed herein are not necessarily limited to this specification.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0054] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, depending on the context, the term "when..." is optionally interpreted to mean "when..." or "on the occasion of..." or "in response to a decision of..." or "in response to the detection of...". Similarly, depending on the context, the phrases "when... is decided" or "[the described condition or event] is detected" are optionally interpreted to mean "when... is decided," or "in response to a decision of...," or "[the described condition or event] is detected," or "[the described condition or event] has been detected."

[0056] In this specification, the use of “to apply to…” or “configured to…” means an open and inclusive language that does not exclude devices to be applied to or arranged to perform additional tasks or steps.

[0057] Furthermore, the use of “based on” implies that any procedure, step, calculation, or other action performed “based on” one or more of the aforementioned conditions or values ​​may, in practice, be based on exceeding additional conditions or values, thus being open and inclusive.

[0058] As used herein, “approximately” or “approximately” includes the stated value and the mean value within an acceptable range of deviation of a particular value, where the acceptable range of deviation is determined taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., limitations of the measurement system) as considered by those skilled in the art.

[0059] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thickness of layers and areas is shown enlarged for clarity. Therefore, variations in shape from the drawings may be assumed, for example, due to manufacturing techniques and / or tolerances. Accordingly, exemplary embodiments should not be interpreted as being limited to the shapes of the areas illustrated herein, and may include, for example, deviations in shape due to manufacturing. For example, an etching area shown as a rectangle typically has curved characteristics. Therefore, the areas shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of areas in the apparatus, nor are they intended to limit the scope of the exemplary embodiments.

[0060] The transistors used in the circuits provided by the embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices having the same characteristics, and in the embodiments of this disclosure, thin-film transistors will be described as examples.

[0061] In some embodiments, the control electrode of each transistor used in the pixel driving circuit is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. The source and drain of the transistor may be structurally symmetrical, and therefore they do not have to be structurally distinguishable; that is, the first electrode and the second electrode of the transistor in the embodiments of this disclosure do not have to be structurally distinguishable. Exemplarily, if the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain. Exemplarily, if the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0062] In the circuits provided by the embodiments of this disclosure, “nodes” do not represent actual existing components, but rather represent the confluence points of relevant electrical connections in a circuit diagram; that is, these nodes are equivalently formed by the confluence points of relevant electrical connections in a circuit diagram.

[0063] In one embodiment, Figure 1 shows the relationship between the luminous efficiency of an LED and the current density flowing through the LED. As can be seen from Figure 1, at low current densities, for example, at current densities J1 to J2, the current density flowing through the LED is small, and the luminous efficiency of the LED is low. At high current densities, for example, at current densities J2 to J3, the luminous efficiency of the LED is high.

[0064] In conventional technology, LEDs have a large light-emitting area, which tends to reduce the current density flowing through the LED, and further reduces the LED's luminous efficiency. However, increasing the current density to improve the LED's luminous efficiency can also increase power consumption. Furthermore, when an LED maintains high luminous efficiency for a long period, it operates under high current density conditions for extended periods, which causes the LED's temperature to rise, leading to heat accumulation, which further affects the LED's structural stability and reduces its luminous efficiency.

[0065] In view of this, the display board 1000 provided by some embodiments of the present disclosure includes a substrate 200 and a plurality of pixel driving circuits 100 provided on one side of the substrate 200, as shown in Figure 2. These plurality of pixel driving circuits 100 cooperate with each other to cause the display board 1000 to display an image.

[0066] There are multiple types of the aforementioned substrate 200, and they can be selectively provided according to actual requirements.

[0067] For example, the substrate 200 may be a rigid substrate. This rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0068] For example, the substrate 200 may be a flexible substrate. This flexible substrate may be, for example, a PET (Polymethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display substrate 1000 may be a flexible display substrate.

[0069] In some examples, as shown in Figure 2, the display board 1000 may further include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of light emission control lines EL provided on one side of the board 200. Here, the plurality of gate lines GL may extend in a first direction X, and the plurality of data lines DL may extend in a first direction X. 2 direction Y The multiple light-emitting control signal lines EL may be extended in the first direction X.

[0070] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be selectively set according to the actual requirements. For example, the angle between the first direction X and the second direction Y may be 85°, 89°, or 90°, etc.

[0071] The above-mentioned multiple pixel driving circuits 100 are, The pixel driving circuits 100 may be arranged in multiple rows and columns, with the pixel driving circuits 100 in each row arranged in a first direction X and the pixel driving circuits 100 in each column arranged in a second direction Y.

[0072] For example, pixel driving circuits 100 arranged in a single row along a first direction X can be called a row of pixel driving circuits 100, and pixel driving circuits 100 arranged in a single column along a second direction Y can be called a column of pixel driving circuits 100. A row of pixel driving circuits 100 may be electrically connected to, for example, at least one gate line GL and at least one light emission control signal line EL, and a column of pixel driving circuits 100 may be electrically connected to, for example, one data line DL. Here, In the same line The number of gate lines GL and light emission control line EL electrically connected to the pixel driving circuit 100 may be determined according to the configuration of the pixel driving circuit 100.

[0073] The pixel driving circuit 100 can emit light by receiving a scanning signal from the gate line GL, a data signal from the data line DL, and an enable signal from the light emission control signal line EL.

[0074] In some examples, as shown in Figures 3 to 5 and Figures 9 to 12, the pixel driving circuit 100 includes a data writing circuit 1, a light emission control circuit 2, and a light-emitting diode chip 3. Here, the data writing circuit 1 and the light emission control circuit 2 are electrically connected, and the light emission control circuit 2 and the light-emitting diode chip 3 are electrically connected.

[0075] For example, see Figures 5 and 14. Figures 15, 17, 19, and 21, figure 22 As shown, the light-emitting diode chip 3 includes a plurality of light-emitting units 32.

[0076] Exemplary, as shown in Figure 5 and Figures 14 to 23, the light-emitting diode chip 3 may further include a base 31. Here, the multiple light-emitting units 32 included in the light-emitting diode chip 3 may be located on the same side of the base 31. That is, the above-mentioned multiple light-emitting units 32 belong to the same light-emitting diode chip 3.

[0077] Furthermore, the light emission control circuit 2 described above can transmit the first voltage signal to the second node N2. The light-emitting diode chip described above. 3This can be used to drive the multiple light-emitting units 32 described above to emit light at different times, or to drive at least two of the light-emitting units 32 to emit light at the same time, in cooperation with the first voltage signal from the second node N2 and the second voltage signal received at the second voltage signal terminal VSS.

[0078] The electrical connection between the data writing circuit 1, the light emission control circuit 2, and the light-emitting diode chip 3, as well as the configuration of the data writing circuit 1 and the light emission control circuit 2, can be found in the related explanations below, so their explanation is omitted here.

[0079] There are multiple types of structures for the light-emitting diode chip 3 described above. For example, the structure of the light-emitting diode chip 3 may be a wire-bonding structure, a vertical structure, or a flip-chip structure.

[0080] The following schematic explanation of the structure of the light-emitting diode chip 3 will be given using Figures 14 to 23 as an example, assuming that the structure of the light-emitting diode chip 3 is a flip-chip structure.

[0081] There are several types of light-emitting diode chips 3 as described above, and they can be selectively provided according to actual needs.

[0082] For example, the light-emitting diode chip 3 may be a sub-millimeter light-emitting diode (Mini LED) chip, or a micro light-emitting diode (Micro LED) chip.

[0083] There are multiple types of base 31 as described above, and they can be selected and set according to actual needs.

[0084] For example, the base 31 may be a gallium phosphide (GaP) base, a gallium arsenide (GaAs) base, a silicon base, a silicon carbide base, a sapphire base, or the like.

[0085] After selectively bonding the light-emitting diode chip 3 to the light-emitting control circuit 2 in the pixel driving circuit 100, the base 31 on the light-emitting diode chip 3 can be removed so that the light-emitting diode chip 3 in the pixel driving circuit 100 contains only the multiple light-emitting parts 32. Of course, the base 31 may be left on after bonding the light-emitting diode chip 3 to the light-emitting control circuit 2 in the pixel driving circuit 100. Specifically, this can be selectively set according to the actual requirements.

[0086] As an example, as shown in Figures 14 to 16, each light-emitting section 32 includes a sequentially stacked first semiconductor layer 321, a quantum well (Multiple Quantum Well, MQW) layer 322, and a second semiconductor layer 323. Here, the first semiconductor layer 321 is closer to the base 31 than the quantum well layer 322. The first semiconductor layer 321 and the quantum well layer 322 may be in direct contact, for example, and the quantum well layer 322 and the second semiconductor layer 323 may be in direct contact, for example.

[0087] For example, the material of the quantum well layer 322 may be gallium nitride (GaN).

[0088] Selectively, the first semiconductor layer 321 and the second semiconductor layer 323 have different doping types.

[0089] For example, the material of the first semiconductor layer 321 may be a P-type semiconductor material, while the material of the second semiconductor layer 323 may be an N-type semiconductor material. Alternatively, the material of the first semiconductor layer 321 may be an N-type semiconductor material, while the material of the second semiconductor layer 323 may be a P-type semiconductor material.

[0090] The materials for the first semiconductor layer 321 and the second semiconductor layer 323 can be of multiple types and can be selectively set according to actual requirements. For example, the first semiconductor layer 321 and the second semiconductor layer 323 may have the same intrinsic semiconductor material, which may be GaN, GaP, aluminum gallium arsenide (AlGaAs), or aluminum gallium indium phosphide (AlGaInP).

[0091] The type of base 31 in the light-emitting diode chip 3 can be determined according to the materials of the first semiconductor layer 321 and the second semiconductor layer 323 in the light-emitting section 32 described above.

[0092] Here, when different voltages are applied to the first semiconductor layer 321 and the second semiconductor layer 323 to form an electric field between them, if the intrinsic semiconductor materials of both the first semiconductor layer 321 and the second semiconductor layer 323 are GaN, the light-emitting unit 32 can emit green or blue light. If the intrinsic semiconductor materials of both the first semiconductor layer 321 and the second semiconductor layer 323 are GaP, AlGaAs, or AlGaInP, the light-emitting unit 32 can emit red light.

[0093] Furthermore, when different voltages are applied to the first semiconductor layer 321 and the second semiconductor layer 323 to form an electric field between them, that is, when a PN junction with a barrier is formed between the first semiconductor layer 321 and the second semiconductor layer 323, when minority carriers and majority carriers recombine in the overlapping region along the stacking direction of the first semiconductor layer 321, the quantum well layer 322, and the second semiconductor layer 323, excess energy is emitted as light, and electrical energy is directly converted into light energy. Therefore, the overlapping region of the first semiconductor layer 321, the quantum well layer 322, and the second semiconductor layer 323 in the stacking direction is basically the light-emitting region of the light-emitting part 32, and the area of ​​the overlapping region of the first semiconductor layer 321, the quantum well layer 322, and the second semiconductor layer 323 in the stacking direction is basically the light-emitting area of ​​the light-emitting part 32.

[0094] As an example, as shown in Figures 14 to 23, the quantum well layers 322 in any two adjacent light-emitting units 32 are provided independently of each other, and the second semiconductor layers 323 in any two adjacent light-emitting units 32 are provided independently of each other. That is, this means that each light-emitting unit 32 can have a corresponding light-emitting region. The light-emitting diode chip 3 includes a plurality of light-emitting units 32 and has a plurality of corresponding independent light-emitting regions.

[0095] Exemplary, as shown in Figures 14 to 23, each light-emitting unit 32 further includes at least one of the first bonding electrode 324 and the second bonding electrode 325. That is, the light-emitting unit 32 may include only the first bonding electrode 324. Alternatively, the light-emitting unit 32 may include only the second bonding electrode 325. Alternatively, the light-emitting unit 32 may include both the first bonding electrode 324 and the second bonding electrode 325.

[0096] For example, the orthogonal projection shape of the first bonding electrode 324 onto the base 31 may be stripe-shaped or block-shaped, and the orthogonal projection area may be large. The orthogonal projection shape of the second bonding electrode 325 onto the base 31 may also be stripe-shaped or block-shaped, and the orthogonal projection area may be large. Selectively, the orthogonal projection areas of the first bonding electrode 324 and the second bonding electrode 325 onto the base 31 are both larger than the orthogonal projection area of ​​the second semiconductor layer 323 onto the base 31, in order to facilitate the subsequent bonding and electrical connection of the light-emitting diode chip 3 to other circuit structures.

[0097] Selectively, as shown in Figures 14 to 23, the first bonding electrode 324 may be electrically connected to the first semiconductor layer 321 of the corresponding light-emitting section 32, and the second bonding electrode 325 may be electrically connected to the second semiconductor layer 323 of the corresponding light-emitting section 32.

[0098] For example, if the light-emitting unit 32 includes only the first bonding electrode 324, the light-emitting unit 32 may share the second bonding electrode 325 with other light-emitting units 32. If the light-emitting unit 32 includes only the second bonding electrode 325, the light-emitting unit 32 may share the first bonding electrode 324 with other light-emitting units 32.

[0099] For example, as shown in Figures 14 to 23, the orthogonal projection of the second semiconductor layer 323 onto the base 31 lies within the range of the orthogonal projection of the first semiconductor layer 321 onto the base 31, and the orthogonal projection of the quantum well layer 322 onto the base 31 lies within the range of the orthogonal projection of the first semiconductor layer 321 onto the base 31. In this way, electrical connection between the first bonding electrode 324 and the first semiconductor layer 321 is facilitated.

[0100] In each light-emitting unit 32, one of the first bonding electrode 324 and the second bonding electrode 325 is electrically connected to the second node N2, and the other is electrically connected to the second voltage signal terminal VSS. This allows the system to drive at least two of the multiple light-emitting units 32 to emit light simultaneously in cooperation with the first voltage signal and the second voltage signal, or to drive one of the multiple light-emitting units 32 to emit light during a certain period, and to drive the other light-emitting units 32 to emit light during the next period.

[0101] Since the light-emitting diode chip 3 includes multiple light-emitting sections 32, the area of ​​the light-emitting region corresponding to each light-emitting section 32 is smaller than the total area of ​​the light-emitting diode chip 3. As a result, when the light-emitting sections 32 are driven to emit light using a voltage signal similar to that of conventional technology, the current density flowing through the light-emitting sections 32 can be improved, thereby improving the luminous efficiency of the light-emitting sections 32 and the light-emitting diode chip 3.

[0102] Based on this, when the light-emitting diode chip 3 needs to display low gradation (for example, 0 nit to 500 nit), the multiple light-emitting units 32 described above can be driven to emit light for different periods, that is, they can be driven to emit light sequentially. This avoids the temperature of the light-emitting diode chip 3 rising due to the long illumination time of one of the light-emitting units 32, which is advantageous for improving heat accumulation and, consequently, prevents a decrease in the luminous efficiency of the light-emitting diode chip 3 due to heat accumulation.

[0103] If the light-emitting diode chip 3 needs to display high gradation (e.g., 500 nits or more), at least two of the multiple light-emitting units 32 described above can be driven to illuminate simultaneously. In this case, the current density flowing through the at least two light-emitting units 32 may be low, such as the current densities of J1 to J2 shown in Figure 1. The at least two light-emitting units 32 as a whole can achieve high gradation display. In this way, the current density flowing through each light-emitting unit 32 can be reduced, which is advantageous in improving the phenomenon of heat accumulation, as it avoids generating a lot of heat even when the at least two light-emitting units 32 need to maintain illumination for a long time, thus preventing the temperature of the light-emitting diode chip 3 from rising, and preventing a decrease in the luminous efficiency of the light-emitting diode chip 3 due to heat accumulation.

[0104] Therefore, the display substrate 1000 provided by some embodiments of this disclosure is advantageous in improving the luminescence efficiency of the light-emitting diode chip 3 by designing the structure of the light-emitting diode chip 3 in the pixel driving circuit 100 to include a plurality of light-emitting parts 32 in which the light-emitting diode chip 3 can emit light independently, thereby reducing the light-emitting area of ​​each light-emitting part 32 and improving the current density flowing through the light-emitting parts 32.

[0105] Also, the display board 1000During display, the LED chip 3 can be driven to sequentially illuminate multiple light-emitting units 32 based on the displayed screen as needed, or to illuminate at least two light-emitting units 32 simultaneously. This prevents the light-emitting unit 32 from having a long illumination time when the current density flowing through it is high, and prevents the current density flowing through it from becoming high when the illumination time of the light-emitting unit 32 is long. Consequently, the temperature of the LED chip 3 can be prevented from rising, which is advantageous in improving the phenomenon of heat accumulation, and consequently prevents a decrease in the luminous efficiency of the LED chip 3 due to heat accumulation.

[0106] Here, there are several possible arrangements of the multiple light-emitting units 32 included in the light-emitting diode chip 3, and these can be selectively set according to the actual requirements.

[0107] In some embodiments, as shown in Figures 14 to 21, there is a gap between the first semiconductor layer 321 in any two adjacent light-emitting units 32, a gap between the quantum well layer 322 in any two adjacent light-emitting units 32, and a gap between the second semiconductor layer 323 in any two adjacent light-emitting units 32. That is, the plurality of light-emitting units 32 are provided independently of each other, and the light-emitting states of different light-emitting units 32 can be flexibly controlled.

[0108] Based on this, the connection relationships between the first semiconductor layer 321 of each light-emitting section 32 and the first bonding electrode 324, and between the second semiconductor layer 323 of each light-emitting section 32 and the second bonding electrode 325, include a variety of configurations and can be selectively set according to actual requirements.

[0109] In some examples, as shown in Figures 14 to 16, each light-emitting unit 32 includes a first bonding electrode 324 and a second bonding electrode 325. However, the first bonding electrode 324 included in different light-emitting units 32 is different, and the second bonding electrode 325 included in different light-emitting units 32 is different.

[0110] In other words, among the multiple light-emitting parts 32 included in the light-emitting diode chip 3, different light-emitting parts 32 do not share either the first bonding electrode 324 or the second bonding electrode 325. The first bonding electrodes 324 included in different light-emitting parts 32 are provided independently of each other, and the second bonding electrodes 325 included in different light-emitting parts 32 are provided independently of each other.

[0111] Exemplary, as shown in Figures 14 to 16, each light-emitting unit 32 further includes a layer-changed electrode 326. The light-emitting diode chip 3 further includes a sealing layer 33 provided on the side of the layer-changed electrode 326 that is farther from the base 31. Here, a passivation layer is provided between the layer-changed electrode 326 and the second semiconductor layer 323, and the orthogonal projection of the first semiconductor layer 321 of each light-emitting unit 32 onto the base 31 lies, for example, within the range of the orthogonal projection of the passivation layer onto the base 31. The first bonding electrode 324 and the second bonding electrode 325 are provided on the side of the sealing layer 33 that is farther from the base 31. The orthogonal projection of the first semiconductor layer 321 of each light-emitting unit 32 onto the base 31 lies, for example, within the range of the orthogonal projection of the sealing layer 33 onto the base 31.

[0112] For example, as shown in Figure 16, the layer conversion electrode 326 penetrates the passivation layer and directly contacts the second semiconductor layer 323, thereby making an electrical connection. Since the orthogonal projection of the layer conversion electrode 326 onto the base 31 and the orthogonal projection of the second semiconductor layer 323 onto the base 31 do not partially overlap, the second semiconductor layer 323 can be converted by the layer conversion electrode 326 and guided to other regions, making it easier to subsequently make an electrical connection with the second bonding electrode 325.

[0113] For example, as shown in Figure 16, the first bonding electrode 324 penetrates the encapsulation layer 33 and the passivation layer and makes direct contact with the first semiconductor layer 321 for electrical connection. The second bonding electrode 325 penetrates the encapsulation layer 33 and makes direct contact with the layer conversion electrode 326, and the second bonding electrode 325 is electrically connected to the second semiconductor layer 323 by the layer conversion electrode 326.

[0114] Selectively, the material of the layer conversion electrode 326 is a material with high light transmittance. For example, the material of the layer conversion electrode 326 is indium tin oxide (ITO).

[0115] By providing the above-mentioned multiple light-emitting units 32 independently of each other, and by providing the first bonding electrode 324 and the second bonding electrode 325 included in different light-emitting units 32 independently of each other, it becomes easy to independently control the light-emitting state of each light-emitting unit 32.

[0116] In this example, as shown in Figures 17 and 18, at least one of the light-emitting units 32 described above may include, for example, a plurality of sub-light-emitting units 32a arranged in series. In this case, the light-emitting unit 32 can be called a high-voltage light-emitting unit, and the voltage difference between the first bonding electrode 324 and the second bonding electrode 325 of the light-emitting unit 32 may be multiple times the voltage difference between the first bonding electrode 324 and the second bonding electrode 325 of the remaining light-emitting units 32. Here, the remaining light-emitting units 32 do not include a plurality of sub-light-emitting units 32a. If each of the multiple light-emitting units 32 included in the light-emitting diode chip 3 includes a plurality of sub-light-emitting units 32a arranged in series, the light-emitting diode chip 3 can be called a high-voltage chip.

[0117] For example, as shown in Figures 17 and 18, each sub-light-emitting section 32a includes a sequentially stacked first sub-semiconductor layer 321a, a first sub-quantum well layer 322a, and a second sub-semiconductor layer 323a. Here, there is a gap between the first sub-semiconductor layers 321a of any two adjacent sub-light-emitting sections 32a, a gap between the first sub-quantum well layers 322a of any two adjacent sub-light-emitting sections 32a, and a gap between the second sub-semiconductor layers 323a of any two adjacent sub-light-emitting sections 32a. In other words, the plurality of sub-light-emitting sections 32a are provided independently of each other.

[0118] Selectively, as shown in Figures 17 and 18, the first sub-semiconductor layer 321a of one sub-light-emitting section 32a is electrically connected to the first bonding electrode 324 of the light-emitting section 32 to which that sub-light-emitting section 32a belongs. The second sub-semiconductor layer 323a of the other sub-light-emitting section 32a is The one sub-light-emitting unit 32a and The other sub-light-emitting section 32a is electrically connected to the second bonding electrode 325 of the light-emitting section 32 to which it belongs.

[0119] The relationship between the one sub-light-emitting section 32a described above and the other sub-light-emitting sections 32a described above is related to the number of sub-light-emitting sections 32a included in the light-emitting section 32.

[0120] As shown in Figures 17 and 18, each sub-light-emitting section 32a may further include, for example, a sub-layer conversion electrode 326a electrically connected to the second sub-semiconductor layer 323a.

[0121] For example, as shown in Figures 17 and 18, the light-emitting unit 32 includes two sub-light-emitting units 32a. In this case, the light-emitting unit 32 is moreover, It may include one bridge electrode 327.

[0122] One end of the bridge electrode 327 described above may be electrically connected to the sub-layer conversion electrode 326a of one of the sub-light-emitting sections 32a, and further, it may be electrically connected to the second sub-semiconductor layer 323a of the one sub-light-emitting section 32a via the sub-layer conversion electrode 326a. The other end of the bridge electrode 327 may be electrically connected to the first sub-semiconductor layer 321a of another sub-light-emitting section 32a, passing through the passivation layer.

[0123] In this way, the one sub-light-emitting section 32a and the other sub-light-emitting section 32a are connected via the bridge electrode 327 by layer conversion, thereby realizing a series arrangement. In the process of driving the light emission of the light-emitting section 32, an electrical signal can be sequentially passed through the first bonding electrode 324 of the light-emitting section 32, the first sub-semiconductor layer 321a of the one sub-light-emitting section 32a, the sub-layer conversion electrode 326a of the one sub-light-emitting section 32a, the bridge electrode 327, the first sub-semiconductor layer 321a of the other sub-light-emitting section 32a, the sub-layer conversion electrode 326a of the other sub-light-emitting section 32a, and the second bonding electrode 325 of the light-emitting section 32 to drive the two sub-light-emitting sections 32a to emit light simultaneously.

[0124] Furthermore, the light-emitting unit 32 includes three sub-light-emitting units 32a. In this case, the light-emitting unit 32 may include two bridge electrodes 327. One of the above-described sub-light-emitting units 32a may be arranged in series with a third sub-light-emitting unit 32a via one bridge electrode 327, and the third sub-light-emitting unit 32a may be arranged in series with the other above-described sub-light-emitting units 32a via another bridge electrode 327. Here, the electrical connection method between two adjacent sub-light-emitting units 32a can be found in the description in the above example, and is therefore omitted here.

[0125] There are several types of orthogonal projection shapes of the bridge electrode 327 onto the base 31, and they can be provided according to the placement position of the sub-light-emitting unit 32a.

[0126] For example, the orthographic projection shape of the bridge electrode 327 onto the base 31 may include a striped shape, a U-shape, or an H-shape.

[0127] In some other examples, as shown in Figures 19 to 21, the multiple light-emitting units 32 included in the light-emitting diode chip 3 include at least one first light-emitting unit 32b and at least one second light-emitting unit 32c. That is, the number of first light-emitting units 32b may be one or more, and the number of second light-emitting units 32c may be one or more.

[0128] For example, see Figure 1 9 As shown, the first semiconductor layer 321 of the first light-emitting section 32b and the second semiconductor layer 323 of the second light-emitting section 32c are electrically connected to one second bonding electrode 325c. That is, the first semiconductor layer 321 of the first light-emitting section 32b and the second semiconductor layer 323 of the second light-emitting section 32c share one second bonding electrode 325c.

[0129] As shown in Figures 19 and 20, the second bonding electrode 325c in this example is, for example, the second bonding electrode 32 of the second light-emitting part 32c. 5 Yes. Of course, since the second bonding electrode 325c described above is further electrically connected to the first semiconductor layer 321 of the first light-emitting unit 32b, this second bonding electrode 325c may be considered as the first bonding electrode 324 of the first light-emitting unit 32b. Embodiment In order to clearly explain the structure of the light-emitting diode chip 3, the second bonding electrode 325c described above is assigned to the second light-emitting portion 32c.

[0130] Exemplary, as shown in Figures 19 and 20, the second semiconductor layer 323 of the first light-emitting section 32b and the first semiconductor layer 321 of the second light-emitting section 32c are electrically connected to the other second bonding electrode 325b. That is, the second semiconductor layer 323 of the first light-emitting section 32b and the first semiconductor layer 321 of the second light-emitting section 32c share the other second bonding electrode 325b.

[0131] As shown in Figures 19 and 20, the second bonding electrode 325b in this example is, for example, the second bonding electrode 32 of the first light-emitting unit 32b 5 Yes. Of course, since the second bonding electrode 325b described above is further electrically connected to the first semiconductor layer 321 of the second light-emitting unit 32c, this second bonding electrode 325b may be considered as the first bonding electrode 324 of the second light-emitting unit 32c. Embodiment In order to clearly explain the structure of the light-emitting diode chip 3, the second bonding electrode 325b described above is assigned to the first light-emitting part 32b.

[0132] In the process of transmitting an electrical signal, the electrical signal is transmitted from the second bonding electrode 325c of the second light-emitting unit 32c to the second bonding electrode 325b of the first light-emitting unit 32b, sequentially via the first semiconductor layer 321 and the second semiconductor layer 323 of the first light-emitting unit 32b, thereby driving the first light-emitting unit 32b to emit light. Alternatively, the electrical signal is transmitted from the second bonding electrode 325b of the first light-emitting unit 32b to the second bonding electrode 325c of the second light-emitting unit 32c, sequentially via the first semiconductor layer 321 and the second semiconductor layer 323 of the second light-emitting unit 32c, thereby driving the second light-emitting unit 32c to emit light.

[0133] The arrangement between the first light-emitting unit 32b and the second light-emitting unit 32c described above can be called a reverse bias arrangement. By adjusting the direction of electrical signal transmission, the first light-emitting unit 32b and the second light-emitting unit 32c can be made to emit light in sequence.

[0134] When the above-described plurality of light-emitting units 32 include a plurality of first light-emitting units 32b and a plurality of second light-emitting units 32c, the plurality of first light-emitting units 32b and the plurality of second light-emitting units 32c are divided into a plurality of groups, each group including one first light-emitting unit 32b and one second light-emitting unit 32c, and the first light-emitting unit 32b and the second light-emitting unit 32c are reverse-biased.

[0135] Of course, other arrangements are possible between the first light-emitting unit 32b and the second light-emitting unit 32c as described above, as long as the first light-emitting unit 32b and the second light-emitting unit 32c can be arranged in reverse bias.

[0136] In this example, as shown in Figures 19 and 20, the light-emitting diode chip 3 further includes, for example, a plurality of connection parts 34.

[0137] For example, as shown in Figure 19, of the first light-emitting section 32b and the second light-emitting section 32c, which are reverse-biased, the first semiconductor layer 321 of the first light-emitting section 32b is electrically connected to the second semiconductor layer 323 of the second light-emitting section 32c via a single connection section 34.

[0138] Selectively, as shown in Figure 20, one end of the connection portion 34 penetrates the passivation layer and directly contacts the first semiconductor layer 321 of the first light-emitting portion 32b for electrical connection. The other end of the connection portion 34 is electrically connected to the layer conversion electrode 326 of the second light-emitting portion 32c, and can further be electrically connected to the second semiconductor layer 323 of the second light-emitting portion 32c via this layer conversion electrode 326.

[0139] In this way, an electrical connection is achieved between the first semiconductor layer 321 of the first light-emitting section 32b and the second semiconductor layer 323 of the second light-emitting section 32c, as well as between the first semiconductor layer 321 of the first light-emitting section 32b and the corresponding second bonding electrode 325c.

[0140] For example, as shown in Figures 19 and 20, of the first light-emitting section 32b and the second light-emitting section 32c, which are reverse-biased, the first semiconductor layer 321 of the second light-emitting section 32c is electrically connected to the second semiconductor layer 323 of the first light-emitting section 32b via a single connection section 34.

[0141] Selectively, as shown in Figures 19 and 20, one end of the connection portion 34 penetrates the passivation layer and directly contacts the first semiconductor layer 321 of the second light-emitting portion 32c for electrical connection. The other end of the connection portion 34 is electrically connected to the layer conversion electrode 326 of the first light-emitting portion 32b, and can further be electrically connected to the second semiconductor layer 323 of the first light-emitting portion 32b via this layer conversion electrode 326.

[0142] In this way, an electrical connection is established between the first semiconductor layer 321 of the second light-emitting section 32c and the second semiconductor layer 323 of the first light-emitting section 32b, as well as between the first semiconductor layer 321 of the second light-emitting section 32c and the corresponding second bonding electrode 325b.

[0143] The material of the connection portion 34 described above can be of several types and can be selectively provided according to actual requirements. For example, chromium (Cr), titanium (Ti), etc. can be used as the material of the connection portion 34. For example, the material of the connection portion 34 is the same as the material of the bridge electrode 327 in some of the above examples.

[0144] The orthographic projection shape of the above-described connection portion 34 onto the base 31 can be of various shapes and can be determined according to the relative positional relationship between the first light-emitting portion 32b and the second light-emitting portion 32c.

[0145] For example, the orthogonal projection shape of the connecting portion 34 onto the base 31 includes a stripe shape, a U-shape, or an H-shape, etc.

[0146] In this example, as shown in Figure 21, the first light-emitting unit 32b described above includes, for example, a plurality of first sub-light-emitting units 32bb arranged in series. Here, each first sub-light-emitting unit 32bb includes a sequentially stacked third sub-semiconductor layer 321b, a second sub-quantum well layer 322b, and a fourth sub-semiconductor layer 323b. The plurality of first sub-light-emitting units 32bb are provided independently of each other, for example.

[0147] As shown in Figure 21, the above-described second light-emitting unit 32c includes, for example, a plurality of second sub-light-emitting units 32cc arranged in series. Here, each second sub-light-emitting unit 32cc includes a sequentially stacked fifth sub-semiconductor layer 321c, a third sub-quantum well layer 322c, and a sixth sub-semiconductor layer 323c. These plurality of second light-emitting units 32c are, for example, provided independently of each other.

[0148] For example, as shown in Figure 21, the third sub-semiconductor layer 321b of one of the multiple first sub-light-emitting units 32bb described above is electrically connected to the corresponding second bonding electrode 325c, and the sixth sub-semiconductor layer 323c of one of the multiple second sub-light-emitting units 32cc described above is electrically connected to the sixth sub-semiconductor layer 323c of one of the multiple second sub-light-emitting units 32cc described above.

[0149] Here, this first sub-light-emitting unit 32bb is the first sub-light-emitting unit 32bb that receives the electrical signal first among the plurality of first sub-light-emitting units 32bb described above. That is, in the process of transmitting the electrical signal, the electrical signal is transmitted to the corresponding second bonding electrode 325 described above. c After passing through, the signal is first transmitted to the first sub-light-emitting unit 32bb, and then transmitted to the remaining first sub-light-emitting units 32bb. This second sub-light-emitting unit 32cc is the second sub-light-emitting unit 32cc that receives the electrical signal last among the multiple second sub-light-emitting units 32cc described above. That is, in the process of transmitting the electrical signal, the electrical signal first passes through the other second sub-light-emitting units 32cc, and then passes through the said second sub-light-emitting unit 32cc to the corresponding second bonding electrode 325 described above. c It is transmitted to.

[0150] In this example, the second bonding electrode 325c is, for example, the second bonding electrode 325 of the second sub-light-emitting section 32cc. Of course, since the above-described second bonding electrode 325c is further electrically connected to the third sub-semiconductor layer 321b of the first sub-light-emitting section 32bb, the second bonding electrode 325c may be considered as the first bonding electrode 324 of the first sub-light-emitting section 32bb. EmbodimentIn order to clearly explain the structure of the light-emitting diode chip 3, the second bonding electrode 325c described above is assigned to the second sub-light-emitting section 32cc.

[0151] For example, as shown in Figure 21, the fifth sub-semiconductor layer 321c of one of the multiple second sub-light-emitting units 32cc described above is electrically connected to the corresponding second bonding electrode 325b, and is electrically connected to the fourth sub-semiconductor layer 323b of one of the multiple first sub-light-emitting units 32bb described above.

[0152] Here, the second sub-light-emitting unit 32cc is the second sub-light-emitting unit 32cc that first receives the electrical signal among the plurality of second sub-light-emitting units 32cc described above. That is, in the process of transmitting the electrical signal, the electrical signal passes through the corresponding other second bonding electrodes 325b described above, is first transmitted to the second sub-light-emitting unit 32cc, and then transmitted to the remaining second sub-light-emitting units 32cc. The first sub-light-emitting unit 32bb is the first sub-light-emitting unit 32bb that last receives the electrical signal among the plurality of first sub-light-emitting units 32bb described above. That is, in the process of transmitting the electrical signal, the electrical signal first passes through the other first sub-light-emitting units 32bb, and then passes through the first sub-light-emitting unit 32bb to be transmitted to the corresponding second bonding electrodes 325b described above.

[0153] In this example, the second bonding electrode 325b is, for example, the second bonding electrode 32 of the first sub-light-emitting unit 32bb. 5 Yes. Of course, since the second bonding electrode 325b described above is further electrically connected to the fifth sub-semiconductor layer 321c of the second sub-light-emitting section 32cc, the second bonding electrode 325b may be considered as the first bonding electrode 324 of the second sub-light-emitting section 32cc. Embodiment In order to clearly explain the structure of the light-emitting diode chip 3, the second bonding electrode 325b described above is assigned to the first sub-light-emitting section 32bb.

[0154] Selectively, the connection method between any two adjacent first sub-light-emitting units 32bb from the above-described plurality of first sub-light-emitting units 32bb can refer to the connection method between any two adjacent sub-light-emitting units 32a in some of the embodiments described above. The connection method between any two adjacent second sub-light-emitting units 32cc from the above-described plurality of second sub-light-emitting units 32cc can refer to the connection method between any two adjacent sub-light-emitting units 32a in some of the embodiments described above. A detailed explanation of this is omitted here.

[0155] In some other embodiments, as shown in Figures 22 and 23, the quantum well layer 322 in each light-emitting section 32 is provided independently, and the second semiconductor layer 323 in each light-emitting section 32 is provided independently. The first semiconductor layer 321 in at least two light-emitting sections 32 forms an integrated structure.

[0156] As a result, as shown in Figures 22 and 23, the first semiconductor layer 321 of at least two of the light-emitting units 32 described above may be electrically connected to the same first bonding electrode 324. In other words, these at least two light-emitting units 32 share one first bonding electrode 324.

[0157] During the transmission of an electrical signal, the electrical signal may be transmitted simultaneously to the first semiconductor layer 321 of the at least two light-emitting units 32 by passing through the first bonding electrode 324 described above. By controlling the connection relationship between the second bonding electrode 325 of the at least two light-emitting units 32 and the second node N2 or the second voltage signal terminal VSS, the at least two light-emitting units 32 can be driven to emit light simultaneously, or they can be driven to emit light at different times.

[0158] By integrating the first semiconductor layer 321 in at least two light-emitting sections 32, the patterning process for the first semiconductor layer 321 can be avoided, simplifying the manufacturing process of the light-emitting diode chip 3, and the number of first bonding electrodes 324 can be reduced, thereby simplifying the structure of the light-emitting diode chip 3.

[0159] For example, as shown in Figures 22 and 23, the first semiconductor layer 321 in the multiple light-emitting parts 32 included in the light-emitting diode chip 3 has an integrated structure. In this way, the material for the first semiconductor layer 321 can be formed on one side of the base 31, and then the first semiconductor layer 321 of the multiple light-emitting parts 32 can be formed. This is advantageous in further reducing the patterning process and further simplifying the manufacturing process of the light-emitting diode chip 3.

[0160] The structure of the pixel driving circuit 100 described above will be schematically explained below with reference to Figures 3 to 5 and Figures 9 to 12.

[0161] In some examples, as shown in Figures 3 to 5 and Figures 9 to 12, the data writing circuit 1 included in the pixel driving circuit 100 described above is electrically connected to the first scan signal terminal Gate 1, the data signal terminal Data, and the first node N1. Here, the data writing circuit 1 is configured to transmit the data signal received at the data signal terminal Data to the first node N1 in response to the first scan signal received at the first scan signal terminal Gate 1.

[0162] For example, if the level of the first scan signal is at the level required to turn on the data writing circuit 1, the data writing circuit 1 can be turned on under the control of the first scan signal, receive the data signal and transmit it to the first node N1, and charge the first node N1.

[0163] In some examples, as shown in Figures 3 to 5 and Figures 9 to 12, the light emission control circuit 2 included in the pixel driving circuit 100 described above is electrically connected to the first node N1, the enable signal terminal EM, the first voltage signal terminal VDD, and the second node N2. Here, the light emission control circuit 2 is configured to transmit the first voltage signal received at the first voltage signal terminal VDD to the second node N2 under the control of the voltage of the first node N1 and the enable signal transmitted by the enable signal terminal EM.

[0164] For example, if the voltage at the first node N1 is the voltage required to turn on the light emission control circuit 2, and the level of the enable signal is the level required to turn on the light emission control circuit 2, the light emission control circuit 2 can be turned on under the control of the voltage and enable signal at the first node N1, receive the first voltage signal and transmit it to the second node N2.

[0165] In some examples, as shown in Figures 3 to 5 and Figures 9 to 12, the light-emitting diode chip 3 included in the pixel driving circuit 100 described above is electrically connected to the second node N2 and the second voltage signal terminal VSS. Here, the light-emitting diode chip 3 includes a plurality of light-emitting units 32. The light-emitting diode chip 3 is configured to drive the plurality of light-emitting units 32 included in the light-emitting diode chip 3 to emit light for different periods, or to drive at least two light-emitting units 32 to emit light for the same period, through the cooperation of a first voltage signal from the second node N2 and a second voltage signal received at the second voltage signal terminal VSS.

[0166] For example, within the same period, the first voltage signal may be at a high level and the second voltage signal at a low level. Alternatively, the first voltage signal may be at a low level and the second voltage signal at a high level. That is, within the same period, a voltage difference exists between the first voltage signal and the second voltage signal. In cooperation with the first and second voltage signals, an electrical signal can be generated between the second node N2 and the second voltage signal terminal VSS to drive the light-emitting unit 32 to emit light. This electrical signal can drive different light-emitting units 32 to emit light for different periods, or drive at least two light-emitting units 32 to emit light simultaneously for the same period.

[0167] The beneficial effects that can be achieved by the pixel driving circuit 100 according to some embodiments of this disclosure are the same as the beneficial effects that can be achieved by the display substrate 1000 according to some embodiments described above, so their explanation is omitted here.

[0168] The term "electrical connection" as used here may refer to either a direct or indirect electrical connection, and can be selectively provided as needed.

[0169] In some embodiments, as shown in Figure 5, the plurality of light-emitting units 32 described above include at least one first light-emitting unit 32b and at least one second light-emitting unit 32c.

[0170] In some examples, as shown in Figure 5, the first bonding electrode 324 of the first light-emitting unit 32b is electrically connected to the second node N2 described above, and the second bonding electrode 325 of the first light-emitting unit 32b is electrically connected to the second voltage signal terminal VSS. The first bonding electrode 324 of the second light-emitting unit 32c is electrically connected to the second voltage signal terminal VSS, and the second bonding electrode 325 of the second light-emitting unit 32c is electrically connected to the second node N2.

[0171] Here, structurally, the first bonding electrode 324 of the first light-emitting section 32b and the second bonding electrode 325 of the second light-emitting section 32c may be the same bonding electrode, and the second bonding electrode 325 of the first light-emitting section 32b and the first bonding electrode 324 of the second light-emitting section 32c may be the same bonding electrode. Specifically, you can refer to the descriptions in some of the embodiments described above, and we will omit those descriptions here.

[0172] As described above, the first light-emitting section 32b and the second light-emitting section 32c are reverse-biased. In this way, when the first voltage signal is at a high level and the second voltage signal is at a low level, the first light-emitting section 32b can be made to light up by the interaction of the first and second voltage signals. When the first voltage signal is at a low level and the second voltage signal is at a high level, the second light-emitting section 32c can be made to light up by the interaction of the first and second voltage signals. In other words, the first light-emitting section 32b and the second light-emitting section 32c may be made to light up sequentially while the light-emitting diode chip 3 is displaying.

[0173] Thus, when the light-emitting diode chip 3 needs to display low gradation, the first light-emitting unit 32b and the second light-emitting unit 32c can be driven to emit light for different periods. This is advantageous in improving heat accumulation and preventing a decrease in the luminous efficiency of the light-emitting diode chip 3 due to heat accumulation, as the temperature of the light-emitting diode chip 3 would rise due to a long illumination time of the first light-emitting unit 32b or the second light-emitting unit 32c.

[0174] Furthermore, by providing the first light-emitting section 32b and the second light-emitting section 32c with reverse bias, it is advantageous to improve the display life of the light-emitting diode chip 3.

[0175] Exemplary, as shown in Figure 5, the electrical connection between the first bonding electrode 324 of the first light-emitting unit 32b and the second node N2 is a direct electrical connection. The electrical connection between the second bonding electrode 325 of the first light-emitting unit 32b and the second voltage signal terminal VSS is a direct electrical connection. The electrical connection between the first bonding electrode 324 of the second light-emitting unit 32c and the second voltage signal terminal VSS is a direct electrical connection. The electrical connection between the second bonding electrode 325 of the second light-emitting unit 32c and the second node N2 is a direct electrical connection.

[0176] Based on the arrangement of the light-emitting portion 32 in the light-emitting diode chip 3, in some examples, the light-emitting control circuit 2 may include a first transistor T1 and a second transistor T2, as shown in Figure 5. Here, the first transistor T1 is, for example, an N-type transistor, and the second transistor T2 is, for example, a P-type transistor.

[0177] Exemplary, as shown in Figure 5, the control electrode of the first transistor T1 is electrically connected to the enable signal terminal EM, the first electrode of the first transistor T1 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0178] For example, if the level of the enable signal transmitted by the enable signal terminal EM is high, the first transistor T1 can be turned on under the control of the enable signal and receive the first voltage signal and transmit it to the third node N3.

[0179] Exemplary, as shown in Figure 5, the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0180] For example, when the voltage at the first node N1 is low, the second transistor T2 is turned on under the control of the voltage at the first node N1, and can transmit the first voltage signal from the third node N3 to the second node N2.

[0181] In some examples, as shown in Figure 5, the data writing circuit 1 may include a 12th transistor T12, where the 12th transistor T12 is, for example, an N-type transistor.

[0182] For example, as shown in Figure 5, the control electrode of the 12th transistor T12 is electrically connected to the first scan signal terminal Gate1, the first electrode of the 12th transistor T12 is electrically connected to the data signal terminal Data, and the second electrode of the 12th transistor T12 is electrically connected to the first node N1.

[0183] For example, if the level of the first scan signal transmitted by the first scan signal terminal Gate1 is high, the 12th transistor T12 can be turned on under the control of the first scan signal, receive a data signal and transmit it to the first node N1 to charge the first node N1.

[0184] In some examples, as shown in Figures 4 and 5, the pixel driving circuit 100 may further include a first reset compensation circuit 4. This first reset compensation circuit 4 is electrically connected to the first scan signal terminal Gate 1, the second scan signal terminal Gate 2, the first node N1, the second node N2, the third node N3, and the second voltage signal terminal VSS. Here, the first reset compensation circuit 4 is configured to reset the pixel driving circuit 100 and compensate the threshold voltage of the second transistor T2 under the control of the first scan signal and the second scan signal received at the second scan signal terminal Gate 2.

[0185] By resetting the pixel driving circuit 100 and compensating the threshold voltage of the second transistor T2, the second transistor T2 in the light emission control circuit 2 can be turned on effectively for the corresponding period. This allows the second transistor T2 to transmit the first voltage signal without loss, which is advantageous for accurately controlling the light emission state of the first light emission unit 32b or the second light emission unit 32c.

[0186] In some examples, as shown in Figure 5, the first reset compensation circuit 4 may include a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. Here, the third transistor T3 and the fourth transistor T4 are, for example, both N-type transistors, and the fifth transistor T5 and the sixth transistor T6 are, for example, both P-type transistors.

[0187] Exemplary, as shown in Figure 5, the control electrode of the third transistor T3 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the third transistor T3 is electrically connected to the second voltage signal terminal VSS, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4.

[0188] For example, if the level of the first scan signal is high and the level of the second voltage signal is low, the third transistor T3 can be turned on under the control of the first scan signal, receive the second voltage signal and transmit it to the fourth node N4, and discharge the fourth node N4 to reset it.

[0189] For example, as shown in Figure 5, the control electrode of the fourth transistor T4 is electrically connected to the second scanning signal terminal Gate2, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5.

[0190] For example, if the level of the second scan signal is high, the fourth transistor T4 can be turned on under the control of the second scan signal, and the signal from the third node N3 can be transmitted to the fifth node N5.

[0191] Exemplary, as shown in Figure 5, the control electrode of the fifth transistor T5 is electrically connected to the second scanning signal terminal Gate2, the first electrode of the fifth transistor T5 is electrically connected to the second node N2, and the second electrode of the fifth transistor T5 is electrically connected to the fifth node N5.

[0192] For example, if the level of the second scan signal is low, the fifth transistor T5 can be turned on under the control of the second scan signal, and the signal from the second node N2 can be transmitted to the fifth node N5.

[0193] Exemplary, as shown in Figure 5, the control electrode of the sixth transistor T6 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0194] For example, when the level of the first scan signal is low, the sixth transistor T6 can be turned on under the control of the first scan signal, and the signal from the fourth node N4 can be transmitted to the first node N1.

[0195] Exemplary, as shown in Figure 5, the first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5. After the fourth node N4 is reset, the voltage difference between the fourth node N4 and the fifth node N5 is maintained substantially constant.

[0196] The following schematic explanation of the pixel driving circuit's operation method will be given with reference to the structure of the pixel driving circuit shown in Figure 5 and the timing diagram shown in Figure 8.

[0197] In some examples, during the display phase of one frame, the method for driving the pixel driving circuit includes a data writing phase S1, a compensation phase S2, and a light emission phase S3. Here, the light emission phase S3 includes, for example, a first light emission phase S31 and a second light emission phase S32.

[0198] During the data writing phase S1, the level of the first scan signal is high, the level of the second scan signal is high, the level of the enable signal is high, the level of the data signal is high, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0199] In response to the first scan signal received at the first scan signal terminal Gate1, the 12th transistor T12 in the data writing circuit 1 is turned on, and the data signal received at the data signal terminal data is transmitted to the first node N1. Since the level of the data signal is high, the voltage of the first node N1 can be raised to a high level by charging the first node N1 with the data signal at this time.

[0200] Furthermore, at this stage, the third transistor T3 in the first reset compensation circuit 4 is turned on under the control of the first scan signal, receives a low-level second voltage signal and transmits it to the fourth node N4, resetting the fourth node N4. The fourth transistor T4 in the first reset compensation circuit 4 is turned on under the control of the second scan signal, and the first transistor T1 in the light emission control circuit 2 is turned on under the control of the enable signal. The first transistor T1 can receive a high-level first voltage signal and transmit it to the third node N3, and the fourth transistor T4 can transmit the first voltage signal from the third node N3 to the fifth node N5, resetting the fifth node N5. In other words, the first capacitor C1 is also reset at this stage.

[0201] In compensation stage S2, the level of the first scan signal is high, the level of the second scan signal is high, the level of the enable signal is low, the level of the data signal is high, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0202] In the first reset compensation circuit 4, the third transistor T3 and the fourth transistor T4 remain in the ON state, the fifth node N5 is leaking current, and the voltage value of the first voltage signal is V Data -V th_tft2 It decreases to V. Data V indicates the voltage value of the data signal. th_tft2 This indicates the threshold voltage of the second transistor T2.

[0203] In the first light emission stage S31 of the light emission stage S3, the level of the first scan signal is low, the level of the second scan signal is high, the level of the enable signal is high, the level of the data signal is low, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0204] In the first reset compensation circuit 4, the fourth transistor T4 remains in the ON state, and the sixth transistor T6 in the first reset compensation circuit 4 is turned ON under the control of the first scan signal.

[0205] In the light emission control circuit 2, the first transistor T1 is turned on under the control of the enable signal. At this time, the voltage difference Vgs between the control electrode of the second transistor T2 and the first electrode in the light emission control circuit 2 is the difference between the voltage at the fourth node N4 and the voltage at the fifth node N5, i.e., Vgs = V SS -(V Data -V th_tft2 ) This is the result. At this time, the second transistor T2 in the light emission control circuit 2 is turned on. The light emission control circuit 2 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2.

[0206] Because the level of the first voltage signal is high and the level of the second voltage signal is low, the first light-emitting part 32b of the light-emitting diode chip 3 can emit light and the second light-emitting part 32c can be turned off in cooperation with the first and second voltage signals.

[0207] If there is one first light-emitting unit 32b, it can be driven to emit light, and if there are at least two first light-emitting units 32b, it can be driven to emit light simultaneously.

[0208] Taking the case where there is one first light-emitting unit 32b as an example, the equivalent circuit diagram of the pixel driving circuit 100 may be as shown in Figure 6, and the current I flowing through the first light-emitting unit 32b is as follows.

[0209]

number

[0210] In the second light emission stage S32 of the light emission stage S3, the level of the first scan signal is low, the level of the second scan signal is low, the level of the enable signal is high, the level of the data signal is low, the level of the first voltage signal is low, and the level of the second voltage signal is high.

[0211] In the first reset compensation circuit 4, the sixth transistor T6 remains in the ON state, and the fifth transistor T5 in the first reset compensation circuit 4 is turned ON under the control of the second scan signal.

[0212] In the light emission control circuit 2, the first transistor T1 remains in the ON state. Since the voltage difference Vgs between the control electrode and the first electrode of the second transistor T2 in the light emission control circuit 2 does not change, the second transistor T2 remains in the ON state.

[0213] Because the level of the first voltage signal is low and the level of the second voltage signal is high, the second light-emitting part 32c of the light-emitting diode chip 3 can emit light and the first light-emitting part 32b can be turned off in cooperation with the first and second voltage signals.

[0214] If there is one second light-emitting unit 32c, it can be driven to emit light, and if there are at least two second light-emitting units 32c, it can be driven to emit light simultaneously.

[0215] Taking the case where there is one second light-emitting unit 32c as an example, the equivalent circuit diagram of the pixel driving circuit 100 may be as shown in Figure 7, and the current I flowing through the second light-emitting unit 32c is still as follows.

[0216]

number

[0217] In the light emission stage S3, the current flowing through the first light-emitting section 32b or the second light-emitting section 32c is independent of the threshold voltage of the second transistor T2. In other words, by providing the first reset compensation circuit 4, the threshold voltage of the second transistor T2 is compensated, thereby avoiding any influence on the light emission state of the first light-emitting section 32b or the second light-emitting section 32c, improving the display stability of the light-emitting diode chip 3, and preventing unevenness and / or instability in the display brightness.

[0218] As can be seen from the above, during display operation of the pixel driving circuit 100, the multiple light-emitting units 32 in the light-emitting diode chip 3 can be driven to emit light for different periods of time, or at least two of the light-emitting units 32 can be driven to emit light for the same period of time.

[0219] In some embodiments, as shown in Figures 10 to 12, the pixel driving circuit 100 further includes a plurality of switching transistors SW. Here, of the plurality of light-emitting units 32 included in the light-emitting diode chip 3, the first bonding electrode 324 of the light-emitting unit 32 is electrically connected to a second node N2 via at least one switching transistor SW, and / or the second bonding electrode 325 of the light-emitting unit 32 is electrically connected to a second voltage signal terminal VSS via at least one switching transistor SW.

[0220] For example, the first bonding electrode 324 of the light-emitting unit 32 may be electrically connected to the second node N2 via one or more switching transistors SW, and the second bonding electrode 325 of the light-emitting unit 32 may be electrically connected directly to the second voltage signal terminal VSS. Alternatively, the first bonding electrode 324 of the light-emitting unit 32 may be electrically connected directly to the second node N2, and the second bonding electrode 325 of the light-emitting unit 32 may be electrically connected to the second voltage signal terminal VSS via one or more switching transistors SW. Alternatively, the first bonding electrode 324 of the light-emitting unit 32 may be electrically connected to the second node N2 via one or more switching transistors SW, and the second bonding electrode 325 of the light-emitting unit 32 may be electrically connected to the second voltage signal terminal VSS via one or more switching transistors SW.

[0221] In some examples, as shown in Figure 12, the number of the multiple switching transistors SW described above is equal to the number of light-emitting units 32 included in the light-emitting diode chip 3. In this case, the first bonding electrode 324 of each light-emitting unit 32 may be electrically directly connected to the second node N2, and the second bonding electrode 325 of the light-emitting unit 32 may be electrically connected to the second voltage signal terminal VSS via a single switching transistor SW.

[0222] In this example, at least two of the above-described multiple light-emitting units 32 may share, for example, the same first bonding electrode 324. In this case, the first semiconductor layer 321 of the at least two light-emitting units 32 may form an integrated structure.

[0223] By providing a switching transistor SW between each light-emitting unit 32 and the second voltage signal terminal VSS, the ON state of the corresponding light-emitting unit 32 can be controlled by this switching transistor SW, and the ON states of multiple light-emitting units 32 can be independently controlled by different switching transistor SWs. This makes it possible to make the multiple light-emitting units 32 emit light for different periods, or to make at least two light-emitting units 32 emit light for the same period.

[0224] In some examples, as shown in Figures 10 and 11, the number of the multiple switching transistors SW described above is greater than the number of light-emitting units 32 included in the light-emitting diode chip 3. In this case, the first bonding electrode 324 of one light-emitting unit 32 may be electrically connected directly to the second node N2 and electrically connected to the first bonding electrode 324 of another light-emitting unit 32 via at least one switching transistor SW. The second bonding electrode 325 of the said light-emitting unit may be electrically connected to the second voltage signal terminal VSS via at least one switching transistor SW and electrically connected to the first bonding electrode 324 of another light-emitting unit 32 via at least one switching transistor SW. The second bonding electrode 325 of the other light-emitting unit 32 may be electrically connected directly to the second voltage signal terminal VSS.

[0225] The multiple light-emitting units 32 described above are, for example, provided independently of each other, and each light-emitting unit 32 includes a first bonding electrode 324 and a second bonding electrode 325, with no bonding electrodes shared between different light-emitting units 32.

[0226] By using a switching transistor SW to set the connection relationship between different light-emitting units 32 and the second node N2 and the second voltage signal terminal VSS, the ON state of each light-emitting unit 32 can be controlled independently. By independently controlling the ON state of multiple light-emitting units 32 using different switching transistor SWs, the multiple light-emitting units 32 can be made to emit light for different periods, or at least two light-emitting units 32 can be made to emit light for the same period.

[0227] For example, as shown in Figure 10, the number of switching transistors SW is set to three, and the number of light-emitting units 32 is set to two. The three switching transistors SW can be referred to as, for example, the first switching transistor SW1, the second switching transistor SW2, and the third switching transistor SW3, and the two light-emitting units 32 can be referred to as, for example, light-emitting unit 32d and light-emitting unit 32e, respectively.

[0228] For example, as shown in Figure 10, the first bonding electrode 324 of the light-emitting unit 32d is electrically directly connected to the second node N2, the second bonding electrode 325 of the light-emitting unit 32d is electrically connected to the second voltage signal terminal VSS via the first switching transistor SW1, and the first bonding electrode 324 of the light-emitting unit 32e is electrically connected via the third switching transistor SW3. The first bonding electrode 324 of the light-emitting unit 32e may further be electrically connected to the second node N2 via the second switching transistor SW2, and the second bonding electrode 325 of the light-emitting unit 32e may be electrically directly connected to the second voltage signal terminal VSS.

[0229] If the first switching transistor SW1 is selectively turned on, the second switching transistor SW2 is turned off, and the third switching transistor SW3 is turned off, the light-emitting part 32d will emit light. If the first switching transistor SW1 is turned off, the second switching transistor SW2 is turned on, and the third switching transistor SW3 is turned off, the light-emitting part 32e will emit light.

[0230] When the first switching transistor SW1 is turned off, the second switching transistor SW2 is turned off, and the third switching transistor SW3 is turned on, the light-emitting parts 32d and 32e light up simultaneously and are arranged in series. When the first switching transistor SW1 is turned on, the second switching transistor SW2 is turned on, and the third switching transistor SW3 is turned off, the light-emitting parts 32d and 32e light up simultaneously and are arranged in parallel.

[0231] By adjusting the ON states of the first switching transistor SW1, the second switching transistor SW2, and the third switching transistor SW3, independent control of the two light-emitting units 32 can be achieved. For example, it is possible to drive one of the two light-emitting units 32 to emit light, or to drive the two light-emitting units 32 to emit light sequentially, or to drive the two light-emitting units 32 to emit light simultaneously. Having multiple light-emitting methods makes it possible to comprehensively select a combination of light-emitting methods for the light-emitting units 32 according to the actual driving capability and power consumption requirements of the pixel driving circuit 100.

[0232] For example, as shown in Figure 11, the number of switching transistors SW is set to six, and the number of light-emitting units 32 is set to three. The six switching transistors SW can be referred to, for example, as the first switching transistor SW1, the second switching transistor SW2, the third switching transistor SW3, the fourth switching transistor SW4, the fifth switching transistor SW5, and the sixth switching transistor SW6, respectively, and the three light-emitting units 32 can be referred to, for example, as light-emitting unit 32d, light-emitting unit 32e, and light-emitting unit 32f, respectively.

[0233] For example, as shown in Figure 11, the first bonding electrode 324 of the light-emitting unit 32d is electrically directly connected to the second node N2, the second bonding electrode 325 of the light-emitting unit 32d is electrically connected to the second voltage signal terminal VSS via the first switching transistor SW1, and is electrically connected to the first bonding electrode 324 of the light-emitting unit 32e via the third switching transistor SW3. The first bonding electrode 324 of the light-emitting unit 32e is further electrically connected to the second node N2 via the second switching transistor SW2, and the second bonding electrode 325 of the light-emitting unit 32e is via the sixth switching transistor SW6 The first bonding electrode 324 of the light-emitting section 32f may be electrically connected directly to the second voltage signal terminal VSS and electrically connected to the first bonding electrode 324 of the light-emitting section 32f via the fifth switching transistor SW5. The first bonding electrode 324 of the light-emitting section 32f may be further electrically connected to the second node N2 via the fourth switching transistor SW4 and the second switching transistor SW2, and the second bonding electrode 325 of the light-emitting section 32f may be electrically connected directly to the second voltage signal terminal VSS.

[0234] If the first switching transistor SW1 is selectively turned on and the remaining switching transistors SW are turned off, the light-emitting part 32d will emit light. If the second switching transistor SW2 is turned on and the sixth switching transistor SW6 is turned on and the remaining switching transistors SW are turned off, the light-emitting part 32e will emit light. If the second switching transistor SW2 is turned on and the fourth switching transistor SW4 is turned on and the remaining switching transistors SW are turned off, the light-emitting part 32f will emit light.

[0235] When the third switching transistor SW3 is turned on, the sixth switching transistor SW6 is turned on, and the remaining switching transistor SW is turned off, the light-emitting parts 32d and 32e light up simultaneously, and they are arranged in series. When the first switching transistor SW1 is turned on, the second switching transistor SW2 is turned on, the sixth switching transistor SW6 is turned on, and the remaining switching transistor SW is turned off, the light-emitting parts 32d and 32e light up simultaneously, and they are arranged in parallel. Of course, by adjusting the ON state of different switching transistor SWs, the light-emitting parts 32d and 32f can be made to light up simultaneously, and they can be arranged in series or in parallel. By adjusting the ON state of different switching transistor SWs, the light-emitting parts 32e and 32f can be made to light up simultaneously, and they can be arranged in series or in parallel. The explanation of this is omitted here.

[0236] When the third switching transistor SW3 is turned on, the fifth switching transistor SW5 is turned on, and the remaining switching transistor SW is turned off, the light-emitting parts 32d, 32e, and 32f light up simultaneously, and the three are arranged in series. When the first switching transistor SW1 is turned on, the second switching transistor SW2 is turned on, the fourth switching transistor SW4 is turned on, the sixth switching transistor SW6 is turned on, and the remaining switching transistor SW is turned off, the light-emitting parts 32d, 32e, and 32f light up simultaneously, and the three are arranged in parallel. When the second switching transistor SW2 is turned on, the third switching transistor SW3 is turned on, the fourth switching transistor SW4 is turned on, the sixth switching transistor SW6 is turned on, and the remaining switching transistors SW are turned off, the light-emitting parts 32d, 32e, and 32f light up simultaneously, and the light-emitting parts 32d and 32e are arranged in series, and the space between the light-emitting parts 32d and 32f and the space between the light-emitting parts 32e and 32f are arranged in parallel. Of course, when the light-emitting sections 32d, 32e, and 32f are illuminated simultaneously by adjusting the ON state of different switching transistors SW, the light-emitting sections 32d and 32f may be arranged in series, with the spaces between 32d and 32e and between 32e and 32f arranged in parallel, or the light-emitting sections 32e and 32f may be arranged in series, with the spaces between 32d and 32e and between 32d and 32f arranged in parallel. The explanation of this is omitted here.

[0237] By adjusting the ON state of different switching transistors SW, the light emission states of different light-emitting units 32 can be controlled independently. Having multiple light emission methods makes it possible to comprehensively select a combination of light emission methods for the light-emitting units 32 according to the actual driving capability and power consumption requirements of the pixel driving circuit 100.

[0238] Depending on the arrangement of the light-emitting portion 32 in the light-emitting diode chip 3, in some examples, the light-emitting control circuit 2 may include a seventh transistor T7 and an eighth transistor T8, as shown in Figures 10 to 12. Here, the seventh transistor T7 and the eighth transistor T8 are, for example, both P-type transistors.

[0239] Exemplary, as shown in Figures 10 to 12, the control electrode of the seventh transistor T7 is electrically connected to the first node N1, the first electrode of the seventh transistor T7 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6.

[0240] For example, when the voltage at the first node N1 is low, the seventh transistor T7 can be turned on under the control of the voltage at the first node N1, and can receive the first voltage signal and transmit it to the sixth node N6.

[0241] For example, as shown in Figures 10 to 12, the control electrode of the eighth transistor T8 is electrically connected to the enable signal terminal EM, the first electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0242] For example, if the level of the enable signal transmitted by the enable signal terminal EM is low, the eighth transistor T8 can be turned on under the control of the enable signal and transmit the first voltage signal from the sixth node N6 to the second node N2.

[0243] In some examples, as shown in Figures 10 to 12, the data writing circuit 1 may include a 12th transistor T12, where the 12th transistor T12 is, for example, a P-type transistor.

[0244] Exemplarily, as shown in FIGS. 10 to 12, the control electrode of the 12th transistor T12 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the 12th transistor T12 is electrically connected to the data signal terminal Data, and the second electrode of the 12th transistor T12 is electrically connected to the first node N1.

[0245] For example, when the level of the first scanning signal transmitted by the first scanning signal terminal Gate1 is at a low level, the 12th transistor T12 is turned on under the control of the first scanning signal, receives the data signal, transmits it to the first node N1, and can charge the first node N1.

[0246] Also, in some examples, as shown in FIGS. 9 to 12, the pixel driving circuit 100 may further include a second reset compensation circuit 5. This second reset compensation circuit 5 is electrically connected to the first scanning signal terminal Gate1, the first node N1, and the sixth node N6. Here, the second reset compensation circuit 5 is configured to compensate the threshold voltage of the 7th transistor T7 in response to the first scanning signal.

[0247] Exemplarily, as shown in FIGS. 9 to 12, the second reset compensation circuit 5 further includes an initial signal terminal Vint and 、 the third scanning signal terminal Gate3 and the fourth scanning signal terminal Gate 4 at least one of and and may be electrically connected thereto. The second reset compensation circuit 5 is further configured to transmit the initial signal received at the initial signal terminal Vint to the first node N1 in response to the third scanning signal received at the third scanning signal terminal Gate3 or the fourth scanning signal received at the fourth scanning signal terminal Gate4, and reset the first node N1.

[0248] For example, when the second reset compensation circuit 5 is electrically connected to the third scan signal terminal Gate3, the second reset compensation circuit 5 responds to the third scan signal received at the third scan signal terminal Gate3, and transmits the initial signal received at the initial signal terminal Vint to the first node N1, and is configured to reset the first node N1. When the second reset compensation circuit 5 is electrically connected to the fourth scan signal terminal Gate4, the second reset compensation circuit 5 responds to the fourth scan signal received at the fourth scan signal terminal Gate4, and transmits the initial signal received at the initial signal terminal Vint to the first node N1, and is configured to reset the first node N1.

[0249] By resetting the first node N1 and compensating the threshold voltage of the seventh transistor T7, the seventh transistor T7 in the light emission control circuit 2 can be turned on well during the corresponding period, which is advantageous for the seventh transistor T7 to transmit the first voltage signal without loss, and the light emission state of the light emitting unit 32 can be accurately controlled.

[0250] In some examples, as shown in FIGS. 10 to 12, the second reset compensation circuit 5 The first When electrically connected to the 3 scan signal terminal Gate3, the second reset compensation circuit 5 includes a ninth transistor T9. Here, the ninth transistor T9 is, for example, a P-type transistor.

[0251] Exemplarily, as shown in FIGS. 10 to 12, the control electrode of the ninth transistor T9 is electrically connected to the third scan signal terminal Gate3, the first electrode of the ninth transistor T9 is electrically connected to the initial signal terminal Vint, and the second electrode of the ninth transistor T9 is electrically connected to the first node N1.

[0252] For example, when the level of the third scan signal is a low level, the ninth transistor T9 is turned on under the control of the third scan signal, receives the initial signal and transmits it to the first node N1, and can reset the first node N1.

[0253] In some examples, as shown in Figures 10 to 12, the second reset compensation circuit 5 The first When electrically connected to the scan signal terminal Gate 4, the second reset compensation circuit 5 includes a tenth transistor T10, where the tenth transistor T10 is, for example, a P-type transistor.

[0254] For example, as shown in Figures 10 to 12, the control electrode of the 10th transistor T10 is electrically connected to the 4th scanning signal terminal Gate4, the first electrode of the 10th transistor T10 is electrically connected to the initial signal terminal Vint, and the second electrode of the 10th transistor T10 is electrically connected to the 1st node N1.

[0255] For example, if the level of the fourth scan signal is low, the tenth transistor T10 can be turned on under the control of the fourth scan signal, receive the initial signal and transmit it to the first node N1, and reset the first node N1.

[0256] In some examples, as shown in Figures 10 to 12, the second reset compensation circuit 5 further includes an eleventh transistor T11 and a second capacitor C2, where the eleventh transistor T11 is, for example, a P-type transistor.

[0257] For example, as shown in Figures 10 to 12, the control electrode of the 11th transistor T11 is electrically connected to the first scanning signal terminal Gate1, the first electrode of the 11th transistor T11 is electrically connected to the 7th node N7, and the second electrode of the 11th transistor T11 is electrically connected to the 6th node N6.

[0258] For example, if the level of the first scan signal is low, the 11th transistor T11 can be turned on under the control of the first scan signal and transmit the signal from the 7th node N7 to the 6th node N6.

[0259] Exemplary, as shown in Figures 10 to 12, the first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the seventh node N7. Here, the control electrode of the seventh transistor T7 is electrically connected to the first node N1 via the second capacitor C2.

[0260] The following schematic explanation of the pixel driving circuit's operation method will be given with reference to the structure of the pixel driving circuit shown in Figures 10 to 12 and the timing diagram shown in Figure 13.

[0261] In some examples, the method for driving the pixel drive circuit during the display phase of one frame includes a reset phase t1, a data writing phase t2, and a light emission phase t3.

[0262] In reset phase t1, the level of the first scan signal is high, the level of the third scan signal is low, the level of the fourth scan signal is high, the level of the enable signal is high, the level of the data signal is low, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0263] In the second reset compensation circuit 5, the ninth transistor T9 is turned on under the control of the third scanning signal, receives the initial signal and transmits it to the first node N1, and resets the first node N1.

[0264] During the data writing phase t2, the level of the first scan signal is low, the level of the third scan signal is high, the level of the fourth scan signal is high, the level of the enable signal is high, the level of the data signal is high, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0265] In response to the first scanning signal received at the first scanning signal terminal Gate1, the twelfth transistor T12 in the data writing circuit 1 is turned on to transmit the data signal received at the data signal terminal Data to the first node N1. Since the level of the data signal is high, at this time, the data signal can charge the first node N1 so that the voltage of the first node N1 becomes high level.

[0266] Also, at this stage, the eleventh transistor T11 in the second reset compensation circuit 5 is turned on under the control of the first scanning signal to compensate the threshold voltage of the seventh transistor T7. At this time, the voltage of the seventh node N7 is V DD +V th_tft7 . Here, V DD represents the voltage value of the first voltage signal, and V th_tft7 represents the threshold voltage of the seventh transistor T7.

[0267] In the light emitting stage t3, the level of the first scanning signal is high, the level of the third scanning signal is high, the level of the fourth scanning signal is low, the level of the enable signal is low, the level of the data signal is low, the level of the first voltage signal is high, and the level of the second voltage signal is low.

[0268] The eighth transistor T8 in the light emitting control circuit 2 is turned on under the control of the enable signal.

[0269] The tenth transistor T10 in the second reset compensation circuit 5 is turned on under the control of the fourth scanning signal, and receives the initial signal and transmits it to the first node N1 so that the voltage of the first node N1 jumps from V Data to V int . At this time, the voltage of the seventh node N7 jumps to V DD +V th_tft7 -(V Data [[ID= thirty-three]] int -V int ), the seventh transistor T7 is in a saturation state, and the voltage difference Vsg between the first electrode and the control electrode of the seventh transistor T7 is the voltage value of the first voltage signal and the first 7This is the difference from the voltage at node N7, i.e., Vsg = V DD -[V DD +V th_tft7 -(V Data -V int )]=V Data -V int -V th_tft7 The light emission control circuit 2 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2.

[0270] In this example, the level of the first voltage signal is high, and the level of the second voltage signal is low. By controlling the ON state of the switching transistor SW, multiple light-emitting units 32 can be driven to emit light for different periods, or at least two light-emitting units 32 can be driven to emit light for the same period.

[0271] Taking the example of driving one of the multiple light-emitting units 32 to emit light, the current I flowing through this light-emitting unit 32 is as follows.

[0272]

number

[0273] Luminescence stage t In 3, the current flowing through the light-emitting section 32 is independent of the threshold voltage of the seventh transistor T7. That is, by providing the second reset compensation circuit 5, the threshold voltage of the seventh transistor T7 is compensated, thereby avoiding affecting the light-emitting state of the light-emitting section 32, improving the display stability of the light-emitting diode chip 3, and preventing unevenness and / or instability in the display brightness.

[0274] The above are merely specific embodiments of the Disclosure, but the scope of protection of the Disclosure is not limited thereto, and any modification or substitution that can be easily conceived by any person skilled in the art within the technical scope of the Disclosure is included within the technical scope of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be governed by the scope of protection set forth in the claims.

Claims

1. A pixel driving circuit, A data writing circuit electrically connected to a first scan signal terminal, a data signal terminal, and a first node, the data writing circuit being configured to transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal, A light-emitting control circuit electrically connected to the first node, an enable signal terminal, a first voltage signal terminal, and a second node, configured to transmit a first voltage signal received at the first voltage signal terminal to the second node under the control of the voltage of the first node and the enable signal transmitted by the enable signal terminal, A light-emitting diode chip electrically connected to the second node and the second voltage signal terminal, Includes multiple switching transistors, Here, the light-emitting diode chip includes a plurality of light-emitting units, and the number of the plurality of light-emitting units is less than the number of the plurality of switching transistors. The light-emitting diode chip is configured to drive the plurality of light-emitting units to emit light for different periods of time, or to drive at least two of the plurality of light-emitting units to emit light for the same period of time, in cooperation with the first voltage signal from the second node and the second voltage signal received at the second voltage signal terminal. The first bonding electrode of one of the plurality of light-emitting units is electrically directly connected to the second node, and is electrically connected to the first bonding electrode of another of the plurality of light-emitting units via at least one of the plurality of switching transistors. The second bonding electrode of one of the plurality of light-emitting units is electrically connected to the second voltage signal terminal via at least one other switching transistor among the plurality of switching transistors, and is electrically connected to the first bonding electrode of the other light-emitting unit via at least one yet another switching transistor among the plurality of switching transistors. The second bonding electrode of the other light-emitting part is electrically directly connected to the second voltage signal terminal in a pixel driving circuit.

2. The plurality of light-emitting units include at least one first light-emitting unit and at least one second light-emitting unit. Here, the first bonding electrode of the first light-emitting unit among the at least one first light-emitting unit is electrically connected to the second node, and the second bonding electrode of the first light-emitting unit is electrically connected to the second voltage signal terminal. The pixel driving circuit according to claim 1, wherein the first bonding electrode of the second light-emitting portion of the at least one second light-emitting portion is electrically connected to the second voltage signal terminal, and the second bonding electrode of the second light-emitting portion is electrically connected to the second node.

3. The light-emitting control circuit includes a first transistor and a second transistor, The control electrode of the first transistor is electrically connected to the enable signal terminal, the first electrode of the first transistor is electrically connected to the first voltage signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The pixel driving circuit according to claim 2, wherein the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the second node.

4. Further including a first reset compensation circuit, The pixel driving circuit according to claim 3, wherein the first reset compensation circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the first node, the second node, the third node, and the second voltage signal terminal, and the first reset compensation circuit is configured to reset the pixel driving circuit and compensate the threshold voltage of the second transistor under the control of the first scan signal and the second scan signal received at the second scan signal terminal.

5. The first reset compensation circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor. The control electrode of the third transistor is electrically connected to the first scanning signal terminal, the first electrode of the third transistor is electrically connected to the second voltage signal terminal, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the second scanning signal terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode of the fifth transistor is electrically connected to the second scanning signal terminal, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the fifth node. The control electrode of the sixth transistor is electrically connected to the first scanning signal terminal, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node. The pixel driving circuit according to claim 4, wherein the first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the fifth node.

6. The light-emitting control circuit includes a seventh transistor and an eighth transistor, The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the first voltage signal terminal, and the second electrode of the seventh transistor is electrically connected to the sixth node. The pixel driving circuit according to claim 1, wherein the control electrode of the eighth transistor is electrically connected to the enable signal terminal, the first electrode of the eighth transistor is electrically connected to the sixth node, and the second electrode of the eighth transistor is electrically connected to the second node.

7. It further includes a second reset compensation circuit, The second reset compensation circuit is electrically connected to the first scan signal terminal, the first node, and the sixth node, and is configured to compensate the threshold voltage of the seventh transistor in response to the first scan signal. The pixel driving circuit according to claim 6, further comprising the second reset compensation circuit, which is electrically connected to an initial signal terminal and at least one of a third scan signal terminal and a fourth scan signal terminal, and which is further configured to transmit an initial signal received at the initial signal terminal to the first node in response to a third scan signal received at the third scan signal terminal or a fourth scan signal received at the fourth scan signal terminal, thereby resetting the first node.

8. The second reset compensation circuit includes an eleventh transistor and a second capacitor, The control electrode of the 11th transistor is electrically connected to the first scanning signal terminal, the first electrode of the 11th transistor is electrically connected to the 7th node, and the second electrode of the 11th transistor is electrically connected to the 6th node. The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the seventh node. Here, the control electrode of the seventh transistor is electrically connected to the first node via the second capacitor. When the second reset compensation circuit is electrically connected to the third scanning signal terminal, the second reset compensation circuit further includes a ninth transistor. The control electrode of the ninth transistor is electrically connected to the third scanning signal terminal, the first electrode of the ninth transistor is electrically connected to the initial signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node. When the second reset compensation circuit is electrically connected to the fourth scanning signal terminal, the second reset compensation circuit further includes a tenth transistor. The pixel driving circuit according to claim 7, wherein the control electrode of the 10th transistor is electrically connected to the 4th scanning signal terminal, the first electrode of the 10th transistor is electrically connected to the initial signal terminal, and the second electrode of the 10th transistor is electrically connected to the first node.

9. The data writing circuit includes a 12th transistor, The pixel driving circuit according to any one of claims 1 to 8, wherein the control electrode of the 12th transistor is electrically connected to the first scanning signal terminal, the first electrode of the 12th transistor is electrically connected to the data signal terminal, and the second electrode of the 12th transistor is electrically connected to the first node.

10. A method for driving a pixel driving circuit according to any one of claims 1 to 9, Including a data writing stage and an illumination stage, During the data writing stage, in response to the first scan signal received at the first scan signal terminal, the data writing circuit is turned on and the data signal received at the data signal terminal is transmitted to the first node. In the light emission stage, the light emission control circuit is turned on under the control of the voltage of the first node and the enable signal received at the enable signal terminal, and the first voltage signal received at the first voltage signal terminal is transmitted to the second node. A method for driving a pixel driving circuit, wherein, in cooperation with a first voltage signal from the second node and a second voltage signal received at the second voltage signal terminal, multiple light-emitting parts in a light-emitting diode chip are made to emit light for different periods, or at least two light-emitting parts are made to emit light for the same period.

11. A display board, circuit board and The invention includes a pixel driving circuit according to any one of the multiple claims 1 to 9, wherein the multiple pixel driving circuits are provided on one side of the substrate. In the aforementioned pixel driving circuit, each of the multiple light-emitting units included in the light-emitting diode chip comprises a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked sequentially, wherein the first semiconductor layer and the second semiconductor layer have different doping types. Here, the light-emitting portion further includes at least one of the first bonding electrode and the second bonding electrode, The first bonding electrode is electrically connected to the first semiconductor layer of the light-emitting portion. The second bonding electrode is electrically connected to the second semiconductor layer of the light-emitting portion, and is part of a display substrate.

12. The light-emitting diode chip further includes a base, The display substrate according to claim 11, wherein the plurality of light-emitting parts included in the light-emitting diode chip are located on the same side of the base.

13. The light-emitting portion includes the first bonding electrode and the second bonding electrode, The display substrate according to claim 11 or 12, wherein the first bonding electrodes included in different light-emitting portions are different, and the second bonding electrodes included in different light-emitting portions are different.

14. The light-emitting unit includes a plurality of sub-light-emitting units arranged in series, Each sub-light-emitting section includes a first sub-semiconductor layer, a first sub-quantum well layer, and a second sub-semiconductor layer that are stacked sequentially. The first sub-semiconductor layer of one sub-light-emitting section in the same light-emitting section is electrically connected to the first bonding electrode of the same light-emitting section. The display substrate according to claim 13, wherein the second sub-semiconductor layer of another sub-light-emitting portion in the same light-emitting portion is electrically connected to the second bonding electrode of the same light-emitting portion.

15. The plurality of light-emitting units include at least one first light-emitting unit and at least one second light-emitting unit. The first bonding electrode of the first light-emitting unit, of the at least one first light-emitting unit, is electrically connected to the second node, and the second bonding electrode of the first light-emitting unit is electrically connected to the second voltage signal terminal. The first bonding electrode of the second light-emitting unit, of the at least one second light-emitting unit, is electrically connected to the second voltage signal terminal, and the second bonding electrode of the second light-emitting unit is electrically connected to the second node. The first semiconductor layer of the first light-emitting portion and the second semiconductor layer of the second light-emitting portion are electrically connected to a single second bonding electrode. The display substrate according to claim 11 or 12, wherein the second semiconductor layer of the first light-emitting portion and the first semiconductor layer of the second light-emitting portion are electrically connected to another second bonding electrode.

16. The light-emitting diode chip further includes a plurality of connection parts, The first semiconductor layer of the first light-emitting section is electrically connected to the second semiconductor layer of the second light-emitting section via one of the plurality of connection sections. The display substrate according to claim 15, wherein the first semiconductor layer of the second light-emitting portion is electrically connected to the second semiconductor layer of the first light-emitting portion via other connection portions among the plurality of connection portions.

17. The first light-emitting unit includes a plurality of first sub-light-emitting units arranged in series, and the second light-emitting unit includes a plurality of second sub-light-emitting units arranged in series. Each first sub-light-emitting section includes a sequentially stacked third sub-semiconductor layer, a second sub-quantum well layer, and a fourth sub-semiconductor layer, and each second sub-light-emitting section includes a sequentially stacked fifth sub-semiconductor layer, a third sub-quantum well layer, and a sixth sub-semiconductor layer. The third sub-semiconductor layer of one of the plurality of first sub-light-emitting units is electrically connected to one of the second bonding electrodes and is electrically connected to the sixth sub-semiconductor layer of one of the plurality of second sub-light-emitting units. The display substrate according to claim 15 or 16, wherein the fifth subsemiconductor layer of another second subsemiconductor of the plurality of second subsemiconductors is electrically connected to the other second bonding electrode and is electrically connected to the fourth subsemiconductor layer of another first subsemiconductor of the plurality of first subsemiconductors.

18. The display substrate according to claim 11 or 12, wherein at least two of the first semiconductor layers of the light-emitting portions are integrally structured and electrically connected to the same first bonding electrode.

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