Electronic control device and electronic control system

Abstract

An electronic control unit (ECUm) comprises a processor (204), a communication circuit (202), and a power supply IC (206). The communication circuit (202), which has received a wake-up instruction, sets a power supply IC (206) activation signal (INH-Vlevel) being a voltage level signal to an enable level. The processor (204), which has received a sleep instruction via the communication circuit (202), transmits a sleep command to the communication circuit (202) and transmits a power-off command to the power supply IC (206). The power supply IC (206) includes a priority wake-up processing unit (246) that allows to continue generation of a power supply voltage in a case in which the power supply is intended to be stopped in response to the power-off command yet the enable level of the power supply IC (206) activation signal (INH-Vlevel) is maintained.

Description

Technical Field

[0001] The present invention relates to an electronic control device, an electronic control system, and the like.

Background Art

[0002] In recent years, the number of electronic devices installed in vehicles has been increasing, and accordingly, the power consumption of electronic control systems has been tending to increase. In particular, there is an increasing demand to reduce the standby current (dark current) during vehicle stop, which directly affects the voltage drop of the battery.

[0003] As a technology for reducing the power consumption of an electronic control system, for example, a technology that utilizes a selective wake-up function to operate only necessary units among a plurality of ECUs (Electronic Control Units), or a technology that sets a processor such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit) to a low power consumption mode, or a technology that effectively uses a sub-processor such as a downsized sub-CPU or sub-MPU is known.

[0004] A technology that utilizes a selective wake-up function is described in, for example, Patent Document 1. In addition, a technology that utilizes the low power consumption mode of a processor is described in, for example, Patent Document 2. In addition, a technology that utilizes a sub-processor is described in, for example, Patent Document 3.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0006] However, there is a need for further reductions in power consumption. Therefore, it is urgent to realize electronic control devices and electronic control systems that can further reduce power consumption while maintaining necessary functions and reliability.

[0007] Furthermore, for example, when a higher-level power control unit, such as a power control ECU, performs power control for multiple lower-level power control units, it is possible that the power control ECU may issue a sleep command to a certain ECU, but then immediately afterward issue a wake-up command to the same ECU due to a rapid change in the vehicle's status, etc.

[0008] In this case, stopping the power supply IC (Integrated Circuit) included in the ECU in response to a sleep command takes a certain amount of time. Therefore, a wake-up command will be received while the power supply IC is being stopped, resulting in a conflict between the processing based on the sleep command and the processing based on the wake-up command received after the sleep command.

[0009] In this case, it is preferable to prioritize processing based on the most recent instruction, the wake-up instruction, and to stop processing based on the currently running sleep instruction to avoid unnecessary power outages. To perform such advanced processing, it is conceivable to use a configuration that utilizes a sub-processor in addition to the main processor.

[0010] However, subprocessors can be considered redundant, and using them increases power consumption. In recent electronic control systems, numerous electronic control devices (electronic control units) are used, and if the power consumption of one electronic control device increases, the power consumption of the entire electronic control system will increase sharply, which goes against the aforementioned requirement for low power consumption.

[0011] The aforementioned Patent Documents 1-3 do not describe these problems, nor do they mention any countermeasures.

[0012] The present invention has been made in view of the above-mentioned problems, and one object of the present invention is to promote the reduction of power consumption of electronic control devices, and to prevent unintended power shutdowns when a wake-up command is received by a communication circuit during the power shutdown process of a power supply IC.

[0013] Other objects of the present invention will become apparent to those skilled in the art by referring to the embodiments and best embodiments described below, as well as the accompanying drawings. [Means for solving the problem]

[0014] The following are examples of embodiments of the present invention to facilitate understanding of its outline. In a first embodiment of the electronic control device of the present invention, the electronic control device connected to a network includes a processor that controls the operation of the electronic control device, a communication circuit that receives sleep commands and wake-up commands from other devices connected via the network and has a first interface for communication with the processor, and a power supply IC that generates a power supply voltage and has a second interface for communication with the processor, wherein the communication circuit, upon receiving the wake-up command, includes a startup signal generation unit that sets the startup signal of the power supply IC as a voltage level signal to the enable level, and transmits the received sleep command to the processor via the first interface, and the processor, upon receiving the sleep command sent from the communication circuit, transmits a sleep command to the communication circuit and a power stop command to the power supply IC, and the power supply IC, when attempting to stop the power supply in response to the power stop command sent from the processor, has a priority wake-up processing unit that, if the enable level of the startup signal of the power supply IC sent from the communication circuit is maintained, prioritizes the startup of the power supply IC due to the startup signal of the power supply IC being enabled over the power stop command and continues to generate the power supply voltage.

[0015] In the first embodiment, the power supply IC has a priority wake-up processing unit. If processing based on a sleep instruction conflicts with processing based on a wake-up instruction received after that sleep instruction, the power supply IC's priority wake-up processing unit executes a process (arbitration process) that prioritizes the most recent instruction, the wake-up instruction. Therefore, a subprocessor becomes unnecessary. By eliminating the subprocessor and its power supply, power consumption can be reduced.

[0016] Furthermore, the communication circuit includes a startup signal generation unit. During the execution of the process for stopping the power supply IC, if a wake-up command is received, the start signal generation unit of the communication circuit sets the start signal of the power supply IC as a voltage level signal to the enable level. As a result, the wake-up command has priority over the sleep command, and the priority wake-up processing unit of the power supply IC continues to generate the power supply voltage.

[0017] As the start signal of the power supply IC, instead of an edge-trigger type start signal, a voltage level signal is used, and when a wake-up command is received, it is only necessary for the communication circuit to change the voltage level of the start signal of the power supply IC to the enable level. Therefore, the configuration is simplified and complex signal processing is not required. This is advantageous for miniaturization and low power consumption of the electronic control unit (ECU).

[0018] In a second aspect subordinate to the first aspect, the start signal of the power supply IC may be transmitted from the communication circuit to the power supply IC through a signal path that does not pass through the sub-processor.

[0019] In the second aspect, the sub-processor is not interposed in the transmission path of the start signal of the power supply IC. Therefore, the sub-processor and the power supply of the sub-processor are not required, and reduction of power consumption, simplification of the configuration, reduction of the software burden, etc. are realized.

[0020] In a third aspect subordinate to the first or second aspect, the first interface and the second interface may be communication interfaces that transmit and receive data in synchronization with the rising edge or falling edge of the clock.

[0021] In the third aspect, the first and second interfaces provided in the communication circuit for performing data communication with the processor are synchronous communication interfaces that transfer data in synchronization with the edge of the clock. For example, a highly reliable communication interface such as SPI (Serial Peripheral Interface) can be used.

[0022] As described in the first aspect, the communication circuit performs data communication at a voltage level with the power supply IC. That is, the communication circuit of this aspect has a novel configuration that combines a data communication interface that performs synchronous communication with the processor and a signal output terminal (broadly speaking, a data communication interface) that performs data communication at a voltage level with the power supply IC.

[0023] If synchronous communication is used even in communication with the power supply IC, when the power supply IC is in the power-off process at the timing of data transfer, the data transfer at that timing is invalidated. Therefore, it is impossible to notify the power supply IC that a wake-up command has been received.

[0024] In the case of a voltage level signal, after the voltage level of the signal changes, the changed voltage level is maintained, so that the power supply IC can obtain a time margin for determining the voltage level of the received signal. That is, the power supply IC can determine the voltage level of the received start signal at any timing. Therefore, the power supply IC can know the fact that a wake-up command has been received.

[0025] In a fourth aspect dependent on any one of the first to third aspects, a signal path for transmitting the start signal of the power supply IC output from the communication circuit to the power supply IC and a monitoring circuit for monitoring the level of the start signal of the power supply IC may be provided between the communication circuit and the processor.

[0026] According to the fourth aspect, the processor can detect, via the monitoring circuit, whether the start signal of the power supply IC is at an enable level or a disable level, for example. For example, when the communication circuit receives a sleep command, the sleep command is sent to the processor, and a process is performed in which the processor that decodes the sleep command sends a sleep command to the communication circuit.

[0027] When the communication circuit enters sleep mode, the power supply IC's activation signal changes from the enable level to the disable level. The processor can detect this change in voltage level via a monitoring circuit and determine whether the communication circuit is operating correctly in accordance with the sleep command.

[0028] If, for example, the power supply IC's startup signal does not change voltage level even after the processor has issued a sleep command to the communication circuit, it is possible to infer, for example, an abnormality in the communication circuit, an abnormality in the communication path between the communication circuit and the processor, or an abnormality in the monitoring circuit, and take appropriate countermeasures. This contributes to suppressing a decline in the reliability of the electronic control unit.

[0029] In a fifth embodiment dependent on any one of the first to fourth embodiments, the power supply IC has a reset unit that outputs a reset signal for resetting the processor, and when the priority wake-up processing unit prioritizes the startup of the power supply IC due to the activation signal of the power supply IC being enabled and continues to generate the power supply voltage, the reset unit may output the reset signal, thereby initializing the processor.

[0030] In the fifth embodiment, the power supply IC has a reset unit. When the power supply IC continues to generate the power supply voltage, the power supply voltage is also supplied to the processor, and the processor continues to operate. In this embodiment, the reset unit outputs a reset signal to the processor, thereby resetting the processor.

[0031] In other words, upon receiving a wake-up instruction, the processor is reset and starts operating from an initialized state (initial start). When the processor is reset, various counters, timers, input / output ports, etc., are initialized, and the internal state of the processor returns to its initial predetermined state. This allows various programs to start normally, even if, for example, a partial problem occurs within the processor, as a reset will return it to its initial predetermined state. This reduces the likelihood of future processor malfunctions (failures), thus contributing to preventing a decline in processor reliability.

[0032] In a sixth embodiment dependent on the fifth embodiment, the power supply IC may cause the reset unit to output the reset signal by transitioning the state of the power supply IC to an initial state.

[0033] In the sixth embodiment, the power supply IC outputs a reset signal from the reset unit by transitioning its internal state to an initial state. In other words, the power-on reset function of the power supply IC, that is, the function that outputs a reset signal to the processor when the power is turned on and starts from the initial state, is used to enable the output of a reset signal. According to this embodiment, a reset signal can be output using existing functions of the power supply IC, eliminating the need for special processing to output the reset signal, and thus reducing the burden on the power supply IC.

[0034] In a seventh aspect of the present invention, the electronic control system of the present invention comprises a plurality of electronic control devices of any one of the first to sixth aspects connected to the network.

[0035] According to the seventh aspect, an electronic control system is constructed by connecting a plurality of the electronic control devices of the present invention to a network. As described above, the electronic control device of the present invention has the function of further reducing power consumption while retaining the necessary functions and reliability. Therefore, while maintaining reliability, a significant reduction in power consumption can be achieved for the entire electronic control system. In recent years, the amount of electronic equipment installed in vehicles has increased, and consequently, the power consumption of electronic control systems has tended to increase. In particular, there is a growing demand to reduce standby current (dark current) when the vehicle is stopped, which directly leads to a drop in battery voltage. This embodiment can satisfy the above requirements. This contributes, for example, to the realization of electric vehicles that can operate for a long time on a single battery charge. [Effects of the Invention]

[0036] According to the present invention, it is possible to promote the reduction of power consumption in electronic control devices and electronic control systems. Furthermore, if a wake-up command is received by the communication circuit while the power supply IC is shutting down, an unintended power shutdown can be avoided.

[0037] Those skilled in the art will readily understand that the embodiments of the present invention illustrated can be further modified without departing from the spirit of the invention. [Brief explanation of the drawing]

[0038] [Figure 1] Figure 1 shows an example of the configuration of an electronic control system using CAN (Controller Area Network). [Figure 2] Figure 2 is a diagram comparing the configuration of the first comparative example, which has a subprocessor, with a configuration without a subprocessor (the configuration used in Figure 1). [Figure 3] Figure 3 shows the configuration and operation of an electronic control unit in a second comparative example, which does not use a subprocessor and uses an edge-trigger type signal as the activation signal for the power supply IC (Integrated Circuit). [Figure 4] Figure 4 shows an example of a specific configuration of an electronic control device in an embodiment of the present invention that does not use a subprocessor and uses a voltage level signal as the startup signal for the power supply IC. [Figure 5] Figure 5 shows the wake-up operation during power-off in an electronic control device according to an embodiment of the present invention. [Figure 6] Figure 6 shows an example of the configuration of an electronic control unit with an added monitoring circuit. [Figure 7] Figure 7 is a flowchart showing an example of the sleep and wake-up procedure in the electronic control unit shown in Figure 6. [Modes for carrying out the invention]

[0039] The best embodiments described below are used to facilitate understanding of the present invention. Therefore, those skilled in the art should note that the present invention is not unduly limited by the embodiments described below. One embodiment of the present invention will now be described with reference to the drawings.

[0040] Figure 1 shows an example of the configuration of an electronic control system using CAN (Controller Area Network).

[0041] In Figure 1, the electronic control system 150 is assumed to be mounted on the vehicle. However, this is just one example and is not limited to this example. The CAN bus (labeled CAN-BUS in Figure 1) is a two-wire communication bus consisting of a high-level CANH and a low-level CANL. Termination resistors 30a and 30b are provided at the ends of CANH and CANL.

[0042] Multiple ECUs (Electronic Control Units) are connected to the CAN bus as electronic control devices. In Figure 1, multiple ECUs are provided, numbered ECU1 to ECUn (where n is a natural number greater than or equal to 3).

[0043] ECU1 to ECUn are installed in the vehicle and constitute the ECU group 200. Each ECU can cooperate with each other via the in-vehicle network (CAN bus) to implement one or more functions.

[0044] In addition, a power control ECU 102 as a higher-level ECU capable of selectively controlling the sleep / wake-up of ECUs 1 to ECUn is connected to the CAN bus. This power control ECU 102 is a higher-level unit responsible for the power management of the lower-level ECUs 1 to ECUn and corresponds to "other devices connected to the network (CAN bus)".

[0045] The power control ECU 102 includes a selective wake-up / sleep communication unit 104. Also, various commands are supplied to the power control ECU 102 from a higher-level device 10, and various sensor signals are supplied from a sensor 20.

[0046] The selective wake-up / sleep communication unit 104 can issue a selective sleep command PF1 and a selective wake-up command PF2 to an ECUm (where m is a natural number satisfying 1 < m < n).

[0047] The battery BATT supplies power to each of ECUs 1 to ECUn via a power line 40.

[0048] In the example of FIG. 1, each of ECUs 1 to ECUn has the same configuration. In each ECU, the same reference numerals are assigned to the common parts. Hereinafter, taking ECUm as an example, the internal configuration will be described.

[0049] The ECUm includes communication terminals D1 and D2 connected to the CAN bus, a power supply terminal D3 connected to the power line 40, a CAN communication circuit (labeled CAN in the diagram) 202, a CPU (Central Processing Unit: hereinafter referred to as CPU) 204 as a processor, a power supply IC (Integrated Circuit) 206 that generates and outputs the power supply voltage VCC, a first SPI bus (labeled SPI-BUS1 in the diagram) for communication between the CAN communication circuit 202 and the CPU 204, a second SPI bus (labeled SPI-BUS2 in the diagram) for communication between the power supply IC 206 and the CPU 204, and a signal path (signal line) L1 that supplies the power supply IC 206 with the power supply IC startup signal INH-Vlevel, which is a voltage level signal output from the CAN communication circuit; in other words, a signal path (signal line) L1 that does not involve a sub-CPU acting as a sub-processor. Note that the power supply IC can be referred to as the power supply circuit.

[0050] In the following explanation, the CAN communication circuit may be simply referred to as the communication circuit or communication unit. The CAN communication circuit 202 also has an INH terminal that outputs the INH-Vlevel startup signal for the power supply IC, which is a voltage level signal.

[0051] Furthermore, the power supply IC 206 has an ENA terminal that receives the power supply IC startup signal INH-Vlevel and a VC terminal that outputs the power supply voltage VCC.

[0052] The CAN communication circuit 202 has a selective receiving function that, upon receiving a selective sleep command PF1 and a selective wake-up command PF2 issued by the power control ECU 102, detects that it has been selected and executes predetermined processing for each command.

[0053] When the CAN communication circuit 202 receives a sleep command PF1, it transmits the received sleep command PF1 to the CPU 204.

[0054] The CPU 204 decodes the received sleep command PF1 to recognize the content of the command, sends a sleep command to the CAN communication circuit 202 via the first SPI bus (SPI-BUS1), and also sends a power-off command to the power supply IC 206 via the second SPI bus (SPI-BUS2).

[0055] When the CAN communication circuit 202 receives a sleep command from the CPU 204, it switches to sleep mode (standby mode or low power mode). Also, when the power supply IC 206 receives a power-off command from the CPU 204, it executes a process to stop generating the power supply voltage VCC (this may be a power shutdown process or a transition to standby mode).

[0056] Furthermore, when the CAN communication circuit 202 receives a selective wake-up command PF2, it detects that it is a wake-up command that specifies itself. Since the CPU 204 is in sleep mode, the CAN communication circuit 202 does not notify the CPU 204 that a wake-up command has been received. Instead, it changes the power supply IC's startup signal INH-Vlevel, which is a voltage level signal, from the disabled level (L) to the enabled level (H).

[0057] When the power supply IC206 detects that the power supply IC's startup signal INH-Vlevel is at the enable level, it starts generating and outputting the power supply voltage VCC. Furthermore, in this case, the power supply IC 206 may output a reset signal RES to the CPU 204 to initiate the CPU 204. This point will be discussed later.

[0058] Furthermore, the CAN communication circuit 202 may receive a wake-up command PF2 immediately after receiving a sleep command PF1, for example.

[0059] In this case, while the power supply IC 206 is performing the power-off process in response to a power-off command from the CPU 204, a wake-up command is received, and the power supply IC's startup signal INH-Vlevel changes to the enable level. In other words, the processing based on the sleep instruction and the processing based on the wake-up instruction received after that sleep instruction will conflict.

[0060] The power supply IC 206 has a priority wake-up processing unit (not shown in Figure 1, reference numeral 246 in Figure 4). This priority wake-up processing unit 246 prioritizes processing based on the most recent instruction, the wake-up instruction, and stops processing based on the currently running sleep instruction, thereby avoiding unnecessary power outages. Details of this process will be described later.

[0061] In other words, in the ECUm of the present invention shown in Figure 1, if processing based on a sleep instruction conflicts with processing based on a wake-up instruction received after the sleep instruction, the power supply IC 206 performs arbitration processing to resolve the conflict.

[0062] One could also consider a configuration where this arbitration process is performed by a sub-CPU, but in this case, power consumption would increase.

[0063] Therefore, the electronic control system in Figure 1 can handle the aforementioned conflict of conflicting instructions with a simple and inexpensive configuration that does not use a sub-CPU.

[0064] Next, refer to Figure 2. Figure 2 is a diagram comparing the configuration of the first comparative example with a subprocessor and the configuration without a subprocessor (the configuration adopted in Figure 1). In Figure 2, A-1 and A-2, the same reference numerals are used for parts common to Figure 1. This is also the case in other figures.

[0065] Furthermore, in Figures 2A-1 and A-2, for the sake of explanation, the battery BATT is depicted as being directly connected to terminal D3, which is used for power supply to the ECUm. This is also the case in Figures 3-6 and 8.

[0066] The first comparative example, A-1 in Figure 2, is a configuration that was considered by the inventors prior to the present invention and is not a known example. In Figure 2A-1, a sub-power supply 207 and a sub-CPU (sub-processor) 209 are provided. Furthermore, the signal output from the CAN communication circuit 202 is not a voltage level signal, but an edge trigger signal INH-edge that has a rising edge or falling edge for data transfer.

[0067] When the CAN communication circuit 202 receives a wake-up command while the power supply IC 206 is shutting down, the CAN communication circuit 202 supplies an edge trigger signal INH-edge to the sub-CPU 209 to notify it that a wake-up command has been received.

[0068] Sub-CPU 209 monitors the power supply voltage VCC generated by the power supply IC. When it detects that the power supply voltage VCC has been stopped by the power supply IC 206 in response to a sleep command output by CPU 204, it immediately supplies an edge trigger signal SO-INH-edge to the power supply IC 206, restarting the power supply IC. This allows for handling situations where a sleep instruction and a wake-up instruction conflict.

[0069] However, the sub-power supply 207 and sub-CPU (sub-processor) 209 can be considered a redundant configuration, and using the sub-power supply 207 and sub-CPU 209 will increase power consumption.

[0070] In recent electronic control systems, numerous electronic control units are used. If the power consumption of one electronic control unit increases, the power consumption of the entire electronic control system increases sharply, which contradicts the aforementioned requirement for low power consumption.

[0071] Therefore, as shown in Figure 2A-2, the sub-power supply 207 and the sub-CPU (sub-processor) 209 were removed, and the power supply IC 206 was configured to perform arbitration processing if a sleep instruction and a wake-up instruction conflicted.

[0072] Furthermore, in Figure 2A-2, the CAN communication circuit 202 supplies the power supply IC 206 with a voltage level signal, which is the startup signal INH-Vlevel for the power supply IC. The power supply IC 206 then supplies the reset signal RES to the CPU 204 to perform an initial start on the CPU 204.

[0073] Comparing A-1 and A-2 in Figure 2, it is clear that A-2 in Figure 2 has a simplified configuration, and therefore, it is possible to reduce power consumption, miniaturize the device, and lower the cost.

[0074] On the other hand, the present invention also gives due consideration to the reliability of the ECU. Although not shown in Figure 2A-1, as shown in Figure 6 later, a monitoring circuit 260 is provided to monitor the INH-Vlevel startup signal of the power supply IC, allowing for identification of the level of the power supply IC startup signal and fault diagnosis of related circuits.

[0075] Furthermore, as mentioned above, resetting CPU204 and performing an initial startup allows various programs to start normally. This helps reduce the possibility of future processor malfunctions (failures).

[0076] Thus, the electronic control unit (ECU) of the present invention can significantly reduce power consumption while ensuring the necessary reliability, and can also achieve a simplified configuration, miniaturization, and cost reduction.

[0077] Next, we will explain why, in this invention, a voltage level signal is used as the startup signal for the power supply IC, rather than an edge trigger signal. In short, if an edge trigger signal is used, if a sleep instruction and a wake-up instruction conflict, arbitration will fail, resulting in an unnecessary power shutdown. We will explain this point in detail.

[0078] Refer to Figure 3. Figure 3 shows the configuration and operation of an electronic control unit in a second comparative example that does not use a subprocessor and uses an edge-triggered signal as the power supply IC activation signal.

[0079] The second comparative example shown in Figure 3A-1 is a configuration that was considered by the inventors prior to the present invention and is not a known example. In the second comparative example shown in Figure 3A-1, the voltage level signal ENH-Vlevel in the configuration of the present invention described in Figure 2A-2 is replaced with the edge trigger signal ENH-edge.

[0080] The left side of A-2 in Figure 3 shows a timing chart illustrating the operation during normal wake-up / sleep processing.

[0081] For example, when power is supplied from the battery at time t1, the ECUm's power supply IC 206 generates and outputs the power supply voltage VCC. Consequently, the power supply IC's startup signal INH-edge, output from the CAN communication circuit 202, changes from L level (disable level) to H level (enable level).

[0082] Furthermore, when a sleep command is received, the CPU 204 sends a sleep command to the CAN communication circuit 202 at time t2, and sends a power-off command to the power supply IC 206 at time t3.

[0083] At time t4, in response to the sleep command, the power supply IC's startup signal INH-edge changes to the L level (disable level). Also at time t4, in response to the power-off command, the generation of the power supply voltage VCC is stopped.

[0084] The right side of A-2 in Figure 3 shows a timing chart illustrating the operation when a wake-up command is received while the power supply IC is performing a power-off process.

[0085] At time t5, the generation of the power supply voltage VCC begins, and the power supply IC's startup signal INH-edge changes from a low level to a high level.

[0086] When a sleep command is received, the CPU 204 sends a sleep command to the CAN communication circuit 202 at time t6, and sends a power-off command to the power supply IC 206 at time t7. In response to the transmission of the sleep command at time t6, the power supply IC's start signal INH-edge changes to a low level.

[0087] The period from time t7 to time t9 is the time during which the power supply IC 206 is performing the power shutdown process.

[0088] At time t8 during that period, when a wake-up command is received, the power supply IC's startup signal INH-edge changes to a high level, and a rising edge occurs. Ideally, the power supply IC 206 should detect that the power supply IC's startup signal INH-edge is at a high level in synchronization with this rising edge, and know that a wake-up command has been received.

[0089] However, at time t8, the power supply IC 206 is in the process of shutting down power. Therefore, at time t8, it is not possible to detect that the power supply IC's startup signal INH-edge is at a high level.

[0090] Therefore, at time t9, the generation of the power supply voltage VCC is stopped in accordance with the sleep command. In other words, an unnecessary power outage occurs. That is, wake-up fails during the power outage.

[0091] Therefore, in this invention, the startup signal of the power supply IC is changed from an edge trigger signal INH-edge to a voltage level signal INH-Vlevel. With a voltage level signal, the voltage level of the startup signal changes and then remains at that level, which allows the power supply IC 206 to have sufficient time to determine the voltage level of the received startup signal.

[0092] In other words, the power supply IC 206 can determine the voltage level of the received wake-up signal at any given time. For example, the power supply IC 206 detects the voltage level of the wake-up signal when the period during which the sleep command from the CPU 204 is in effect ends. This allows the power supply IC 206 to know that a wake-up command has been received. This point will be explained in detail using Figure 5.

[0093] Next, refer to Figure 4. Figure 4 shows an example of a specific configuration of an electronic control device in an embodiment of the present invention that does not use a subprocessor and uses a voltage level signal as the startup signal for the power supply IC. In Figure 4, the same reference numerals are used for parts that are common with the previously shown figure.

[0094] The CAN communication circuit 202 includes a common-mode filter 220 for removing noise, a transceiver 222, a CAN controller 224, a first SPI interface unit (I / F) 228, and a startup signal generation unit 228 that generates and outputs a voltage level signal, which is the startup signal ENH-Vlevel, for the power supply IC.

[0095] The power supply IC's startup signal ENH-Vlevel is sent to the power supply IC 206 via signal path L1, which does not involve the sub-CPU (sub-processor). Since power supplies for the sub-CPU and sub-CPU are not required, power consumption is reduced, the configuration is simplified, and the software burden is reduced.

[0096] Furthermore, the power supply IC 206 includes a startup signal receiving unit 240 that receives the startup signal INH-Vlevel of the power supply IC, a comparator 244 that compares the received startup signal INH-Vlevel of the power supply IC with a reference voltage Vref, a determination unit 242 that determines whether the received startup signal ENH-Vlevel of the power supply IC is at a disabled level (L) or an enabled level (H), a priority wake-up processing unit 246, a power supply generation unit 248 that generates the power supply voltage VCC, a reset unit (RS) 250 that outputs a reset signal RES to the CPU 204, and a second SPI interface unit (I / F) 252.

[0097] The first and second SPI interface sections (I / F) 226 and 252 are sometimes simply referred to as the first and second interfaces. The first and second SPI interface sections (I / F) 226 and 252 are synchronous data communication interfaces that transfer data in synchronization with the clock edge. By providing this interface, the CAN communication circuit 202 can use SPI, which is a highly reliable communication interface.

[0098] The CAN communication circuit 202 has a novel configuration that combines a data communication interface 226 that performs synchronous communication with the CPU 204 and a signal output terminal INH (broadly speaking, a data communication interface) that performs voltage level data communication with the power supply IC 206.

[0099] The first SPI bus, SPI-BUS1, and the second SPI bus, SPI-BUS2, each have communication lines for the data transfer clock SCLK, input data MOSI, output data MISO, and chip select signal CS. The input data MOSI and output data MISO are transferred in synchronization with the rising or falling edge of the clock SCLK.

[0100] Furthermore, the CPU 204 has SPI interface sections 227 and 253.

[0101] In the CAN communication circuit 202, the startup signal generation unit 228, upon receiving a wake-up command, sets the startup signal INH-Vlevel of the power supply IC, which is a voltage level signal, to the enable level (H level).

[0102] Furthermore, when the CAN communication circuit 202 receives a sleep command, it transmits the received sleep command to the CPU 204 via the first SPI bus SPI-BUS1.

[0103] When the CPU 204 receives a sleep command from the CAN communication circuit 202, it decodes the command, sends a sleep command to the CAN communication circuit 202, and also sends a power-off command to the power supply IC 206.

[0104] When the power supply IC 206 attempts to shut down its power supply in response to a power shutdown command sent from the CPU 204, the priority wake-up processing unit 246 determines whether the power supply IC's startup signal INH-Vlevel sent from the CAN communication circuit 202 is at the enable level (H level), or in other words, whether the enable level (H level) is being maintained.

[0105] If the enable level (H level) is maintained, the priority wake-up processing unit 246 prioritizes the activation of the power supply IC 206 due to the activation signal INH-Vlevel of the power supply IC being enabled over the power-off command, and continues to generate the power supply voltage VCC.

[0106] By using a voltage level signal instead of an edge-triggered startup signal as the startup signal for power supply IC 206, the enable level is maintained even after receiving a sleep command, thus providing power supply IC 206 with sufficient time to detect that enable level.

[0107] In other words, the priority wake-up processing unit 246 can determine, for example, whether the power supply IC's startup signal INH-Vlevel is at the enable level at the time of attempting to shut off the power supply. As a result of this determination, the power supply IC 206 can know that a wake-up command has been received. Therefore, the generation of the power supply voltage VCC continues, and unnecessary power shutdowns do not occur.

[0108] The ECUm in Figure 4 has a simplified configuration and does not require complex signal processing. This is advantageous for miniaturizing and reducing the power consumption of the electronic control unit (ECU).

[0109] Furthermore, the power supply IC 206 has a reset unit (RS) 250. When the power supply IC 206 continues to generate the power supply voltage, the power supply voltage VCC is also supplied to the CPU 204, and the CPU 204 continues to operate. In this embodiment, the reset unit (RS) 250 outputs a reset signal RES to the CPU 204, thereby resetting the CPU 204.

[0110] In other words, upon receiving the wake-up command, the CPU 204 is reset, and operation begins from an initialized state (initial start). When CPU204 is reset, various counters, timers, input / output ports, etc., are initialized, and the internal state of CPU204 returns to its initial predetermined state.

[0111] This allows various programs to start normally, even if, for example, a partial problem occurs inside the CPU204, as a reset will return it to its initial predetermined state.

[0112] This reduces the likelihood of future processor malfunctions (failures), thus contributing to preventing a decline in processor reliability.

[0113] Alternatively, the power supply IC 206 may output a reset signal RES from the reset unit (RS) 250 by transitioning its state to its initial state.

[0114] In other words, the power-on reset function of the power supply IC 206, that is, the function that outputs a reset signal RES to the CPU 204 when the power is turned on and starts from the initial state, is used to enable the output of the reset signal RES.

[0115] In this case, the reset signal can be output using the existing functions of the power supply IC 206, eliminating the need for special processing to output the reset signal, and thus reducing the burden on the power supply IC 206.

[0116] Next, refer to Figure 5. Figure 5 shows the wake-up operation during power-off in an electronic control device according to an embodiment of the present invention.

[0117] Figure 5A-1 is a simplified representation of the configuration in Figure 4, and is essentially the same as Figure 2A-2 shown earlier. Figure 5A-2 shows a timing chart illustrating the wake-up operation while the power supply is off.

[0118] At time t10, the power supply voltage VCC becomes 5V, and consequently, the power supply IC's startup signal INH-Vlevel becomes the enable level (H level).

[0119] The voltage at the ENA terminal of power supply IC 206 changes in accordance with the voltage level of the power supply IC's startup signal, INH-Vlevel.

[0120] At time t11, the reset signal RES changes from L to H. At time t12, a sleep command is output from CPU 204. Consequently, at time t13, the power supply IC's start signal INH-Vlevel becomes disabled (L level).

[0121] Furthermore, at time t13, a power-off command is output from CPU204. The power-off processing period T1 is from time t13 to time t15.

[0122] At time t14, a wake-up command is received. Consequently, at time t14, the power supply IC's startup signal INH-Vlevel becomes the enable level (H level). This enable level (H level) persists during the latter half of the power-off processing period T1, period T2.

[0123] At time t15, which marks the end of the power-off processing period T1, the enable level (H level) of the power supply IC's startup signal INH-Vlevel remains active. Therefore, the power supply IC 206's priority wake-up processing unit 246 prioritizes processing based on the wake-up instruction. Consequently, the power supply voltage VCC remains at 5V even after time t15, and no unnecessary power-off occurs.

[0124] Furthermore, at time t15, the reset signal RES changes from a low level to a high level, creating a rising edge. This resets and initializes CPU204. In other words, the initial start of CPU204 is achieved.

[0125] Next, refer to Figure 6. Figure 6 shows an example of the configuration of an electronic control unit with an added monitoring circuit.

[0126] In Figure 6, a monitoring circuit 260 for the power supply IC startup signal (hereinafter simply referred to as the monitoring circuit) is added to the configuration shown in A-1 of Figure 5. This monitoring circuit 260 is located between the signal path L1, which transmits the INH-Vlevel startup signal for the power supply IC output from the CAN communication circuit 202 to the power supply IC 206, and the CPU 204.

[0127] The monitoring circuit 260 includes a voltage holding circuit consisting of a resistor R1 and a capacitor C1, a base resistor R2, an NPN transistor TR1, a load resistor R3, and a bias resistor R4 that generates a bias voltage between the base and emitter of the NPN transistor TR1.

[0128] When the power supply IC's startup signal INH-Vlevel is at the disabled level (L level), the NPN transistor TR1 turns off, and the CPU204's monitoring terminal CH becomes high (H) at the power supply voltage VCC.

[0129] On the other hand, when the power supply IC's startup signal INH-Vlevel is at the enable level (H level), the NPN transistor TR1 turns on, collector current flows through the load resistor R3, and a voltage drop occurs. Therefore, the monitoring terminal CH of the CPU204 becomes the voltage obtained by subtracting the voltage drop from the power supply voltage VCC (L).

[0130] In other words, the CPU 204 can monitor the voltage level of the power supply IC's startup signal INH-Vlevel by detecting the voltage of the monitoring terminal CH. Specifically, the CPU 204 can detect, for example, whether the power supply IC's startup signal INH-Vlevel is at the enable level (H) or the disable level (L) via the monitoring circuit 260.

[0131] For example, when the CAN communication circuit 202 receives a sleep command, as explained earlier, the sleep command is sent to the CPU 204, and the CPU 204, having decoded the sleep command, sends a sleep command back to the CAN communication circuit 202.

[0132] When the CAN communication circuit 202 enters sleep mode, the power supply IC's startup signal INH-Vlevel changes from the enable level (H) to the disable level (L). The CPU 204 can detect a change in the voltage level via the monitoring circuit 260, thereby determining whether the CAN communication circuit 202 is operating correctly in accordance with the sleep command.

[0133] If, even after the CPU 204 issues a sleep command to the CAN communication circuit 202, no change in the voltage level of the power supply IC's startup signal INH-Vlevel occurs, it is possible to infer an abnormality in the CAN communication circuit 202, an abnormality in the communication path (SPI-BUS1) between the CAN communication circuit 202 and the CPU 204, or an abnormality in the monitoring circuit 260, and a predetermined countermeasure can be taken. Prescribed countermeasures include, for example, notifying the user of the abnormality and restarting the ECU. The ability to quickly implement appropriate countermeasures contributes to suppressing the deterioration of the reliability of electronic control units (ECUs).

[0134] Next, refer to Figure 7. Figure 7 is a flowchart showing an example of the sleep and wake-up procedure in the electronic control unit shown in Figure 6.

[0135] In step S1, the CPU, upon receiving the sleep command, sends a sleep command to the CAN communication circuit. In step S2, the CAN communication circuit determines whether or not a sleep command has been issued.

[0136] If the result in step S2 is N, then in step S3, the CAN communication circuit maintains the enable level of the power supply IC's startup signal. If the answer is Y in step S2, then in step S4, the CAN communication circuit disables the power supply IC's startup signal.

[0137] In step S5, the CPU monitors the voltage level of the power supply IC's startup signal via the monitoring circuit.

[0138] In step S6, the CPU determines whether the power supply IC's startup signal is at a disabled level.

[0139] If the result in step S6 is N, the CPU determines in step S7 that there is an abnormality in the CAN communication circuit, an abnormality in SPI-BUS1, or an abnormality in the monitoring circuit, because the level of the power supply IC's startup signal is not at the level corresponding to the sleep command transmitted in step S1.

[0140] If the answer is Y in step S6, then in step S8, the CPU sends a power-off command to the power supply IC.

[0141] In step S9, the power supply IC determines whether a wake-up command has been received, that is, whether the power supply IC's startup signal is at the enable level, while the power-off command is in effect, in other words, while the power-off process is in effect.

[0142] If the result in step S9 is N, then in step S10, the CPU will perform a power off or shutdown in accordance with the sleep command.

[0143] If the answer is Y in step S9, in step S11, the power supply IC continues to generate the power supply voltage, prioritizing the fact that the power supply IC's startup signal is at the enable level. Meanwhile, the CPU is reset by the reset signal from the power supply IC and performs an initial start.

[0144] As described above, according to the embodiment of the present invention, since a subprocessor (subCPU) is not used in the electronic control device, a significant reduction in power consumption is possible, and consequently, the power consumption of the electronic control system can also be promoted. Furthermore, the electronic control unit has a simplified configuration in which the power supply IC's startup signal is a voltage level signal, and a priority wake-up processing unit is provided in the power supply IC. Therefore, it is possible to achieve miniaturization, cost reduction, and a reduction in the processing load of the electronic control unit. Furthermore, if the communication circuit receives a wake-up command while the power supply IC is shutting down, an unintended power shutdown can be avoided. Furthermore, by resetting the CPU or by installing a monitoring circuit to monitor the voltage level of the power supply IC's startup signal, the deterioration of the reliability of the electronic control unit can be suppressed. Furthermore, even if a sleep command is received immediately after the electronic control unit is started up, the electronic control unit can be put into sleep mode in accordance with the sleep command.

[0145] Thus, as described above, the electronic control device of the present invention has the function of further reducing power consumption while retaining the necessary functions and reliability. Therefore, while maintaining reliability, a significant reduction in power consumption can be achieved for the entire electronic control system. In recent years, the amount of electronic equipment installed in vehicles has increased, and consequently, the power consumption of electronic control systems has tended to increase. In particular, there is a growing demand to reduce standby current (dark current) when the vehicle is stopped, which directly leads to a drop in battery voltage. The present invention can meet the above requirements. This contributes, for example, to the realization of electric vehicles, electric two-wheeled vehicles, etc., that can operate for a long time on a single battery charge.

[0146] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and applications are possible. For example, the electronic control device and electronic control system of the present invention can be installed in electric vehicles and so-called hybrid vehicles, as well as for use in ships and general industrial applications. [Industrial applicability]

[0147] The present invention is suitable, for example, as an electronic control device and an electronic control system mounted on a vehicle. [Explanation of symbols]

[0148] 10...Higher-level device, 20...Sensor, 30a, 30b...Termination resistor, 40...Power line, 102...Other devices connected to the network (e.g., power control ECU), 104...Selective wake-up / sleep communication unit, 150...Electronic control system, 200...ECU group, 202...CAN communication circuit (communication circuit), 204...CPU (Central Processing Unit, Processor), 206...Power IC (Power circuit, integrated circuit for power supply), 220...Common mode filter, 222...Transceiver (CAN transceiver), 224...CAN controller, 226...First interface unit (first SPI interface unit), 227...SPI interface unit, 228...Startup signal generation unit (Power IC startup signal generation unit), 240...Startup signal receiving unit (Power IC startup signal receiving unit), 242...Determination unit, 244...Comparator (Comparison unit), 246...Priority wake-up processing unit, 250...Reset unit (Reset circuit), 252...Second interface unit (Second SPI interface unit), 253...SPI interface unit, 260...Monitoring circuit, BATT...Battery, ECU (ECU1~ECUm)...Electronic control unit as an electronic control device, INH-Vlevel...Power IC startup signal (Voltage level signal, Power IC startup signal which is a voltage level signal), RES...Reset signal, SPI-BUS1...First SPI bus, SPI-BUS2...Second SPI bus

Claims

1. An electronic control device connected to a network, A processor that controls the operation of the aforementioned electronic control unit, A communication circuit that receives sleep commands and wake-up commands from other devices connected via the aforementioned network, and has a first interface for communication with the processor, A power supply IC that generates a power supply voltage and has a second interface for communication with the processor, It has, The aforementioned communication circuit is Upon receiving the wake-up command, the system includes a startup signal generation unit that sets the startup signal of the power supply IC, as a voltage level signal, to the enable level, and transmits the received sleep command to the processor via the first interface. The aforementioned processor, Upon receiving the sleep command sent from the communication circuit, the system transmits a sleep command to the communication circuit and a power-off command to the power supply IC. The aforementioned power supply IC is When attempting to shut down the power supply in response to the power shutdown command sent from the processor, if the enable level of the power supply IC startup signal sent from the communication circuit is maintained, the system has a priority wake-up processing unit that prioritizes the startup of the power supply IC due to the enable status of the power supply IC startup signal over the power shutdown command, thereby continuing the generation of the power supply voltage. Electronic control unit.

2. The startup signal for the power supply IC is transmitted from the communication circuit to the power supply IC via a signal path that does not go through the subprocessor. The electronic control device according to claim 1.

3. The first interface and the second interface are communication interfaces that transmit and receive data in synchronization with the rising or falling edge of the clock. The electronic control device according to claim 1.

4. A power supply IC startup signal monitoring circuit is provided between the signal path that transmits the startup signal of the power supply IC output from the communication circuit to the power supply IC and the processor, for monitoring the level of the startup signal of the power supply IC. The electronic control device according to claim 1.

5. The aforementioned power supply IC is It has a reset unit that outputs a reset signal to reset the processor, When the priority wake-up processing unit prioritizes the activation of the power supply IC due to the activation signal of the power supply IC being enabled and continues to generate the power supply voltage, it outputs the reset signal from the reset unit, thereby initializing the processor. The electronic control device according to claim 1.

6. The power supply IC outputs the reset signal from the reset unit by transitioning the state of the power supply IC to its initial state. The electronic control device according to claim 5.

7. An electronic control system in which a plurality of electronic control devices according to any one of claims 1 to 6 are connected to the network.

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