control device

Abstract

To provide a control device for collating outputs of a plurality of processing devices that can accurately collate data even if inconsistent output order exists among the processing devices.SOLUTION: A device includes: a first comparison circuit for comparing a control signal stored in a first memory circuit with a control signal output by a second processing device; a second comparison circuit for comparing a control signal stored in a second memory circuit with a control signal output by a first processing device; a third comparison circuit for comparing a control signal output by the first processing device with a control signal output by the second processing device; a first selection circuit for selecting data from data output by the first processing device and data output by the first memory circuit; a second selection circuit for selecting data from data output by the second processing device and data output by the second memory circuit; a selection signal generation circuit for generating selection signals for the first selection circuit and the second selection circuit from comparison results output by the comparison circuits; and a collation circuit for collating the data selected by the first selection circuit and the second selection circuit.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a control device.

Background Art

[0002] As the background art in this technical field, for example, there is Patent Document 1. This publication describes a data collation device that can accurately collate data even when the synchronization of data sent from a plurality of data sources is shifted. The data collation device of Patent Document 1 includes a synchronization signal generation circuit 10 that generates a synchronization signal 3 based on data 1a and 1b sent from a plurality of data sources A and B, a synchronization deviation detection circuit 20 that generates a synchronization adjustment signal 5 based on the synchronization signal 3, and a synchronization adjustment collation circuit 30 that adjusts the collation timing based on the synchronization adjustment signal 5 to collate the data 1a and 1b. It collates the data 1a and 1b that may be out of synchronization sent from the two data sources A and B. In the data collation device of FIG. 1 disclosed in Patent Document 1, the amount of synchronization deviation is detected by a synchronization deviation detection circuit, and by selecting the data of an appropriate collation shift register with a multiplexer according to the detected amount of synchronization deviation, it is ensured that the inputs of the collation circuit are synchronized, making it possible to collate accurately.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the background technology, when the data source processing unit includes a CPU, a common method is to execute multiple processes in a time-sharing manner by interrupting the CPU. For example, if an interrupt occurs while a task is being executed, the task is interrupted, an interrupt routine is executed, and the interrupted task is resumed after the interrupt routine is completed. Even if the same program is executed on multiple CPUs, if the synchronization between the CPUs is off, the point at which a task is interrupted may differ depending on the CPU. In that case, an output that occurred before the interrupt routine was processed by one processing unit may occur after the interrupt routine was processed by another processing unit, resulting in an inconsistent output order among the multiple processing units. The data matching device disclosed in Patent Document 1 does not handle cases where the output order is inconsistent and cannot accurately match the data.

[0005] This invention has been made in view of the above problems, and aims to accurately compare data even if there is a discrepancy in the order of the outputs in a control device that compares the outputs of multiple processing devices. [Means for solving the problem]

[0006] One representative control device of the present invention that solves the above problems is a first processing device that outputs a first control signal and first data, a second processing device that outputs a second control signal and second data, a first storage circuit that stores the first control signal and first data output by the first processing device, a second storage circuit that stores the second control signal and second data output by the second processing device, a first comparison circuit that compares the first control signal stored in the first storage circuit and output by the first storage circuit with the second control signal output by the second processing device, or compares the first data stored in the first storage circuit and output by the first storage circuit with the second data output by the second processing device, and compares the second control signal stored in the second storage circuit and output by the second storage circuit with the first control signal output by the first processing device, or stores the first control signal stored in the second storage circuit and output by the second storage circuit The device comprises: a second comparison circuit that compares the second data output by the first processing unit with the first data output by the first processing unit; a third comparison circuit that compares the first control signal output by the first processing unit with the second control signal output by the second processing unit, or compares the first data output by the first processing unit with the second data output by the second processing unit; a first selection circuit that selects data to be matched from the first data output by the first processing unit with the first data output by the first memory circuit; a second selection circuit that selects data to be matched from the second data output by the second processing unit with the second data output by the second memory circuit; a selection signal generation circuit that generates selection signals for the first and second selection circuits from the comparison results output by the first, second, and third comparison circuits; and a matching circuit that matches the data selected by the first selection circuit with the data selected by the second selection circuit. [Effects of the Invention]

[0007] According to the present invention, it is possible to accurately match data even if there is a discrepancy in the order of the output. Issues, structures, and effects other than those mentioned above will be clarified by the following explanation of the implementation methods. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram common to the control devices according to Embodiments 1 to 3 of the present invention. [Figure 2] Figure 2 is a block diagram showing an example of a synchronization circuit in the control device shown in Figure 1. [Figure 3] Figure 3 is a state transition diagram showing an example of the operation of the first request holding circuit in the synchronization circuit of Figure 2. [Figure 4] Figure 4 is a state transition diagram showing an example of the operation of the second request holding circuit in the synchronization circuit of Figure 2. [Figure 5] Figure 5 is a state transition diagram showing an example of the operation of the first response holding circuit in the synchronization circuit of Figure 2. [Figure 6] Figure 6 is a state transition diagram showing an example of the operation of the second response holding circuit in the synchronization circuit of Figure 2. [Figure 7] Figure 7 is a timing diagram showing a first example of the operation of the synchronization circuit in Figure 2. [Figure 8] Figure 8 is a timing diagram showing a second example of the operation of the synchronization circuit in Figure 2. [Figure 9] Figure 9 is a block diagram showing a first example of the sequence adjustment circuit in the control device shown in Figure 1. [Figure 10] Figure 10 is a table showing an example of the operation of the selection signal generation circuit in the sequence adjustment circuit of Figure 9. [Figure 11] Figure 11 is a timing diagram showing an example of the operation of the sequence adjustment circuit in Figure 9. [Figure 12] Figure 12 is a block diagram showing a second example of the sequence adjustment circuit in the control device shown in Figure 1. [Figure 13] Figure 13 is a block diagram showing a third example of the sequence adjustment circuit in the control device shown in Figure 1. [Figure 14] Figure 14 is a table showing an example of the operation of the selection signal generation circuit in the sequence adjustment circuit of Figure 13. [Figure 15] Figure 15 is a timing diagram showing an example of the operation of the sequence adjustment circuit in Figure 13. [Modes for carrying out the invention]

[0009] Hereinafter, Examples 1 to 3 according to the present invention will be described with reference to the drawings. Example 1 is shown in FIGS. 1 to 11, Example 2 is shown in FIGS. 1 to 8 and FIG. 12, and Example 3 is shown in FIGS. 1 to 8 and FIGS. 13 to 15. Note that the present invention is not limited by this embodiment. Also, in the description of the drawings, the same parts are denoted by the same reference numerals.

[0010] In the following description, the type of a signal may be specified using the reference numeral attached to the signal line through which the signal is transmitted. For example, when a control signal is transmitted through signal line A, the signal transmitted through signal line A may be referred to as control signal A. This also applies to other types of signals such as request signals, response signals, and data.

[0011] [Example 1] Example 1 will be described with reference to FIGS. 1 to 11. FIG. 1 is a block diagram common to the control devices according to Examples 1 to 3 of the present invention. Note that the description of FIG. 1 is omitted in the descriptions of Examples 2 to 3 described later. As shown in FIG. 1, the control device 10 of Example 1 includes a first processing device 100, a second processing device 120, an output stop circuit 152, an order adjustment circuit 140, a collation circuit 150, and an input control circuit 170. For example, the control device 10 controls the device 160 via the collation circuit 150.

[0012] Note that there are three variations of the order adjustment circuit 140, and the order adjustment circuits 140A (FIG. 9), 140B (FIG. 12), and 140C (FIG. 13) are shown in Examples 1 to 3, respectively. In Example 1, these common parts will be described as the order adjustment circuit 140.

[0013] The first processing device 100 outputs a first control signal and first data. Also, the second processing device 120 outputs a second control signal and second data. Specifically, the first processing device 100 includes a CPU 101, a synchronization circuit 103, a RAM 104, a ROM 105, an output circuit 107, an input circuit 108, a bus 102, and a bus 106. The second processing device 120 includes a CPU 121, a synchronization circuit 123, a RAM 124, a ROM 125, an output circuit 127, an input circuit 128, a bus 122, and a bus 126. Note that the second processing device 120 has the same configuration as that of the first processing device 100. In the following description, the description of the second processing device 120 may be omitted.

[0014] The CPU 101 executes the following processing according to the program stored in the ROM 105. First, the CPU 101 receives information about the device 160 from the input circuit 108 via the bus 106, the synchronization circuit 103, and the bus 102, and performs predetermined control processing. Then, the information necessary for controlling the device 160 is output from the CPU 101 to the bus 109 via the bus 102, the synchronization circuit 103, the bus 106, and the output circuit 107. The RAM 104 is used to save the intermediate progress of the control processing. The operation of the CPU 121 is the same as that of the CPU 101.

[0015] The synchronization circuit 103 is a circuit for exchanging information between buses 102 and 106, which have different operating frequencies. Generally, increasing the operating frequency of the CPU has a large impact on system performance, but increasing the operating frequency of other circuits has a small impact on system performance. For this reason, it is common practice to operate the CPU at a relatively high operating frequency and other circuits at a relatively low operating frequency. Against this backdrop, Figure 1 shows an example where the operating frequency of bus 102 is higher than that of bus 106. As will be described later, the difference in operating frequencies between buses 102 and 106 can cause a timing difference between the operation of CPU 101 and CPU 121. This timing difference can lead to a timing difference in interrupts, causing the output order of the first processing unit 100 and the second processing unit 120 to be inconsistent. The operation of the synchronization circuit 123 is the same as that of the synchronization circuit 103.

[0016] When input circuit 108 receives an input request from CPU 101 via bus 102, synchronization circuit 103, and bus 106, it outputs that input request to input control circuit 170 via bus 110. Furthermore, when input circuit 108 receives data corresponding to the input request output from input control circuit 170 via bus 110, it outputs that data to CPU 101 via bus 106, synchronization circuit 103, and bus 102. The operation of input circuit 128 is the same as that of input circuit 108.

[0017] When output circuit 107 receives information from CPU 101 via bus 102, synchronization circuit 103, and bus 106, it outputs the received information to bus 109. The value output to bus 109 may be a digital value for an AD (Analog-to-Digital) conversion circuit present in device 160. Alternatively, the value output to bus 109 may be a command value for changing the state of switches or AD conversion circuits present in device 160. The value output to bus 109 consists of a control signal including an enable signal and an address value, and data. The operation of output circuit 127 is the same as that of output circuit 107.

[0018] Initially, the verification circuit 150 outputs a stop command of 0 (output enabled) to the output stop circuit 152 via the signal line 151. The verification circuit 150 also receives the outputs of the output circuits 107 and 127, whose order and output timing have been adjusted by the sequence adjustment circuit 140, via buses 141 and 142. If the values ​​do not match as a result, the verification circuit 150 outputs a stop command of 1 (output stopped) to the output stop circuit 152 via the signal line 151.

[0019] The timing at which the verification circuit 150 resets the stop command to 0 (output enabled) may be when buses 141 and 142 coincide. Alternatively, the timing at which the stop command is reset to 0 (output enabled) may be when a signal indicating a system reset state, not explicitly shown in Figure 1, is asserted. In this case, even if buses 141 and 142 coincide, the stop command will remain at 1 (output stopped) until the system reset state is reached.

[0020] The output stop circuit 152 outputs the value of bus 109 to bus 161 if the stop command received from the verification circuit 150 via signal line 151 is 0 (output enabled). The output stop circuit 152 also outputs a predetermined value to bus 161 if the stop command received from the verification circuit 150 via signal line 151 is 1 (output stopped). In this case, the value output to bus 161 is defined as a value necessary to safely stop the device 160.

[0021] The input control circuit 170 sequentially executes the following processes. First, the input control circuit 170 receives an input request from the input circuit 108 via the bus 110. Next, the input control circuit 170 selects either the information of the device 160 acquired from the signal line 162 or the information of the device 160 that was previously acquired from the signal line 162 and stored internally. The selected information is output from the input control circuit 170 to the input circuit 108 via the bus 110.

[0022] Furthermore, the input control circuit 170 sequentially executes the following processes. First, the input control circuit 170 receives an input request from the input circuit 128 via the bus 130. Next, the input control circuit 170 selects either the information of the device 160 acquired from the signal line 162 or the information of the device 160 that was previously acquired from the signal line 162 and stored internally. The selected information is output from the input control circuit 170 to the input circuit 128 via the bus 130.

[0023] The internal state of device 160 changes over time. Therefore, if there is a discrepancy between the time of the input request from input circuit 108 and the time of the input request from input circuit 128, the information about device 160 acquired from signal line 162 at the time of the input request may have different values. If the value output to input circuit 108 and the value output to input circuit 128 are different, a discrepancy will occur between the processing result of the first processing unit 100 and the processing result of the second processing unit 120, and the matching circuit 150 will detect a mismatch during the matching process. To prevent such a situation, the input control circuit 170 internally stores the output value to the input circuit that first receives the input request, and outputs the internally stored value to the input circuit that receives the input request later. By performing this process, it is guaranteed that the value output to input circuit 108 and the value output to input circuit 128 will be the same.

[0024] Figure 2 is a block diagram showing an example of the synchronization circuit 103 in the control device shown in Figure 1. The synchronization circuit 103 consists of a circuit that transmits request information and output data from bus 102 to bus 106, and a circuit that transmits input data from bus 106 to bus 102. Figure 2 shows the circuit that transmits request information and output data from bus 102 to bus 106. The configuration of the circuit that transmits input data from bus 106 to bus 102 is the same as the circuit in Figure 2, except that the direction of information transmission is different.

[0025] The synchronization circuit 103 in Figure 2 includes a first request holding circuit 211, a first storage circuit 231, a second storage circuit 233, a second request holding circuit 251, a first response holding circuit 254, a third storage circuit 234, a fourth storage circuit 232, a second response holding circuit 212, a control signal storage circuit 252, and a data storage circuit 253. The bus 102 includes signal lines for transmitting a clock signal 201, a request signal 202, a control signal 203, data 204, and a response signal 205. The control signal 203 may include the type of request (input or output), an address for selecting one of several storage circuits to which the request is directed, or a byte enable indicating which bytes of data are valid if the output data consists of multiple bytes. Bus 106 similarly includes signal lines for transmitting a clock signal 261, a request signal 262, a control signal 263, data 264, and a response signal 265.

[0026] The first request holding circuit 211, upon receiving a value of 1 from signal line 202 indicating a request, outputs a value of 1 to signal line 221 for a certain period of time, indicating a request. The method for determining the period for which 1 is output will be described later.

[0027] The first memory circuit 231 captures the value of signal line 221 on the rising edge of the clock signal 261 and outputs it to signal line 241.

[0028] The second memory circuit 233 captures the value of signal line 241 on the rising edge of the clock signal 261 and outputs it to signal line 243.

[0029] The second memory circuit 233 is responsible for preventing the propagation of intermediate values ​​that occur when transmitting signals between different clocks. While signal line 221 operates in synchronization with clock signal 201, the first memory circuit 231 captures the value of signal line 221 on the rising edge of clock signal 261. Therefore, the value of signal line 221 may change almost simultaneously with the rising edge of clock signal 261, in which case the value of signal line 241 may be between 0 and 1. However, even in such cases, the value of signal line 241 converges to either 0 or 1 within the time of one cycle of clock signal 261. Since the value of signal line 241 has converged to either 0 or 1 when the second memory circuit captures the value of signal line 241, it is possible to prevent the propagation of intermediate values ​​to signal line 243.

[0030] The second request holding circuit 251, upon receiving a value of 1 from signal line 243 indicating a request, outputs a value of 1 to signal line 262 for a certain period of time. The method for determining the period for which 1 is output will be described later.

[0031] The first response holding circuit 254, when it receives a value of 1 from signal line 265 while signal line 262 is in a requested state (value of 1), outputs a value of 1 to signal line 244 for a certain period of time (value of 1). The method for determining the period for which 1 is output will be described later.

[0032] The third memory circuit 234 captures the value of signal line 244 on the rising edge of the clock signal 201 and outputs it to signal line 242.

[0033] The fourth memory circuit 232 captures the value of signal line 242 on the rising edge of the clock signal 201 and outputs it to signal line 222. Similar to the second memory circuit 233, the fourth memory circuit 232 plays a role in preventing the propagation of intermediate values ​​that occur when transmitting signals between different clocks.

[0034] The second response holding circuit 212, upon receiving a value of 1 from the signal line 222 indicating a response, outputs a value of 1 to the signal line 205 for a certain period of time, indicating a response. The method for determining the period for which 1 is output will be described later.

[0035] The control signal memory circuit 252 captures the value of signal line 203 on the rising edge of the clock signal 261 and outputs it to signal line 263. There is a possibility that intermediate values ​​may occur on signal line 263 due to signal transmission between different clocks, but this is not a problem because, as will be explained later, the value of signal line 263 is not used until it converges to 0 or 1.

[0036] The data storage circuit 253 captures the value of signal line 204 on the rising edge of the clock signal 261 and outputs it to signal line 264. Intermediate values ​​may occur on signal line 264 due to signal transmission between different clocks, but this is not a problem because, like signal line 263, the value of signal line 264 is not used until it converges to 0 or 1.

[0037] The clock signals 201 and 261 are generated, for example, from a crystal oscillator located within the first processing unit 100. In the first processing unit 100, the clock signal 201 is used by the CPU 101, and the clock signal 261 is used by components other than the CPU 101.

[0038] Figure 3 is a state transition diagram showing an example of the operation of the first request holding circuit 211 in the synchronization circuit 103 of Figure 2. The state transition diagram of Figure 3 has a first no-request output state 301, a request output state 302, and a second no-request output state 303. In the first no-request output state 301 and the second no-request output state 303, the request signal 221, which is the output of the first request holding circuit 211, is 0, and in the request output state 302, the request signal 221 of the first request holding circuit 211 is 1. Here, the first no-request output state 301 and the second no-request output state 303 are states when the value of signal line 202 is 0, indicating no request as a request signal, and the value of signal line 203 is invalid. The request output state 302 is a state when the value of signal line 202 is 1, indicating a request as a request signal, and the value of signal line 203 is valid.

[0039] If the value of signal line 202 becomes 1 in the first no-request output state 301, the system transitions to the request output state 302 on the rising edge of the next clock signal 201. If the value of signal line 202 is 0, the system remains in the first no-request output state 301.

[0040] If the value of signal line 222 becomes 1 in the requested output state 302, the system transitions to the second requested output state 303 on the rising edge of the next clock signal 201. If the value of signal line 222 is 0, the system remains in the requested output state 302.

[0041] If, in the second no-request output state 303, the value of signal line 222 is 0 and the value of signal line 202 is 1, the system will transition to the request output state 302 on the rising edge of the next clock signal 201.

[0042] If the value of signal line 222 is 0 and the value of signal line 202 is 0 in the second no-request output state 303, the system transitions to the first no-request output state 301 on the rising edge of the next clock signal 201. If signal line 222 is 1, the system remains in the second no-request output state 303.

[0043] Figure 4 is a state transition diagram showing an example of the operation of the second request holding circuit 251 in the synchronization circuit 103 of Figure 2. The state transition diagram of Figure 4 has a first no-request output state 401, a request output state 402, and a second no-request output state 403. In the first no-request output state 401 and the second no-request output state 403, the request signal 262, which is the output of the second request holding circuit 251, is 0, and in the request output state 402, the request signal 262 of the second request holding circuit 251 is 1. Here, the first no-request output state 401 and the second no-request state 403 are states when the value of signal line 202 is 0, indicating no request as a request signal, and the value of signal line 203 is invalid. The request output state 402 is a state when the value of signal line 202 is 1, indicating a request as a request signal, and the value of signal line 203 is valid.

[0044] If the value of signal line 243 becomes 1 in the first no-request output state 401, the system transitions to the request output state 402 on the rising edge of the next clock signal 261. If the value of signal line 243 is 0, the system remains in the first no-request output state 401.

[0045] If the value of signal line 265 becomes 1 in the requested output state 402, the system transitions to the second requested output state 403 on the rising edge of the next clock signal 261. If the value of signal line 265 is 0, the system remains in the requested output state 402.

[0046] If signal line 243 becomes 0 in the second no-request output state 403, the system transitions to the no-request output state 401 on the rising edge of the next clock signal 261. If signal line 243 is 1, the system remains in the second no-request output state 403.

[0047] Figure 5 is a state transition diagram showing an example of the operation of the first response holding circuit 254 in the synchronization circuit 103 of Figure 2. The state transition diagram of Figure 5 has a no-response output state 501 and a response output state 502. In the no-response output state 501, the value of the response signal 244, which is the output of the first response holding circuit 254, is 0, and in the response output state 502, the value of the response signal 244 of the first response holding circuit 254 is 1. Here, the no-response output state 501 is the state when the value of signal line 262 is 0, indicating no request as a request signal, or when the value of signal line 265 is 0, indicating no response as a response signal. The response output state 502 is the state when the value of signal line 262 is 1, indicating a request as a request signal, and the value of signal line 265 is 1, indicating a response as a response signal.

[0048] If the value of signal line 262 and the value of signal line 265 become 1 while the system is in no response state 501, the system will transition to the response state 502 on the rising edge of the next clock signal 261. If the value of signal line 262 or the value of signal line 265 is 0, the system will remain in no response state 501.

[0049] If the value of signal line 243 becomes 0 in response output state 502, the system transitions to no response output state 501 on the rising edge of the next clock signal 261. If the value of signal line 243 is 1, the system remains in request output state 502.

[0050] Figure 6 is a state transition diagram showing an example of the operation of the second response holding circuit 212 in the synchronization circuit 103 of Figure 2. The state transition diagram of Figure 6 has a first no-response output state 601, a response output state 602, and a second no-response output state 603. In the first no-response output state 601 and the second no-response output state 603, the value of the response signal 205, which is the output of the second response holding circuit 212, is 0, and in the response output state 602, the value of the response signal 205 of the second response holding circuit 212 is 1. Here, the first no-response output state 601 and the second no-response output state 603 are states when the value of signal line 262 is 0, indicating no request as a request signal, or when the value of signal line 265 is 0, indicating no response as a response signal. Furthermore, the requested output state 602 is the state when the value of signal line 262 is 1, indicating a request as a request signal, and the value of signal line 265 is 1, indicating a response as a response signal.

[0051] If the value of signal line 222 becomes 1 in the first no-response state 601, the system transitions to the response-enabled state 602 on the rising edge of the next clock signal 201. If the value of signal line 222 is 0, the system remains in the first no-response state 601.

[0052] In the response output state 602, the system always transitions to the second response output-less state 603 on the rising edge of the next clock signal 201.

[0053] If signal line 222 becomes 0 in the second no-response state 603, the system transitions to the first no-response state 601 on the rising edge of the next clock signal 201. If signal line 222 is 1, the system remains in the second no-response state 603.

[0054] Figure 7 is a timing diagram showing a first example of the operation of the synchronization circuit 103 in Figure 2. Cycle 701 is a numbered representation of each period of the clock signal 201. Odd-numbered cycles are shown, and even-numbered cycles are omitted. Cycle 702 is a numbered representation of each period of the clock signal 261.

[0055] The request signal 202, once it becomes 1, holds its value until the response signal 205 becomes 1, and then becomes 0 in the next cycle.

[0056] The control signal 203 and data 204 output a value corresponding to the request in the cycle when the request signal 202 becomes 1, and hold the same value until the response signal 205 becomes 1. The control signal 203 outputs the first request A-1 in cycle 1 and the second request A-2 in cycle 17. The data 204 outputs the first data D-1 in cycle 1 and the second data D-2 in cycle 17.

[0057] The output value of the request signal 221 is determined according to the state transitions of the first request holding circuit 211, as described in Figure 3.

[0058] The request signal 241 (a signal transmitted on signal line 241) reflects the value of the request signal 221 at the rising edge of the clock signal 261.

[0059] The value of the request signal 243 (a signal transmitted on signal line 243) is reflected on the rising edge of the clock signal 261.

[0060] The output value of the request signal 262 (the signal transmitted on signal line 262) is determined according to the state transitions of the second request holding circuit 251, as explained in Figure 4.

[0061] The control signal 263 (the signal transmitted on signal line 263) reflects the value A-1 of control signal 203 in the first cycle of clock signal 261, and the value A-2 of control signal 203 in the eighth cycle. When the value of control signal 263 changes in the first or eighth cycle of clock signal 261, intermediate values ​​may occur due to signal transmission between different clocks, but it will converge to 0 or 1 during the first or eighth cycle of clock signal 261. The value of control signal 263 is taken into the connected circuit when the request signal 262 is 1, so the value of control signal 263 will not be an intermediate value during that period.

[0062] Data 264 reflects the value D-1 of data 204 in the first cycle of clock signal 261, and the value D-2 of data 204 in the eighth cycle. In data 264 as well, intermediate values ​​may occur due to signal transmission between different clocks, but similar to control signal 263, it will not be an intermediate value during the period it is incorporated into the connected circuit.

[0063] The response signal 265 is a signal output by the access destination circuit connected to the bus 106. Its operation may differ depending on the access destination, but here we show an example where it becomes 1 in the cycle following the value of the request signal 262 becoming 1.

[0064] The output value of the response signal 244 is determined according to the state transitions of the first response holding circuit 254, as described in Figure 5.

[0065] The response signal 242 (the signal transmitted on signal line 242) reflects the value of the response signal 244 at the rising edge of the clock signal 201.

[0066] The response signal 222 (the signal transmitted on signal line 222) reflects the value of the response signal 242 at the rising edge of the clock signal 201.

[0067] The output value of the response signal 205 (the signal transmitted on signal line 205) is determined according to the state transitions of the second response holding circuit 212, as explained in Figure 6.

[0068] Through the above series of operations, the transfer of one request A-1 and data D-1 is completed in the first 15th cycles of the clock signal 201, and the transfer of the second request A-2 and data D-2 begins in the 17th cycle.

[0069] Figure 8 is a timing diagram showing a second example of the operation of the synchronization circuit 103 in Figure 2. In the timing diagram of Figure 7, the time difference between the rising edge of response signal 244 and the rising edge of the 13th cycle of clock signal 201 is small, but it was assumed that the value of 1 of response signal 244 propagates to response signal 242 on the 13th cycle of clock signal 201. Depending on the operating speed of the circuit, the propagation of the value of 1 of response signal 244 to response signal 242 may occur on the 14th cycle of clock signal 201. Figure 8 illustrates such a case. Compared to Figure 7, the rising edge of response signal 242 is delayed by one cycle from clock signal 201, which in turn delays response signal 222 by one cycle, and the timing at which the value of response signal 205 becomes 1 is also delayed by one cycle. As a result, the timing at which the transfer of the second request A-2 and data D-2 begins is also delayed by one cycle.

[0070] As described above, the operation of the synchronization circuit 103 may differ due to the circuit's delay time and the time difference between the rise times of the clocks. For example, if the synchronization circuit 103 of the first processing unit 100 operates at the timing shown in Figure 7, and the synchronization circuit 123 of the second processing unit 120 operates at the timing shown in Figure 8, a timing difference will occur between the operation of the first processing unit 100 and the second processing unit 120, resulting in a mismatch in the output order due to the difference in interrupt timing.

[0071] Figure 9 is a block diagram showing a first example of the sequence adjustment circuit 140 in the control device of Figure 1. The sequence adjustment circuit 140A in Figure 9 includes a first control signal memory circuit 911, a first data memory circuit 912, a second control signal memory circuit 913, a second data memory circuit 914, a first comparison circuit 931, a second comparison circuit 933, a third comparison circuit 932, a selection signal generation circuit 951, a first control signal selection circuit 971, a first data selection circuit 972, a second control signal selection circuit 973, and a second data selection circuit 974.

[0072] Each circuit included in the sequence adjustment circuit 140A performs its function based on the output of the first processing unit 100 transmitted via bus 109 and the output of the second processing unit 120 transmitted via bus 129. The timing of each circuit's function is determined by the clock signal 261 in the first processing unit 100 (or the clock signal in the second processing unit 120), for example, by switching functions on the rising edge of the clock signal 261. The sequence adjustment circuit 140A compares the output of bus 109 and the output of bus 129 and outputs to bus 141 and bus 142 at the same timing. In this way, even if there is a timing difference between the output of bus 109 and the output of bus 129, or if the output order does not match, the sequence adjustment circuit 140A can adjust for the differences and output to the verification circuit 150. A detailed explanation follows below.

[0073] Bus 109 includes signal lines for transmitting control signal 901 and data 902. Control signal 901 may include whether a request exists, the type of request (input or output), an address for selecting one of several memory circuits as the destination, or a byte enable indicating which bytes are valid if the output data consists of multiple bytes. Bus 129 similarly includes signal lines for transmitting control signal 903 and data 904. Bus 141 similarly includes signal lines for transmitting control signal 981 and data 982. Bus 142 similarly includes signal lines for transmitting control signal 983 and data 984.

[0074] The first memory circuit stores the first control signal (a signal transmitted on signal line 901) and the first data (a signal transmitted on signal line 902) output by the first processing unit 100. Specifically, the first memory circuit can be configured to include a first control signal memory circuit 911 and a first data memory circuit 912.

[0075] The first control signal storage circuit 911 stores the value of signal line 901 when there is a request for signal line 901 and the control signal for signal line 901 has not been selected by the first control signal selection circuit 971.

[0076] The first data storage circuit 912 stores the value of signal line 902 when there is a request on signal line 901 and the control signal for signal line 901 has not been selected by the first control signal selection circuit 971.

[0077] Furthermore, the second memory circuit stores the second control signal (a signal transmitted on the signal line 903) and the second data (a signal transmitted on the signal line 904) output by the second processing unit 120. Specifically, the second memory circuit can be configured to include a second control signal memory circuit 913 and a second data memory circuit 914.

[0078] The second control signal memory circuit 913 stores the value of signal line 903 when there is a request for signal line 903 and the control signal for signal line 903 has not been selected by the second control signal selection circuit 973.

[0079] The second data storage circuit 914 stores the value of signal line 904 when there is a request on signal line 903 and the control signal for signal line 903 has not been selected by the second control signal selection circuit 973.

[0080] The first comparison circuit 931 compares the first control signal stored in the first memory circuit and output by the first memory circuit with the second control signal output by the second processing unit. Specifically, the first comparison circuit 931 compares the control signal on signal line 921 with the control signal on signal line 903, and outputs 1 to signal line 941 if they match, and 0 if they do not match.

[0081] The second comparison circuit 933 compares the second control signal stored in the second memory circuit and output by the second memory circuit with the first control signal output by the first processing unit. Specifically, the second comparison circuit 933 compares the control signal on signal line 923 with the control signal on signal line 901, and outputs 1 to signal line 943 if they match, and 0 if they do not match.

[0082] The third comparison circuit 932 compares the first control signal output by the first processing unit 100 with the second control signal output by the second processing unit 120. Specifically, the third comparison circuit 932 compares the control signal on signal line 901 with the control signal on signal line 903, outputting 1 to signal line 942 if they match, and 0 if they do not match.

[0083] The selection signal generation circuit 951 generates selection signals for the first and second selection circuits, which will be described later, from the comparison results output by the first comparison circuit 931, the second comparison circuit 933, and the third comparison circuit 932. Specifically, the selection signal generation circuit 951 takes the comparison results from signal lines 941, 943, and 942 and outputs selection signals 961 and 962 according to predetermined rules. The rules for determining the output will be described later.

[0084] The first selection circuit selects data to match from the first data output by the first processing unit 100 and the first data output by the first storage circuit. Specifically, the first selection circuit can be configured to include a first control signal selection circuit 971 and a first data selection circuit 972.

[0085] The first control signal selection circuit 971 selects either the control signal for signal line 901 or the control signal for signal line 921 according to the selection signal 961 and outputs it to signal line 981.

[0086] The first data selection circuit 972 selects either the data from signal line 902 or the data from signal line 922 according to the selection signal 961 and outputs it to signal line 982.

[0087] The second selection circuit selects data to match from the second data output by the second processing unit 120 and the second data output by the second storage circuit. Specifically, the second selection circuit can be configured to include a second control signal selection circuit 973 and a second data selection circuit 974.

[0088] The second control signal selection circuit 973 selects either the control signal for signal line 903 or the control signal for signal line 923 according to the selection signal 962 and outputs it to signal line 983.

[0089] The second data selection circuit 974 selects either the data from signal line 904 or the data from signal line 924 according to the selection signal 962 and outputs it to signal line 984.

[0090] The data selected by the first selection circuit and the data selected by the second selection circuit are compared by the matching circuit 150.

[0091] Figure 10 is a table showing an example of the operation of the selection signal generation circuit 951 in the sequence adjustment circuit 140A of Figure 9.

[0092] The selection signal generation circuit 951 outputs a selection signal to the first selection circuit to select the first data output by the first memory circuit and to the second selection circuit to select the second data output by the second processing unit 120 when the first comparison circuit 931 detects a match. Specifically, when the output 941 of the first comparison circuit 931 is 1, the selection signal generation circuit 951 outputs selection signals 961 and 962 to the first control signal selection circuit 971 to the value of signal line 921, data 982 to the value of signal line 922, the output 983 of the second control signal selection circuit 973 to the value of signal line 903, and data 984 to the value of signal line 904.

[0093] The selection signal generation circuit 951 also outputs a selection signal when the second comparison circuit 933 detects a match, such that the first selection circuit selects the first data output by the first processing unit 100, and the second selection circuit selects the second data output by the second memory circuit. Specifically, when the output 941 of the first comparison circuit 931 is 0 and the output 943 of the second comparison circuit 933 is 1, the selection signal generation circuit 951 outputs selection signals 961 and 962 such that the output 981 of the first control signal selection circuit 971 becomes the value of signal line 901, data 982 becomes the value of signal line 902, the output 983 of the second control signal selection circuit 973 becomes the value of signal line 923, and data 984 becomes the value of signal line 924.

[0094] The selection signal generation circuit 951 also outputs a selection signal to cause the first selection circuit to select the first data output by the first processing unit 100 and the second selection circuit to select the second data output by the second processing unit 120 when the third comparison circuit 942 detects a match. Specifically, when the output 941 of the first comparison circuit 931 is 0, the output 943 of the second comparison circuit 933 is 0, and the output 942 of the third comparison circuit 932 is 1, the selection signal generation circuit 951 outputs selection signals 961 and 962 to cause the output 981 of the first control signal selection circuit 971 to be the value of signal line 901, data 982 to be the value of signal line 902, the output 983 of the second control signal selection circuit 973 to be the value of signal line 903, and data 984 to be the value of signal line 904.

[0095] The selection signal generation circuit 951 also outputs selection signals 961 and 962 such that when the output 941 of the first comparison circuit 931 is 0, the output 943 of the second comparison circuit 933 is 0, and the output 942 of the third comparison circuit 932 is 0, the output 981 of the first control signal selection circuit 971 is "not requested" and the output 983 of the second control signal selection circuit 973 is "not requested". In this case, data 982 and data 984 are "don't care".

[0096] Figure 11 is a timing diagram showing an example of the operation of the sequence adjustment circuit 140A in Figure 9. The cycle columns in Figure 11 are numbered to represent each period of the clock signal 261 in Figure 2. Buses 109 and 129, which are inputs to the sequence adjustment circuit 140A in Figure 9, may not output valid values. For example, bus 109 outputs a valid value only when the output circuit 107 in Figure 1 receives information from bus 106. The output circuit 107 receives information from bus 106 only when both signal line 262 (the signal line transmitted by the output of the second request holding circuit 251) and signal line 265 (the signal line transmitted by the input of the first response holding circuit 254) of the synchronization circuit in Figure 2 are 1, and the value of signal line 263 (the signal line transmitted by the output of the control signal memory circuit 252) indicates a data acquisition request to the output circuit 107. In the example in Figure 7, signal lines 262 and 265 both transmit a value of 1 only in the 5th and 13th cycles. Considering the conditions of signal line 263, it can be seen that only a very small number of cycles output a valid value to bus 109. The shaded rows in Figure 11 show cycles in which no valid value is output to either bus 109 or 129, and each row represents multiple cycles.

[0097] In Figure 11, <t1> ~ <t5>(i1) to (i3) are outputs of the interrupting task. Signal line 901 has <t3>and <t4>While (i1)~(i3) are output between them, signal line 903 has <t2>and <t3>(i1) to (i3) are output between them, and their order is different.

[0098] In cycles a, b, f, g, and h, the output 941 of the first comparator circuit 931 (the signal transmitted on signal line 941) is 1, so the value of signal line 921 is output to signal line 981 and the value of signal line 903 is output to signal line 983.

[0099] In cycles c, d, and e, the output 942 of the third comparator circuit 932 (the signal transmitted on signal line 942) is 1, so the value of signal line 901 is output to signal line 981 and the value of signal line 903 is output to signal line 983.

[0100] As described above, according to this disclosure, by using the outputs of the first comparison circuit 931, the second comparison circuit 933, and the third comparison circuit 932 to detect the corresponding outputs of the first processing unit 100 and the second processing unit 120, and by selecting the corresponding outputs with the first selection circuit (first control signal selection circuit 971 and first data selection circuit 972) and the second selection circuit (second control signal selection circuit 973 and second data selection circuit 974), the order of the outputs of the first processing unit 100 and the second processing unit 120 can be made identical. As a result, the order and output cycles of the control signals output to signal line 981 and signal line 983 match, making accurate matching possible.

[0101] Note that in Figure 11, there is no cycle in which the output 943 of the second comparator circuit 933 is 1. This is because the operation of signal line 901 precedes that of signal line 903. In the case where the values ​​of signal line 901 and signal line 903 are reversed, the output 943 of the second comparator circuit 943 becomes 1 instead of the output 941 of the first comparator circuit 931.

[0102] [Example 2] Figure 12 is a block diagram showing a second example of the sequence adjustment circuit 140 in the control device of Figure 1. The operation of the components with the same reference numerals as in Figure 9 is the same as in Figure 9. The difference between the sequence adjustment circuit 140A in Figure 9 and the sequence adjustment circuit 140B in Figure 12 is that the first comparison circuit 1231, the second comparison circuit 1233, and the third comparison circuit 1232 compare data instead of control signals.

[0103] The first comparison circuit 1231 compares the first data stored in and output by the first memory circuit with the second data output by the second processing unit 120. Specifically, the first comparison circuit 1231 compares the data on signal line 922 with the data on signal line 904, outputting 1 to signal line 941 if they match, and 0 if they do not match.

[0104] The second comparison circuit 1233 compares the second data stored in and output by the second memory circuit with the first data output by the first processing unit 100. Specifically, the second comparison circuit 1233 compares the data on signal line 924 with the data on signal line 902, outputting 1 to signal line 943 if they match, and 0 if they do not match.

[0105] The third comparison circuit 1232 compares the first data output by the first processing unit 100 with the second data output by the second processing unit 120. Specifically, the third comparison circuit 1232 compares the data on signal line 902 with the data on signal line 904, outputting 1 to signal line 942 if they match, and 0 if they do not match.

[0106] By comparing data rather than control signals, the physical components of the first, second, and third comparison circuits can be reduced from those shown in Figure 9 when the data requires fewer signal lines than the control signals.

[0107] The operation of the sequence adjustment circuit 140B in Figure 12 is the same as the operation of the sequence adjustment circuit 140A shown in Figures 10 and 11.

[0108] [Example 3] Figure 13 is a block diagram showing a third example of the sequence adjustment circuit 140 in the control device of Figure 1. The operation of the components with the same reference numerals as in Figure 9 is the same as in Figure 9. The difference between the sequence adjustment circuit 140A in Figure 9 and the sequence adjustment circuit 140C in Figure 13 is the addition of a third control signal memory circuit 1311, a third data memory circuit 1312, a fourth control signal memory circuit 1313, a fourth data memory circuit 1314, a fourth comparison circuit 1331, and a fifth comparison circuit 1333. Consequently, the configurations of the selection signal generation circuit 1351, the first control signal selection circuit 1371, the first data selection circuit 1372, the second control signal selection circuit 1373, and the second data selection circuit 1374 also differ from those in Figure 9.

[0109] The third memory circuit stores the first control signal and the first data output by the first memory circuit. Specifically, the third memory circuit can be configured to include a third control signal memory circuit 1311 and a third data memory circuit 1312.

[0110] The third control signal storage circuit 1311 stores the value of signal line 921 when there is a request for signal line 901, the control signal for signal line 901 or signal line 921 has not been selected by the first control signal selection circuit 1371, and a valid control signal is stored in the first control signal storage circuit 911.

[0111] The third data storage circuit 1312 stores the value of signal line 922 when there is a request on signal line 901, the control signal for signal line 901 or signal line 921 has not been selected by the first control signal selection circuit 1371, and a valid control signal is stored in the first control signal storage circuit 911.

[0112] The fourth memory circuit stores the second control signal and the second data output by the second memory circuit. Specifically, the fourth memory circuit can be configured to include a fourth control signal memory circuit 1313 and a fourth data memory circuit 1314.

[0113] The fourth control signal memory circuit 1313 stores the value of signal line 923 when there is a request for signal line 903, the control signal for signal line 903 or signal line 923 has not been selected by the second control signal selection circuit 1373, and a valid control signal is stored in the second control signal memory circuit 913.

[0114] The fourth data storage circuit 1314 stores the value of signal line 924 when there is a request on signal line 903, the control signal for signal line 903 or signal line 923 is not selected by the second control signal selection circuit 1373, and a valid control signal is stored in the second control signal storage circuit 913.

[0115] The fourth comparison circuit 1331 compares the first control signal stored in the third memory circuit and output by the third memory device with the second control signal output by the second processing unit 120. Specifically, the fourth comparison circuit 1331 compares the control signal on signal line 1321 with the control signal on signal line 903, outputting 1 to signal line 1341 if they match, and 0 if they do not match.

[0116] The fifth comparison circuit 1333 compares the second control signal stored in the fourth memory circuit and output by the fourth memory circuit with the first control signal output by the first processing unit 100. Specifically, the fifth comparison circuit 1333 compares the control signal on signal line 1323 with the control signal on signal line 901, outputting 1 to signal line 1343 if they match, and 0 if they do not match.

[0117] The selection signal generation circuit 1351 generates selection signals for the first and second selection circuits from the comparison results output by the first comparison circuit 931, the second comparison circuit 933, the third comparison circuit 932, the fourth comparison circuit 1331, and the fifth comparison circuit 1333. Specifically, the selection signal generation circuit 1351 takes the comparison results from signal lines 941, 943, 942, 1341, and 1343 and outputs selection signals 1361 and 1362 according to predetermined rules. The rules for determining the output will be described later.

[0118] The first control signal selection circuit 1371 selects one of the control signals for signal line 901, signal line 921, or signal line 1321 according to the selection signal 1361, and outputs it to signal line 981.

[0119] The first data selection circuit 1372 selects either the data from signal line 902, the data from signal line 922, or the data from signal line 1322 according to the selection signal 1361, and outputs it to signal line 982.

[0120] The second control signal selection circuit 1373 selects one of the control signals for signal line 903, signal line 923, or signal line 1323 according to the selection signal 1362, and outputs it to signal line 983.

[0121] The second data selection circuit 1374 selects one of the data from signal line 904, signal line 924, or signal line 1324 according to the selection signal 1362, and outputs it to signal line 984.

[0122] Figure 14 is a table showing an example of the operation of the selection signal generation circuit 1351 in the sequence adjustment circuit 140C of Figure 13. Figure 14 shows the output of the control signal, but the data output is similar.

[0123] The selection signal generation circuit 1351 outputs a selection signal such that, when the fourth comparison circuit 1331 detects a match, the first selection circuit selects the first data output by the third memory circuit, and the second selection circuit selects the second data output by the second processing unit 120. Specifically, when the output 1341 of the fourth comparison circuit 1331 is 1, the selection signal generation circuit 1351 outputs selection signals 1361 and 1362 such that the output 981 of the first control signal selection circuit 1371 becomes the value of signal line 1321, and the output 983 of the second control signal selection circuit 1373 becomes the value of signal line 903.

[0124] The selection signal generation circuit 1351 also outputs a selection signal such that, when the first comparison circuit 931 detects a match, the first selection circuit selects the first data output by the first memory circuit, and the second selection circuit selects the second data output by the second processing unit 120. Specifically, when the output 1341 of the fourth comparison circuit 1331 is 0 and the output of the first comparison circuit 931 is 1, the selection signal generation circuit 1351 outputs selection signals 1361 and 1362 such that the output 981 of the first control signal selection circuit 1371 becomes the value of signal line 921, and the output 983 of the second control signal selection circuit 1373 becomes the value of signal line 903.

[0125] The selection signal generation circuit 1351 also outputs a selection signal to cause the first selection circuit to select the first data output by the first processing unit 100 and the second selection circuit to select the second data output by the fourth memory circuit when the fifth comparison circuit 1333 detects a match. Specifically, when the output 1341 of the fourth comparison circuit 1331 is 0, the output of the first comparison circuit 931 is 0, and the output of the fifth comparison circuit 1333 is 1, the selection signal generation circuit 1351 outputs selection signals 1361 and 1362 such that the output 981 of the first control signal selection circuit 1371 becomes the value of signal line 901 and the output 983 of the second control signal selection circuit 1373 becomes the value of signal line 1323.

[0126] The selection signal generation circuit 1351 also outputs a selection signal when the second comparison circuit 933 detects a match, such that the first selection circuit selects the first data output by the first processing unit 100, and the second selection circuit selects the data output by the second memory circuit. Specifically, when the output 1341 of the fourth comparison circuit 1331 is 0, the output of the first comparison circuit 931 is 0, the output of the fifth comparison circuit 1333 is 0, and the output of the second comparison circuit 933 is 1, the selection signal generation circuit 1351 outputs selection signal 1361 and selection signal 1362 such that the output 981 of the first control signal selection circuit 1371 becomes the value of signal line 901, and the output 983 of the second control signal selection circuit 1373 becomes the value of signal line 923.

[0127] The selection signal generation circuit 1351 also outputs a selection signal to cause the first selection circuit to select the first data output by the first processing unit, and the second selection circuit to select the second data output by the second processing unit, when the third comparison circuit 932 detects a match. Specifically, when the output 1341 of the fourth comparison circuit 1331 is 0, the output of the first comparison circuit 931 is 0, the output of the fifth comparison circuit 1333 is 0, the output of the second comparison circuit 933 is 0, and the output of the third comparison circuit 932 is 1, the selection signal generation circuit 1351 outputs selection signals 1361 and 1362 such that the output 981 of the first control signal selection circuit 1371 becomes the value of signal line 901, and the output 983 of the second control signal selection circuit 1373 becomes the value of signal line 903.

[0128] The selection signal generation circuit 1351 also outputs selection signals 1361 and 1362 such that when the output 1341 of the fourth comparator circuit 1331 is 0, the output of the first comparator circuit 931 is 0, the output of the fifth comparator circuit 1333 is 0, the output of the second comparator circuit 933 is 0, and the output of the third comparator circuit 932 is 0, the output 981 of the first control signal selection circuit 1371 is not requested and the output 983 of the second control signal selection circuit 1373 is not requested.

[0129] Figure 15 is a timing diagram showing an example of the operation of the sequence adjustment circuit 140C in Figure 13. The meaning of the shaded rows is the same as in Figure 11. As shown in Figure 11, when the difference in operation between signal line 901 and signal line 903 is small, the operation of the sequence adjustment circuit 140C is the same as in Figure 11. On the other hand, the sequence adjustment circuit 140B in Figure 9 only has a memory circuit that holds one value for each of signal line 901 and signal line 903, so it could not handle cases where the difference between signal line 901 and signal line 903 was large. For example, as shown in Figure 15, if signal line 903 <t1>Before the output is sent to signal line 901 <t1>and <t2>When these two values ​​are output, the sequence adjustment circuit 140B in Figure 9 cannot handle it. On the other hand, in the sequence adjustment circuit 140C in Figure 13, there is a memory circuit that holds two values ​​for each of the signal lines 901 and 903, so the output on signal line 901 <t1>and <t2>It is possible to remember both.

[0130] In cycles b, c, g, and h, the output 1341 of the fourth comparator circuit 1331 is 1, so the value of signal line 1321 is output to signal line 981 and the value of signal line 903 is output to signal line 983.

[0131] In cycles d, e, and f, the output 942 of the third comparator circuit 932 is 1, so the value of signal line 901 is output to signal line 981 and the value of signal line 903 is output to signal line 983.

[0132] In cycle i, the output 941 of the first comparator circuit 931 is 1, so the value of signal line 921 is output to signal line 981 and the value of signal line 903 is output to signal line 983.

[0133] As a result, the order and cycle of the control signals output to signal line 981 and signal line 983 match, making accurate matching possible.

[0134] Note that in Figure 15, there is no cycle in which the output 1343 of the fifth comparator circuit 1333 is 1. This is because the operation of signal line 901 precedes that of signal line 903. In the case where the values ​​of signal line 901 and signal line 903 are reversed, the output 1343 of the fifth comparator circuit 1333 becomes 1 instead of the output 1341 of the fourth comparator circuit 1331.

[0135] [Other examples] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention. For example, the sequence adjustment circuit 140B of Example 2 and the sequence adjustment circuit 140C shown in Example 3 may be combined to create a configuration in which the fourth comparison circuit and the fifth comparison circuit compare data instead of control signals.

[0136] The comparison circuit configuration is as follows: The first comparison circuit compares the first data stored in and output by the first memory circuit with the second data output by the second processing unit 120. The second comparison circuit compares the second data stored in and output by the second memory circuit with the first data output by the first processing unit 100. The third comparison circuit compares the first data output by the first processing unit 100 with the second data output by the second processing unit 120.

[0137] Furthermore, the fourth comparison circuit compares the first data stored in the third memory circuit and output by the third memory device with the second data output by the second processing device. The fifth comparison circuit compares the second data stored in the fourth memory circuit and output by the fourth memory circuit with the first data output by the first processing device. [Explanation of Symbols]

[0138] 10 Control device 100 First processing unit Buses 102, 104-106, 109, 110, 122, 126, 129, 130, 141, 142, 161 103 Synchronization circuit 120 Second processing unit 140 Sequence adjustment circuit 150 Verification Circuits Signal lines 201-205, 221, 222, 241, 242, 243, 244, 261-265, 901-904, 921-924, 941-943, 961, 962, 981-984, 1321-1324, 1341, 1343, 1361, 1362 911 First control signal memory circuit 912 First data storage circuit 913 Second control signal memory circuit 914 Second data storage circuit 931 First comparison circuit 932 Third comparison circuit 933 Second comparison circuit 951 Selection signal generation circuit 971, 1371 First control signal selection circuit 972, 1372 First data selection circuit 973, 1373 Second control signal selection circuit 974, 1374 Second data selection circuit 1231 First comparison circuit 1232 Third comparison circuit, 1233 Second comparison circuit 1311 Third control signal memory circuit 1312 Third data storage circuit 1313 Fourth control signal memory circuit 1314 Fourth data storage circuit 1331 Fourth comparison circuit 1333 Fifth comparison circuit 1351 Selection signal generation circuit < / t1>

Claims

1. A first processing unit that outputs a first control signal and first data, A second processing unit that outputs a second control signal and a second data, A first storage circuit that stores the first control signal output by the first processing unit and the first data, A second storage circuit that stores the second control signal output by the second processing unit and the second data, A first comparison circuit that compares a first control signal stored in the first memory circuit and output by the first memory circuit with a second control signal output by the second processing unit, or compares a first data stored in the first memory circuit and output by the first memory circuit with a second data output by the second processing unit, A second comparison circuit that compares the second control signal stored in the second memory circuit and output by the second memory circuit with the first control signal output by the first processing unit, or compares the second data stored in the second memory circuit and output by the second memory circuit with the first data output by the first processing unit, A third comparison circuit that compares the first control signal output by the first processing unit with the second control signal output by the second processing unit, or compares the first data output by the first processing unit with the second data output by the second processing unit, A first selection circuit that selects data to compare from the first data output by the first processing unit and the first data output by the first storage circuit, A second selection circuit that selects data to compare from the second data output by the second processing unit and the second data output by the second storage circuit, A selection signal generation circuit that generates selection signals for the first selection circuit and the second selection circuit from the comparison results output by the first comparison circuit, the second comparison circuit and the third comparison circuit, A comparison circuit that compares the data selected by the first selection circuit with the data selected by the second selection circuit, A control device characterized by having the following features.

2. In the control device according to claim 1, The first comparison circuit compares the first control signal output by the first memory circuit with the second control signal output by the second processing unit. The second comparison circuit compares the second control signal output by the second memory circuit with the first control signal output by the first processing unit. The third comparison circuit compares the first control signal output by the first processing unit with the second control signal output by the second processing unit. A control device characterized by the following.

3. In the control device according to claim 1, The first comparison circuit compares the first data output by the first memory circuit with the second data output by the second processing unit. The second comparison circuit compares the second data output by the second memory circuit with the first data output by the first processing unit. The third comparison circuit compares the first data output by the first processing unit with the second data output by the second processing unit. A control device characterized by the following.

4. In the control device according to claim 1, The selection signal generation circuit, when the first comparison circuit detects a match, The first selection circuit selects the first data output by the first memory circuit, and The selection signal is output to the second selection circuit so that it selects the second data output by the second processing unit. The selection signal generation circuit also, when the second comparison circuit detects a match, The first selection circuit selects the first data output by the first processing unit, and The second selection circuit outputs the selection signal so as to select the second data output by the second memory circuit. The selection signal generation circuit also, when the third comparison circuit detects a match, The first selection circuit selects the first data output by the first processing unit, and The second selection circuit outputs the selection signal so as to select the second data output by the second processing unit. A control device characterized by the following.

5. In the control device according to claim 1, A third memory circuit that stores the first control signal output by the first memory circuit and the first data, A fourth memory circuit that stores the second control signal output by the second memory circuit and the second data, A fourth comparison circuit that compares the first control signal stored in the third memory circuit and output by the third memory circuit with the second control signal output by the second processing unit, or compares the first data stored in the third memory circuit and output by the third memory circuit with the second data output by the second processing unit, The system includes a fifth comparison circuit that compares the second control signal stored in the fourth memory circuit and output by the fourth memory circuit with the first control signal output by the first processing unit, or compares the second data stored in the fourth memory circuit and output by the fourth memory circuit with the first data output by the first processing unit. The selection signal generation circuit generates selection signals for the first and second selection circuits from the comparison results output by the first, second, third, fourth, and fifth comparison circuits. A control device characterized by the following.

6. In the control device according to claim 5, The selection signal generation circuit, when the fourth comparison circuit detects a match, The first selection circuit is made to select the first data output by the third memory circuit, and The second selection circuit outputs the selection signal to cause the second data output by the second processing unit to be selected. The selection signal generation circuit also, when the first comparison circuit detects a match, The first selection circuit selects the first data output by the first memory circuit, and The second selection circuit outputs the selection signal to cause the second data output by the second processing unit to be selected. The selection signal generation circuit also, when the fifth comparison circuit detects a match, The first selection circuit selects the first data output by the first processing unit, and The second selection circuit outputs the selection signal so that it selects the second data output by the fourth memory circuit. The selection signal generation circuit also, when the second comparison circuit detects a match, The first selection circuit selects the first data output by the first processing unit, and The second selection circuit outputs the selection signal so that it selects the data output by the second memory circuit, and The selection signal generation circuit also, when the third comparison circuit detects a match, The first selection circuit selects the first data output by the first processing unit, and The second selection circuit outputs the selection signal so as to select the second data output by the second processing unit. A control device characterized by the following.

Images