Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor that can suppress a decrease in strength against external stress even when the thickness is reduced. A multilayer ceramic capacitor 1 comprises: a multilayer body 10 in which a plurality of dielectric layers 20 formed from a ceramic material and a plurality of internal electrode layers 30 are layered; a plurality of external electrodes 40 disposed on at least a second main surface TS2 of the multilayer body 10; and a stress suppression film 50 that suppresses stress applied to the multilayer body 10 and the plurality of external electrodes 40. The stress suppression film 50 is formed from an insulating material and extends along a first main surface TS1 and two end surfaces LS1, LS2 or along the first main surface TS1 and two side surfaces to cover the multilayer body 10 and the plurality of external electrodes 40. The ends of the stress suppression film 50 protrude with respect to the outermost surfaces of the plurality of external electrodes 40 on the second main surface TS2 side.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] A multilayer ceramic capacitor including a laminate in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, and an external electrode disposed on an end face or a side face of the laminate is known. In such a multilayer ceramic capacitor, further miniaturization and thinning are required (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a multilayer ceramic capacitor is thinned, the strength of the laminate, particularly the ceramic layer, decreases, and the multilayer ceramic capacitor may be damaged by the stress from a mounter during mounting. For example, cracks may occur in the ceramic layer of the laminate. If the cracks occurring in the ceramic layer progress to the internal electrode layer, for example, moisture may penetrate into the cracks, and the insulation of the multilayer ceramic capacitor may decrease.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress a decrease in strength against external stress even when thinned.

Means for Solving the Problems

[0006] The multilayer ceramic capacitor according to the present invention is a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of a ceramic material are laminated, the laminate having a first main surface and a second main surface facing each other in the lamination direction, two side surfaces facing each other in the width direction intersecting the lamination direction, and two end surfaces facing each other in the length direction intersecting the lamination direction and the width direction, a plurality of external electrodes disposed on at least the second main surface of the laminate, and a stress-suppressing film for suppressing stress on the laminate and the plurality of external electrodes. The stress-suppressing film is made of an insulating material and extends along the first main surface and the two end surfaces, or along the first main surface and the two side surfaces, so as to cover the laminate and the plurality of external electrodes. The ends of the stress-suppressing film protrude beyond the outermost surface of the plurality of external electrodes on the second main surface side. [Effects of the Invention]

[0007] According to the present invention, even when a multilayer ceramic capacitor is made thinner, a decrease in strength against external stress can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a multilayer ceramic capacitor according to this embodiment. [Figure 2] Figure 1 shows a cross-sectional view (LT section) of a multilayer ceramic capacitor along line II-II. [Figure 3] Figure 1 shows a cross-sectional view (WT section) of a multilayer ceramic capacitor along line III-III. [Figure 4] This is a perspective view showing a modified multilayer ceramic capacitor according to this embodiment. [Figure 5] Figure 4 shows a cross-sectional view of the multilayer ceramic capacitor along the VV line (LT section). [Figure 6] Figure 4 shows a cross-sectional view (WT cross-section) of a multilayer ceramic capacitor along the line VI-VI. [Figure 7]This is a perspective view showing a modified multilayer ceramic capacitor according to this embodiment. [Figure 8] Figure 7 shows a cross-sectional view (LT section) of the multilayer ceramic capacitor shown along line VIII-VIII. [Figure 9] Figure 7 shows a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor along the line IX-IX. [Figure 10] This is a perspective view showing a modified multilayer ceramic capacitor according to this embodiment. [Figure 11] This is a perspective view showing a modified multilayer ceramic capacitor according to this embodiment. [Figure 12] This is a perspective view showing a modified multilayer ceramic capacitor according to this embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, an example of an embodiment of the present invention will be described with reference to the attached drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0010] <Multilayer ceramic capacitor> Figure 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line II-II, and Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line III-III. The multilayer ceramic capacitor 1 shown in Figures 1 to 3 comprises a laminate 10, external electrodes 40, and a stress-suppressing film 50. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0011] Figures 1 to 3 and the drawings described later show the XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10. Accordingly, the cross section shown in Figure 2 is also called the LT cross section, and the cross section shown in Figure 3 is also called the WT cross section.

[0012] Note that the length direction L, the width direction W, and the stacking direction T do not necessarily have a mutually orthogonal relationship, and may have a mutually intersecting relationship.

[0013] The laminate 10 has a substantially rectangular parallelepiped shape, and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L.

[0014] It is preferable that the corners and ridge lines of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge line portion is a portion where two surfaces of the laminate 10 intersect.

[0015] As shown in FIGS. 2 and 3, the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T. Further, the laminate 10 has an inner layer portion 100 and a first outer layer portion 101 and a second outer layer portion 10 that are arranged so as to sandwich the inner layer portion 100 in the stacking direction T. the second outer layer portion 102

[0016] The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other through the dielectric layers 20. The inner layer portion 100 is a portion that generates capacitance and functions substantially as a capacitor.

[0017] The first outer layer 101 is located on the side of the first main surface TS1 of the laminate 10, and the second outer layer 102 is located on the side of the second main surface TS2 of the laminate 10. More specifically, the first outer layer 101 is located between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1, and the second outer layer 102 is located between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2. The first outer layer 101 and the second outer layer 102 do not include the internal electrode layers 30, but each includes portions of the dielectric layers 20 other than those for the inner layer 100. The first outer layer 101 and the second outer layer 102 function as protective layers for the inner layer 100.

[0018] As the material for the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the main component can be used. In addition, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds may be added as minor components to the material for the dielectric layer 20. More specifically, the dielectric layer 20 includes a plurality of dielectric grains. The dielectric grains are barium titanate-based ceramics such as perovskite-type compounds containing Ba and Ti. The dielectric grains may also contain at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y as minor components.

[0019] The thickness of the dielectric layer 20 is not particularly limited, but may be, for example, 0.30 μm or more and 5.0 μm or less. The number of dielectric layers 20 is not particularly limited, but may be, for example, 5 or more and 2000 or less. Note that this number of dielectric layers 20 is the total number of dielectric layers in the inner layer and the dielectric layers in the outer layer.

[0020] As shown in Figures 2 and 3, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0021] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

[0022] The opposing electrode portion 311 and the opposing electrode portion 321 face each other via the dielectric layer 20 in the stacking direction T of the laminate 10. The shape of the opposing electrode portion 311 and the opposing electrode portion 321 is not particularly limited and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions (effective regions) that generate capacitance and function substantially as capacitors.

[0023] The leading electrode portion 312 extends from the opposing electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The leading electrode portion 322 extends from the opposing electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The shape of the leading electrode portions 312 and 322 is not particularly limited and may be, for example, substantially rectangular.

[0024] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap exists between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. Also, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap exists between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 mainly contain metallic Ni. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also mainly contain at least one of the following metals, such as Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy, or may contain other components. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 20, as components other than the main component. In this specification, the main component metal is defined as the metal component with the highest weight percentage.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but may be, for example, 0.30 μm or more and 1.0 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but may be, for example, 5 or more and 2000 or less.

[0027] As shown in Figure 3, the laminate 10 has, in the width direction W, an electrode-facing portion W30 on which the internal electrode layer 30 faces, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode-facing portion W30. The first side gap portion WG1 is located between the electrode-facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode-facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but include only the dielectric layer 20. The first side gap WG1 and the second side gap WG2 function as protective layers for the internal electrode layer 30. The first side gap WG1 and the second side gap WG2 are also referred to as the W gap.

[0028] As shown in Figure 2, the laminate 10 has, in the longitudinal direction L, an electrode-facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode-facing portion L30 and the first end face LS1, and the second end gap portion LG2 is located between the electrode-facing portion L30 and the second end face LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap portion LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap portion LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap portion LG1 functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap portion LG2 functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap portion LG1 and the second end gap portion LG2 are also called L gaps.

[0029] The electrode opposing portion L30 contains the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The leading electrode portion 312 of the first internal electrode layer 31 is located in the first end gap portion LG1, and the leading electrode portion 322 of the second internal electrode layer 32 is located in the second end gap portion LG2.

[0030] The dimensions of the laminate 10 described above are not particularly limited, but for example, the length in the longitudinal direction L may be 0.05 mm or more and 1.00 mm or less, the width in the width direction W may be 0.10 mm or more and 0.50 mm or less, and the thickness in the lamination direction T may be 0.10 mm or more and 0.50 mm or less. Furthermore, the dimensions of the multilayer ceramic capacitor 1, including the external electrodes 40 described later, are not particularly limited, but for example, the length in the longitudinal direction L may be 0.05 mm or more and 1.00 mm or less, the width in the width direction W may be 0.10 mm or more and 0.50 mm or less, and the thickness in the stacking direction T may be 0.10 mm or more and 0.50 mm or less.

[0031] Furthermore, a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30 is, for example, to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction, or further, the average of measurements taken at multiple locations in the stacking direction.

[0032] Similarly, a method for measuring the thickness of the laminate 10 or the multilayer ceramic capacitor 1 includes, for example, observing the LT cross-section near the center in the width direction of the laminate exposed by polishing, or the WT cross-section near the center in the length direction of the laminate or multilayer ceramic capacitor exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the length or width direction. Similarly, a method for measuring the length of the laminate 10 or the length of the multilayer ceramic capacitor 1 is, for example, to observe the LT cross-section near the center in the width direction of the laminate or multilayer ceramic capacitor, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the stacking direction. Similarly, a method for measuring the width of the laminate 10 or the multilayer ceramic capacitor 1 includes, for example, observing the WT cross-section near the center in the longitudinal direction of the laminate or multilayer ceramic capacitor, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction.

[0033] The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0034] The first external electrode 41 is positioned on at least the second main surface TS2 of the laminate 10, specifically on a portion of the second main surface TS2 on the side of the first end face LS1. In the examples of Figures 1 to 3, the first external electrode 41 is also positioned on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. That is, the first external electrode 41 is L-shaped in the LT cross-section and is positioned on a portion of the second main surface TS2 of the laminate 10 on the side of the first end face LS1 and along the first end face LS1. In the examples of Figures 1 to 3, the first external electrode 41 is not positioned on the first main surface TS1 or the two side surfaces WS1 and WS2.

[0035] The second external electrode 42 is positioned on at least the second main surface TS2 of the laminate 10, specifically on a portion of the second end face LS2 side of the second main surface TS2. In the examples of Figures 1 to 3, the second external electrode 42 is also positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. That is, the second external electrode 42 is L-shaped and is positioned on a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10 and along the second end face LS2. In the examples of Figures 1 to 3, the second external electrode 42 is not positioned on the first main surface TS1 or the two side surfaces WS1 and WS2.

[0036] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may consist only of the first plating layer 416, and the second external electrode 42 may consist only of the second plating layer 426.

[0037] The first and second base electrode layers 415 and 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. The metal may also mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0038] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0039] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the above-described firing layer, or they may be formed directly on the laminate without forming a firing layer.

[0040] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, the resin layer may consist of multiple layers.

[0041] The thickness of each layer of the first base electrode layer 415 and the second base electrode layer 425, which are fired layers or resin layers, is not particularly limited and may be 1 μm or more and 10 μm or less.

[0042] Alternatively, the first underlay electrode layer 415 and the second underlay electrode layer 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, with metal particles deposited on them.

[0043] The first plating layer 416 covers at least a portion of the first underlay electrode layer 415, and the second plating layer 426 covers at least a portion of the second underlay electrode layer 425. The first plating layer 416 and the second plating layer 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0044] Each of the first plating layer 416 and the second plating layer 426 may be formed from multiple layers. Preferably, it is a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier.

[0045] The thickness of each layer of the first plating layer 416 and the second plating layer 426 is not particularly limited and may be 1 μm or more and 10 μm or less.

[0046] <<Stress-suppressing film>> The stress-suppressing film 50 suppresses the stress applied to the laminate 10 and the external electrode 40. The stress-suppressing film 50 extends along the first main surface (top surface) TS1 and two end faces LS1, LS2, and also along the first main surface TS1 and two side faces WS1, WS2, so as to cover the laminate 10 and the external electrode 40.

[0047] The edge of the stress-suppressing film 50 protrudes by D1 from the outermost surface (the surface located closest to the bottom) of the external electrode 40 on the second main surface (bottom surface, mounting surface) TS2 side. The protrusion dimension D1 of the edge of the stress-suppressing film 50 should be between 5 μm and 10 μm. A stress-suppressing effect is obtained when D1 is 5 μm or more, and connectivity between the external electrode 40 and the paste solder is obtained when D1 is 10 μm or less.

[0048] In the stress-suppressing film 50, the film thickness Da of the main surface portion (first portion) along the first main surface TS1 and the film thickness Db of the side portion (second portion) along the two end faces LS1, LS2 and the two side surfaces WS1, WS2 satisfy the following relationship. 0.8Da≧Db The film thickness Da of the main surface portion (first portion) should be between 4.5 μm and 5.5 μm.

[0049] If the film thickness Da of the main surface portion (first portion) is relatively thick, the main surface portion of the stress-suppressing film 50 that is aligned with the first main surface TS1 can receive the suction force applied to the first main surface TS1, which is the upper surface, when adsorbed by the mounter, thereby suppressing the suction force applied to the laminate 10. On the other hand, if the film thickness Db of the side portion (second portion) is relatively thin, the solder pads on the mounting substrate can be made smaller, enabling high-density mounting.

[0050] The stress-suppressing film 50 is made of an insulating material. This prevents short circuits of the external electrodes 40.

[0051] Preferably, the strength of the stress-suppressing film 50 is higher than the strength of the multiple dielectric layers 20 of the laminate 10. Specifically, in terms of resistance to stress during mounting using a mounter, it is preferable that the strength of the stress-suppressing film 50 is higher than the strength of the multiple dielectric layers 20 of the laminate 10. For example, the Young's modulus of the stress-suppressing film 50 is preferably 400 GPa or more and 1500 GPa or less.

[0052] From the viewpoint of insulation and strength, suitable materials for the stress-suppressing film 50 include diamond-like carbon or glass. Among these, diamond-like carbon is preferred as the material for the stress-suppressing film 50.

[0053] <Manufacturing method> Next, the manufacturing method of the multilayer ceramic capacitor 1 described above will be explained. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and conductive paste contain a binder and a solvent. Known materials can be used as the binder and solvent.

[0054] Next, an internal electrode pattern is formed on the dielectric sheet by printing a conductive paste onto the dielectric sheet, for example, in a predetermined pattern. Screen printing or gravure printing can be used as methods for forming the internal electrode pattern.

[0055] Next, a predetermined number of dielectric sheets for the second outer layer 102, which do not have the internal electrode pattern printed on them, are stacked. On top of that, dielectric sheets for the inner layer 100, which have the internal electrode pattern printed on them, are stacked sequentially. On top of that, a predetermined number of dielectric sheets for the first outer layer 101, which do not have the internal electrode pattern printed on them, are stacked. This completes the production of the laminated sheet.

[0056] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block. Then, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, dielectric sheets for the first side margin W11 and the second side margin W12 may be attached to the side surface of the laminated chip. Also, at this time, the corners and edges of the laminated chip are rounded by barrel polishing or the like. Next, the laminated chips are fired to produce a laminated body 10. The firing temperature depends on the dielectric and internal electrode materials, but is preferably between 900°C and 1400°C.

[0057] Next, a conductive paste, which is the electrode material for the base electrode layer (for the first base electrode layer 415), is applied to the second main surface TS2 and the first end surface LS1 of the laminate 10 using a coating method. Similarly, a conductive paste, which is the electrode material for the base electrode layer (for the second base electrode layer 425), is applied to the second main surface TS2 and the second end surface LS2 of the laminate 10 using a coating method. Subsequently, the first base electrode layer 415 and the second base electrode layer 425 are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0058] Alternatively, the first and second base electrode layers 415, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0059] Furthermore, in the above description, the base electrode layer was formed and fired after firing the laminated chip, that is, the laminate and the external electrode were fired separately. However, the base electrode layer may be formed and fired before firing the laminated chip, that is, the laminate and the external electrode may be fired simultaneously.

[0060] Subsequently, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42.

[0061] Next, a stress-suppressing film 50 is formed to cover the laminate 10 and the external electrode 40. Methods for forming the stress-suppressing film 50 include PVD (Physical Vapor Deposition) methods such as sputtering, or vapor deposition. At this time, the protrusion dimension D1 of the stress-suppressing film 50 can be adjusted by adjusting the height of the mounting jig. Note that the shape of the protruding portion in Figure 1, and later in Figures 4, 7, and 10-12, may be deformed by the mounting jig. Through the above process, the multilayer ceramic capacitor 1 described above is obtained.

[0062] In conventional multilayer ceramic capacitors that do not have a stress-suppressing film 50, when the multilayer ceramic capacitor is made thinner, the strength of the laminate 10, especially the ceramic layer (dielectric layer 20), decreases, and the multilayer ceramic capacitor may be damaged by stress from the mounter during mounting. For example, when mounting using a mounter, stress is applied to the first main surface TS1, which is the top surface of the multilayer ceramic capacitor, and this causes stress on the external electrodes 40 on the second main surface TS2, which is the bottom surface (mounting surface) of the multilayer ceramic capacitor, which may damage the multilayer ceramic capacitor. For example, cracks may occur in the ceramic layer (dielectric layer 20) of the laminate 10. If the cracks in the ceramic layer (dielectric layer 20) propagate to the internal electrode layer 30, for example, moisture may penetrate the cracks, reducing the insulation properties of the multilayer ceramic capacitor.

[0063] In this regard, according to the multilayer ceramic capacitor 1 of this embodiment, the stress-suppressing film 50 extends along the first main surface (top surface) TS1 and the two end surfaces LS1 and LS2 so as to cover the laminate 10 and the external electrode 40, and also extends along the first main surface (top surface) TS1 and the two side surfaces WS1 and WS2, and the end of the stress-suppressing film 50 protrudes by D1 from the outermost surface (the surface located on the bottom side) of the external electrode 40 on the second main surface (bottom surface, mounting surface) TS2 side. As a result, when mounting using a mounter, the stress applied to the first main surface TS1 side, which is the top surface, can be distributed from the main surface portion of the stress-suppressing film 50 along the first main surface TS1 to the end surface portions along the two end surfaces LS1 and LS2, and to the side surface portions along the two side surfaces WS1 and WS2, and released to the protruding end. This suppresses the stress on the external electrodes 40 and the laminate 10 on the second main surface TS2, which serves as the bottom surface (mounting surface), and prevents cracks from forming in the ceramic layer (dielectric layer 20) of the laminate 10. Thus, with the multilayer ceramic capacitor 1 of this embodiment, even with a thinner design, a decrease in strength against external stress can be suppressed.

[0064] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, the adsorption force applied to the first main surface TS1, which is the upper surface, during adsorption by the mounter can also be received by the main surface portion of the stress suppression film 50 that is aligned with the first main surface TS1. This makes it possible to suppress the adsorption force applied to the laminate 10.

[0065] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, the stress-suppressing film 50 covers the external electrodes 40 on the end faces LS1, LS2 or the side faces WS1, WS2, thereby preventing paste solder from bulging on the end faces LS1, LS2 or the side faces WS1, WS2. This allows for smaller solder pads on the mounting substrate, enabling high-density mounting.

[0066] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, since the external electrodes 40 are not formed on the first main surface TS1 side, the number of layers in the laminate 10 can be increased, and the effective capacitor region can be increased. Also, since the external electrodes 40 are not formed on the two side surfaces WS1 and WS2, the area of ​​the laminate 10 can be increased, and the effective capacitor region can be increased.

[0067] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible. For example, in the embodiments described above, the stress-suppressing film 50 is shown as extending along five surfaces: the first main surface (top surface) TS1, the two end surfaces LS1 and LS2, and the two side surfaces WS1 and WS2. However, the present invention is not limited thereto, and the stress-suppressing film 50 may extend along only three surfaces: the first main surface (top surface) TS1 and the two end surfaces LS1 and LS2. Alternatively, the stress-suppressing film 50 may extend along only three surfaces: the first main surface (top surface) TS1 and the two side surfaces WS1 and WS2.

[0068] Furthermore, in the embodiments described above, an example was given in which two external electrodes 40 are arranged on a portion of the two end faces LS1,LS2 and on the two end faces LS1,LS2 of the second main surface TS2 of the laminate 10. However, in the present invention, the shape, number, and placement of the external electrodes 40 are not limited thereto. For example, the present invention is also applicable to an embodiment in which a plurality of external electrodes 40 are arranged on at least a portion of the second main surface TS2 of the laminate 10. The present invention is also applicable to an embodiment in which a plurality of external electrodes 40 are arranged on at least a portion of the two side surfaces WS1,WS2 of the second main surface TS2. Below, several examples of the shape, number, and placement of the external electrodes 40 are shown.

[0069] (Variation 1) Figure 4 is a perspective view showing a modified example of this embodiment of a multilayer ceramic capacitor, Figure 5 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 4 along line VV, and Figure 6 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 4 along line VI-VI. The multilayer ceramic capacitor 1 shown in Figures 4 to 6 differs from the multilayer ceramic capacitor 1 shown in Figures 1 to 3 in the shape of its external electrodes 40.

[0070] The first external electrode 41 is located only on the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, specifically on a portion of the second main surface TS2 on the side of the first end face LS1. In other words, the first external electrode 41 is not located on the first end face LS1, the first main surface (top surface) TS1, the first side surface WS1, or the second side surface WS2. In this case, for example, the first external electrode 41 and the first internal electrode layer 31 may be connected by one or more vias 35 extending in the stacking direction T on the side of the first end face LS1 of the laminate 10.

[0071] The second external electrode 42 is located only on the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, specifically on a portion of the second end surface LS2 side of the second main surface TS2. In other words, the second external electrode 42 is not located on the second end surface LS2, the first main surface (top surface) TS1, the first side surface WS1, or the second side surface WS2. In this case, for example, the second external electrode 42 and the second internal electrode layer 32 can be connected by one or more vias 35 extending in the stacking direction T on the second end surface LS2 side of the laminate 10.

[0072] The method for forming the vias 35 is not limited, but for example, after the above-mentioned laminated block has been fabricated but before the laminated chip has been cut out, a plurality of holes arranged in the width direction near the edge of the laminated chip may be formed, and the formed holes may be filled with conductive paste.

[0073] (Modification 2) Figure 7 is a perspective view showing a modified example of this embodiment of a multilayer ceramic capacitor, Figure 8 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 7 along line VIII-VIII, and Figure 9 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 7 along line IX-IX. The multilayer ceramic capacitor 1 shown in Figures 7 to 9 differs from the multilayer ceramic capacitor 1 shown in Figures 1 to 3 in the shape of its external electrodes 40.

[0074] The first external electrode 41 is positioned on a portion of the first end face LS1 side and on the first end face LS1 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and is connected to the first internal electrode layer 31. In the examples of Figures 7 to 9, the first external electrode 41 is also positioned on a portion of the first end face LS1 side of the first main surface (top surface) TS1 of the laminate 10, on a portion of the first end face LS1 side of the first side surface WS1 of the laminate 10, and on a portion of the first end face LS1 side of the second side surface WS2 of the laminate 10. That is, the first external electrode 41 has a U-shape (Angular U-shape) in the LT cross section and is positioned along a portion of the first end face LS1 side of the second main surface TS2 of the laminate 10, on the first end face LS1, and on a portion of the first end face LS1 side of the first main surface TS1. Furthermore, the first external electrode 41 has an angular U-shape in the LW cross-section and is positioned along a portion of the first end face LS1 side of the first side surface WS1 of the laminate 10, the first end face LS1, and a portion of the first end face LS1 side of the second side surface WS2.

[0075] The second external electrode 42 is positioned on a portion of the second end face LS2 side and on the second end face LS2 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and is connected to the second internal electrode layer 32. In the examples of Figures 7 to 9, the second external electrode 42 is also positioned on a portion of the second end face LS2 side of the first main surface (top surface) TS1 of the laminate 10, on a portion of the second end face LS2 side of the first side surface WS1 of the laminate 10, and on a portion of the second end face LS2 side of the second side surface WS2 of the laminate 10. That is, the second external electrode 42 has an angular U-shape in the LT cross-section and is positioned along a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10, on the second end face LS2, and on a portion of the second end face LS2 side of the first main surface TS1. Furthermore, the second external electrode 42 has an angular U-shape in the LW cross-section and is positioned along a portion of the second end face LS2 side of the first side surface WS1 of the laminate 10, the second end face LS2, and a portion of the second end face LS2 side of the second side surface WS2.

[0076] In this case, a flat plate-shaped spacer member 55 may be placed in the portion of each of the first main surface TS1 and the second main surface TS2 where the multiple external electrodes 40 are not placed. In this case, the stress suppression film 50 only needs to extend on the first main surface TS1 so as to further cover the spacer member 55. This makes it possible to suppress the step difference between the portion of the first main surface TS1, which is the upper surface, where the external electrodes 40 are placed and the portion where the external electrodes 40 are not placed, thereby improving the adsorption performance by the mounter. In the form before the stress suppression film 50 is formed, there is no distinction between the upper and lower surfaces, so it is preferable to place the spacer member 55 on both the first main surface TS1 and the second main surface TS2.

[0077] (Variation 3) Figure 10 is a perspective view showing a modified example of a multilayer ceramic capacitor according to this embodiment. The multilayer ceramic capacitor 1 shown in Figure 10 differs from the multilayer ceramic capacitor 1 shown in Figures 7 to 9 in the number of external electrodes 40.

[0078] For example, in the multilayer ceramic capacitor 1 shown in Figures 7 to 9, the external electrodes 40 include a third external electrode 43 and a fourth external electrode 44, in addition to the first external electrode 41 and the second external electrode 42. Thus, the multilayer ceramic capacitor 1 includes a third external electrode 43 and a fourth external electrode 44, in addition to the first external electrode 41 and the second external electrode 42, and is therefore referred to as a three-terminal multilayer ceramic capacitor. The features of the present invention are also applicable to such three-terminal multilayer ceramic capacitors.

[0079] The third external electrode 43 is positioned between the first external electrode 41 and the second external electrode 42, on a portion of the first side surface WS1 side and on the first side surface WS1 on the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In the example of Figure 10, the third external electrode 43 is also positioned on a portion of the first side surface WS1 side of the first main surface (top surface) TS1 of the laminate 10. That is, the third external electrode 43 has a U-shape (Angular U-shape) in the WT cross section and is positioned along a portion of the first side surface WS1 side, the first side surface WS1, and a portion of the first side surface WS1 side of the second main surface TS2 of the laminate 10.

[0080] The fourth external electrode 44 is positioned between the first external electrode 41 and the second external electrode 42, on a portion of the second side surface WS2 side and on the second side surface WS2 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In the example of Figure 10, the fourth external electrode 44 is also positioned on a portion of the second side surface WS2 side of the first main surface (top surface) TS1 of the laminate 10. That is, the fourth external electrode 44 has a U-shape (Angular U-shape) in the WT cross section and is positioned along a portion of the second side surface WS2 side, the second side surface WS2, and a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10.

[0081] In the multilayer ceramic capacitor 1 shown in Figure 10, as in the multilayer ceramic capacitors 1 shown in Figures 7 to 9, a flat plate-shaped spacer member 55 may be placed in the portion of each of the first main surface TS1 and the second main surface TS2 where the multiple external electrodes 40 are not arranged. In this case, the stress-suppressing film 50 only needs to extend on the first main surface TS1 so as to cover the spacer member 55.

[0082] In Figure 10, an external electrode 40 with an angular U-shape cross-section is shown as an example. However, the features of the present invention are not limited to this, and the multilayer ceramic capacitor 1 shown in Figure 10 can also be applied to a multilayer ceramic capacitor 1 having an L-shaped cross-section external electrode 40, similar to the multilayer ceramic capacitor 1 shown in Figures 1 to 3. In this case, the third external electrode 43 is L-shaped in the WT cross-section and is arranged along a part of the first side surface WS1 and the first side surface WS1 on the second main surface TS2 of the laminate 10. The fourth external electrode 44 is L-shaped in the WT cross-section and is arranged along a part of the second side surface WS2 and the second side surface WS2 on the second main surface TS2 of the laminate 10.

[0083] Furthermore, the features of the present invention are also applicable to multilayer ceramic capacitors 1 in which, similar to the multilayer ceramic capacitors 1 shown in Figures 4 to 6, external electrodes 40 are provided only on the second main surface TS2.

[0084] (Modification 4) Figure 11 is a perspective view showing a modified example of a multilayer ceramic capacitor according to this embodiment. The multilayer ceramic capacitor 1 shown in Figure 11 differs from the multilayer ceramic capacitor 1 shown in Figures 7 to 9 in the number and arrangement of the external electrodes 40.

[0085] For example, the external electrodes 40 include a first external electrode 41, a second external electrode 42, a third external electrode 43, and a fourth external electrode 44 at the four corners of the laminate 10 when viewed from the second main surface TS2 side. Such a multilayer ceramic capacitor 1 may include, for example, two multilayer ceramic capacitor elements between the first external electrode 41 and the second external electrode 42, and between the third external electrode 43 and the fourth external electrode 44. The features of the present invention are also applicable to such multi-terminal multilayer ceramic capacitors.

[0086] The first external electrode 41 is positioned at the corners on the first end face LS1 side and the first side surface WS1 side of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and also at a portion of the first end face LS1 and a portion of the first side surface WS1. In the example of Figure 11, the first external electrode 41 is also positioned at the corners on the first end face LS1 side and the first side surface WS1 side of the first main surface (top surface) TS1 of the laminate 10. That is, the first external electrode 41 has a U-shape (Angular U-shape) in the LT cross section and is positioned along a portion of the first end face LS1 side of the second main surface TS2 of the laminate 10, the first end face LS1, and a portion of the first end face LS1 side of the first main surface TS1. Furthermore, the first external electrode 41 has a U-shape (Angular U-shape) in the WT cross-section and is positioned along a portion of the first side surface WS1 side of the second main surface TS2 of the laminate 10, the first side surface WS1, and a portion of the first side surface WS1 side of the first main surface TS1.

[0087] The second external electrode 42 is positioned at the corners of the second end face LS2 side and the first side surface WS1 side of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and also at a portion of the second end face LS2 and a portion of the first side surface WS1. In the example of Figure 11, the second external electrode 42 is also positioned at the corners of the second end face LS2 side and the first side surface WS1 side of the first main surface (top surface) TS1 of the laminate 10. That is, the second external electrode 42 has an angular U-shape in the LT cross section and is positioned along a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10, the second end face LS2, and a portion of the second end face LS2 side of the first main surface TS1. Furthermore, the second external electrode 42 has an angular U-shape in the WT cross-section and is positioned along a portion of the first side surface WS1 side of the second main surface TS2 of the laminate 10, the first side surface WS1, and a portion of the first side surface WS1 side of the first main surface TS1.

[0088] The third external electrode 43 is positioned at the corners on the first end face LS1 side and the second side surface WS2 side of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and also at a portion of the first end face LS1 and a portion of the second side surface WS2. In addition, in the example of Figure 11, the third external electrode 43 is also positioned at the corners on the first end face LS1 side and the second side surface WS2 side of the first main surface (top surface) TS1 of the laminate 10. That is, the third external electrode 43 has a U-shape (Angular U-shape) in the LT cross section and is positioned along a portion of the first end face LS1 side of the second main surface TS2 of the laminate 10, the first end face LS1, and a portion of the first end face LS1 side of the first main surface TS1. Furthermore, the third external electrode 43 has an angular U-shape in the WT cross-section and is positioned along a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10, the second side surface WS2, and a portion of the second side surface WS2 side of the first main surface TS1.

[0089] The fourth external electrode 44 is positioned at the corners on the second end face LS2 side and the second side surface WS2 side of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10, and also at a portion of the second end face LS2 and a portion of the second side surface WS2. In addition, in the example of Figure 11, the fourth external electrode 44 is also positioned at the corners on the second end face LS2 side and the second side surface WS2 side of the first main surface (top surface) TS1 of the laminate 10. That is, the fourth external electrode 44 has a U-shape (Angular U-shape) in the LT cross section and is positioned along a portion of the second end face LS2 side of the second main surface TS2 of the laminate 10, the second end face LS2, and a portion of the second end face LS2 side of the first main surface TS1. Furthermore, the fourth external electrode 44 has an angular U-shape in the WT cross-section and is positioned along a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10, the second side surface WS2, and a portion of the second side surface WS2 side of the first main surface TS1.

[0090] In the multilayer ceramic capacitor 1 shown in Figure 11, as in the multilayer ceramic capacitors 1 shown in Figures 7 to 9, a flat plate-shaped spacer member 55 may be placed in the portion of the first main surface TS1 and the second main surface TS2 where the multiple external electrodes 40 are not arranged. In this case, the stress-suppressing film 50 only needs to extend on the first main surface TS1 so as to cover the spacer member 55.

[0091] In Figure 11, an external electrode 40 with an angular U-shaped cross-section is shown as an example of the shape of the external electrode 40. However, the features of the present invention are not limited to this, and the invention is also applicable to a multilayer ceramic capacitor 1 shown in Figure 10, which has an L-shaped cross-section external electrode 40, similar to the multilayer ceramic capacitor 1 shown in Figures 1 to 3. In this case, the first external electrode 41 is L-shaped in the LT cross-section and is arranged along a part of the first end face LS1 side and the first end face LS1 on the second main surface TS2 of the laminate 10, and is L-shaped in the WT cross-section and is arranged along a part of the first side WS1 side and the first side WS1 on the second main surface TS2 of the laminate 10. Furthermore, the second external electrode 42 is L-shaped in the LT cross-section and is positioned along a portion of the second end face LS2 side and the second end face LS2 on the second main surface TS2 of the laminate 10, and is L-shaped in the WT cross-section and is positioned along a portion of the first side surface WS1 side and the first side surface WS1 on the second main surface TS2 of the laminate 10. Furthermore, the third external electrode 43 is L-shaped in the LT cross-section and is positioned along a portion of the first end face LS1 side and the first end face LS1 on the second main surface TS2 of the laminate 10, and is L-shaped in the WT cross-section and is positioned along a portion of the second side surface WS2 side and the second side surface WS2 on the second main surface TS2 of the laminate 10. Furthermore, the fourth external electrode 44 is L-shaped in the LT cross-section and is positioned along a portion of the second end face LS2 side and the second end face LS2 of the second main surface TS2 of the laminate 10, and is L-shaped in the WT cross-section and is positioned along a portion of the second side surface WS2 side and the second side surface WS2 of the second main surface TS2 of the laminate 10.

[0092] Furthermore, the features of the present invention are also applicable to multilayer ceramic capacitors 1 in which, similar to the multilayer ceramic capacitors 1 shown in Figures 4 to 6, external electrodes 40 are provided only on the second main surface TS2.

[0093] (Variation 5) Figure 12 is a perspective view showing a modified example of a multilayer ceramic capacitor according to this embodiment. The multilayer ceramic capacitor 1 shown in Figure 12 differs from the multilayer ceramic capacitor 1 shown in Figures 7 to 9 in the number and position of the external electrodes 40.

[0094] For example, the external electrodes 40 include a first external electrode 41, a third external electrode 43, a fifth external electrode 45, and a seventh external electrode 47 on the first side WS1 side of the laminate 10, and a second external electrode 42, a fourth external electrode 44, a sixth external electrode 46, and an eighth external electrode 48 on the second side WS2 side of the laminate 10. In such a multilayer ceramic capacitor 1, four multilayer ceramic capacitor elements can be arranged in an array, for example, between the first external electrode 41 and the second external electrode 42, between the third external electrode 43 and the fourth external electrode 44, between the fifth external electrode 45 and the sixth external electrode 46, and between the seventh external electrode 47 and the eighth external electrode 48. The features of the present invention are also applicable to such array-type multilayer ceramic capacitors.

[0095] Each of the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 is positioned on a portion of the first side surface WS1 side and on the first side surface WS1 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In addition, in the example of Figure 12, each of the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 is also positioned on a portion of the first side surface WS1 side of the first main surface (top surface) TS1 of the laminate 10. Specifically, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each U-shaped (Angular U-shape) in the WT cross-section and are arranged along a portion of the second main surface TS2 of the laminate 10 on the first side surface WS1, the first side surface WS1, and a portion of the first main surface TS1 on the first side surface WS1.

[0096] The second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are located on a portion of the second side surface WS2 side and on the second side surface WS2 of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10. In addition, in the example of Figure 12, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are also located on a portion of the second side surface WS2 side of the first main surface (top surface) TS1 of the laminate 10. That is, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 have a U-shape (Angular U-shape) in the WT cross section and are located along a portion of the second side surface WS2 side, the second side surface WS2, and a portion of the second side surface WS2 side of the second main surface TS2 of the laminate 10.

[0097] In the multilayer ceramic capacitor 1 shown in Figure 12, as in the multilayer ceramic capacitors 1 shown in Figures 7 to 9, a flat plate-shaped spacer member 55 may be placed in the portion of each of the first main surface TS1 and the second main surface TS2 where the multiple external electrodes 40 are not arranged. In this case, the stress-suppressing film 50 only needs to extend on the first main surface TS1 so as to cover the spacer member 55.

[0098] In Figure 12, an external electrode 40 with an angular U-shape cross-section is shown as an example. However, the features of the present invention are not limited to this, and the multilayer ceramic capacitor 1 shown in Figure 12 can also be applied to a multilayer ceramic capacitor 1 that has an L-shaped cross-section external electrode 40, similar to the multilayer ceramic capacitor 1 shown in Figures 1 to 3. In this case, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each L-shaped in the WT cross-section and are arranged along a part of the first side surface WS1 and the first side surface WS1 on the second main surface TS2 of the laminate 10. The second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are L-shaped in the WT cross-section and are arranged along a part of the second side surface WS2 and the second side surface WS2 on the second main surface TS2 of the laminate 10.

[0099] Furthermore, the features of the present invention are also applicable to multilayer ceramic capacitors 1 in which, similar to the multilayer ceramic capacitors 1 shown in Figures 4 to 6, external electrodes 40 are provided only on the second main surface TS2.

[0100] In the above-described modifications 1 to 5, the stress-suppressing film 50 is shown to extend along five surfaces: the first main surface (top surface) TS1, the two end surfaces LS1 and TS2, and the two side surfaces WS1 and WS2. However, the present invention is not limited thereto, and the stress-suppressing film 50 may extend along three surfaces: the first main surface (top surface) TS1 and the two end surfaces LS1 and LS2. Alternatively, the stress-suppressing film 50 may extend along three surfaces: the first main surface (top surface) TS1 and the two side surfaces WS1 and WS2.

[0101] Furthermore, the present invention may also take the following forms. <1> A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic material, wherein the laminate has a first main surface and a second main surface facing each other in the stacking direction, two side surfaces facing each other in the width direction intersecting the stacking direction, and two end surfaces facing each other in the length direction intersecting the stacking direction and the width direction. A plurality of external electrodes arranged on at least the second main surface of the laminate, A stress-suppressing film that suppresses stress on the laminate and the plurality of external electrodes, Equipped with, The aforementioned stress-suppressing film is It is made of insulating material, Extending along the first main surface and the two end faces, or extending along the first main surface and the two side faces, so as to cover the laminate and the plurality of external electrodes, The end of the stress-suppressing film protrudes from the outermost surface of the plurality of external electrodes on the second main surface side. Multilayer ceramic capacitor.

[0102] <2> The stress-suppressing film extends along the first main surface and the two end faces, and extends along the first main surface and the two side surfaces. <1> The multilayer ceramic capacitor described above.

[0103] <3> The strength of the stress-suppressing film is higher than the strength of the plurality of dielectric layers of the laminate. <1> or <2> The multilayer ceramic capacitor described above.

[0104] <4> The Young's modulus of the stress-suppressing film is between 400 GPa and 1500 GPa. <1> from <3> A multilayer ceramic capacitor as described in any of the following.

[0105] <5> The stress-suppressing film includes diamond-like carbon or glass as its material. <1> from <4> A multilayer ceramic capacitor as described in any of the following.

[0106] <6> In the stress-suppressing film, the film thickness Da of the first portion along the first main surface and the film thickness Db of the second portion along the two end faces or the two side faces satisfy the following relationship: <1> from <5> A multilayer ceramic capacitor as described in any of the following. 0.8Da≧Db

[0107] <7> The film thickness Da of the first portion is 4.5 μm or more and 5.5 μm or less. <6> The multilayer ceramic capacitor described above.

[0108] <8> Each of the aforementioned plurality of external electrodes is In a cross-section along the stacking direction and the length direction, it has an L-shape and is arranged along one of the second main surface and one of the two end faces of the stacked body, or In a cross-section along the stacking direction and the width direction, it has an L-shape and is arranged along the second main surface and one of the two side surfaces of the stacked body. <1> from <7> A multilayer ceramic capacitor as described in any of the following.

[0109] <9> Each of the plurality of external electrodes is arranged along only the second main surface of the laminate, The laminate extends in the stacking direction and has a plurality of vias connecting the plurality of external electrode layers and different portions of the plurality of internal electrode layers, <1> from <7> A multilayer ceramic capacitor as described in any of the following.

[0110] <10> Each of the aforementioned plurality of external electrodes is In a cross-section along the stacking direction and the length direction, it is U-shaped and arranged along the second main surface of the stack, one of the two end faces and the first main surface, or The cross-section along the stacking direction and the width direction is U-shaped, and is arranged along the second main surface, one of the two side surfaces, and the first main surface of the stacked body. A flat spacer member is placed in the portion of each of the first main surface and the second main surface where the plurality of external electrodes are not arranged. The stress-suppressing film extends on the first main surface to further cover the spacer member. <1> from <7> A multilayer ceramic capacitor as described in any of the following. [Explanation of symbols]

[0111] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First counter electrode section 312 First extraction electrode section 32 Second internal electrode layer 321 Second counter electrode section 322 Second extraction electrode section 35 Beer 40 External electrode 41 First external electrode 415 First Underlay Electrode Layer 416 First plating layer 42 Second external electrode 425 Second Underlay Electrode Layer 426 Second plating layer 50 Stress-suppressing film 55 Spacer member 100 Inner layer 101 First outer layer 102 Second outer layer L30 Electrode facing part LG1 First end gap section LG2 Second end gap section W30 Electrode facing part WG1 First side gap section WG2 Second side gap section L (Length direction) T Stacking direction W (width direction) LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First Aspect WS2 Second Aspect

Claims

1. A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic material, wherein the laminate has a first main surface and a second main surface facing each other in the stacking direction, two side surfaces facing each other in the width direction intersecting the stacking direction, and two end surfaces facing each other in the length direction intersecting the stacking direction and the width direction. A plurality of external electrodes arranged on at least the second main surface of the laminate, A stress-suppressing film that suppresses stress on the laminate and the plurality of external electrodes, Equipped with, The aforementioned stress-suppressing film is It is made of insulating material, Extending along the first main surface and the two end faces, or extending along the first main surface and the two side faces, so as to cover the laminate and the plurality of external electrodes, The end of the stress-suppressing film protrudes beyond the outermost surface of the plurality of external electrodes on the second main surface side. Multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the stress-suppressing film extends along the first main surface and the two end faces, and extends along the first main surface and the two side surfaces.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the strength of the stress-suppressing film is higher than the strength of the plurality of dielectric layers of the laminate.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the Young's modulus of the stress-suppressing film is 400 GPa or more and 1500 GPa or less.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the stress-suppressing film comprises diamond-like carbon or glass as a material.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein the thickness Da of the first portion along the first main surface and the thickness Db of the second portion along the two end faces or the two side surfaces satisfy the following relationship. 0.8Da ≥ Db

7. The multilayer ceramic capacitor according to claim 6, wherein the film thickness Da of the first portion is 4.5 μm or more and 5.5 μm or less.

8. Each of the aforementioned plurality of external electrodes is In a cross-section along the stacking direction and the length direction, it has an L-shape and is arranged along one of the second main surface and the two end faces of the stacked body, or In a cross-section along the stacking direction and the width direction, it has an L-shape and is arranged along the second main surface and one of the two side surfaces of the stacked body. A multilayer ceramic capacitor according to claim 1 or 2.

9. Each of the plurality of external electrodes is arranged along only the second main surface of the laminate, The laminate extends in the stacking direction and has a plurality of vias connecting the plurality of external electrode layers and different portions of the plurality of internal electrode layers, A multilayer ceramic capacitor according to claim 1 or 2.

10. Each of the aforementioned plurality of external electrodes is In a cross-section along the stacking direction and the length direction, it is U-shaped and arranged along the second main surface, one of the two end faces and the first main surface of the stacked body, or The cross-section along the stacking direction and the width direction is U-shaped, and is arranged along the second main surface, one of the two side surfaces, and the first main surface of the stacked body. A flat spacer member is placed in the portion of each of the first main surface and the second main surface where the plurality of external electrodes are not arranged. The stress-suppressing film extends on the first main surface to further cover the spacer member. A multilayer ceramic capacitor according to claim 1 or 2.

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