High-voltage tunable multilayer capacitor
The multilayer capacitor with tunable dielectric layers addresses the low capacitance issue at high power levels by achieving substantial capacitance variation, enhancing its applicability in diverse circuits and systems.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KYOCERA AVX COMPONENTS CORP
- Filing Date
- 2023-06-01
- Publication Date
- 2026-06-30
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
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Abstract
Description
[Technical Field]
[0001] Cross-reference of related applications
[0001] This application is a U.S. Provisional Patent Application No. 62 / 555, with a filing date of September 8, 2017. The applicant claims interest in the application of No. 924, the entirety of which is incorporated herein by reference. [Background technology]
[0002]
[0002] Tuned capacitors have been proposed for various applications that depend on the variable dielectric properties of the dielectric material. Here it is. In the case of such capacitors, the capacitance at zero bias is typically close to its maximum value, and the capacitance decreases with the applied voltage. The change in capacitance allows these units to be used to construct tuneable circuits in filters, matching networks, resonant circuits, and other applications from audible to RF and microwave frequencies. Despite the benefits of such capacitors, their use has been relatively limited, partly due to the relatively low capacitance values achieved at high power and voltage levels. Therefore, there is now a need for voltage-tuneable capacitors with improved properties that can be used in a wider range of possible applications. [Overview of the Initiative] [Means for solving the problem]
[0003]
[0003] According to one embodiment of the present disclosure, the first active terminal is in electrical contact with the first active A tunable multilayer capacitor is disclosed, comprising a first DC bias electrode and a second active electrode in electrical contact with a second active termination. The capacitor also comprises a first DC bias electrode in electrical contact with a first DC bias termination and a second DC bias electrode in electrical contact with a second DC bias termination. The capacitor also comprises a plurality of dielectric layers provided between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprises a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC voltage across the first and second DC bias electrodes. At least one of the plurality of dielectric layers has a thickness greater than about 15 micrometers.
[0004]
[0004] According to another embodiment of the present disclosure, the first active terminal is in electrical contact with the first active terminal A tunable multilayer capacitor is disclosed, comprising an electrode and a second active electrode in electrical contact with a second active termination. The capacitor also comprises a first DC bias electrode in electrical contact with a first DC bias termination and a second DC bias electrode in electrical contact with a second DC bias termination. The capacitor also comprises a plurality of dielectric layers provided between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers comprises a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC voltage across the first and second DC bias electrodes. The applied DC voltage is greater than about 100V without exceeding about 50% of the breakdown voltage of the tunable dielectric material.
[0005]
[0005] Other features and aspects of the present invention are described in further detail below.
[0006] A complete and implementable disclosure of the present invention intended for those skilled in the art would represent the best mode of the invention. This is described in more detail in the remainder of the specification, including reference to the attached figures. [Brief explanation of the drawing]
[0006] [Figure 1]
[0007] A graph showing the capacitance change achievable using the subject matter of the present disclosure over a range of normalized bias voltage changes. [Figure 2A]
[0008] A cross-sectional view of an exemplary embodiment of a four-terminal bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 2B] An exploded plan view of an exemplary embodiment of a four-terminal bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 2C] An exploded perspective view of an exemplary embodiment of a four-terminal bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 2D]
[0009] An overall side, top, and end perspective views of an assembled device according to the exemplary embodiments of FIGS. 2A-2C. [Figure 2E]
[0010] A representative diagram of a shunt configuration of the exemplary embodiments of FIGS. 2A-2D. [Figure 2F] A representative diagram of a series configuration of the exemplary embodiments of FIGS. 2A-2D. [Figure 3A]
[0011] A cross-sectional view of an exemplary embodiment of a four-terminal tunable cascaded configuration multilayer capacitor according to the subject matter of the present disclosure. [Figure 3B] An exploded plan view of an exemplary embodiment of a four-terminal tunable cascaded configuration multilayer capacitor according to the subject matter of the present disclosure. [Figure 3C] An exploded perspective view of an exemplary embodiment of a four-terminal tunable cascaded configuration multilayer capacitor according to the subject matter of the present disclosure. [Figure 3D]
[0012] A representative diagram of a shunt configuration of the exemplary embodiments of FIGS. 3A-3C. [Figure 3E] A representative diagram of a series configuration of the exemplary embodiments of FIGS. 3A-3C. [Figure 4A]
[0013] A cross-sectional view of an exemplary embodiment of a four-terminal tunable partial bias configuration multilayer capacitor according to the subject matter of the present disclosure. [Figure 4B] An exploded plan view of an exemplary embodiment of a four-terminal tunable partial bias configuration multilayer capacitor according to the subject matter of the present disclosure. [Figure 4C]
[0014] These are representative views of exemplary embodiments of FIGS. 4A and 4B. [Figure 5]
[0015] A diagram representing an exemplary chip manufacturing automated process (CMAP) embodiment according to the subject matter of the present disclosure, which can be used in the exemplary manufacturing apparatus embodiments disclosed together. [Figure 6]
[0016] A cross-sectional view of an exemplary embodiment of a bias-type asymmetric multilayer capacitor according to the subject matter of the present disclosure. [Figure 7A]
[0017] A cross-sectional view of an exemplary embodiment of a 1:1 ratio duplicate type symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 7B] A partially exploded perspective view of an exemplary embodiment of a 1:1 ratio duplicate type symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 7C]
[0018] A cross-sectional view of another exemplary embodiment of a 1:1 ratio duplicate type symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 7D] A partially exploded perspective view of another exemplary embodiment of a 1:1 ratio duplicate type symmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 8]
[0019] A cross-sectional view of an exemplary embodiment of an 11:1 ratio non-shielded type asymmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 9]
[0020] A cross-sectional view of an exemplary embodiment of an 11:1 ratio shielded type asymmetric design of a bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 10]
[0021] A cross-sectional view of an exemplary embodiment of a composition blend bias-type multilayer capacitor according to the subject matter of the present disclosure. [Figure 11]
[0022] (a)-(c) are diagrams showing symmetric directions that can be used for active and bias terminations in an embodiment of the present invention. [Figure 12]
[0023] This figure shows an embodiment of a stacked capacitor array having single-lead and lead frame attachments according to an aspect of the subject matter of this disclosure. [Figure 13]
[0024] This figure shows the measured capacitance of an example of a multilayer capacitor array according to an embodiment of this disclosure at applied DC bias voltage levels ranging from 0V to 200V. [Modes for carrying out the invention]
[0007]
[0025] The repeated use of reference numerals throughout this specification and the accompanying drawings is intended to represent the same or similar features, elements, or steps in this specification and the accompanying drawings.
[0026] This discussion merely describes illustrative embodiments and is not intended to limit broader embodiments of the present invention; it should be understood by those skilled in the art that these broader embodiments are embodied in the illustrative structures.
[0008]
[0027] Generally speaking, the present invention relates to a multilayer capacitor comprising a plurality of dielectric layers interposed between alternating active electrode layers. At least a portion of the dielectric layers comprises a tunable material that exhibits a variable dielectric constant upon application of an applied voltage. More specifically, such a material typically has a "voltage tuning coefficient" ranging from about 10% to about 90%, in some embodiments from about 20% to about 80%, and in some embodiments from about 30% to about 70%, and the "voltage tuning coefficient" is given by the following general formula: T = 100 × (ε0 - ε ν ) / ε0 It is determined according to the following, During the ceremony, T is the voltage tuning coefficient, ε0 is the static dielectric constant of the material without an applied voltage. ε ν This is the variable dielectric constant of the material after the application of an applied voltage (DC).
[0009]
[0028] The static dielectric constant of a material typically ranges from about 100 to about 25,000, from about 200 to about 10,000 in some embodiments, and from about 500 to about 9,000 in some embodiments, as can be determined by ASTM D2149-13 at operating temperatures ranging from about -55°C to about 150°C (e.g., 25°C) and frequencies ranging from about 100 Hz to about 1 GHz (e.g., 1 kHz). Of course, it should be understood that a specific value of static dielectric constant is generally selected based on the particular application in which the capacitor is used. When an increased DC bias is applied, the dielectric constant generally decreases within the ranges described above. The tuning voltage applied to induce a desired change in dielectric constant may vary with respect to the voltage at which the dielectric composition begins to conduct under the application of an electric field ("breakdown voltage"), which can generally be determined by ASTM D149-13 at a temperature of 25°C. In most embodiments, the applied DC bias voltage is about 50% or less of the breakdown voltage of the dielectric composition, about 30% or less in some embodiments, and about 0.5% to about 10% in some embodiments.
[0010]
[0029] Various tunable dielectric materials may be commonly used as is well known. Particularly suitable materials are dielectrics whose base composition includes one or more ferroelectric base phases, such as perovskites, tungsten bronze materials (e.g., sodium barium niobate), and layered structural materials (e.g., bismuth titanate). Suitable perovskites may include, for example, barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate, barium strontium zirconate, barium calcium zirconate, etc.), lead titanate and related solid solutions (e.g., lead zirconate, lead zirconate lanthanum), sodium bismuth titanate, etc. In one particular embodiment, for example, formula Ba x Sr 1-xBarium strontium titanate of TiO3 (「BSTO」) may be used, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other electronically tunable dielectric materials may be used, in part or in whole, instead of barium strontium titanate. For example, one example is Ba x Ca 1-x TiO3, where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6. Other suitable perovskites are Pb x Zr 1-x TiO3 (「PZT」), lead lanthanum zirconium titanate (「PLZT」) where x ranges from about 0.05 to about 0.4, lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb 2O6, PbTa2O6, KSr(NbO3) and NaBa2(NbO3)5KHb2PO4 may be included. Even further complex perovskites may include A[B1 1 / 3 B2 2 / 3 O3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), and B2 is Ta z Nb 1-z (z can be a value from 0 to 1). As illustrated in the exemplary embodiment of FIG. 10, by combining two end-component compositions in alternating layers, a potential dielectric material of interest can be formed. Such end-component compositions may be chemically similar, but may differ in the ratio of A-site dopants, as described above. For example, Composition 1 (132 in FIG. 10) may be a perovskite compound of the general formula (A1 x ,A2 (1-x) )BO3, and Composition 2 (134) may be of the general formula (A1 y ,A2 (1-y))BO3 perovskite is also acceptable, where A1 and A2 are from Ba, Sr, Mg and Ca, and the potential B site members are Zr, Ti and Sn, and "x" and "y" indicate the mole fraction of each component. A specific example for compound 1 is (Ba 0.8 Sr 0.2 )It may also be TiO3, and compound 2 is (Ba 0.6 Sr 0.4 )TiO3 may also be used. These two compounds may be combined in alternating layers in a sintered multilayer capacitor having a tunable electrode structure, as shown in Figure 10, so that the dielectric properties of each material are superimposed.Optionally, the perovskite material may also be doped with rare earth oxides ("REO") in amounts of 5.0 mol percent or less, and more preferably from 0.1 to 1 mol percent. Suitable rare earth oxide dopants for this purpose may include, for example, scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
[0011]
[0030] Regardless of the specific material used, the use of a tunable dielectric material can enable the resulting capacitance of a capacitor to be tuned by applying a DC bias voltage through bias terminations. More specifically, a capacitor includes a set of first active electrodes in electrical contact with a first active termination (e.g., input termination) and a set of second active electrodes in electrical contact with a second active termination (e.g., output termination). The capacitor also includes a set of first DC bias electrodes in electrical contact with a first DC bias termination and a set of second DC bias electrodes in electrical contact with a second DC bias termination. When provided in a circuit, a DC power source (e.g., battery, constant voltage power source, multi-output power source, DC-DC converter, etc.) can provide a DC bias to the capacitor through the first and second bias terminations, which are typically bipolar in that they have opposite polarities. The electrodes and terminals may be formed from any of the various different metals known to exist, including noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, etc.), and various combinations thereof. A dielectric layer is interposed between each active electrode and bias electrode.
[0012]
[0031] Regardless of the specific configuration used, the inventors have found that capacitors exhibiting excellent tuning over a wide range of voltage and capacitance values can be achieved through selective control of the properties of the tunable dielectric material, the number of dielectric layers, and the thickness of the dielectric layers. For example, such capacitors may enable higher applied DC bias voltages and higher capacitances for a single capacitor (compared to a composite capacitor connected in parallel) with a smaller overall size than previously thought possible. In some embodiments, for example, the applied DC bias voltage may be greater than about 10V, greater than about 50V in some embodiments, greater than about 100V in some embodiments, greater than about 350V in some embodiments, greater than about 500V in some embodiments, greater than about 750V in some embodiments, greater than about 1000V in some embodiments, greater than about 1200V in some embodiments, and greater than about 1500V in some embodiments. For example, in some embodiments The applied DC bias voltage may range from about 10V to about 1500V, in some embodiments from about 20V to about 1000V, and in some embodiments from about 30V to about 750V, in some embodiments from about 40V to about 500V, and in some embodiments from about 50V to about 350V. Similarly, the applied bias field may range from about 0.2V / μm to about 50V / μm, in some embodiments from about 0.5V / μm to about 40V / μm, in some embodiments from about 0.5V / μm to about 25V / μm, and in some embodiments from about 1V / μm to about 7V / μm.
[0013]
[0032] The capacitance value may also be controlled within a wider range than previously thought possible. For example, the capacitor may be constructed to have a tuning capability with initial capacitance values ranging from 0.5 to 50,000,000 picofarads ("pF"), as described later. Thus, the capacitor may be used in applications requiring high capacitance, such as values of 100pF or more, about 10,000pF or more in some embodiments, about 100,000 to about 10,000,000pF in some embodiments, about 200,000 to about 5,000,000pF in some embodiments, and about 400,000 to about 3,500,000pF in some embodiments. Similarly, in other embodiments, the capacitor may be used in applications requiring low capacitance, such as values of less than 100pF, about 50pF or more in some embodiments, about 0.5 to about 30pF in some embodiments, and about 1 to about 10pF in some embodiments. The degree to which the capacitance can be tuned may vary as desired. For example, the capacitance may be tuned from about 10% of its initial value to about 100%, from about 20% to about 95% in some embodiments, and from about 30% to about 80% in some embodiments. The capacitance may be determined using an Agilent 4294A impedance analyzer at a frequency of 1 kHz or 1 MHz, a temperature of about 25°C, and a fixed amplitude of 500 mV.
[0014]
[0033] In some embodiments, the dielectric layer may have a thickness ranging from about 5 micrometers (μm) to about 150 μm, in some embodiments from about 15 μm to about 100 μm, and in some embodiments from about 30 μm to about 70 μm, for example, about 50 μm. The electrode layer may have a thickness ranging from about 0.5 μm to about 3.0 μm, in some embodiments from about 1 μm to about 2.5 μm, and in some embodiments from about 1 μm to about 2 μm, for example, about 1.5 μm.
[0015]
[0034] The total number of active and bias electrode layers may vary. For example, in some embodiments, the total number of active electrode layers may range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, and in some embodiments from about 30 to about 120, for example, about 50. For example, in some embodiments, the total number of bias electrodes may range from 2 to about 10,000, in some embodiments from 2 to about 1,000, in some embodiments from about 10 to about 500, and in some embodiments from about 30 to about 120, for example, about 50. It should be understood that the numbers of electrodes and bias layers depicted in the figures and described herein are illustrative only.
[0016]
[0035] The length of the capacitor may range, for example, from about 1 millimeter (mm) to about 50 mm, from about 2 mm to about 35 mm in some embodiments, from about 5 mm to about 15 mm in some embodiments, and from about 7 mm to about 14 mm in some embodiments. The width of the capacitor may range, for example, from about 1 mm to about 50 mm, from about 2 mm to about 35 mm in some embodiments, from about 5 mm to about 15 mm in some embodiments, and from about 7 mm to about 14 mm in some embodiments.
[0017]
[0036] The height of the capacitor may range, for example, from about 0.5 mm to about 14 mm, from about 0.75 mm to about 7 mm in some embodiments, from about 1 mm to about 5 mm in some embodiments, from about 2 mm to about 5 mm in some embodiments, for example, to about 3 mm. The ratio of the length of the capacitor to the height of the capacitor may range, for example, from about 1 to about 15, from about 2 to about 7 in some embodiments, from about 3 to about 5 in some embodiments, for example, to about 4. The ratio of the width of the capacitor to the height of the capacitor may range, for example, from about 1 to about 15, from about 2 to about 7 in some embodiments, from about 3 to about 5 in some embodiments, for example, to about 4.
[0018]
[0037] Figure 1 illustrates, in graphical form, the capacitance changes that can be achieved over a range of normalized bias voltage variations. In detail, the horizontal axis graphs the normalized bias voltage as a percentage of the device's rated voltage, such as from 0% to 150%. As shown in the figure, the corresponding change in the device's effective capacitance is graphed on the vertical axis as a percentage change from the capacitance value without any bias. As illustrated by the graph in Figure 1, a 150% increase in the normalized bias voltage approaches an 80% decrease in the unbiased capacitance value, as illustrated, along a relatively linear curve. Thus, the voltage-tunable capacitor devices according to the subject matter of this disclosure facilitate maximizing efficiency over a range of operating conditions.
[0019]
[0038] Referring here to Figures 2A-2D, one particular embodiment of a capacitor 10 that can be formed by the present invention is described in further detail here. As shown, the capacitor 10 includes a plurality of dielectric layers 12 that are alternately stacked over two separate sets of active electrodes 14 and 20 and two separate sets of bias electrodes 22 and 26. The capacitor may also be a hexahedron, such as a rectangular shape. In the exemplary embodiment, a first active termination 16 is electrically connected to the first active electrode 14, and a second active termination 18 is electrically connected to the second active electrode 20. The first bias electrode 22 is electrically connected to a first DC bias (+) termination 30 via an extension member 24 (e.g., a tab) that extends to the side of the capacitor 10. Similarly, the second bias electrode 26 is electrically connected to a second DC bias (-) termination 32 via an extension member 28. Thus, the resulting capacitor 10 includes four separate terminations. In some embodiments, the active terminations 16, 18 may wrap around each end of the capacitor 10 to provide larger terminations 16, 18 for electrically connecting the capacitor 10 to the circuit. The DC bias terminations 30, 32 may be configured as strips that do not extend along the entire side of the capacitor 10. In other embodiments, however, the DC bias terminations 30, 32 may instead wrap around the side of the capacitor 10, and the active terminations 16, 18 may be configured as strips that do not extend along the entire end of the capacitor.
[0020]
[0039] Figures 2E and 2F illustrate representative diagrams of the shunt configuration and series configuration, respectively, of the illustrative embodiments shown in Figures 2A to 2D. As shown in the figures, in the shunt configuration, a ground 34 is also provided for the bias input.
[0021]
[0040] In the embodiments described above, the active electrodes are stacked such that each alternating electrode is connected to the opposite end. In some embodiments, the alternating layers may be connected to the same end through the use of a “cascaded” configuration in which each set of active electrodes is spaced laterally rather than stacked. One embodiment of such a cascaded capacitor 49 is illustrated in Figures 3A–3C. As depicted, the capacitor 49 includes a plurality of dielectric layers 44 arranged for two separate sets of active electrodes 36 and 40 and two separate sets of bias electrodes 46 and 50. In the exemplary embodiment, in this example, a first active termination 38 is electrically connected to the first active electrode 36, and a second active termination 42 is electrically connected to the second active electrode 40. The first bias electrode 46 is connected to the first active electrode 49 via an extension member 48 that extends to the side of the capacitor 49. The DC bias (-) termination 54 is electrically connected. Similarly, the second bias electrode 50 is electrically connected to the second DC bias (+) termination 56 via the extension member 52. Figures 3D and 3E illustrate representative diagrams of the shunt configuration and series configuration, respectively, of the illustrative embodiments shown in Figures 3A-3C. As shown, in the shunt configuration, a ground 58 is also provided with respect to the bias input.
[0022]
[0041] Figures 4A-4C illustrate another embodiment of a capacitor 59 which may be formed in a partially cascaded configuration according to the present invention. The capacitor 59 is considered “partially cascaded” because only a portion 60 of the total active capacitance region is biased (see Figure 4A). The addition of bias stray electrodes, as illustrated, causes the application of an external voltage to change the dielectric of the total capacitance, which will be determined by other factors and characteristics. As illustrated by such figures, the dielectric layer 62 may be alternately stacked over first and second sets of active electrodes 64 and 66, first and second sets of bias electrodes 68 and 72, and a plurality of stray electrodes 76. The first active electrode 64 is electrically connected to a first active termination 78, while the second active electrode 66 is electrically connected to a second active termination 80. The first bias electrode 68 is electrically connected to a first DC bias (+) termination 82 via an extension member 70 that extends to the side of the capacitor 59. Similarly, the second bias electrode 72 is electrically connected to the second DC bias (-) termination 84 via the extension member 74. It should be understood that the number of electrode layers illustrated in Figure 4A is illustrative only. As described above, in some embodiments, the number of active electrodes may range from 2 to about 10,000. As described above, in some embodiments, the number of bias electrodes may range from 2 to about 10,000.
[0023]
[0042] Further embodiments according to the present disclosure are illustrated in Figures 7A and 7B. In these embodiments, first and second sets of active electrodes 114, 120 are stacked with first and second sets of bias electrodes 122, 126 in an alternating 1:1 ratio pattern, respectively. Referring to Figure 7B, in some embodiments, the lead wires 124, 128 of the bias electrodes 122, 126 may be configured as protruding tabs. The lead wires 124, 128 may contact the DC bias terminations 30, 32 in a completed form as illustrated in Figure 2D. It should be understood that the number of electrode layers illustrated in Figures 7A and 7B is illustrative only.
[0024]
[0043] Another embodiment according to the present disclosure is illustrated in Figures 7C and 7D. In this embodiment, the active electrodes 114, 120 may include respective lead wires 125 and 127, which may be configured as protruding tabs. The lead wires 125, 127 may be electrically connected to respective active terminations 16, 18, as illustrated in Figure 7D. This embodiment may provide improved lamination between the edges of the capacitor layers, more specifically at the corners of the layers, resulting in a more robust capacitor. Additionally, this configuration may reduce the occurrence of delamination problems during manufacturing.
[0025]
[0044] Additionally, the widths of tabs 124, 125, 126, and 127 may be selected to favorably provide greater electrical contact (e.g., with less resistance) to the respective electrodes 114, 120, 122, and 126. Additionally, the widths of tabs 124 and 128 and the widths of terminations 30 and 32 associated with the DC bias electrodes 122 and 126 may be selected to avoid contact between the bias electrode terminations 30 and 32 and the signal electrode terminations 16 and 18. For example, in some embodiments, tabs 124, 125, 126, and 127 may extend along the edge of the capacitor by 10% or more, 30% or more in some embodiments, and 60% or more in some embodiments. It should be understood that the number of electrode layers illustrated in Figures 7A-7D is illustrative only. As described above, in some embodiments, the number of active electrodes may range from 2 to approximately 10,000. In some embodiments, the number of bias electrodes may range from 2 to about 10,000.
[0026]
[0045] In the embodiments described above, the electrodes are generally used in a “symmetrical” configuration, in that the distance (or dielectric thickness) between the first active electrode and the second active electrode is the same as the distance between the first bias electrode and the second bias electrode. In some embodiments, however, it may be desirable to achieve an “asymmetrical” configuration by varying this thickness. For example, the distance between the first and second active electrodes may be smaller than the distance between the first and second bias electrodes. In yet another embodiment, the distance between the first and second active electrodes may be larger than the distance between the first and second bias electrodes. In particular, this may increase the DC field applied for a given level of applied DC bias, which will increase the level of tuning to a given DC bias voltage. Such an arrangement may also allow for the use of materials with relatively greater tuning to relatively modest DC voltages and modest tuning (potentially having lower loss and temperature / frequency variability). Such asymmetrical configurations can be achieved in various ways, but it is typically desired to use an additional “floating” bias electrode between each pair of active electrodes. Referring to Figure 6, for example, one embodiment of such an asymmetric capacitor is illustrated, which includes first and second active electrodes 114 and 120, respectively, in conjunction with first and second bias electrodes 122 and 126, respectively.
[0027]
[0046] Figure 8 illustrates another embodiment of an asymmetric capacitor in which every 11th electrode is an active electrode rather than a bias electrode (11:1 ratio design). In this case, each such active electrode (e.g., an AC electrode) may be surrounded by a pair of DC bias electrodes having opposite polarities. Thus, a bias field may be generated across each AC electrode. Such a structure may provide capacitive coupling between the polarities of the AC signal and the DC bias voltage, and vice versa. Each AC electrode 214, 220 may be positioned between a pair of bias electrodes 222, 226 having opposite polarities. The first set of bias electrodes 222 may all have the same polarity, and the second set of bias electrodes 226 (illustrated by dashed lines) may all have the opposite polarity of the first set of bias electrodes 222. This configuration may provide capacitive coupling between each AC electrode 214, 220 and both DC bias polarities.
[0028]
[0047] Figure 9 illustrates a cross-sectional view of an exemplary embodiment of an 11:1 ratio "shielded" asymmetric design of a biased multilayer capacitor according to the subject of this disclosure. This example is similar to the example illustrated in Figure 8, except that each AC electrode 314, 320 is surrounded by a pair of DC electrodes (322 or 326) having the same polarity. One set of bias electrodes 322 may all have the same polarity, and the other set of bias electrodes 326 (illustrated by dashed lines) may all have opposite polarity. The material between the two DC electrodes (322 or 326) having the same polarity may not provide tuning, but the material may potentially provide shielding to the AC signal to reduce associated noise. Such a structure may also provide coupling between each of the first set of AC electrodes 314 and only a single DC bias polarity. Similarly, such a structure may provide capacitive coupling between a second set of AC electrodes 320 and only an opposite DC bias polarity.
[0029]
[0048] It should be understood that the number of electrode layers illustrated in Figures 8 and 9 is illustrative only. As mentioned above, in some embodiments, the number of active electrodes may range from 2 to about 10,000. As mentioned above, in some embodiments, the number of bias electrodes may range from 2 to about 10,000.
[0030]
[0049] While not always required, it is typically desirable that the active and DC bias terminations be symmetrically arranged with respect to the capacitor axis. For example, in one embodiment... In this configuration, the capacitor may include opposing first and second end regions spaced apart in the longitudinal direction, and opposing first and side regions spaced apart in the transverse direction. In one embodiment, active terminations may be provided in each end region of the capacitor, while DC bias terminations may be provided in each side region of the capacitor. When arranged symmetrically, the active terminations and / or DC bias terminations may be equidistant from the longitudinal and / or transverse axes extending through the geometric center of the capacitor. Referring to Figure 11(a), for example, one embodiment of a capacitor 1000 is illustrated, which includes longitudinal axis "x" and transverse axis "y" perpendicular to each other and extending through the geometric center "C". In this particular embodiment, the capacitor 1000 includes first and second active terminations 1100 and 1120, respectively, provided in the end regions of the capacitor 1000 and centered with respect to both axes "x" and "y". Similarly, the capacitor 1000 includes first and second bias terminations 1140 and 1160 provided in the side region of the capacitor 1000 and further centered with respect to both axes "x" and "y".
[0031]
[0050] In one embodiment, it may be desirable to have two or more terminations on the same side of the capacitor. Figure 11(b) illustrates one embodiment of capacitor 2000, for example, including a first active termination 2100 and a second active termination 2140 located in the same side region. Capacitor 2000 also includes a first bias termination 2160 and a second bias termination 2120, both located in a different side region opposite to the side region of the active terminations. Despite being located only in the side region, the active terminations 2100 and 2140 are still symmetrically positioned, both equidistant from axes "x" and "y". Similarly, the bias terminations 2160 and 2120 are also equidistant from axes "x" and "y". In the embodiments described above, the first active termination and the first bias termination are located opposite to their respective second active terminations and second bias terminations. Of course, this is by no means mandatory. In Figure 11(c), for example, a capacitor 3000 is illustrated that includes first and second active electrode terminations 3100 and 3160, respectively, which are located in an oblique configuration on opposite side regions. Nevertheless, the first active termination 3100 and the second active termination 3160 are still symmetrically positioned, both at equidistant from axes "x" and "y". Similarly, the capacitor 3000 also includes first and second bias terminations 3120 and 3140, which are located in an oblique configuration on opposite side regions, also at equidistant from axes "x" and "y".
[0032]
[0051] The subject matter of this disclosure equally encompasses related and / or corresponding methods for improved voltage-tunable devices, including, for example, the production of such devices, as well as the use of devices in combination with related networking. As a further example, Figure 5 represents a chip manufacturing automated process (CMAP) 86, which can be used in conjunction with the illustrative manufacturing apparatus embodiments disclosed herein. As illustrated, process 86 may include several sequential steps, in some examples involving a ceramic station or three ovens interposed by other steps / phases such as the use of a screen head or elevator and conveyor functions, as typically illustrated. Those skilled in the art will understand that the exact provision of sequential steps will depend on which of the illustrative device embodiments (or modifications thereof) disclosed herein is being produced. Furthermore, the individual steps shown are intended only to represent the type of step shown and do not imply that the use of other embodiments beyond the general nature of the steps shown is essential. For example, the screen head step may involve the use of a stainless steel screen with electrode paste for screen lamination of electrode layers, or other techniques for such a step may be practiced. For example, more conventional steps of alternating stacking and lamination (with tape) may be performed. In any of the steps (or other), a person skilled in the art will recognize that selected steps may be performed to produce a particular design selected for a given application of the subject matter of this disclosure.
[0033]
[0052] Referring to Figure 12, a multilayer capacitor array 4000 may be formed by stacking individual capacitors 10, for example, as illustrated in Figures 2A to 2D. The multilayer capacitor array 4000 may provide increased capacitance compared to a single capacitor 10 and may allow for simpler manufacturing and assembly. The capacitors 10 may be connected in parallel. For example, a first lead frame 4002 may connect each first active termination 16, and a second lead frame 4004 may connect each second active termination 19. A first single lead 4006 may connect each first DC bias termination 30, and a second single lead 4008 may connect each second DC bias termination 32. As described above with respect to Figures 2A to 2D, in some embodiments, the structures of the active terminations 16, 18 and the DC bias terminations 30, 32 may be reversed. For example, the DC bias terminations 30, 32 may wrap around the capacitor 10 instead of the active terminations 16, 18 which wrap around the capacitor 10 as illustrated in Figure 12. In some embodiments, the multilayer capacitor array 4000 may include 2 to 24 capacitors, 3 to 12 capacitors in some embodiments, and 4 to 6 capacitors in some embodiments. In other embodiments, the multilayer capacitor array 4000 may include 24 or more capacitors.
[0034]
[0053] The capacitors of the present invention can be used in a wide variety of applications, including, for example, circuits used in aircraft. For example, one application may include AC circuits operating in frequency ranges from about 200 Hz to about 1200 Hz, in some embodiments from about 300 Hz to about 1100 Hz, and in some embodiments from about 400 Hz to about 1000 Hz. In such applications, the capacitors may have capacitances ranging from about 5 microfarads (μF) to about 15 μF, and in some embodiments from about 8 μF to about 12 μF, for example, about 10 μF. The applied bias voltage may range from about 100 V to about 300 V, in some embodiments from about 150 V to about 250 V, for example, 200 V.
[0035]
[0054] Further applications may include circuits enabled for tuning the oscillation frequency of switch-mode power supplies. Through the use of the capacitors of the present invention, better tuning at high DC voltages (i.e., bias voltages) can be selectively obtained while allowing the use of materials that have relatively modest tuning but potentially lower loss and lower temperature / frequency variability. Other suitable applications may include, for example, waveguides, RF applications (e.g., delay lines), antenna structures, filters (e.g., load point filters and circuits), matching networks, resonant circuits, smoothing capacitors in variable load circuits, and other applications.
[0036] Examples
[0055] A multilayer capacitor array comprising multiple tunable multilayer capacitors according to an aspect of the present disclosure has been illustrated. The multilayer capacitor array, assembled as illustrated in Figure 12, included three tunable multilayer capacitors. The capacitor array had an overall length of approximately 12.7 mm (0.5 inches), an overall width of approximately 12.7 mm (0.5 inches), and an overall height of approximately 3.1 mm (0.12 inches).
[0037]
[0056] Each of the three capacitors in the array contained a dielectric material containing barium titanate. Each dielectric layer had a thickness of approximately 50 μm. There were 54 active electrodes and 55 bias electrodes arranged alternately. Each individual capacitor had a capacitance of approximately 1.8 μF.
[0038]
[0057] An AC sinusoidal signal with an amplitude of 1V and a frequency of 1kHz was applied over active terminations 16 and 19 (via the first and second lead frames 4002 and 4004). Various DC bias voltage levels were applied over DC bias terminations 30 and 32 (via the first and second single leads 4006 and 4008).
[0039]
[0058] Figure 13 illustrates the measured capacitance of the multilayer capacitor array across the first and second lead frames 4002 and 4004 at DC bias voltage levels ranging from 0V to 200V. As shown in Figure 13, the measured capacitance between the active terminations 16 and 19 decreased from 5.47μF at a DC bias voltage of 0V to approximately 3.66μF at a DC bias voltage of 200V. The measured capacitance values and applied DC bias voltages plotted in Figure 13 are presented in the table below, along with the "tunability" parameter. The "tunability" parameter was calculated as the measured capacitance at each DC bias voltage level divided by the initial capacitance at a DC bias voltage of 0V (5.47μF).
[0040] [Table 1]
[0041]
[0059] These and other modifications and variations of the present invention can be carried out by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the various embodiments can be interchanged in whole or in part. Furthermore, those skilled in the art will recognize that the above description is merely illustrative and is not intended to limit the invention to what is further described in the appended claims.
Claims
1. A first active electrode in electrical contact with a first active terminal, A second active electrode is in electrical contact with the second active terminal, A first DC bias electrode that is in electrical contact with the first DC bias termination, The second DC bias electrode is in electrical contact with the second DC bias termination, The device comprises a plurality of dielectric layers provided between the first and second active electrodes and between the first and second DC bias electrodes, At least a portion of the dielectric layer includes a tunable dielectric material that exhibits a variable dielectric constant upon application of a DC bias voltage across the first and second DC bias electrodes, The thickness of each dielectric layer of the plurality of dielectric layers ranges from approximately 50 micrometers to approximately 150 micrometers. The distance between the first active electrode and the second active electrode is greater than or approximately the same as the distance between the first DC bias electrode and the second DC bias electrode. A tunable multilayer capacitor in which the applied DC bias voltage ranges from approximately 100V to approximately 1000V.
2. The capacitor according to claim 1, wherein the capacitor has a length ranging from about 7 mm to about 14 mm.
3. The capacitor according to claim 1, wherein the capacitor has a width ranging from approximately 7 mm to approximately 14 mm.
4. The capacitor according to claim 1, wherein the capacitor has a height of approximately 2 mm to approximately 5 mm.
5. The capacitor according to claim 1, wherein the ratio of the length of the capacitor divided by the height of the capacitor is approximately 3 to approximately 5.
6. The capacitor according to claim 1, wherein the total number of first and second active electrodes is approximately 10 to approximately 100.
7. The aforementioned tunable dielectric material has a voltage tuning coefficient ranging from approximately 10% to approximately 95%, and the voltage tuning coefficient is given by the following general formula: T=100×(e) ０ -e ν ) / e ０ It is determined according to the following, During the ceremony, T is the voltage tuning coefficient, ε ０ This is the static dielectric constant of the tunable dielectric material without an applied voltage. ε ν This is the variable dielectric constant of the tunable dielectric material after the application of the applied voltage (DC). The capacitor according to claim 1.
8. The capacitor according to claim 7, wherein the static dielectric constant of the tunable dielectric material is between approximately 100 and approximately 10,000, as determined by ASTM D2149-13 at an operating temperature of 25°C and a frequency of 1 kHz.
9. The capacitor according to claim 1, wherein the first and second active terminations and the first and second DC bias terminations are provided symmetrically with respect to the capacitor.
10. The capacitor according to claim 1, wherein the capacitor can be tuned to capacitance values ranging from approximately 200,000 pF to approximately 5,000,000 pF.
11. The capacitor according to claim 1, wherein the capacitor can be tuned to a capacitance value of approximately 200,000 pF or less.
12. The capacitor according to claim 1, wherein the first DC bias electrode includes a tab extending to the first DC bias termination, or the second DC bias electrode includes a tab extending to the second DC bias termination, or a combination thereof.
13. The capacitor according to claim 1, wherein the first active electrode includes a tab extending to the first active terminal, or the second active electrode includes a tab extending to the second active terminal, or a combination thereof.
14. The capacitor according to claim 1, further comprising at least one stray electrode.
15. The first active electrode is one of a plurality of first active electrodes. The aforementioned second active electrode is one of a plurality of second active electrodes, The first DC bias electrode is one of a plurality of first DC bias electrodes, The aforementioned second DC bias electrode is one of a plurality of second DC bias electrodes, The plurality of first active electrodes are stacked along the stacking direction to form a first assembly. The plurality of second active electrodes are stacked along the stacking direction to form a second assembly. The capacitor according to claim 1, wherein the first set is spaced apart from the second set along a transverse direction perpendicular to the stacking direction.
16. A circuit comprising a capacitor according to claim 1, and a power supply that supplies the applied DC bias voltage to the capacitor through the first and second DC bias terminations.
17. The circuit according to claim 16, wherein the applied DC bias voltage is greater than about 100V without exceeding about 50% of the breakdown voltage of the tunable dielectric material.
18. A multilayer capacitor array comprising the capacitor described in claim 1, a first lead frame connected to each first active termination, and a second lead frame connected to each second active termination.