High capacitance embedded components package

Abstract

The disclosure relates to a high capacitance embedded components package (100) comprising: at least two laminate layers (110a, 110b) stacked on top of each other, wherein each laminate layer (110a, 110b) comprises a plurality of capacitors (120) embedded therein, each capacitor (120) comprising a first terminal (121) and a second terminal (122); wherein each laminate layer (110a, 110b) comprises one or more metal layers (111, 112) electrically connecting the first terminals (121) and the second terminals (122) of the plurality of capacitors (120); and at least one connection metal layer (131, 132) electrically interconnecting the one or more metal layers (111, 112) of the at least two laminate layers (110a, 110b) with one another for an electrical interconnection of the plurality of capacitors (120) of the at least two laminate layers (110a, 110b) to a high capacitance embedded components package. The disclosure further relates to methods for producing such package.

Description

[0001] HIGH CAPACITANCE EMBEDDED COMPONENTS PACKAGE

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of chip embedding and packaging technology for power packaging. In particular, the disclosure relates to a high capacitance embedded components package (ECP) and methods for producing such package. Specifically, a high capacitance ECP module is disclosed.

[0004] BACKGROUND

[0005] Chip embedding technology is a relatively new packaging technology that is nowadays used also for power packaging. The main benefits of the embedding technology are that it allows to reduce the parasitic inductances and to maximize the electrical performance of the modules and at the same time to reduce the package size. One of the most demanding challenge coming from the markets is that there is a strong demand to increase the module performance and at the same time to reduce the module size and thickness and increase the power density. This is a big challenge not only for how to improve the thermal performance of the module but also how to increase the capacitance density inside the modules. In advanced power modules a high number of capacitors and a high capacitance is needed to be integrated to the module. These modules can contain 10-30 large size output capacitors, for example, and similar or even more smaller size input capacitors.

[0006] SUMMARY

[0007] This disclosure provides a solution for overcoming the above-described problems with chip embedding technology. In particular a solution is presented how to obtain increased capacitance density to achieve high-speed output voltage regulation and to allow the use of advanced power topologies.

[0008] The foregoing and other objects and other objectives are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] This disclosure presents a new type of high capacitance module where multiple MLCC (multi-layer ceramic capacitors) or other capacitors (e.g. silicon capacitors or other types of discrete capacitors such as thin film capacitors, capacitance layer, etc.) are embedded inside a PCB laminate layer and multiple of these layers are stacked above each other. The components can be connected parallel or in series and one package can contain only one or several component groups. The module can be designed to be mounted horizontally or vertically on the system board.

[0010] Embodiments described in this disclosure describe methods to manufacture a laminate-based package that includes several ECP layers that each contains multiple embedded capacitors that are connected parallel or in series. The package can be designed to be horizontally or vertically mounted on the system board so that the whole module is rotated 90 degree and connected from the side wall of the package.

[0011] In such novel laminate-based package, MLCC or silicon capacitors can be embedded inside a laminate with CE / ECP technology, for example. Several ECP layers with embedded components can be stacked together and connected to each other with plated vias or slots, for example. The capacitors can be connected to each other parallel or in series. The package can contain one, two or several layer with embedded capacitors, for example. The module can contain one or several capacitor groups, for example. The package can be separated with dicing or cutting process so that one side of the plated via or slot is exposed. The package can be flipped 90 degrees prior the mounting to the PCB board so that the components are vertically inside the package.

[0012] The novel package described herein can be used like a normal component or capacitor package or module and it makes no major big differences to the applications or way how the application can be designed.

[0013] The novel high capacitance embedded components package described in this disclosure can be applied in PSIP (Power supply in package), DC / DC converters, BMP (board mounted power) modules and other types of power modules where high capacitance needs to be integrated into the subsystem or next to the subsystem.

[0014] For this novel high capacitance embedded components package a high number of capacitors, and a high capacitance can be integrated in such package. The package can contain, for example, 10-30 large size output capacitors and similar or even more smaller size input capacitors.

[0015] The novel high capacitance embedded components package can be applied for example, for highly compact DC-DC converter modules for xPUs (auxiliary processing units that run inside a data center server or appliance) and HPC (high-performance computing) systems for processing massive amounts of data and performing complex calculations at high speeds.

[0016] The disclosed high capacitance embedded components package provides low voltage drop and settling times for dynamic voltage scaling and high bandwidth output voltage control (for example / s~l-2 MHz). Very high currents and current density requirements can be fulfilled, about 1000 A output currents, for example. The high capacitance embedded components package enables power topologies that make use of several flying capacitors. Hybrid switches capacitor topologies can be applied. The disclosed high capacitance embedded components package provides vertical power delivery to reduce losses on the PDN (packet data network). It allows a modular assembly of the module.

[0017] In order to describe the disclosure in detail, the following terms, abbreviations and notations will be used:

[0018] PCB Printed Circuit Board

[0019] CE Chip Embedding

[0020] ECP Embedded Component (or Chip) Package or Packaging

[0021] PTH Plated Through Hole(s)

[0022] LTI Lead Tip Inspection

[0023] MLCC Multi-Layer Ceramic Capacitor(s)

[0024] PSIP Power Supply In Package

[0025] BMP Board Mounted Power Module FR-4: Composite material that is widely used PCB laminate. It consists of epoxy resin that is reinforced with woven glass fiber.

[0026] In this disclosure, chip embedding technology is described. Chip embedding technology can also be used for power packaging. The main benefits of the embedding technology are that it allows to reduce the parasitic inductances and to maximize the electrical performance of the modules and at the same time to reduce the package size. In addition to embed the semiconductor devices ECP technology can also be used to embed other components like capacitors, resistors and other electrical components that are compatible with embedding process from size and structure point of view and have compatible pad metallization that can be used in micro via drilling and plating processes. Although the ECP process is currently used only to embed components inside one layer (due to complexity, yield, high number of connections, etc.) it can also be used to manufacture 3D stacked structures where the components are embedded inside multiple PCB layers that are stacked above each other and connected together with plated micro vias and / or plated side wall connections. Due to simple design, robust component and only limited number of connections to each component (typically only 2) the 3D ECP process is very suitable for paralleling multiple passive components that are stacked in multiple layers above each other.

[0027] There are several different types of embedding processes available: In a typical chip embedding process, the electronic components (chips, capacitors, resistors, etc.) are either placed inside an opening in a PCB core layer or soldered on a two or multilayer PCB board. The actual embedding inside the final PCB board can be performed by laminating FR4 prepregs or other polymer sheets above and below the core layer that holds the components to be embedded. The electrical connection between the embedded components and the PCB metal layers can be formed by soldering the component terminals to the inner laminate layers and subsequently laminating the PCB layers together. In more advanced embedding technologies, the components can be electrically connected by galvanically filled micro vias which is more robust, since there is no remelting of solder inside the package or board, which has to be considered when mounting the other components to the outer layers of the PCB. The micro vias are usually formed after lamination by laser drilling from the top surface through the thin laminate layer to the active chip pads or to the terminals of an embedded component package.

[0028] Through-hole technology refers to the mounting scheme used for electronic components that involves the use of leads on the components that are inserted into holes drilled in printed circuit boards (PCB) and soldered to pads on the opposite side either by manual assembly (hand placement) or by the use of automated insertion mount machines. In through-hole technology, the components are mounted on the PCB board by inserting their leads through the respective hole. These holes are called through holes since they are drilled from the top to the bottom of the board. According to a first aspect, the disclosure relates to a high capacitance embedded components package comprising: at least two laminate layers stacked on top of each other, wherein each laminate layer comprises a plurality of capacitors embedded therein, each capacitor comprising a first terminal and a second terminal; wherein each laminate layer comprises one or more metal layers electrically connecting the first terminals and the second terminals of the plurality of capacitors; and at least one connection metal layer electrically interconnecting the one or more metal layers of the at least two laminate layers with one another for an electrical interconnection of the plurality of capacitors of the at least two laminate layers to a high capacitance embedded components package.

[0029] A high capacitance embedded components package according to the disclosure is a package with multiple electrically interconnected capacitors which overall capacitance is larger than the individual capacitances of the capacitors.

[0030] Such high capacitance embedded components package provides a very high capacitance density (multiple paralleled capacitors) to achieve high-speed output voltage regulation and to allow the use of advanced power topologies.

[0031] In an exemplary implementation of the high capacitance embedded components package, the at least one connection metal layer comprises at least one or a combination of a plated side wall, a plated through hole, a plated slot, an embedded sinter lamination and a hybrid bonding layer.

[0032] This provides the advantage that the heat extraction path of the device can be routed via package side walls which results in improved thermal dissipation of the semiconductor package.

[0033] In an exemplary implementation of the high capacitance embedded components package, the one or more metal layers comprise a first metal layer electrically connecting the first terminals and a second metal layer electrically connecting the second terminals of the plurality of capacitors.

[0034] Such design facilitates routing of the capacitor terminals from an inside of the package to an outside of the package.

[0035] In an exemplary implementation of the high capacitance embedded components package, the first metal layer of each laminate layer is routed from inside the laminate layer to a first side wall of the package; and the second metal layer of each laminate layer is routed from inside the laminate layer to a second side wall or to the first side wall of the package.

[0036] The package may comprise a first main surface and a second main surface opposing the first main surface, and one or more side walls between the first main surface and the second main surface as shown in Figure la, for example.

[0037] The side walls may also be referred to as “side faces”, “side surfaces” or simply as “sides” of the package.

[0038] This routing to the side walls improves heat transfer from inside the package to the outside.

[0039] In an exemplary implementation of the high capacitance embedded components package, the at least one connection metal layer comprises a first connection metal layer and a second connection metal layer; wherein the first connection metal layer at least partially covers the first side wall, forming a plated first side wall that electrically connects the first metal layer; and wherein the second connection metal layer at least partially covers the second side wall, forming a plated second side wall that electrically connects the second metal layer.

[0040] This results in improved thermal and electrical performance due to electrical and thermal conduction via the side walls. In an exemplary implementation of the high capacitance embedded components package, the first connection metal layer forms a first terminal of the high capacitance embedded components package; and the second connection metal layer forms a second terminal of the high capacitance embedded components package.

[0041] This allows to use the connection metal layers as terminals of the package which results in large connection areas for improved heat transfer.

[0042] In an exemplary implementation of the high capacitance embedded components package, the first terminals and the second terminals of the plurality of capacitors are electrically connected to the respective metal layers by plated micro vias.

[0043] These plated micro vias allow an easy manufacturing of the laminate layers and the whole package.

[0044] In an exemplary implementation of the high capacitance embedded components package, the plurality of capacitors embedded in a respective laminate layer are electrically connected in parallel or in series; and / or wherein the plurality of capacitors embedded in two or more of the laminate layers are electrically connected in parallel or in series; and / or wherein the plurality of capacitors embedded in the at least two laminate layers are divided into groups, wherein the capacitors of a respective group are electrically connected in parallel or in series.

[0045] This provides design flexibility since different electrical connection of the capacitors and dividing the capacitors into groups can be implemented.

[0046] In an exemplary implementation of the high capacitance embedded components package, the plurality of capacitors of the package are divided into several independent capacitor blocks, each capacitor block being electrically connected to a first pad and a second pad arranged at a bottom or a side wall of the package.

[0047] This allows to integrate different independent capacitor groups into a single package.

[0048] In an exemplary implementation of the high capacitance embedded components package, the package is configured to operate as a capacitor block or capacitor package with an overall capacitance corresponding to the electrical interconnection of the plurality of capacitors of the at least two laminate layers.

[0049] This allows providing a package with multiple electrically interconnected capacitors which overall capacitance is larger than the individual capacitances of the capacitors.

[0050] Such high capacitance embedded components package provides a very high capacitance density (multiple paralleled capacitors) to achieve high-speed output voltage regulation and to allow the use of advanced power topologies.

[0051] In an exemplary implementation of the high capacitance embedded components package, the package is configured to operate as a capacitor block or capacitor package without any active components embedded in the high capacitance embedded components package.

[0052] Such package can be implemented without active components such as chips, integrated circuits, etc. A high capacitance embedded components package can be provided with a large number of capacitors. According to a second aspect, the disclosure relates to a high capacitance circuit board, comprising: a system board having a first main surface; and a high capacitance embedded components package according to the first aspect described above that is mounted onto the first main surface of the system board.

[0053] Such a circuit board provides a very high capacitance density (multiple paralleled capacitors) to achieve high-speed output voltage regulation and to allow the use of advanced power topologies. Size, shape and capacitance of the circuit board can be adjusted based on requirements. The circuit board is compatible with multiple types of capacitors, not depending on the supplier.

[0054] In an exemplary implementation of the high capacitance circuit board, the high capacitance embedded components package is horizontally or vertically mounted onto the system board.

[0055] Not only a single high capacitance embedded components package but multiple such packages can be flexible mounted onto the system board which allows a high degree of design flexibility.

[0056] In an exemplary implementation of the high capacitance circuit board, the plurality of capacitors of the at least two laminate layers are aligned in a direction that is either horizontal or vertical to the first main surface of the system board.

[0057] Not only the package as such can be flexible mounted, also the capacitors embedded in the laminate layers can be flexible aligned within their respective package, further enhancing the design flexibility.

[0058] In an exemplary implementation of the high capacitance circuit board, the high capacitance circuit board comprises: one or more solder pads arranged on the first main surface of the system board; wherein the high capacitance embedded components package is electrically connected to the system board by one or more solder platings or solder fillets arranged between the one or more solder pads and the at least one connection metal layer.

[0059] Such solder platings or solder fillets enable optimal thermal dissipation from the package to the system board due to their large contact areas.

[0060] In an exemplary implementation of the high capacitance circuit board, the one or more solder platings or solder fillets are formed to extract at least a portion of heat generated by the plurality of capacitors of the high capacitance embedded components package via the at least one connection metal layer to the at least one solder pad of the system board.

[0061] This allows optimal heat transmission of the heat generated by the capacitors.

[0062] According to a third aspect, the disclosure relates to a method for manufacturing a capacitor embedded laminate layer, the method comprising: providing a laminate layer with openings in the laminate layer; mounting at least one capacitor with a first and a second terminal inside the openings of the laminate layer; embedding the at least one capacitor inside the laminate layer by lamination to form a capacitor embedded laminate layer; cutting microvias into the capacitor embedded laminate layer to open the terminals of the at least one capacitor; electrically contacting the terminals of the at least one capacitor by metal plating; and structuring the capacitor embedded laminate layer.

[0063] By such method an easy manufacturing of a capacitor embedded laminate layer as described above with respect to the first aspect can be implemented. According to a fourth aspect, the disclosure relates to a method for manufacturing a high capacitance embedded components package, the method comprising: laying -up at least two capacitor embedded laminate layers and laminating the layed-up at least two capacitor embedded laminate layers to form a lay-up package, the lay-up package comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side; cutting through holes or slot openings into the lay-up package extending from the top side to the bottom side of the lay-up package, wherein the through holes or slot openings are cutting through a metal plating of the at least two capacitor embedded laminate layers, the metal plating providing an electrically and thermally connection of the connection terminals of the embedded capacitors; metal plating the through holes or slot openings of the lay-up package to electrically and thermally connect the connection terminals of the embedded capacitors; and dicing the lay-up package by cutting from a middle of a through hole or slot opening of the lay-up package and exposing one side of the plated through hole or slot opening to form a high capacitance embedded components package.

[0064] By such method an easy manufacturing of a high capacitance embedded components package as described above with respect to the first aspect can be implemented.

[0065] In an exemplary implementation of the method, laying-up the at least two capacitor embedded laminate layers comprises placing prepreg material and metal foils above and / or below the capacitor embedded laminate layers and / or placing prepreg material between the capacitor embedded laminate layers to form the lay-up package.

[0066] The metal foils can form the metal layers that electrically connect the first and second terminals of the capacitors. The prepreg material can be used for embedding the capacitors in the laminate layers.

[0067] In an exemplary implementation of the method, the method comprises: placing the high capacitance embedded components package in a vertical or horizontal position with respect to a first main surface of a system board; and mounting the high capacitance embedded components package in the vertical or horizontal position onto the system board.

[0068] The method allows a flexible mounting of one or more high capacitance embedded components packages as described above onto the system board which allows a high degree of design flexibility.

[0069] The main features and advantages of embodiments described in this disclosure can be given as follows:

[0070] A high capacitance embedded components package (i.e., capacitor module) is provided that has very high capacitance density (multiple paralleled capacitors). The capacitor module can have multiple capacitors groups.

[0071] The embedding process and stacking process are relatively simple: Simple alignment of the layers; all connections between the layers can be done in the final step with large size side wall connections or plated through holes.

[0072] The capacitor module can be mounted horizontally or vertically on a system board depending on application requirements. Size, shape and capacitance can be adjusted based on the needs. The package is compatible with all capacitors having Cu metallization (not supplier related).

[0073] The high capacitance ECP module has higher buffer capacitance per area and per volume, thus alleviating the high bandwidth requirements. It allows for increase of number of level / stages (for same area) of power converter using advanced topologies, resulting in a higher converter efficiency. It allows higher power density for same footprint of current per area without running into thermal issues (lower equivalent ESR). The high capacitance ECP module allows for simplification of the converter system (module) assembly and hence a higher reliability. It allows for simplification of the PCB designs and thus faster time to market. The high capacitance ECP module is suitable for modular vertical power delivery and thus lower losses on the PDN.

[0074] BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0076] Figures la and lb show a schematic cross section and top view of a high capacitance embedded components package 100 according to a first embodiment;

[0077] Figures 2a and 2b show a schematic cross section and side view of a high capacitance embedded components package 100 according to a second embodiment;

[0078] Figure 3 shows a schematic diagram illustrating a method 300 for manufacturing a capacitor embedded laminate layer according to an embodiment;

[0079] Figure 4 shows a schematic diagram illustrating a method 400 for manufacturing a high capacitance embedded components package 100 according to an embodiment; and

[0080] Figure 5 shows a schematic cross section of a high capacitance circuit board 500 according to an embodiment.

[0081] DETAILED DESCRIPTION OF EMBODIMENTS

[0082] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

[0083] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0084] This disclosure includes two embodiments of a high capacitance embedded components package (see Figures la / b and 2a / b) and the process to manufacture such a package (see Figures 3 and 4) where capacitors are connected in parallel as an example. The first embodiment described below with respect to Figure 1 presents the concept where components are horizontally inside the high capacitance module and the second embodiment described with respect to Figure 2 presents the concept where the module is 90° degree flipped and the components are arranged vertically inside the module. The idea is not only limited to these embodiments also other type of configurations can be manufactured (e.g. capacitors in series, in multiple groups that are parallel and / or series). The disclosure further presents a high capacitance circuit board (see Figure 5). Figures la and lb show a schematic cross section (Fig. la) and top view (Fig. lb) of a high capacitance embedded components package 100 according to a first embodiment. The package 100 is horizontally mounted in this example although a vertical mounting can be implemented as well. The capacitors are connected from opposite sides.

[0085] The high capacitance embedded components package 100 comprises at least two laminate layers 110a, 110b stacked on top of each other. Each laminate layer 110a, 110b comprises a plurality of capacitors 120 embedded therein. Each capacitor 120 comprises a first terminal 121 and a second terminal 122. Each laminate layer 110a, 110b comprises one or more metal layers

[0086] 111, 112 electrically connecting the first terminals 121 and the second terminals 122 of the plurality of capacitors 120.

[0087] The high capacitance embedded components package 100 comprises at least one connection metal layer 131, 132 electrically interconnecting the one or more metal layers 111, 112 of the at least two laminate layers 110a, 110b with one another for an electrical interconnection of the plurality of capacitors 120 of the at least two laminate layers 110a, 110b to a high capacitance embedded components package.

[0088] A high capacitance embedded components package as described in this disclosure is a package with multiple electrically interconnected capacitors which overall capacitance is larger than the individual capacitances of the capacitors.

[0089] The at least one connection metal layer 131, 132 may comprise at least one or a combination of a plated side wall, a plated through hole, a plated slot, an embedded sinter lamination and a hybrid bonding layer. Elybrid bonding and such a hybrid bonding layer is described below (after description of Figure 5).

[0090] To improve the performance the connection between connection metal layers 131, 132 and the one or more metal layers 111,

[0091] 112, such connection can be implemented by using hybrid bonding, e.g., as described below. Hybrid bonding can be applied to improve heat extraction from the capacitors inside the package 100 towards the package sidewalls.

[0092] The plated side walls, i.e., the connection metal layers 131, 132 of the package improve the soldering, allow LH and heat transfer. Large area / cross section side wall connections instead of limited number of plated vias also helps to minimize the current density in copper routing from inside the package to the package outside.

[0093] Hybrid bonding as referred to in this disclosure is a process that allows simultaneously bonding of metallic contacts and dielectric areas in one bonding process. Hybrid bonding can be used for 3D-integration on wafer level and on package level. A method or process to form these connections has the following characteristics: Using a standard PCB lamination process (bond temperature, pressure, format); using hybrid bonding to bond metal to metal and dielectric to dielectric in one step; Several premanufactured layers can be connected to each other in one lamination step or in several sequential lamination steps; the bonding materials can be attached or applied to the surface of the laminate layers or placed between the laminate layers prior to bonding.

[0094] A high capacitance embedded components package 100 as described above, which connection metal layers may comprise a hybrid bonding layer may be produced by using a hybrid bonding process and a method for producing such high capacitance embedded components package 100 by using hybrid bonding is described below (after the description with respect to Figure 5).

[0095] The one or more metal layers 111, 112 may comprise a first metal layer 111 electrically connecting the first terminals 121 and a second metal layer 112 electrically connecting the second terminals 122 of the plurality of capacitors 120. The first metal layer 111 of each laminate layer 110a, 110b may be routed from inside the laminate layer to a first side wall 101c of the package 100 as shown in Figure la / b.

[0096] The second metal layer 112 of each laminate layer 110a, 110b may be routed from inside the laminate layer to a second side wall 101 d or to the first side wall 101c of the package 100 as shown in Figure la / b.

[0097] The package 100 may comprise a first main surface 101a and a second main surface 101b opposing the first main surface 101a, and one or more side walls 101c, 10 Id between the first main surface 101a and the second main surface 101b as shown in Figure la, for example.

[0098] The at least one connection metal layer 131, 132 may comprise a first connection metal layer 131 and a second connection metal layer 132. The first connection metal layer 131 may at least partially cover the first side wall 101 c as shown in F igure la, forming a plated first side wall that electrically connects the first metal layer 111. The second connection metal layer 132 may at least partially cover the second side wall 10 Id as shown in Figure la, forming a plated second side wall that electrically connects the second metal layer 112.

[0099] The first connection metal layer 131 may form a first terminal 102 of the high capacitance embedded components package 100. The second connection metal layer 132 may form a second terminal 103 of the high capacitance embedded components package 100 as shown in Figure la.

[0100] The first terminals 121 and the second terminals 122 of the plurality of capacitors 120 may be electrically connected to the respective metal layers 111, 112 by plated micro vias 123 as shown in Figure la.

[0101] The plurality of capacitors 120 embedded in a respective laminate layer 110a, 110b may be electrically connected in parallel or in series (Figure la / b shows an exemplary parallel connection). The plurality of capacitors 120 embedded in two or more of the laminate layers 110a, 110b may be electrically connected in parallel or in series (Figure la / b shows an exemplary parallel connection). The plurality of capacitors 120 embedded in the at least two laminate layers 110a, 110b may be divided into groups (not shown in the Figures), wherein the capacitors of a respective group are electrically connected in parallel or in series.

[0102] The plurality of capacitors 120 of the package 100 may be divided into several independent capacitor blocks (not shown in the Figures). Each capacitor block may be electrically connected to a first pad and a second pad arranged at a bottom 101b or a side wall 101c, 101 d of the package 100.

[0103] The high capacitance embedded components package 100 may be configured to operate as a capacitor block or capacitor package with an overall capacitance corresponding to the electrical interconnection of the plurality of capacitors 120 of the at least two laminate layers 110a, 110b.

[0104] The high capacitance embedded components package 100 may be configured to operate as a capacitor block or capacitor package without any active components embedded in the high capacitance embedded components package 100, as shown in the Figures.

[0105] In the following, an exemplary configuration for a high capacitance module (also referred herein as high capacitance embedded components package 100) where the parallel components are arranged horizontally inside the module is described. The basic idea is to embed multiple capacitors inside a PCB layer 110a, 110b and stack at least two (or more) of these layers 110a, 110b together as shown in Figure la / b. The connections between the embedded capacitors 120 and the laminate are done with plated micro vias 123 and between the different ECP layers 110a, 110b with plated PTHs or slots that can be diced half during package separation. If needed additional through holes or hybrid bonding can be used to make the connection between HS (high-side) and LS (low-side) more effective.

[0106] An example of such a high capacitance module 100 is presented in Figure la / b. In this example, an exemplary number of sixteen capacitors 120 are connected parallel in one ECP layer (top view) and four of these layers are stacked above each other (cross section). In the example module, a number of 64 MLCC capacitors 120 can be embedded inside PCB laminates 110a, 110b and all capacitors 120 can be connected in parallel. The left side terminals of all embedded capacitors 120 are connected together (see Figure la) and routed to the left side of the module and other terminals to the right side as shown in Figure la. An MLCC capacitor is non-polarized and has not + and - terminals. The contact pads of the module 100 are located on the bottom side 101b of the module 100. In the Figures the layers 110a, 110b are connected together with plated side walls (here referred to as connection metal layers 131, 132), the plated side walls can also be used to make the soldering more easy, effective and reliable (solder fillet will rise to the sidewalls). Instead of plated sidewalls also plated PTH or embedded sinter lamination connection can be used.

[0107] Figures 2a and 2b show a schematic cross section (Fig. 2a) and side view (Fig. 2b) of a high capacitance embedded components package 100 according to a second embodiment. In this example, the package 100 is vertically mounted in contrast to Figures la and lb where the package 100 is horizontally mounted. In the cross section shown in Figure 2a, the capacitors are connected from opposite sides; in the side view shown in Figure 2b, the capacitors are connected from the same side.

[0108] The high capacitance embedded components package 100 comprises at least two laminate layers 110a, 110b stacked on top of each other. In this configuration where a vertically mounting of the package 100 is shown, the at least two laminate layers 110a, 110b are stacked next to each other. Each laminate layer 110a, 110b comprises a plurality of capacitors 120 embedded therein. Each capacitor 120 comprises a first terminal 121 and a second terminal 122. Each laminate layer 110a, 110b comprises one or more metal layers 111, 112 electrically connecting the first terminals 121 and the second terminals 122 of the plurality of capacitors 120.

[0109] The high capacitance embedded components package 100 comprises at least one connection metal layer 131, 132 electrically interconnecting the one or more metal layers 111, 112 of the at least two laminate layers 110a, 110b with one another for an electrical interconnection of the plurality of capacitors 120 of the at least two laminate layers 110a, 110b to a high capacitance embedded components package.

[0110] In the following, an exemplary configuration for a high capacitance module (also referred herein as high capacitance embedded components package 100) where the parallel components are arranged vertically inside the module 100 is described.

[0111] The connections between the embedded capacitors 120 and the laminate 110a, 110b can be implemented with plated micro vias 123 as shown in Figures 2a and 2b and between the different ECP layers with plated PTHs or slots that are diced half during package separation. If needed additional through holes or hybrid bonding can be used to make the connection between HS (high-side) and LS (low-side) more effective. In the example shown in Figures 2a and 2b, an exemplary number of twelve capacitors 120 are connected in parallel in one ECP layer (top view) and five of these layers are stacked above each other (as shown in the cross section, Figure 2a). In the example module 100, an exemplary number of sixty MLCC capacitors 120 are embedded inside PCB laminates and all capacitors are connected in parallel. The left side terminals of all embedded capacitors 120 are connected together and routed to the left side of the module and other terminals to the right side. Note that an MLCC capacitor is non-polarized and has not + and - terminals. As shown in Figures 2a / b, the layers 110a, 110b are connected together with plated side walls, the plated side walls can also be used as a soldering pad of the module 100. After package separation the module 100 is flipped by 90° degrees and mounted to system boards so that the capacitors 120 are vertically arranged inside the package 100.

[0112] Figure 3 shows a schematic diagram illustrating a method 300 for manufacturing a capacitor embedded laminate layer according to an embodiment. The capacitor embedded laminate layer may correspond to one of the laminate layers 110a, 110b with embedded capacitors 120 as described above with respect to Figures la / b and 2a / b.

[0113] The method 300 comprises the following:

[0114] Providing 301, 302, 303, 304 a laminate layer 321 with openings 322 in the laminate layer 321;

[0115] Mounting 305 at least one capacitor 120 with a first 121 and a second 122 terminal inside the openings 322 of the laminate layer 321;

[0116] Embedding 306, 307 the at least one capacitor 120 inside the laminate layer 321 by lamination to form a capacitor embedded laminate layer 110a;

[0117] Cutting 308 microvias 323 into the capacitor embedded laminate layer 110a to open the terminals 121, 122 of the at least one capacitor 120;

[0118] Electrically contacting 309 the terminals 121, 122 of the at least one capacitor 120 by metal plating; and

[0119] Structuring 310, 311 the capacitor embedded laminate layer 110a.

[0120] This embodiment describes a first process flow to manufacture a laminate layer 110a, 110b with embedded capacitors 120 as described above with respect to Figures la / b and 2a / b. The whole process comprises the first process flow 300 as shown in Figure 3 and a second process flow 400 as shown in Figure 4. The basic idea of the whole process is to embed at least two capacitors 120 inside separate PCB core layers (see Figure 3), laminate these core layers together and connect the laminate layers with plated side wall slots that are diced half during package separation (see Figure 4). Instead of dicing also e.g. routing can be used.

[0121] In the first process as shown in Figure 3 capacitors 120 are embedded inside a 2-layer PCB. The capacitors 120 can be embedded inside the PCB using normal PCB process.

[0122] The ECP process may contain the following steps as shown in Figure 3:

[0123] A laminate layer 321, e.g. FR4 laminate can be provided 301.

[0124] PTH Drilling 302: Mechanical or laser drilling of the vias. Optional process is connections between top and bottom side of the core is needed in the design.

[0125] Cutting 303 of the cavities for the components that will be embedded. Inside one cavity one or several capacitors can be placed next to each other. The cutting can be performed with laser, mechanical routing or punching. Bonding tape is laminated 304 on bottom side of the core layer. UV release tape, thermal release tape or other bonding tape can be used.

[0126] Capacitors (referred herein as dies) can be placed 305 inside the opening 322 with e.g. pick and placement machine.

[0127] Prepreg or other resin foil and Cu seed layer foil can be laminated 306 on top side of the core layer.

[0128] After bonding tape is removed 307 a prepreg or other resin foil and Cu seed layer foil can be laminated 307 on bottom side of the core layer.

[0129] Micro vias to the capacitor metallization can be drilled 308, for example with UV laser. The vias can be on one side or on both sides of the core layer.

[0130] Capacitors can be connected with electroless and electro plating 309 to the Cu seed layer

[0131] The structuring can be performed by using photo lithography process 310 and etching 311. A pattern plating process can also be used.

[0132] Figure 4 shows a schematic diagram illustrating a method 400 for manufacturing a high capacitance embedded components package 100 according to an embodiment.

[0133] The method 400 comprises the following:

[0134] Laying-up 401 at least two capacitors embedded laminate layers 110a, 110b, e.g. as described above with respect to Figures la / b, 2a / b and 3, and laminating 402 the layed-up at least two capacitor embedded laminate layers 110a, 110b to form a lay-up package 411 , the lay-up package 411 comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side; cutting 403 through holes or slot openings 412 into the lay-up package 411 extending from the top side to the bottom side of the lay-up package 411, wherein the through holes or slot openings 412 are cutting through a metal plating 111, 112 of the at least two capacitor embedded laminate layers 110a, 110b, the metal plating providing an electrically and thermally connection of the connection terminals 121, 122 of the embedded capacitors 120;

[0135] Metal plating 404 the through holes or slot openings 412 of the lay-up package 411 to electrically and thermally connect the connection terminals 121, 122 of the embedded capacitors 120; and

[0136] Dicing 405 the lay-up package 411 by cutting from a middle of a through hole or slot opening 412 of the lay-up package 411 and exposing one side of the plated through hole or slot opening 412 to form a high capacitance embedded components package 100.

[0137] Laying-up 401 the at least two capacitor embedded laminate layers 110a, 110b may comprise placing prepreg material 422, 423 and metal foils 421 above and / or below the capacitor embedded laminate layers 110a, 110b and / or placing prepreg material 423 between the capacitor embedded laminate layers 110a, 110b to form the lay-up package 411.

[0138] The method 400 may further comprising: placing 406 the high capacitance embedded components package 100 in a vertical or horizontal position with respect to a first main surface 510a of a system board 510 as shown in Figure 5, for example; and mounting the high capacitance embedded components package 100 in the vertical or horizontal position onto the system board 510.

[0139] This embodiment describes a second process flow 400 to manufacture a high capacitance embedded components package 100 including stacked laminate layers 110a, 110b with embedded capacitors 120 as described above with respect to Figures la / b and 2a / b. The whole process comprises the first process flow 300 as described above with respect to Figure 3 and a second process flow 400 as shown in Figure 4.

[0140] The second process flow 400 in the manufacturing process is the layup and lamination step where multiple (2 or more) core layers with multiple embedded capacitors are laminated together with normal PCB vacuum lamination process, for example. This process is described here in Figure 4. The layup may comprise the following layers:

[0141] Cu foil 421, (not needed if core layer with embedded capacitors is structured only from one side);

[0142] Prepreg 422 (not needed if core layer with embedded capacitors is structured only from one side);

[0143] First embedded core layer 110a with embedded capacitors;

[0144] Prepreg 423; additional core layer with or without Cu (to increase the package thickness or improve routing capability or thermal performance);

[0145] Prepreg;

[0146] Second embedded core layer with embedded dies 110b (can be multiplied as many times as needed);

[0147] Cu foil 421, (not needed if core layer with embedded dies is structured only from one side);

[0148] Prepreg (not needed if core layer with embedded dies is structured only from one side).

[0149] After lamination 402 mechanical drilled through large slot openings are manufactured on the edge areas of the modules. After drilling step Cu is plated on the side walls of the PTHs or slots 412 with normal electroless and electrochemical plating processes 404 and the copper layer is structured with normal photolithography and etching processes 405. The package can be separated with mechanical dicing or other package separation process. The dicing can be performed from the center line of the plated PTH or slot so that one side of the plated side wall is exposed. An additional routing process can be used at least on the footprint side to remove the laminate bridges between the slots to make the footprint flat and easier for assembly and soldering. After separation that package can be flipped by 90 degrees, so that the capacitors 120 inside the package 100 are vertically arranged.

[0150] Figure 5 shows a schematic cross section of a high capacitance circuit board 500 according to an embodiment.

[0151] The high capacitance circuit board 500 comprises: a system board 510 having a first main surface 510a; and a high capacitance embedded components package 100 as described above with respect to Figures la / b and 2a / b which is mounted onto the first main surface 510a of the system board 510. The high capacitance embedded components package 100 may be horizontally or vertically mounted onto the system board 510. In Figure 5, an exemplary vertically mounted package 100 is shown.

[0152] The plurality of capacitors 120 of the at least two laminate layers 110a, 110b may be aligned in a direction that is either horizontal or vertical to the first main surface 510a of the system board 510. In Figure 5, the capacitors 120 are vertically aligned as an example configuration.

[0153] The high capacitance circuit board 500 may comprise: one or more solder pads 511 arranged on the first main surface 510a of the system board 510. The high capacitance embedded components package 100 may be electrically connected to the system board 510 by one or more solder platings 513 or solder fillets 513 arranged between the one or more solder pads 511 and the at least one connection metal layer 131, 132 as shown in Figure 5.

[0154] The one or more solder platings 513 or solder fillets 513 may be formed to extract at least a portion of heat generated by the plurality of capacitors 120 of the high capacitance embedded components package 100 via the at least one connection metal layer 131, 132 to the at least one solder pad 511 of the system board 510.

[0155] An additional heat sink may be mounted to the system board 510, e.g. on its bottom side.

[0156] Hybrid Bonding

[0157] In the following a high capacitance embedded components package 100 that may be produced by applying hybrid bonding (and other technologies) and a method for producing a high capacitance embedded components package 100 by using hybrid bonding (and other technologies) is described. The high capacitance embedded components package 100 may correspond to the high capacitance embedded components package 100 as described above with respect to Figures 1 to 5.

[0158] Note that the metal layers described in the following with respect to the hybrid bonding may be different from the metal layers described above with respect to the Figures.

[0159] Such high capacitance embedded components package 100 provides the advantage of having direct vertical connections between two or more laminate core layers 110a, 110b. These vertical connections can be made within the projected physical outline of embedded components if the laminate layer have such embedded components; they are not confined to a certain shape or size, i.e., they can be flexible designed in shape and size; they do not need an outer layer plating process to form the electrical connection; they are suitable for power electronics, since they have low inductance and high current capability; they are reliable and do not remelt at bond temperature. These vertical connections can be formed, for example by solid-liquid interdiffusion (SLID), transient liquid phase (TLP) bonding or sintering.

[0160] Thus, the high capacitance embedded components package 100 provides increased power density and efficiency, short, current- capable low-parasitic interconnection paths, a very good thermal management and improved electrical isolation. Conductor traces with a current capability of several ten Amperes up to hundreds of Amperes and even higher, and power modules with an internal stray inductance below about 10 nH and even lower can be achieved.

[0161] The one or more metal layers 131, 132 can be redistribution or routing metal layers for redistributing or routing current paths. It understands that the high capacitance embedded components package 100 is not restricted to a specific number of metal layers or laminate layers. The high capacitance embedded components package 100 can have any number of such layers. In an exemplary implementation of the high capacitance embedded components package 100, the connection metal layer forms a non-remelting electrical and mechanical connection.

[0162] Such a “non-remelting” connection is different from a normal solder connection such as formed during a conventional TC / NCP process (thermo-compression bonding with solder and pre-applied non-conductive polymer). A non-remelting connection provides the advantage that it is a connection which will not remelt or decompose at temperatures much higher than the process temperature it was formed.

[0163] In an exemplary implementation of the high capacitance embedded components package 100, the connection metal layer forms one of a diffusion soldering connection or a sintering connection.

[0164] Diffusion soldering or diffusion bonding is a metal joining technique which can be advantageously applied to electronic packaging. It operates on the principle of interdiffusion of two dissimilar metals, wherein a liquid phase is completely transformed into solid state by means of metallic phase reactions and intermetallic compound formation. Similar terms for such technique are transient liquid phase bonding, solid-liquid interdiffusion, isothermal solidification. The technique provides the advantage that the resulting solid phase has a higher melting point than the temperature of the formation process.

[0165] Sintering is the process of compacting and forming a solid mass of material by heat or pressure without melting it to the point of liquefaction. Sintering happens as part of a manufacturing process used with metals, ceramics, plastics, and other materials. The atoms in the materials diffuse across the boundaries of the particles, fusing the particles together and creating one solid piece. The advantage of sintering is the following: Because the sintering temperature does not have to reach the melting point of the material, sintering is often chosen as the shaping process for materials with extremely high melting points.

[0166] The connection metal of the connection metal layer can form a composed metal layer, for example. Such composed metal layer may include a compound from more than two metals, e.g., such as inter-metallic layer, or a connection of metal layers consisting of one single metal, or a connection of a metal and a polymer or polymer mixture.

[0167] For such inter-metallic layer, the melting point of the inter metallic layer is higher than the lamination / process temperature where it was formed.

[0168] The connection metal layer may consist of more than 80% metal and less than 20% pores or polymers, for example.

[0169] The connection metal layer is designed for high current loads.

[0170] In one embodiment, the inter-metallic layer may have a minimum lateral size of typically >lmm in each dimension, but not smaller than 0.1 mm.

[0171] The intermetallic layer may have a large cross-section, short length and good conductor and due to that is suitable for high current loads.

[0172] In one embodiment, the connection metal layer may have a typical thickness of 5 to 50 um, but not thicker than 0.2 mm (in case of a single layer structure).

[0173] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0174] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0175] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0176] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1. A high capacitance embedded components package (100) comprising: at least two laminate layers (110a, 110b) stacked on top of each other, wherein each laminate layer (110a, 110b) comprises a plurality of capacitors (120) embedded therein, each capacitor (120) comprising a first terminal (121) and a second terminal (122); wherein each laminate layer (110a, 110b) comprises one or more metal layers (111, 112) electrically connecting the first terminals (121) and the second terminals (122) of the plurality of capacitors (120); and at least one connection metal layer (131, 132) electrically interconnecting the one or more metal layers (111, 112) of the at least two laminate layers (110a, 110b) with one another for an electrical interconnection of the plurality of capacitors (120) of the at least two laminate layers (110a, 110b) to a high capacitance embedded components package.

2. The high capacitance embedded components package (100) of claim 1, wherein the at least one connection metal layer (131, 132) comprises at least one or a combination of a plated side wall, a plated through hole, a plated slot, an embedded sinter lamination and a hybrid bonding layer.

3. The high capacitance embedded components package (100) of claim 1 or 2, wherein the one or more metal lay ers ( 111 , 112) comprise a first metal lay er ( 111 ) electrically connecting the first terminals (121) and a second metal layer (112) electrically connecting the second terminals (122) of the plurality of capacitors (120).

4. The high capacitance embedded components package (100) of claim 3, wherein the first metal layer ( 111 ) of each laminate layer (110a, 110b) is routed from inside the laminate layer to a first side wall (101c) of the package (100); and wherein the second metal layer (112) of each laminate layer (110a, 110b) is routed from inside the laminate layer to a second side wall ( 101 d) or to the first side wall (101c) of the package (100).

5. The high capacitance embedded components package (100) of claim 4, wherein the at least one connection metal layer (131, 132) comprises a first connection metal layer (131) and a second connection metal layer (132); and wherein the first connection metal layer (131) at least partially covers the first side wall (101c), forming a plated first side wall that electrically connects the first metal layer (111); and wherein the second connection metal layer (132) at least partially covers the second side wall (lOld), forming a plated second side wall that electrically connects the second metal layer (112).

6. The high capacitance embedded components package (100) of claim 5, wherein the first connection metal layer (131) forms a first terminal ( 102) of the high capacitance embedded components package (100); andwherein the second connection metal layer (132) forms a second terminal (103) of the high capacitance embedded components package (100).

7. The high capacitance embedded components package (100) of any of the preceding claims, wherein the first terminals (121) and the second terminals (122) of the plurality of capacitors (120) are electrically connected to the respective metal layers (111, 112) by plated microvias (123).

8. The high capacitance embedded components package (100) of any of the preceding claims, wherein the plurality of capacitors (120) embedded in a respective laminate layer (110a, 110b) are electrically connected in parallel or in series; and / or wherein the plurality of capacitors (120) embedded in two or more of the laminate layers (110a, 110b) are electrically connected in parallel or in series; and / or wherein the plurality of capacitors (120) embedded in the at least two laminate layers (110a, 110b) are divided into groups, wherein the capacitors of a respective group are electrically connected in parallel or in series.

9. The high capacitance embedded components package (100) of any of the preceding claims, wherein the plurality of capacitors (120) of the package (100) are divided into several independent capacitor blocks, each capacitor block being electrically connected to a first pad and a second pad arranged at a bottom (101b) or a side wall (101c, lOld) of the package (100).

10. The high capacitance embedded components package (100) of any of the preceding claims, being configured to operate as a capacitor block or capacitor package with an overall capacitance corresponding to the electrical interconnection of the plurality of capacitors (120) of the at least two laminate layers (110a, 110b).

11. The high capacitance embedded components package (100) of any of the preceding claims, being configured to operate as a capacitor block or capacitor package without any active components embedded in the high capacitance embedded components package (100).

12. A high capacitance circuit board (500), comprising: a system board (510) having a first main surface (510a); and a high capacitance embedded components package (100) according to any of the preceding claims mounted onto the first main surface (510a) of the system board (510).

13. The high capacitance circuit board (500) of claim 12, wherein the high capacitance embedded components package (100) is horizontally or vertically mounted onto the system board (510).

14. The high capacitance circuit board (500) of claim 13,wherein the plurality of capacitors (120) of the at least two laminate layers (110a, 110b) are aligned in a direction that is either horizontal or vertical to the first main surface (510a) of the system board (510).

15. The high capacitance circuit board (500) of any of claims 12 to 14, comprising: one or more solder pads (511 ) arranged on the first main surface (510a) of the system board (510); wherein the high capacitance embedded components package (100) is electrically connected to the system board (510) by one or more solder platings (513) or solder fillets (513) arranged between the one or more solder pads (511) and the at least one connection metal layer (131, 132).

16. The high capacitance circuit board (500) of claim 15, wherein the one or more solder platings (513) or solder fillets (513) are formed to extract at least a portion of heat generated by the plurality of capacitors (120) of the high capacitance embedded components package (100) via the at least one connection metal layer (131, 132) to the at least one solder pad (511) of the system board (510).

17. A method (300) for manufacturing a capacitor embedded laminate layer (110a), the method (300) comprising: providing (301, 302, 303, 304) a laminate layer (321) with openings (322) in the laminate layer (321); mounting (305) at least one capacitor (120) with a first and a second terminal inside the openings (322) of the laminate layer (321); embedding (306, 307) the at least one capacitor (120) inside the laminate layer (321) by lamination to form a capacitor embedded laminate layer (110a); cutting (308) micro vias (323) into the capacitor embedded laminate layer (110a) to open the terminals (121, 122) of the at least one capacitor (120); electrically contacting (309) the terminals (121, 122) of the at least one capacitor (120) by metal plating; and structuring (310, 311) the capacitor embedded laminate layer (110a).

18. A method (400) for manufacturing a high capacitance embedded components package (100), the method comprising: laying-up (401 ) at least two capacitor embedded laminate layers (110a, 110b) and laminating (402) the layed-up at least two capacitor embedded laminate layers (110a, 110b) to form a lay-up package (411), the lay-up package (411) comprising a top side and a bottom side opposing the top side and side walls between the top side and the bottom side; cutting (403) through holes or slot openings (412) into the lay-up package (411) extending from the top side to the bottom side of the lay-up package (411), wherein the through holes or slot openings (412) are cutting through a metal plating (111, 112) of the at least two capacitor embedded laminate layers (110a, 110b), the metal plating providing an electrically and thermally connection of the connection terminals (121, 122) of the embedded capacitors (120); metal plating (404) the through holes or slot openings (412) of the lay-up package (411) to electrically and thermally connect the connection terminals (121, 122) of the embedded capacitors (120); anddicing (405) the lay-up package (411) by cutting from a middle of a through hole or slot opening (412) of the layup package (411) and exposing one side of the plated through hole or slot opening (412) to form a high capacitance embedded components package (100).

19. The method (400) of claim 18, wherein laying-up (401 ) the at least two capacitor embedded laminate layers (110a, 110b) comprises placing prepreg material (422, 423) and metal foils (421) above and / or below the capacitor embedded laminate layers (110a, 110b) and / or placing prepreg material (423) between the capacitor embedded laminate layers (110a, 110b) to form the lay-up package (411).

20. The method (400) of claim 18 or 19, comprising: placing (406) the high capacitance embedded components package (100) in a vertical or horizontal position with respect to a first main surface (510a) of a system board (510); and mounting the high capacitance embedded components package (100) in the vertical or horizontal position onto the system board (510).

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